4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <rte_common.h>
39 #include <rte_memory.h>
40 #include <rte_malloc.h>
41 #include <rte_cycles.h>
42 #include <rte_prefetch.h>
43 #include <rte_branch_prediction.h>
46 #include "rte_sched.h"
47 #include "rte_bitmap.h"
48 #include "rte_sched_common.h"
49 #include "rte_approx.h"
51 #ifdef __INTEL_COMPILER
52 #pragma warning(disable:2259) /* conversion may lose significant bits */
55 #ifndef RTE_SCHED_OPTIMIZATIONS
56 #define RTE_SCHED_OPTIMIZATIONS 0
59 #if RTE_SCHED_OPTIMIZATIONS
60 #include <immintrin.h>
63 #define RTE_SCHED_ENQUEUE 1
65 #ifndef RTE_SCHED_TB_RATE_CONFIG_ERR
66 #define RTE_SCHED_TB_RATE_CONFIG_ERR (1e-7)
69 #define RTE_SCHED_WRR 1
71 #ifndef RTE_SCHED_WRR_SHIFT
72 #define RTE_SCHED_WRR_SHIFT 3
75 #ifndef RTE_SCHED_PORT_N_GRINDERS
76 #define RTE_SCHED_PORT_N_GRINDERS 8
78 #if (RTE_SCHED_PORT_N_GRINDERS == 0) || (RTE_SCHED_PORT_N_GRINDERS & (RTE_SCHED_PORT_N_GRINDERS - 1))
79 #error Number of grinders must be non-zero and a power of 2
81 #if (RTE_SCHED_OPTIMIZATIONS && (RTE_SCHED_PORT_N_GRINDERS != 8))
82 #error Number of grinders must be 8 when RTE_SCHED_OPTIMIZATIONS is set
85 #define RTE_SCHED_GRINDER_PCACHE_SIZE (64 / RTE_SCHED_QUEUES_PER_PIPE)
87 #define RTE_SCHED_PIPE_INVALID UINT32_MAX
89 #define RTE_SCHED_BMP_POS_INVALID UINT32_MAX
91 struct rte_sched_subport {
92 /* Token bucket (TB) */
93 uint64_t tb_time; /* time of last update */
95 uint32_t tb_credits_per_period;
99 /* Traffic classes (TCs) */
100 uint64_t tc_time; /* time of next update */
101 uint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
102 uint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
105 /* TC oversubscription */
107 uint32_t tc_ov_wm_min;
108 uint32_t tc_ov_wm_max;
109 uint8_t tc_ov_period_id;
115 struct rte_sched_subport_stats stats;
118 struct rte_sched_pipe_profile {
119 /* Token bucket (TB) */
121 uint32_t tb_credits_per_period;
124 /* Pipe traffic classes */
126 uint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
127 uint8_t tc_ov_weight;
130 uint8_t wrr_cost[RTE_SCHED_QUEUES_PER_PIPE];
133 struct rte_sched_pipe {
134 /* Token bucket (TB) */
135 uint64_t tb_time; /* time of last update */
138 /* Pipe profile and flags */
141 /* Traffic classes (TCs) */
142 uint64_t tc_time; /* time of next update */
143 uint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
145 /* Weighted Round Robin (WRR) */
146 uint8_t wrr_tokens[RTE_SCHED_QUEUES_PER_PIPE];
148 /* TC oversubscription */
149 uint32_t tc_ov_credits;
150 uint8_t tc_ov_period_id;
152 } __rte_cache_aligned;
154 struct rte_sched_queue {
159 struct rte_sched_queue_extra {
160 struct rte_sched_queue_stats stats;
167 e_GRINDER_PREFETCH_PIPE = 0,
168 e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS,
169 e_GRINDER_PREFETCH_MBUF,
174 * Path through the scheduler hierarchy used by the scheduler enqueue
175 * operation to identify the destination queue for the current
176 * packet. Stored in the field pkt.hash.sched of struct rte_mbuf of
177 * each packet, typically written by the classification stage and read
178 * by scheduler enqueue.
180 struct rte_sched_port_hierarchy {
181 uint32_t queue:2; /**< Queue ID (0 .. 3) */
182 uint32_t traffic_class:2; /**< Traffic class ID (0 .. 3)*/
183 uint32_t pipe:20; /**< Pipe ID */
184 uint32_t subport:6; /**< Subport ID */
185 uint32_t color:2; /**< Color */
188 struct rte_sched_grinder {
190 uint16_t pcache_qmask[RTE_SCHED_GRINDER_PCACHE_SIZE];
191 uint32_t pcache_qindex[RTE_SCHED_GRINDER_PCACHE_SIZE];
196 enum grinder_state state;
199 struct rte_sched_subport *subport;
200 struct rte_sched_pipe *pipe;
201 struct rte_sched_pipe_profile *pipe_params;
204 uint8_t tccache_qmask[4];
205 uint32_t tccache_qindex[4];
211 struct rte_sched_queue *queue[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
212 struct rte_mbuf **qbase[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
213 uint32_t qindex[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
217 struct rte_mbuf *pkt;
220 uint16_t wrr_tokens[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
221 uint16_t wrr_mask[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
222 uint8_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
225 struct rte_sched_port {
226 /* User parameters */
227 uint32_t n_subports_per_port;
228 uint32_t n_pipes_per_subport;
231 uint32_t frame_overhead;
232 uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
233 uint32_t n_pipe_profiles;
234 uint32_t pipe_tc3_rate_max;
236 struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][e_RTE_METER_COLORS];
240 uint64_t time_cpu_cycles; /* Current CPU time measured in CPU cyles */
241 uint64_t time_cpu_bytes; /* Current CPU time measured in bytes */
242 uint64_t time; /* Current NIC TX time measured in bytes */
243 double cycles_per_byte; /* CPU cycles per byte */
245 /* Scheduling loop detection */
247 uint32_t pipe_exhaustion;
250 struct rte_bitmap *bmp;
251 uint32_t grinder_base_bmp_pos[RTE_SCHED_PORT_N_GRINDERS] __rte_aligned_16;
254 struct rte_sched_grinder grinder[RTE_SCHED_PORT_N_GRINDERS];
255 uint32_t busy_grinders;
256 struct rte_mbuf **pkts_out;
259 /* Queue base calculation */
260 uint32_t qsize_add[RTE_SCHED_QUEUES_PER_PIPE];
263 /* Large data structures */
264 struct rte_sched_subport *subport;
265 struct rte_sched_pipe *pipe;
266 struct rte_sched_queue *queue;
267 struct rte_sched_queue_extra *queue_extra;
268 struct rte_sched_pipe_profile *pipe_profiles;
270 struct rte_mbuf **queue_array;
271 uint8_t memory[0] __rte_cache_aligned;
272 } __rte_cache_aligned;
274 enum rte_sched_port_array {
275 e_RTE_SCHED_PORT_ARRAY_SUBPORT = 0,
276 e_RTE_SCHED_PORT_ARRAY_PIPE,
277 e_RTE_SCHED_PORT_ARRAY_QUEUE,
278 e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA,
279 e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES,
280 e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY,
281 e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY,
282 e_RTE_SCHED_PORT_ARRAY_TOTAL,
285 #ifdef RTE_SCHED_COLLECT_STATS
287 static inline uint32_t
288 rte_sched_port_queues_per_subport(struct rte_sched_port *port)
290 return RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport;
295 static inline uint32_t
296 rte_sched_port_queues_per_port(struct rte_sched_port *port)
298 return RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport * port->n_subports_per_port;
302 rte_sched_port_check_params(struct rte_sched_port_params *params)
306 if (params == NULL) {
311 if ((params->socket < 0) || (params->socket >= RTE_MAX_NUMA_NODES)) {
316 if (params->rate == 0) {
321 if (params->mtu == 0) {
325 /* n_subports_per_port: non-zero, power of 2 */
326 if ((params->n_subports_per_port == 0) || (!rte_is_power_of_2(params->n_subports_per_port))) {
330 /* n_pipes_per_subport: non-zero, power of 2 */
331 if ((params->n_pipes_per_subport == 0) || (!rte_is_power_of_2(params->n_pipes_per_subport))) {
335 /* qsize: non-zero, power of 2,
336 * no bigger than 32K (due to 16-bit read/write pointers) */
337 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
338 uint16_t qsize = params->qsize[i];
340 if ((qsize == 0) || (!rte_is_power_of_2(qsize))) {
345 /* pipe_profiles and n_pipe_profiles */
346 if ((params->pipe_profiles == NULL) ||
347 (params->n_pipe_profiles == 0) ||
348 (params->n_pipe_profiles > RTE_SCHED_PIPE_PROFILES_PER_PORT)) {
352 for (i = 0; i < params->n_pipe_profiles; i ++) {
353 struct rte_sched_pipe_params *p = params->pipe_profiles + i;
355 /* TB rate: non-zero, not greater than port rate */
356 if ((p->tb_rate == 0) || (p->tb_rate > params->rate)) {
360 /* TB size: non-zero */
361 if (p->tb_size == 0) {
365 /* TC rate: non-zero, less than pipe rate */
366 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
367 if ((p->tc_rate[j] == 0) || (p->tc_rate[j] > p->tb_rate)) {
372 /* TC period: non-zero */
373 if (p->tc_period == 0) {
377 #ifdef RTE_SCHED_SUBPORT_TC_OV
378 /* TC3 oversubscription weight: non-zero */
379 if (p->tc_ov_weight == 0) {
384 /* Queue WRR weights: non-zero */
385 for (j = 0; j < RTE_SCHED_QUEUES_PER_PIPE; j ++) {
386 if (p->wrr_weights[j] == 0) {
396 rte_sched_port_get_array_base(struct rte_sched_port_params *params, enum rte_sched_port_array array)
398 uint32_t n_subports_per_port = params->n_subports_per_port;
399 uint32_t n_pipes_per_subport = params->n_pipes_per_subport;
400 uint32_t n_pipes_per_port = n_pipes_per_subport * n_subports_per_port;
401 uint32_t n_queues_per_port = RTE_SCHED_QUEUES_PER_PIPE * n_pipes_per_subport * n_subports_per_port;
403 uint32_t size_subport = n_subports_per_port * sizeof(struct rte_sched_subport);
404 uint32_t size_pipe = n_pipes_per_port * sizeof(struct rte_sched_pipe);
405 uint32_t size_queue = n_queues_per_port * sizeof(struct rte_sched_queue);
406 uint32_t size_queue_extra = n_queues_per_port * sizeof(struct rte_sched_queue_extra);
407 uint32_t size_pipe_profiles = RTE_SCHED_PIPE_PROFILES_PER_PORT * sizeof(struct rte_sched_pipe_profile);
408 uint32_t size_bmp_array = rte_bitmap_get_memory_footprint(n_queues_per_port);
409 uint32_t size_per_pipe_queue_array, size_queue_array;
413 size_per_pipe_queue_array = 0;
414 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
415 size_per_pipe_queue_array += RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS * params->qsize[i] * sizeof(struct rte_mbuf *);
417 size_queue_array = n_pipes_per_port * size_per_pipe_queue_array;
421 if (array == e_RTE_SCHED_PORT_ARRAY_SUBPORT) return base;
422 base += RTE_CACHE_LINE_ROUNDUP(size_subport);
424 if (array == e_RTE_SCHED_PORT_ARRAY_PIPE) return base;
425 base += RTE_CACHE_LINE_ROUNDUP(size_pipe);
427 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE) return base;
428 base += RTE_CACHE_LINE_ROUNDUP(size_queue);
430 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA) return base;
431 base += RTE_CACHE_LINE_ROUNDUP(size_queue_extra);
433 if (array == e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES) return base;
434 base += RTE_CACHE_LINE_ROUNDUP(size_pipe_profiles);
436 if (array == e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY) return base;
437 base += RTE_CACHE_LINE_ROUNDUP(size_bmp_array);
439 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY) return base;
440 base += RTE_CACHE_LINE_ROUNDUP(size_queue_array);
446 rte_sched_port_get_memory_footprint(struct rte_sched_port_params *params)
448 uint32_t size0, size1;
451 status = rte_sched_port_check_params(params);
453 RTE_LOG(NOTICE, SCHED,
454 "Port scheduler params check failed (%d)\n", status);
459 size0 = sizeof(struct rte_sched_port);
460 size1 = rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_TOTAL);
462 return (size0 + size1);
466 rte_sched_port_config_qsize(struct rte_sched_port *port)
469 port->qsize_add[0] = 0;
470 port->qsize_add[1] = port->qsize_add[0] + port->qsize[0];
471 port->qsize_add[2] = port->qsize_add[1] + port->qsize[0];
472 port->qsize_add[3] = port->qsize_add[2] + port->qsize[0];
475 port->qsize_add[4] = port->qsize_add[3] + port->qsize[0];
476 port->qsize_add[5] = port->qsize_add[4] + port->qsize[1];
477 port->qsize_add[6] = port->qsize_add[5] + port->qsize[1];
478 port->qsize_add[7] = port->qsize_add[6] + port->qsize[1];
481 port->qsize_add[8] = port->qsize_add[7] + port->qsize[1];
482 port->qsize_add[9] = port->qsize_add[8] + port->qsize[2];
483 port->qsize_add[10] = port->qsize_add[9] + port->qsize[2];
484 port->qsize_add[11] = port->qsize_add[10] + port->qsize[2];
487 port->qsize_add[12] = port->qsize_add[11] + port->qsize[2];
488 port->qsize_add[13] = port->qsize_add[12] + port->qsize[3];
489 port->qsize_add[14] = port->qsize_add[13] + port->qsize[3];
490 port->qsize_add[15] = port->qsize_add[14] + port->qsize[3];
492 port->qsize_sum = port->qsize_add[15] + port->qsize[3];
496 rte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)
498 struct rte_sched_pipe_profile *p = port->pipe_profiles + i;
500 RTE_LOG(DEBUG, SCHED, "Low level config for pipe profile %u:\n"
501 " Token bucket: period = %u, credits per period = %u, size = %u\n"
502 " Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\n"
503 " Traffic class 3 oversubscription: weight = %hhu\n"
504 " WRR cost: [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu]\n",
509 p->tb_credits_per_period,
512 /* Traffic classes */
514 p->tc_credits_per_period[0],
515 p->tc_credits_per_period[1],
516 p->tc_credits_per_period[2],
517 p->tc_credits_per_period[3],
519 /* Traffic class 3 oversubscription */
523 p->wrr_cost[ 0], p->wrr_cost[ 1], p->wrr_cost[ 2], p->wrr_cost[ 3],
524 p->wrr_cost[ 4], p->wrr_cost[ 5], p->wrr_cost[ 6], p->wrr_cost[ 7],
525 p->wrr_cost[ 8], p->wrr_cost[ 9], p->wrr_cost[10], p->wrr_cost[11],
526 p->wrr_cost[12], p->wrr_cost[13], p->wrr_cost[14], p->wrr_cost[15]);
529 static inline uint64_t
530 rte_sched_time_ms_to_bytes(uint32_t time_ms, uint32_t rate)
532 uint64_t time = time_ms;
533 time = (time * rate) / 1000;
539 rte_sched_port_config_pipe_profile_table(struct rte_sched_port *port, struct rte_sched_port_params *params)
543 for (i = 0; i < port->n_pipe_profiles; i ++) {
544 struct rte_sched_pipe_params *src = params->pipe_profiles + i;
545 struct rte_sched_pipe_profile *dst = port->pipe_profiles + i;
548 if (src->tb_rate == params->rate) {
549 dst->tb_credits_per_period = 1;
552 double tb_rate = ((double) src->tb_rate) / ((double) params->rate);
553 double d = RTE_SCHED_TB_RATE_CONFIG_ERR;
555 rte_approx(tb_rate, d, &dst->tb_credits_per_period, &dst->tb_period);
557 dst->tb_size = src->tb_size;
559 /* Traffic Classes */
560 dst->tc_period = (uint32_t) rte_sched_time_ms_to_bytes(src->tc_period, params->rate);
561 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
562 dst->tc_credits_per_period[j] = (uint32_t) rte_sched_time_ms_to_bytes(src->tc_period, src->tc_rate[j]);
564 #ifdef RTE_SCHED_SUBPORT_TC_OV
565 dst->tc_ov_weight = src->tc_ov_weight;
569 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
570 uint32_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
571 uint32_t lcd, lcd1, lcd2;
574 qindex = j * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS;
576 wrr_cost[0] = src->wrr_weights[qindex];
577 wrr_cost[1] = src->wrr_weights[qindex + 1];
578 wrr_cost[2] = src->wrr_weights[qindex + 2];
579 wrr_cost[3] = src->wrr_weights[qindex + 3];
581 lcd1 = rte_get_lcd(wrr_cost[0], wrr_cost[1]);
582 lcd2 = rte_get_lcd(wrr_cost[2], wrr_cost[3]);
583 lcd = rte_get_lcd(lcd1, lcd2);
585 wrr_cost[0] = lcd / wrr_cost[0];
586 wrr_cost[1] = lcd / wrr_cost[1];
587 wrr_cost[2] = lcd / wrr_cost[2];
588 wrr_cost[3] = lcd / wrr_cost[3];
590 dst->wrr_cost[qindex] = (uint8_t) wrr_cost[0];
591 dst->wrr_cost[qindex + 1] = (uint8_t) wrr_cost[1];
592 dst->wrr_cost[qindex + 2] = (uint8_t) wrr_cost[2];
593 dst->wrr_cost[qindex + 3] = (uint8_t) wrr_cost[3];
596 rte_sched_port_log_pipe_profile(port, i);
599 port->pipe_tc3_rate_max = 0;
600 for (i = 0; i < port->n_pipe_profiles; i ++) {
601 struct rte_sched_pipe_params *src = params->pipe_profiles + i;
602 uint32_t pipe_tc3_rate = src->tc_rate[3];
604 if (port->pipe_tc3_rate_max < pipe_tc3_rate) {
605 port->pipe_tc3_rate_max = pipe_tc3_rate;
610 struct rte_sched_port *
611 rte_sched_port_config(struct rte_sched_port_params *params)
613 struct rte_sched_port *port = NULL;
614 uint32_t mem_size, bmp_mem_size, n_queues_per_port, i;
616 /* Check user parameters. Determine the amount of memory to allocate */
617 mem_size = rte_sched_port_get_memory_footprint(params);
622 /* Allocate memory to store the data structures */
623 port = rte_zmalloc("qos_params", mem_size, RTE_CACHE_LINE_SIZE);
628 /* User parameters */
629 port->n_subports_per_port = params->n_subports_per_port;
630 port->n_pipes_per_subport = params->n_pipes_per_subport;
631 port->rate = params->rate;
632 port->mtu = params->mtu + params->frame_overhead;
633 port->frame_overhead = params->frame_overhead;
634 memcpy(port->qsize, params->qsize, sizeof(params->qsize));
635 port->n_pipe_profiles = params->n_pipe_profiles;
638 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
641 for (j = 0; j < e_RTE_METER_COLORS; j++) {
642 /* if min/max are both zero, then RED is disabled */
643 if ((params->red_params[i][j].min_th |
644 params->red_params[i][j].max_th) == 0) {
648 if (rte_red_config_init(&port->red_config[i][j],
649 params->red_params[i][j].wq_log2,
650 params->red_params[i][j].min_th,
651 params->red_params[i][j].max_th,
652 params->red_params[i][j].maxp_inv) != 0) {
660 port->time_cpu_cycles = rte_get_tsc_cycles();
661 port->time_cpu_bytes = 0;
663 port->cycles_per_byte = ((double) rte_get_tsc_hz()) / ((double) params->rate);
665 /* Scheduling loop detection */
666 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
667 port->pipe_exhaustion = 0;
670 port->busy_grinders = 0;
671 port->pkts_out = NULL;
672 port->n_pkts_out = 0;
674 /* Queue base calculation */
675 rte_sched_port_config_qsize(port);
677 /* Large data structures */
678 port->subport = (struct rte_sched_subport *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_SUBPORT));
679 port->pipe = (struct rte_sched_pipe *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_PIPE));
680 port->queue = (struct rte_sched_queue *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE));
681 port->queue_extra = (struct rte_sched_queue_extra *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA));
682 port->pipe_profiles = (struct rte_sched_pipe_profile *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES));
683 port->bmp_array = port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY);
684 port->queue_array = (struct rte_mbuf **) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY));
686 /* Pipe profile table */
687 rte_sched_port_config_pipe_profile_table(port, params);
690 n_queues_per_port = rte_sched_port_queues_per_port(port);
691 bmp_mem_size = rte_bitmap_get_memory_footprint(n_queues_per_port);
692 port->bmp = rte_bitmap_init(n_queues_per_port, port->bmp_array, bmp_mem_size);
693 if (port->bmp == NULL) {
694 RTE_LOG(ERR, SCHED, "Bitmap init error\n");
697 for (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i ++) {
698 port->grinder_base_bmp_pos[i] = RTE_SCHED_PIPE_INVALID;
705 rte_sched_port_free(struct rte_sched_port *port)
707 /* Check user parameters */
712 rte_bitmap_free(port->bmp);
717 rte_sched_port_log_subport_config(struct rte_sched_port *port, uint32_t i)
719 struct rte_sched_subport *s = port->subport + i;
721 RTE_LOG(DEBUG, SCHED, "Low level config for subport %u:\n"
722 " Token bucket: period = %u, credits per period = %u, size = %u\n"
723 " Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\n"
724 " Traffic class 3 oversubscription: wm min = %u, wm max = %u\n",
729 s->tb_credits_per_period,
732 /* Traffic classes */
734 s->tc_credits_per_period[0],
735 s->tc_credits_per_period[1],
736 s->tc_credits_per_period[2],
737 s->tc_credits_per_period[3],
739 /* Traffic class 3 oversubscription */
745 rte_sched_subport_config(struct rte_sched_port *port,
747 struct rte_sched_subport_params *params)
749 struct rte_sched_subport *s;
752 /* Check user parameters */
753 if ((port == NULL) ||
754 (subport_id >= port->n_subports_per_port) ||
759 if ((params->tb_rate == 0) || (params->tb_rate > port->rate)) {
763 if (params->tb_size == 0) {
767 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
768 if ((params->tc_rate[i] == 0) || (params->tc_rate[i] > params->tb_rate)) {
773 if (params->tc_period == 0) {
777 s = port->subport + subport_id;
779 /* Token Bucket (TB) */
780 if (params->tb_rate == port->rate) {
781 s->tb_credits_per_period = 1;
784 double tb_rate = ((double) params->tb_rate) / ((double) port->rate);
785 double d = RTE_SCHED_TB_RATE_CONFIG_ERR;
787 rte_approx(tb_rate, d, &s->tb_credits_per_period, &s->tb_period);
789 s->tb_size = params->tb_size;
790 s->tb_time = port->time;
791 s->tb_credits = s->tb_size / 2;
793 /* Traffic Classes (TCs) */
794 s->tc_period = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, port->rate);
795 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
796 s->tc_credits_per_period[i] = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, params->tc_rate[i]);
798 s->tc_time = port->time + s->tc_period;
799 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
800 s->tc_credits[i] = s->tc_credits_per_period[i];
803 #ifdef RTE_SCHED_SUBPORT_TC_OV
804 /* TC oversubscription */
805 s->tc_ov_wm_min = port->mtu;
806 s->tc_ov_wm_max = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, port->pipe_tc3_rate_max);
807 s->tc_ov_wm = s->tc_ov_wm_max;
808 s->tc_ov_period_id = 0;
814 rte_sched_port_log_subport_config(port, subport_id);
820 rte_sched_pipe_config(struct rte_sched_port *port,
823 int32_t pipe_profile)
825 struct rte_sched_subport *s;
826 struct rte_sched_pipe *p;
827 struct rte_sched_pipe_profile *params;
828 uint32_t deactivate, profile, i;
830 /* Check user parameters */
831 profile = (uint32_t) pipe_profile;
832 deactivate = (pipe_profile < 0);
833 if ((port == NULL) ||
834 (subport_id >= port->n_subports_per_port) ||
835 (pipe_id >= port->n_pipes_per_subport) ||
836 ((!deactivate) && (profile >= port->n_pipe_profiles))) {
840 /* Check that subport configuration is valid */
841 s = port->subport + subport_id;
842 if (s->tb_period == 0) {
846 p = port->pipe + (subport_id * port->n_pipes_per_subport + pipe_id);
848 /* Handle the case when pipe already has a valid configuration */
850 params = port->pipe_profiles + p->profile;
852 #ifdef RTE_SCHED_SUBPORT_TC_OV
853 double subport_tc3_rate = ((double) s->tc_credits_per_period[3]) / ((double) s->tc_period);
854 double pipe_tc3_rate = ((double) params->tc_credits_per_period[3]) / ((double) params->tc_period);
855 uint32_t tc3_ov = s->tc_ov;
857 /* Unplug pipe from its subport */
858 s->tc_ov_n -= params->tc_ov_weight;
859 s->tc_ov_rate -= pipe_tc3_rate;
860 s->tc_ov = s->tc_ov_rate > subport_tc3_rate;
862 if (s->tc_ov != tc3_ov) {
863 RTE_LOG(DEBUG, SCHED,
864 "Subport %u TC3 oversubscription is OFF (%.4lf >= %.4lf)\n",
865 subport_id, subport_tc3_rate, s->tc_ov_rate);
870 memset(p, 0, sizeof(struct rte_sched_pipe));
877 /* Apply the new pipe configuration */
878 p->profile = profile;
879 params = port->pipe_profiles + p->profile;
881 /* Token Bucket (TB) */
882 p->tb_time = port->time;
883 p->tb_credits = params->tb_size / 2;
885 /* Traffic Classes (TCs) */
886 p->tc_time = port->time + params->tc_period;
887 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
888 p->tc_credits[i] = params->tc_credits_per_period[i];
891 #ifdef RTE_SCHED_SUBPORT_TC_OV
893 /* Subport TC3 oversubscription */
894 double subport_tc3_rate = ((double) s->tc_credits_per_period[3]) / ((double) s->tc_period);
895 double pipe_tc3_rate = ((double) params->tc_credits_per_period[3]) / ((double) params->tc_period);
896 uint32_t tc3_ov = s->tc_ov;
898 s->tc_ov_n += params->tc_ov_weight;
899 s->tc_ov_rate += pipe_tc3_rate;
900 s->tc_ov = s->tc_ov_rate > subport_tc3_rate;
902 if (s->tc_ov != tc3_ov) {
903 RTE_LOG(DEBUG, SCHED,
904 "Subport %u TC3 oversubscription is ON (%.4lf < %.4lf)\n",
905 subport_id, subport_tc3_rate, s->tc_ov_rate);
907 p->tc_ov_period_id = s->tc_ov_period_id;
908 p->tc_ov_credits = s->tc_ov_wm;
916 rte_sched_port_pkt_write(struct rte_mbuf *pkt,
917 uint32_t subport, uint32_t pipe, uint32_t traffic_class,
918 uint32_t queue, enum rte_meter_color color)
920 struct rte_sched_port_hierarchy *sched
921 = (struct rte_sched_port_hierarchy *) &pkt->hash.sched;
923 sched->color = (uint32_t) color;
924 sched->subport = subport;
926 sched->traffic_class = traffic_class;
927 sched->queue = queue;
931 rte_sched_port_pkt_read_tree_path(const struct rte_mbuf *pkt,
932 uint32_t *subport, uint32_t *pipe,
933 uint32_t *traffic_class, uint32_t *queue)
935 const struct rte_sched_port_hierarchy *sched
936 = (const struct rte_sched_port_hierarchy *) &pkt->hash.sched;
938 *subport = sched->subport;
940 *traffic_class = sched->traffic_class;
941 *queue = sched->queue;
946 rte_sched_port_pkt_read_color(const struct rte_mbuf *pkt)
948 const struct rte_sched_port_hierarchy *sched
949 = (const struct rte_sched_port_hierarchy *) &pkt->hash.sched;
951 return (enum rte_meter_color) sched->color;
955 rte_sched_subport_read_stats(struct rte_sched_port *port,
957 struct rte_sched_subport_stats *stats,
960 struct rte_sched_subport *s;
962 /* Check user parameters */
963 if ((port == NULL) ||
964 (subport_id >= port->n_subports_per_port) ||
969 s = port->subport + subport_id;
971 /* Copy subport stats and clear */
972 memcpy(stats, &s->stats, sizeof(struct rte_sched_subport_stats));
973 memset(&s->stats, 0, sizeof(struct rte_sched_subport_stats));
975 /* Subport TC ovesubscription status */
982 rte_sched_queue_read_stats(struct rte_sched_port *port,
984 struct rte_sched_queue_stats *stats,
987 struct rte_sched_queue *q;
988 struct rte_sched_queue_extra *qe;
990 /* Check user parameters */
991 if ((port == NULL) ||
992 (queue_id >= rte_sched_port_queues_per_port(port)) ||
997 q = port->queue + queue_id;
998 qe = port->queue_extra + queue_id;
1000 /* Copy queue stats and clear */
1001 memcpy(stats, &qe->stats, sizeof(struct rte_sched_queue_stats));
1002 memset(&qe->stats, 0, sizeof(struct rte_sched_queue_stats));
1005 *qlen = q->qw - q->qr;
1010 static inline uint32_t
1011 rte_sched_port_qindex(struct rte_sched_port *port, uint32_t subport, uint32_t pipe, uint32_t traffic_class, uint32_t queue)
1015 result = subport * port->n_pipes_per_subport + pipe;
1016 result = result * RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE + traffic_class;
1017 result = result * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS + queue;
1022 static inline struct rte_mbuf **
1023 rte_sched_port_qbase(struct rte_sched_port *port, uint32_t qindex)
1025 uint32_t pindex = qindex >> 4;
1026 uint32_t qpos = qindex & 0xF;
1028 return (port->queue_array + pindex * port->qsize_sum + port->qsize_add[qpos]);
1031 static inline uint16_t
1032 rte_sched_port_qsize(struct rte_sched_port *port, uint32_t qindex)
1034 uint32_t tc = (qindex >> 2) & 0x3;
1036 return port->qsize[tc];
1039 #ifdef RTE_SCHED_DEBUG
1042 rte_sched_port_queue_is_empty(struct rte_sched_port *port, uint32_t qindex)
1044 struct rte_sched_queue *queue = port->queue + qindex;
1046 return (queue->qr == queue->qw);
1050 rte_sched_port_queue_is_full(struct rte_sched_port *port, uint32_t qindex)
1052 struct rte_sched_queue *queue = port->queue + qindex;
1053 uint16_t qsize = rte_sched_port_qsize(port, qindex);
1054 uint16_t qlen = queue->qw - queue->qr;
1056 return (qlen >= qsize);
1059 #endif /* RTE_SCHED_DEBUG */
1061 #ifdef RTE_SCHED_COLLECT_STATS
1064 rte_sched_port_update_subport_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1066 struct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));
1067 uint32_t tc_index = (qindex >> 2) & 0x3;
1068 uint32_t pkt_len = pkt->pkt_len;
1070 s->stats.n_pkts_tc[tc_index] += 1;
1071 s->stats.n_bytes_tc[tc_index] += pkt_len;
1075 rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1077 struct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));
1078 uint32_t tc_index = (qindex >> 2) & 0x3;
1079 uint32_t pkt_len = pkt->pkt_len;
1081 s->stats.n_pkts_tc_dropped[tc_index] += 1;
1082 s->stats.n_bytes_tc_dropped[tc_index] += pkt_len;
1086 rte_sched_port_update_queue_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1088 struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1089 uint32_t pkt_len = pkt->pkt_len;
1091 qe->stats.n_pkts += 1;
1092 qe->stats.n_bytes += pkt_len;
1096 rte_sched_port_update_queue_stats_on_drop(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1098 struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1099 uint32_t pkt_len = pkt->pkt_len;
1101 qe->stats.n_pkts_dropped += 1;
1102 qe->stats.n_bytes_dropped += pkt_len;
1105 #endif /* RTE_SCHED_COLLECT_STATS */
1107 #ifdef RTE_SCHED_RED
1110 rte_sched_port_red_drop(struct rte_sched_port *port, struct rte_mbuf *pkt, uint32_t qindex, uint16_t qlen)
1112 struct rte_sched_queue_extra *qe;
1113 struct rte_red_config *red_cfg;
1114 struct rte_red *red;
1116 enum rte_meter_color color;
1118 tc_index = (qindex >> 2) & 0x3;
1119 color = rte_sched_port_pkt_read_color(pkt);
1120 red_cfg = &port->red_config[tc_index][color];
1122 if ((red_cfg->min_th | red_cfg->max_th) == 0)
1125 qe = port->queue_extra + qindex;
1128 return rte_red_enqueue(red_cfg, red, qlen, port->time);
1132 rte_sched_port_set_queue_empty_timestamp(struct rte_sched_port *port, uint32_t qindex)
1134 struct rte_sched_queue_extra *qe;
1135 struct rte_red *red;
1137 qe = port->queue_extra + qindex;
1140 rte_red_mark_queue_empty(red, port->time);
1145 #define rte_sched_port_red_drop(port, pkt, qindex, qlen) 0
1147 #define rte_sched_port_set_queue_empty_timestamp(port, qindex)
1149 #endif /* RTE_SCHED_RED */
1151 #ifdef RTE_SCHED_DEBUG
1154 debug_pipe_is_empty(struct rte_sched_port *port, uint32_t pindex)
1158 qindex = pindex << 4;
1160 for (i = 0; i < 16; i ++){
1161 uint32_t queue_empty = rte_sched_port_queue_is_empty(port, qindex + i);
1162 uint32_t bmp_bit_clear = (rte_bitmap_get(port->bmp, qindex + i) == 0);
1164 if (queue_empty != bmp_bit_clear){
1165 rte_panic("Queue status mismatch for queue %u of pipe %u\n", i, pindex);
1177 debug_check_queue_slab(struct rte_sched_port *port, uint32_t bmp_pos, uint64_t bmp_slab)
1183 rte_panic("Empty slab at position %u\n", bmp_pos);
1187 for (i = 0, mask = 1; i < 64; i ++, mask <<= 1) {
1188 if (mask & bmp_slab){
1189 if (rte_sched_port_queue_is_empty(port, bmp_pos + i)) {
1190 printf("Queue %u (slab offset %u) is empty\n", bmp_pos + i, i);
1197 rte_panic("Empty queues in slab 0x%" PRIx64 "starting at position %u\n",
1202 #endif /* RTE_SCHED_DEBUG */
1204 static inline uint32_t
1205 rte_sched_port_enqueue_qptrs_prefetch0(struct rte_sched_port *port, struct rte_mbuf *pkt)
1207 struct rte_sched_queue *q;
1208 #ifdef RTE_SCHED_COLLECT_STATS
1209 struct rte_sched_queue_extra *qe;
1211 uint32_t subport, pipe, traffic_class, queue, qindex;
1213 rte_sched_port_pkt_read_tree_path(pkt, &subport, &pipe, &traffic_class, &queue);
1215 qindex = rte_sched_port_qindex(port, subport, pipe, traffic_class, queue);
1216 q = port->queue + qindex;
1218 #ifdef RTE_SCHED_COLLECT_STATS
1219 qe = port->queue_extra + qindex;
1227 rte_sched_port_enqueue_qwa_prefetch0(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf **qbase)
1229 struct rte_sched_queue *q;
1230 struct rte_mbuf **q_qw;
1233 q = port->queue + qindex;
1234 qsize = rte_sched_port_qsize(port, qindex);
1235 q_qw = qbase + (q->qw & (qsize - 1));
1237 rte_prefetch0(q_qw);
1238 rte_bitmap_prefetch0(port->bmp, qindex);
1242 rte_sched_port_enqueue_qwa(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf **qbase, struct rte_mbuf *pkt)
1244 struct rte_sched_queue *q;
1248 q = port->queue + qindex;
1249 qsize = rte_sched_port_qsize(port, qindex);
1250 qlen = q->qw - q->qr;
1252 /* Drop the packet (and update drop stats) when queue is full */
1253 if (unlikely(rte_sched_port_red_drop(port, pkt, qindex, qlen) || (qlen >= qsize))) {
1254 rte_pktmbuf_free(pkt);
1255 #ifdef RTE_SCHED_COLLECT_STATS
1256 rte_sched_port_update_subport_stats_on_drop(port, qindex, pkt);
1257 rte_sched_port_update_queue_stats_on_drop(port, qindex, pkt);
1262 /* Enqueue packet */
1263 qbase[q->qw & (qsize - 1)] = pkt;
1266 /* Activate queue in the port bitmap */
1267 rte_bitmap_set(port->bmp, qindex);
1270 #ifdef RTE_SCHED_COLLECT_STATS
1271 rte_sched_port_update_subport_stats(port, qindex, pkt);
1272 rte_sched_port_update_queue_stats(port, qindex, pkt);
1278 #if RTE_SCHED_ENQUEUE == 0
1281 rte_sched_port_enqueue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
1287 for (i = 0; i < n_pkts; i ++) {
1288 struct rte_mbuf *pkt;
1289 struct rte_mbuf **q_base;
1290 uint32_t subport, pipe, traffic_class, queue, qindex;
1294 rte_sched_port_pkt_read_tree_path(pkt, &subport, &pipe, &traffic_class, &queue);
1296 qindex = rte_sched_port_qindex(port, subport, pipe, traffic_class, queue);
1298 q_base = rte_sched_port_qbase(port, qindex);
1300 result += rte_sched_port_enqueue_qwa(port, qindex, q_base, pkt);
1309 * The enqueue function implements a 4-level pipeline with each stage processing
1310 * two different packets. The purpose of using a pipeline is to hide the latency
1311 * of prefetching the data structures. The naming convention is presented in the
1314 * p00 _______ p10 _______ p20 _______ p30 _______
1315 * ----->| |----->| |----->| |----->| |----->
1316 * | 0 | | 1 | | 2 | | 3 |
1317 * ----->|_______|----->|_______|----->|_______|----->|_______|----->
1322 rte_sched_port_enqueue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
1324 struct rte_mbuf *pkt00, *pkt01, *pkt10, *pkt11, *pkt20, *pkt21, *pkt30, *pkt31, *pkt_last;
1325 struct rte_mbuf **q00_base, **q01_base, **q10_base, **q11_base, **q20_base, **q21_base, **q30_base, **q31_base, **q_last_base;
1326 uint32_t q00, q01, q10, q11, q20, q21, q30, q31, q_last;
1327 uint32_t r00, r01, r10, r11, r20, r21, r30, r31, r_last;
1332 /* Less then 6 input packets available, which is not enough to feed the pipeline */
1333 if (unlikely(n_pkts < 6)) {
1334 struct rte_mbuf **q_base[5];
1337 /* Prefetch the mbuf structure of each packet */
1338 for (i = 0; i < n_pkts; i ++) {
1339 rte_prefetch0(pkts[i]);
1342 /* Prefetch the queue structure for each queue */
1343 for (i = 0; i < n_pkts; i ++) {
1344 q[i] = rte_sched_port_enqueue_qptrs_prefetch0(port, pkts[i]);
1347 /* Prefetch the write pointer location of each queue */
1348 for (i = 0; i < n_pkts; i ++) {
1349 q_base[i] = rte_sched_port_qbase(port, q[i]);
1350 rte_sched_port_enqueue_qwa_prefetch0(port, q[i], q_base[i]);
1353 /* Write each packet to its queue */
1354 for (i = 0; i < n_pkts; i ++) {
1355 result += rte_sched_port_enqueue_qwa(port, q[i], q_base[i], pkts[i]);
1361 /* Feed the first 3 stages of the pipeline (6 packets needed) */
1364 rte_prefetch0(pkt20);
1365 rte_prefetch0(pkt21);
1369 rte_prefetch0(pkt10);
1370 rte_prefetch0(pkt11);
1372 q20 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt20);
1373 q21 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt21);
1377 rte_prefetch0(pkt00);
1378 rte_prefetch0(pkt01);
1380 q10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);
1381 q11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);
1383 q20_base = rte_sched_port_qbase(port, q20);
1384 q21_base = rte_sched_port_qbase(port, q21);
1385 rte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);
1386 rte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);
1388 /* Run the pipeline */
1389 for (i = 6; i < (n_pkts & (~1)); i += 2) {
1390 /* Propagate stage inputs */
1401 q30_base = q20_base;
1402 q31_base = q21_base;
1404 /* Stage 0: Get packets in */
1406 pkt01 = pkts[i + 1];
1407 rte_prefetch0(pkt00);
1408 rte_prefetch0(pkt01);
1410 /* Stage 1: Prefetch queue structure storing queue pointers */
1411 q10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);
1412 q11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);
1414 /* Stage 2: Prefetch queue write location */
1415 q20_base = rte_sched_port_qbase(port, q20);
1416 q21_base = rte_sched_port_qbase(port, q21);
1417 rte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);
1418 rte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);
1420 /* Stage 3: Write packet to queue and activate queue */
1421 r30 = rte_sched_port_enqueue_qwa(port, q30, q30_base, pkt30);
1422 r31 = rte_sched_port_enqueue_qwa(port, q31, q31_base, pkt31);
1423 result += r30 + r31;
1426 /* Drain the pipeline (exactly 6 packets). Handle the last packet in the case
1427 of an odd number of input packets. */
1428 pkt_last = pkts[n_pkts - 1];
1429 rte_prefetch0(pkt_last);
1431 q00 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt00);
1432 q01 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt01);
1434 q10_base = rte_sched_port_qbase(port, q10);
1435 q11_base = rte_sched_port_qbase(port, q11);
1436 rte_sched_port_enqueue_qwa_prefetch0(port, q10, q10_base);
1437 rte_sched_port_enqueue_qwa_prefetch0(port, q11, q11_base);
1439 r20 = rte_sched_port_enqueue_qwa(port, q20, q20_base, pkt20);
1440 r21 = rte_sched_port_enqueue_qwa(port, q21, q21_base, pkt21);
1441 result += r20 + r21;
1443 q_last = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt_last);
1445 q00_base = rte_sched_port_qbase(port, q00);
1446 q01_base = rte_sched_port_qbase(port, q01);
1447 rte_sched_port_enqueue_qwa_prefetch0(port, q00, q00_base);
1448 rte_sched_port_enqueue_qwa_prefetch0(port, q01, q01_base);
1450 r10 = rte_sched_port_enqueue_qwa(port, q10, q10_base, pkt10);
1451 r11 = rte_sched_port_enqueue_qwa(port, q11, q11_base, pkt11);
1452 result += r10 + r11;
1454 q_last_base = rte_sched_port_qbase(port, q_last);
1455 rte_sched_port_enqueue_qwa_prefetch0(port, q_last, q_last_base);
1457 r00 = rte_sched_port_enqueue_qwa(port, q00, q00_base, pkt00);
1458 r01 = rte_sched_port_enqueue_qwa(port, q01, q01_base, pkt01);
1459 result += r00 + r01;
1462 r_last = rte_sched_port_enqueue_qwa(port, q_last, q_last_base, pkt_last);
1469 #endif /* RTE_SCHED_ENQUEUE */
1471 #if !defined(RTE_SCHED_SUBPORT_TC_OV)
1474 grinder_credits_update(struct rte_sched_port *port, uint32_t pos)
1476 struct rte_sched_grinder *grinder = port->grinder + pos;
1477 struct rte_sched_subport *subport = grinder->subport;
1478 struct rte_sched_pipe *pipe = grinder->pipe;
1479 struct rte_sched_pipe_profile *params = grinder->pipe_params;
1483 n_periods = (port->time - subport->tb_time) / subport->tb_period;
1484 subport->tb_credits += n_periods * subport->tb_credits_per_period;
1485 subport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);
1486 subport->tb_time += n_periods * subport->tb_period;
1489 n_periods = (port->time - pipe->tb_time) / params->tb_period;
1490 pipe->tb_credits += n_periods * params->tb_credits_per_period;
1491 pipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);
1492 pipe->tb_time += n_periods * params->tb_period;
1495 if (unlikely(port->time >= subport->tc_time)) {
1496 subport->tc_credits[0] = subport->tc_credits_per_period[0];
1497 subport->tc_credits[1] = subport->tc_credits_per_period[1];
1498 subport->tc_credits[2] = subport->tc_credits_per_period[2];
1499 subport->tc_credits[3] = subport->tc_credits_per_period[3];
1500 subport->tc_time = port->time + subport->tc_period;
1504 if (unlikely(port->time >= pipe->tc_time)) {
1505 pipe->tc_credits[0] = params->tc_credits_per_period[0];
1506 pipe->tc_credits[1] = params->tc_credits_per_period[1];
1507 pipe->tc_credits[2] = params->tc_credits_per_period[2];
1508 pipe->tc_credits[3] = params->tc_credits_per_period[3];
1509 pipe->tc_time = port->time + params->tc_period;
1515 static inline uint32_t
1516 grinder_tc_ov_credits_update(struct rte_sched_port *port, uint32_t pos)
1518 struct rte_sched_grinder *grinder = port->grinder + pos;
1519 struct rte_sched_subport *subport = grinder->subport;
1520 uint32_t tc_ov_consumption[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
1521 uint32_t tc_ov_consumption_max;
1522 uint32_t tc_ov_wm = subport->tc_ov_wm;
1524 if (subport->tc_ov == 0) {
1525 return subport->tc_ov_wm_max;
1528 tc_ov_consumption[0] = subport->tc_credits_per_period[0] - subport->tc_credits[0];
1529 tc_ov_consumption[1] = subport->tc_credits_per_period[1] - subport->tc_credits[1];
1530 tc_ov_consumption[2] = subport->tc_credits_per_period[2] - subport->tc_credits[2];
1531 tc_ov_consumption[3] = subport->tc_credits_per_period[3] - subport->tc_credits[3];
1533 tc_ov_consumption_max = subport->tc_credits_per_period[3] -
1534 (tc_ov_consumption[0] + tc_ov_consumption[1] + tc_ov_consumption[2]);
1536 if (tc_ov_consumption[3] > (tc_ov_consumption_max - port->mtu)) {
1537 tc_ov_wm -= tc_ov_wm >> 7;
1538 if (tc_ov_wm < subport->tc_ov_wm_min) {
1539 tc_ov_wm = subport->tc_ov_wm_min;
1544 tc_ov_wm += (tc_ov_wm >> 7) + 1;
1545 if (tc_ov_wm > subport->tc_ov_wm_max) {
1546 tc_ov_wm = subport->tc_ov_wm_max;
1552 grinder_credits_update(struct rte_sched_port *port, uint32_t pos)
1554 struct rte_sched_grinder *grinder = port->grinder + pos;
1555 struct rte_sched_subport *subport = grinder->subport;
1556 struct rte_sched_pipe *pipe = grinder->pipe;
1557 struct rte_sched_pipe_profile *params = grinder->pipe_params;
1561 n_periods = (port->time - subport->tb_time) / subport->tb_period;
1562 subport->tb_credits += n_periods * subport->tb_credits_per_period;
1563 subport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);
1564 subport->tb_time += n_periods * subport->tb_period;
1567 n_periods = (port->time - pipe->tb_time) / params->tb_period;
1568 pipe->tb_credits += n_periods * params->tb_credits_per_period;
1569 pipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);
1570 pipe->tb_time += n_periods * params->tb_period;
1573 if (unlikely(port->time >= subport->tc_time)) {
1574 subport->tc_ov_wm = grinder_tc_ov_credits_update(port, pos);
1576 subport->tc_credits[0] = subport->tc_credits_per_period[0];
1577 subport->tc_credits[1] = subport->tc_credits_per_period[1];
1578 subport->tc_credits[2] = subport->tc_credits_per_period[2];
1579 subport->tc_credits[3] = subport->tc_credits_per_period[3];
1581 subport->tc_time = port->time + subport->tc_period;
1582 subport->tc_ov_period_id ++;
1586 if (unlikely(port->time >= pipe->tc_time)) {
1587 pipe->tc_credits[0] = params->tc_credits_per_period[0];
1588 pipe->tc_credits[1] = params->tc_credits_per_period[1];
1589 pipe->tc_credits[2] = params->tc_credits_per_period[2];
1590 pipe->tc_credits[3] = params->tc_credits_per_period[3];
1591 pipe->tc_time = port->time + params->tc_period;
1594 /* Pipe TCs - Oversubscription */
1595 if (unlikely(pipe->tc_ov_period_id != subport->tc_ov_period_id)) {
1596 pipe->tc_ov_credits = subport->tc_ov_wm * params->tc_ov_weight;
1598 pipe->tc_ov_period_id = subport->tc_ov_period_id;
1602 #endif /* RTE_SCHED_TS_CREDITS_UPDATE, RTE_SCHED_SUBPORT_TC_OV */
1605 #ifndef RTE_SCHED_SUBPORT_TC_OV
1608 grinder_credits_check(struct rte_sched_port *port, uint32_t pos)
1610 struct rte_sched_grinder *grinder = port->grinder + pos;
1611 struct rte_sched_subport *subport = grinder->subport;
1612 struct rte_sched_pipe *pipe = grinder->pipe;
1613 struct rte_mbuf *pkt = grinder->pkt;
1614 uint32_t tc_index = grinder->tc_index;
1615 uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1616 uint32_t subport_tb_credits = subport->tb_credits;
1617 uint32_t subport_tc_credits = subport->tc_credits[tc_index];
1618 uint32_t pipe_tb_credits = pipe->tb_credits;
1619 uint32_t pipe_tc_credits = pipe->tc_credits[tc_index];
1622 /* Check queue credits */
1623 enough_credits = (pkt_len <= subport_tb_credits) &&
1624 (pkt_len <= subport_tc_credits) &&
1625 (pkt_len <= pipe_tb_credits) &&
1626 (pkt_len <= pipe_tc_credits);
1628 if (!enough_credits) {
1632 /* Update port credits */
1633 subport->tb_credits -= pkt_len;
1634 subport->tc_credits[tc_index] -= pkt_len;
1635 pipe->tb_credits -= pkt_len;
1636 pipe->tc_credits[tc_index] -= pkt_len;
1644 grinder_credits_check(struct rte_sched_port *port, uint32_t pos)
1646 struct rte_sched_grinder *grinder = port->grinder + pos;
1647 struct rte_sched_subport *subport = grinder->subport;
1648 struct rte_sched_pipe *pipe = grinder->pipe;
1649 struct rte_mbuf *pkt = grinder->pkt;
1650 uint32_t tc_index = grinder->tc_index;
1651 uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1652 uint32_t subport_tb_credits = subport->tb_credits;
1653 uint32_t subport_tc_credits = subport->tc_credits[tc_index];
1654 uint32_t pipe_tb_credits = pipe->tb_credits;
1655 uint32_t pipe_tc_credits = pipe->tc_credits[tc_index];
1656 uint32_t pipe_tc_ov_mask1[] = {UINT32_MAX, UINT32_MAX, UINT32_MAX, pipe->tc_ov_credits};
1657 uint32_t pipe_tc_ov_mask2[] = {0, 0, 0, UINT32_MAX};
1658 uint32_t pipe_tc_ov_credits = pipe_tc_ov_mask1[tc_index];
1661 /* Check pipe and subport credits */
1662 enough_credits = (pkt_len <= subport_tb_credits) &&
1663 (pkt_len <= subport_tc_credits) &&
1664 (pkt_len <= pipe_tb_credits) &&
1665 (pkt_len <= pipe_tc_credits) &&
1666 (pkt_len <= pipe_tc_ov_credits);
1668 if (!enough_credits) {
1672 /* Update pipe and subport credits */
1673 subport->tb_credits -= pkt_len;
1674 subport->tc_credits[tc_index] -= pkt_len;
1675 pipe->tb_credits -= pkt_len;
1676 pipe->tc_credits[tc_index] -= pkt_len;
1677 pipe->tc_ov_credits -= pipe_tc_ov_mask2[tc_index] & pkt_len;
1682 #endif /* RTE_SCHED_SUBPORT_TC_OV */
1686 grinder_schedule(struct rte_sched_port *port, uint32_t pos)
1688 struct rte_sched_grinder *grinder = port->grinder + pos;
1689 struct rte_sched_queue *queue = grinder->queue[grinder->qpos];
1690 struct rte_mbuf *pkt = grinder->pkt;
1691 uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1693 if (!grinder_credits_check(port, pos)) {
1697 /* Advance port time */
1698 port->time += pkt_len;
1701 port->pkts_out[port->n_pkts_out ++] = pkt;
1703 grinder->wrr_tokens[grinder->qpos] += pkt_len * grinder->wrr_cost[grinder->qpos];
1704 if (queue->qr == queue->qw) {
1705 uint32_t qindex = grinder->qindex[grinder->qpos];
1707 rte_bitmap_clear(port->bmp, qindex);
1708 grinder->qmask &= ~(1 << grinder->qpos);
1709 grinder->wrr_mask[grinder->qpos] = 0;
1710 rte_sched_port_set_queue_empty_timestamp(port, qindex);
1713 /* Reset pipe loop detection */
1714 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
1715 grinder->productive = 1;
1720 #if RTE_SCHED_OPTIMIZATIONS
1723 grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)
1725 __m128i index = _mm_set1_epi32 (base_pipe);
1726 __m128i pipes = _mm_load_si128((__m128i *)port->grinder_base_bmp_pos);
1727 __m128i res = _mm_cmpeq_epi32(pipes, index);
1728 pipes = _mm_load_si128((__m128i *)(port->grinder_base_bmp_pos + 4));
1729 pipes = _mm_cmpeq_epi32(pipes, index);
1730 res = _mm_or_si128(res, pipes);
1732 if (_mm_testz_si128(res, res))
1741 grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)
1745 for (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i ++) {
1746 if (port->grinder_base_bmp_pos[i] == base_pipe) {
1754 #endif /* RTE_SCHED_OPTIMIZATIONS */
1757 grinder_pcache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t bmp_pos, uint64_t bmp_slab)
1759 struct rte_sched_grinder *grinder = port->grinder + pos;
1762 grinder->pcache_w = 0;
1763 grinder->pcache_r = 0;
1765 w[0] = (uint16_t) bmp_slab;
1766 w[1] = (uint16_t) (bmp_slab >> 16);
1767 w[2] = (uint16_t) (bmp_slab >> 32);
1768 w[3] = (uint16_t) (bmp_slab >> 48);
1770 grinder->pcache_qmask[grinder->pcache_w] = w[0];
1771 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos;
1772 grinder->pcache_w += (w[0] != 0);
1774 grinder->pcache_qmask[grinder->pcache_w] = w[1];
1775 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 16;
1776 grinder->pcache_w += (w[1] != 0);
1778 grinder->pcache_qmask[grinder->pcache_w] = w[2];
1779 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 32;
1780 grinder->pcache_w += (w[2] != 0);
1782 grinder->pcache_qmask[grinder->pcache_w] = w[3];
1783 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 48;
1784 grinder->pcache_w += (w[3] != 0);
1788 grinder_tccache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t qindex, uint16_t qmask)
1790 struct rte_sched_grinder *grinder = port->grinder + pos;
1793 grinder->tccache_w = 0;
1794 grinder->tccache_r = 0;
1796 b[0] = (uint8_t) (qmask & 0xF);
1797 b[1] = (uint8_t) ((qmask >> 4) & 0xF);
1798 b[2] = (uint8_t) ((qmask >> 8) & 0xF);
1799 b[3] = (uint8_t) ((qmask >> 12) & 0xF);
1801 grinder->tccache_qmask[grinder->tccache_w] = b[0];
1802 grinder->tccache_qindex[grinder->tccache_w] = qindex;
1803 grinder->tccache_w += (b[0] != 0);
1805 grinder->tccache_qmask[grinder->tccache_w] = b[1];
1806 grinder->tccache_qindex[grinder->tccache_w] = qindex + 4;
1807 grinder->tccache_w += (b[1] != 0);
1809 grinder->tccache_qmask[grinder->tccache_w] = b[2];
1810 grinder->tccache_qindex[grinder->tccache_w] = qindex + 8;
1811 grinder->tccache_w += (b[2] != 0);
1813 grinder->tccache_qmask[grinder->tccache_w] = b[3];
1814 grinder->tccache_qindex[grinder->tccache_w] = qindex + 12;
1815 grinder->tccache_w += (b[3] != 0);
1819 grinder_next_tc(struct rte_sched_port *port, uint32_t pos)
1821 struct rte_sched_grinder *grinder = port->grinder + pos;
1822 struct rte_mbuf **qbase;
1826 if (grinder->tccache_r == grinder->tccache_w) {
1830 qindex = grinder->tccache_qindex[grinder->tccache_r];
1831 qbase = rte_sched_port_qbase(port, qindex);
1832 qsize = rte_sched_port_qsize(port, qindex);
1834 grinder->tc_index = (qindex >> 2) & 0x3;
1835 grinder->qmask = grinder->tccache_qmask[grinder->tccache_r];
1836 grinder->qsize = qsize;
1838 grinder->qindex[0] = qindex;
1839 grinder->qindex[1] = qindex + 1;
1840 grinder->qindex[2] = qindex + 2;
1841 grinder->qindex[3] = qindex + 3;
1843 grinder->queue[0] = port->queue + qindex;
1844 grinder->queue[1] = port->queue + qindex + 1;
1845 grinder->queue[2] = port->queue + qindex + 2;
1846 grinder->queue[3] = port->queue + qindex + 3;
1848 grinder->qbase[0] = qbase;
1849 grinder->qbase[1] = qbase + qsize;
1850 grinder->qbase[2] = qbase + 2 * qsize;
1851 grinder->qbase[3] = qbase + 3 * qsize;
1853 grinder->tccache_r ++;
1858 grinder_next_pipe(struct rte_sched_port *port, uint32_t pos)
1860 struct rte_sched_grinder *grinder = port->grinder + pos;
1861 uint32_t pipe_qindex;
1862 uint16_t pipe_qmask;
1864 if (grinder->pcache_r < grinder->pcache_w) {
1865 pipe_qmask = grinder->pcache_qmask[grinder->pcache_r];
1866 pipe_qindex = grinder->pcache_qindex[grinder->pcache_r];
1867 grinder->pcache_r ++;
1869 uint64_t bmp_slab = 0;
1870 uint32_t bmp_pos = 0;
1872 /* Get another non-empty pipe group */
1873 if (unlikely(rte_bitmap_scan(port->bmp, &bmp_pos, &bmp_slab) <= 0)) {
1877 #ifdef RTE_SCHED_DEBUG
1878 debug_check_queue_slab(port, bmp_pos, bmp_slab);
1881 /* Return if pipe group already in one of the other grinders */
1882 port->grinder_base_bmp_pos[pos] = RTE_SCHED_BMP_POS_INVALID;
1883 if (unlikely(grinder_pipe_exists(port, bmp_pos))) {
1886 port->grinder_base_bmp_pos[pos] = bmp_pos;
1888 /* Install new pipe group into grinder's pipe cache */
1889 grinder_pcache_populate(port, pos, bmp_pos, bmp_slab);
1891 pipe_qmask = grinder->pcache_qmask[0];
1892 pipe_qindex = grinder->pcache_qindex[0];
1893 grinder->pcache_r = 1;
1896 /* Install new pipe in the grinder */
1897 grinder->pindex = pipe_qindex >> 4;
1898 grinder->subport = port->subport + (grinder->pindex / port->n_pipes_per_subport);
1899 grinder->pipe = port->pipe + grinder->pindex;
1900 grinder->pipe_params = NULL; /* to be set after the pipe structure is prefetched */
1901 grinder->productive = 0;
1903 grinder_tccache_populate(port, pos, pipe_qindex, pipe_qmask);
1904 grinder_next_tc(port, pos);
1906 /* Check for pipe exhaustion */
1907 if (grinder->pindex == port->pipe_loop) {
1908 port->pipe_exhaustion = 1;
1909 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
1915 #if RTE_SCHED_WRR == 0
1917 #define grinder_wrr_load(a,b)
1919 #define grinder_wrr_store(a,b)
1922 grinder_wrr(struct rte_sched_port *port, uint32_t pos)
1924 struct rte_sched_grinder *grinder = port->grinder + pos;
1925 uint64_t slab = grinder->qmask;
1927 if (rte_bsf64(slab, &grinder->qpos) == 0) {
1928 rte_panic("grinder wrr\n");
1932 #elif RTE_SCHED_WRR == 1
1935 grinder_wrr_load(struct rte_sched_port *port, uint32_t pos)
1937 struct rte_sched_grinder *grinder = port->grinder + pos;
1938 struct rte_sched_pipe *pipe = grinder->pipe;
1939 struct rte_sched_pipe_profile *pipe_params = grinder->pipe_params;
1940 uint32_t tc_index = grinder->tc_index;
1941 uint32_t qmask = grinder->qmask;
1944 qindex = tc_index * 4;
1946 grinder->wrr_tokens[0] = ((uint16_t) pipe->wrr_tokens[qindex]) << RTE_SCHED_WRR_SHIFT;
1947 grinder->wrr_tokens[1] = ((uint16_t) pipe->wrr_tokens[qindex + 1]) << RTE_SCHED_WRR_SHIFT;
1948 grinder->wrr_tokens[2] = ((uint16_t) pipe->wrr_tokens[qindex + 2]) << RTE_SCHED_WRR_SHIFT;
1949 grinder->wrr_tokens[3] = ((uint16_t) pipe->wrr_tokens[qindex + 3]) << RTE_SCHED_WRR_SHIFT;
1951 grinder->wrr_mask[0] = (qmask & 0x1) * 0xFFFF;
1952 grinder->wrr_mask[1] = ((qmask >> 1) & 0x1) * 0xFFFF;
1953 grinder->wrr_mask[2] = ((qmask >> 2) & 0x1) * 0xFFFF;
1954 grinder->wrr_mask[3] = ((qmask >> 3) & 0x1) * 0xFFFF;
1956 grinder->wrr_cost[0] = pipe_params->wrr_cost[qindex];
1957 grinder->wrr_cost[1] = pipe_params->wrr_cost[qindex + 1];
1958 grinder->wrr_cost[2] = pipe_params->wrr_cost[qindex + 2];
1959 grinder->wrr_cost[3] = pipe_params->wrr_cost[qindex + 3];
1963 grinder_wrr_store(struct rte_sched_port *port, uint32_t pos)
1965 struct rte_sched_grinder *grinder = port->grinder + pos;
1966 struct rte_sched_pipe *pipe = grinder->pipe;
1967 uint32_t tc_index = grinder->tc_index;
1970 qindex = tc_index * 4;
1972 pipe->wrr_tokens[qindex] = (uint8_t) ((grinder->wrr_tokens[0] & grinder->wrr_mask[0]) >> RTE_SCHED_WRR_SHIFT);
1973 pipe->wrr_tokens[qindex + 1] = (uint8_t) ((grinder->wrr_tokens[1] & grinder->wrr_mask[1]) >> RTE_SCHED_WRR_SHIFT);
1974 pipe->wrr_tokens[qindex + 2] = (uint8_t) ((grinder->wrr_tokens[2] & grinder->wrr_mask[2]) >> RTE_SCHED_WRR_SHIFT);
1975 pipe->wrr_tokens[qindex + 3] = (uint8_t) ((grinder->wrr_tokens[3] & grinder->wrr_mask[3]) >> RTE_SCHED_WRR_SHIFT);
1979 grinder_wrr(struct rte_sched_port *port, uint32_t pos)
1981 struct rte_sched_grinder *grinder = port->grinder + pos;
1982 uint16_t wrr_tokens_min;
1984 grinder->wrr_tokens[0] |= ~grinder->wrr_mask[0];
1985 grinder->wrr_tokens[1] |= ~grinder->wrr_mask[1];
1986 grinder->wrr_tokens[2] |= ~grinder->wrr_mask[2];
1987 grinder->wrr_tokens[3] |= ~grinder->wrr_mask[3];
1989 grinder->qpos = rte_min_pos_4_u16(grinder->wrr_tokens);
1990 wrr_tokens_min = grinder->wrr_tokens[grinder->qpos];
1992 grinder->wrr_tokens[0] -= wrr_tokens_min;
1993 grinder->wrr_tokens[1] -= wrr_tokens_min;
1994 grinder->wrr_tokens[2] -= wrr_tokens_min;
1995 grinder->wrr_tokens[3] -= wrr_tokens_min;
2000 #error Invalid value for RTE_SCHED_WRR
2002 #endif /* RTE_SCHED_WRR */
2004 #define grinder_evict(port, pos)
2007 grinder_prefetch_pipe(struct rte_sched_port *port, uint32_t pos)
2009 struct rte_sched_grinder *grinder = port->grinder + pos;
2011 rte_prefetch0(grinder->pipe);
2012 rte_prefetch0(grinder->queue[0]);
2016 grinder_prefetch_tc_queue_arrays(struct rte_sched_port *port, uint32_t pos)
2018 struct rte_sched_grinder *grinder = port->grinder + pos;
2019 uint16_t qsize, qr[4];
2021 qsize = grinder->qsize;
2022 qr[0] = grinder->queue[0]->qr & (qsize - 1);
2023 qr[1] = grinder->queue[1]->qr & (qsize - 1);
2024 qr[2] = grinder->queue[2]->qr & (qsize - 1);
2025 qr[3] = grinder->queue[3]->qr & (qsize - 1);
2027 rte_prefetch0(grinder->qbase[0] + qr[0]);
2028 rte_prefetch0(grinder->qbase[1] + qr[1]);
2030 grinder_wrr_load(port, pos);
2031 grinder_wrr(port, pos);
2033 rte_prefetch0(grinder->qbase[2] + qr[2]);
2034 rte_prefetch0(grinder->qbase[3] + qr[3]);
2038 grinder_prefetch_mbuf(struct rte_sched_port *port, uint32_t pos)
2040 struct rte_sched_grinder *grinder = port->grinder + pos;
2041 uint32_t qpos = grinder->qpos;
2042 struct rte_mbuf **qbase = grinder->qbase[qpos];
2043 uint16_t qsize = grinder->qsize;
2044 uint16_t qr = grinder->queue[qpos]->qr & (qsize - 1);
2046 grinder->pkt = qbase[qr];
2047 rte_prefetch0(grinder->pkt);
2049 if (unlikely((qr & 0x7) == 7)) {
2050 uint16_t qr_next = (grinder->queue[qpos]->qr + 1) & (qsize - 1);
2052 rte_prefetch0(qbase + qr_next);
2056 static inline uint32_t
2057 grinder_handle(struct rte_sched_port *port, uint32_t pos)
2059 struct rte_sched_grinder *grinder = port->grinder + pos;
2061 switch (grinder->state) {
2062 case e_GRINDER_PREFETCH_PIPE:
2064 if (grinder_next_pipe(port, pos)) {
2065 grinder_prefetch_pipe(port, pos);
2066 port->busy_grinders ++;
2068 grinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;
2075 case e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS:
2077 struct rte_sched_pipe *pipe = grinder->pipe;
2079 grinder->pipe_params = port->pipe_profiles + pipe->profile;
2080 grinder_prefetch_tc_queue_arrays(port, pos);
2081 grinder_credits_update(port, pos);
2083 grinder->state = e_GRINDER_PREFETCH_MBUF;
2087 case e_GRINDER_PREFETCH_MBUF:
2089 grinder_prefetch_mbuf(port, pos);
2091 grinder->state = e_GRINDER_READ_MBUF;
2095 case e_GRINDER_READ_MBUF:
2097 uint32_t result = 0;
2099 result = grinder_schedule(port, pos);
2101 /* Look for next packet within the same TC */
2102 if (result && grinder->qmask) {
2103 grinder_wrr(port, pos);
2104 grinder_prefetch_mbuf(port, pos);
2108 grinder_wrr_store(port, pos);
2110 /* Look for another active TC within same pipe */
2111 if (grinder_next_tc(port, pos)) {
2112 grinder_prefetch_tc_queue_arrays(port, pos);
2114 grinder->state = e_GRINDER_PREFETCH_MBUF;
2117 if ((grinder->productive == 0) && (port->pipe_loop == RTE_SCHED_PIPE_INVALID)) {
2118 port->pipe_loop = grinder->pindex;
2120 grinder_evict(port, pos);
2122 /* Look for another active pipe */
2123 if (grinder_next_pipe(port, pos)) {
2124 grinder_prefetch_pipe(port, pos);
2126 grinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;
2130 /* No active pipe found */
2131 port->busy_grinders --;
2133 grinder->state = e_GRINDER_PREFETCH_PIPE;
2138 rte_panic("Algorithmic error (invalid state)\n");
2144 rte_sched_port_time_resync(struct rte_sched_port *port)
2146 uint64_t cycles = rte_get_tsc_cycles();
2147 uint64_t cycles_diff = cycles - port->time_cpu_cycles;
2148 double bytes_diff = ((double) cycles_diff) / port->cycles_per_byte;
2150 /* Advance port time */
2151 port->time_cpu_cycles = cycles;
2152 port->time_cpu_bytes += (uint64_t) bytes_diff;
2153 if (port->time < port->time_cpu_bytes) {
2154 port->time = port->time_cpu_bytes;
2157 /* Reset pipe loop detection */
2158 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
2162 rte_sched_port_exceptions(struct rte_sched_port *port, int second_pass)
2166 /* Check if any exception flag is set */
2167 exceptions = (second_pass && port->busy_grinders == 0) ||
2168 (port->pipe_exhaustion == 1);
2170 /* Clear exception flags */
2171 port->pipe_exhaustion = 0;
2177 rte_sched_port_dequeue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
2181 port->pkts_out = pkts;
2182 port->n_pkts_out = 0;
2184 rte_sched_port_time_resync(port);
2186 /* Take each queue in the grinder one step further */
2187 for (i = 0, count = 0; ; i ++) {
2188 count += grinder_handle(port, i & (RTE_SCHED_PORT_N_GRINDERS - 1));
2189 if ((count == n_pkts) ||
2190 rte_sched_port_exceptions(port, i >= RTE_SCHED_PORT_N_GRINDERS)) {