net/qede/base: add support for 2x10G mode
authorRasesh Mody <rasesh.mody@cavium.com>
Thu, 5 Jan 2017 07:04:01 +0000 (23:04 -0800)
committerFerruh Yigit <ferruh.yigit@intel.com>
Tue, 17 Jan 2017 18:40:53 +0000 (19:40 +0100)
Add support for 2x10G mode

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
doc/guides/nics/qede.rst
drivers/net/qede/base/ecore.h
drivers/net/qede/base/ecore_dev.c
drivers/net/qede/base/nvm_cfg.h

index e033980..c410edc 100644 (file)
@@ -32,7 +32,7 @@ QEDE Poll Mode Driver
 ======================
 
 The QEDE poll mode driver library (**librte_pmd_qede**) implements support
-for **QLogic FastLinQ QL4xxxx 25G/40G/100G CNA** family of adapters as well
+for **QLogic FastLinQ QL4xxxx 10G/25G/40G/100G CNA** family of adapters as well
 as their virtual functions (VF) in SR-IOV context. It is supported on
 several standard Linux distros like RHEL7.x, SLES12.x and Ubuntu.
 It is compile-tested under FreeBSD OS.
index 71ce24b..034e885 100644 (file)
@@ -302,6 +302,7 @@ enum ecore_port_mode {
        ECORE_PORT_MODE_DE_2X25G,
        ECORE_PORT_MODE_DE_1X25G,
        ECORE_PORT_MODE_DE_4X25G,
+       ECORE_PORT_MODE_DE_2X10G,
 };
 
 enum ecore_dev_cap {
index 86b4bff..5a29c45 100644 (file)
@@ -2474,6 +2474,9 @@ static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
        case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
                p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
                break;
+       case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
+               p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
+               break;
        case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
                p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
                break;
index 8e9c08a..4edffac 100644 (file)
@@ -144,6 +144,7 @@ struct nvm_cfg1_glob {
                #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC
                #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD
                #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE
+               #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF
                #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_MASK 0x00000100
                #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_OFFSET 8
                #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_DISABLED 0x0
@@ -578,6 +579,7 @@ struct nvm_cfg1_glob {
                #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X50G 0x40
                #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_BB_1X100G \
                        0x80
+               #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X10G 0x100
        u32 reserved[41]; /* 0x9C */
 };