net/cxgbe: rework and use 32-bit port capability
authorRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Wed, 28 Feb 2018 18:04:52 +0000 (23:34 +0530)
committerFerruh Yigit <ferruh.yigit@intel.com>
Fri, 30 Mar 2018 12:08:43 +0000 (14:08 +0200)
The new code uses the new 32-bit Port Capabilities exclusively and
only translates to/from the old 16-bit Port Capabilities at the last
point possible when talking to older Firmware.

For the old versus new Firmware issue, we use the new FW_PARAMS_CMD[PFVF,
CAPS32] command to tell the Firmware that we want Asynchronous Port Status
updates to use the new 32-bit version of the Port Information message.  If
we get an error, we know we're dealing with older Firmware, and if not,
we'll start getting th new 32-bit Port Capability message formats.

Also, refactor t4_handle_fw_rpl() to handle new 32-bit Port Capability
replies from firmware in t4_handle_get_port_info().

Original work by Surendra Mobiya <surendra@chelsio.com>

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
doc/guides/nics/cxgbe.rst
drivers/net/cxgbe/base/common.h
drivers/net/cxgbe/base/t4_hw.c
drivers/net/cxgbe/base/t4fw_interface.h

index 6126167..c4afe86 100644 (file)
@@ -82,7 +82,7 @@ Supported Chelsio T6 NICs
 Prerequisites
 -------------
 
-- Requires firmware version **1.16.43.0** and higher. Visit
+- Requires firmware version **1.17.14.0** and higher. Visit
   `Chelsio Download Center <http://service.chelsio.com>`_ to get latest firmware
   bundled with the latest Chelsio Unified Wire package.
 
@@ -210,7 +210,7 @@ Unified Wire package for Linux operating system are as follows:
 
    .. code-block:: console
 
-      firmware-version: 1.16.43.0, TP 0.1.4.9
+      firmware-version: 1.17.14.0, TP 0.1.4.9
 
 Running testpmd
 ~~~~~~~~~~~~~~~
@@ -268,7 +268,7 @@ devices managed by librte_pmd_cxgbe in Linux operating system.
       EAL:   PCI memory mapped at 0x7fd7c0200000
       EAL:   PCI memory mapped at 0x7fd77cdfd000
       EAL:   PCI memory mapped at 0x7fd7c10b7000
-      PMD: rte_cxgbe_pmd: fw: 1.16.43.0, TP: 0.1.4.9
+      PMD: rte_cxgbe_pmd: fw: 1.17.14.0, TP: 0.1.4.9
       PMD: rte_cxgbe_pmd: Coming up as MASTER: Initializing adapter
       Interactive-mode selected
       Configuring Port 0 (socket 0)
@@ -352,7 +352,7 @@ Unified Wire package for FreeBSD operating system are as follows:
 
    .. code-block:: console
 
-      dev.t5nex.0.firmware_version: 1.16.43.0
+      dev.t5nex.0.firmware_version: 1.17.14.0
 
 Running testpmd
 ~~~~~~~~~~~~~~~
@@ -470,7 +470,7 @@ devices managed by librte_pmd_cxgbe in FreeBSD operating system.
       EAL:   PCI memory mapped at 0x8007ec000
       EAL:   PCI memory mapped at 0x842800000
       EAL:   PCI memory mapped at 0x80086c000
-      PMD: rte_cxgbe_pmd: fw: 1.16.43.0, TP: 0.1.4.9
+      PMD: rte_cxgbe_pmd: fw: 1.17.14.0, TP: 0.1.4.9
       PMD: rte_cxgbe_pmd: Coming up as MASTER: Initializing adapter
       Interactive-mode selected
       Configuring Port 0 (socket 0)
index 9888628..365e9e6 100644 (file)
@@ -239,6 +239,7 @@ struct adapter_params {
        struct arch_specific_params arch; /* chip specific params */
 
        bool ulptx_memwrite_dsgl;          /* use of T5 DSGL allowed */
+       u8 fw_caps_support;               /* 32-bit Port Capabilities */
 };
 
 /* Firmware Port Capabilities types.
@@ -246,6 +247,12 @@ struct adapter_params {
 typedef u16 fw_port_cap16_t;    /* 16-bit Port Capabilities integral value */
 typedef u32 fw_port_cap32_t;    /* 32-bit Port Capabilities integral value */
 
+enum fw_caps {
+       FW_CAPS_UNKNOWN = 0,    /* 0'ed out initial state */
+       FW_CAPS16       = 1,    /* old Firmware: 16-bit Port Capabilities */
+       FW_CAPS32       = 2,    /* new Firmware: 32-bit Port Capabilities */
+};
+
 struct link_config {
        fw_port_cap32_t pcaps;          /* link capabilities */
        fw_port_cap32_t acaps;          /* advertised capabilities */
@@ -265,6 +272,7 @@ struct link_config {
        unsigned char autoneg;          /* autonegotiating? */
 
        unsigned char link_ok;          /* link up? */
+       unsigned char link_down_rc;     /* link down reason */
 };
 
 #include "adapter.h"
index 46b296a..c66e2a6 100644 (file)
@@ -2791,6 +2791,43 @@ void t4_dump_version_info(struct adapter *adapter)
 
 #define ADVERT_MASK (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) | \
                     FW_PORT_CAP32_ANEG)
+/**
+ *     fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
+ *     @caps16: a 16-bit Port Capabilities value
+ *
+ *     Returns the equivalent 32-bit Port Capabilities value.
+ */
+static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
+{
+       fw_port_cap32_t caps32 = 0;
+
+#define CAP16_TO_CAP32(__cap) \
+       do { \
+               if (caps16 & FW_PORT_CAP_##__cap) \
+                       caps32 |= FW_PORT_CAP32_##__cap; \
+       } while (0)
+
+       CAP16_TO_CAP32(SPEED_100M);
+       CAP16_TO_CAP32(SPEED_1G);
+       CAP16_TO_CAP32(SPEED_25G);
+       CAP16_TO_CAP32(SPEED_10G);
+       CAP16_TO_CAP32(SPEED_40G);
+       CAP16_TO_CAP32(SPEED_100G);
+       CAP16_TO_CAP32(FC_RX);
+       CAP16_TO_CAP32(FC_TX);
+       CAP16_TO_CAP32(ANEG);
+       CAP16_TO_CAP32(MDIX);
+       CAP16_TO_CAP32(MDIAUTO);
+       CAP16_TO_CAP32(FEC_RS);
+       CAP16_TO_CAP32(FEC_BASER_RS);
+       CAP16_TO_CAP32(802_3_PAUSE);
+       CAP16_TO_CAP32(802_3_ASM_DIR);
+
+#undef CAP16_TO_CAP32
+
+       return caps32;
+}
+
 /**
  *     fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
  *     @caps32: a 32-bit Port Capabilities value
@@ -2900,6 +2937,7 @@ int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
                  struct link_config *lc)
 {
        unsigned int fw_mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO);
+       unsigned int fw_caps = adap->params.fw_caps_support;
        fw_port_cap32_t fw_fc, cc_fec, fw_fec, rcap;
        struct fw_port_cmd cmd;
 
@@ -2941,9 +2979,15 @@ int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
                                       F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
                                       V_FW_PORT_CMD_PORTID(port));
        cmd.action_to_len16 =
-               cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
+               cpu_to_be32(V_FW_PORT_CMD_ACTION(fw_caps == FW_CAPS16 ?
+                                                FW_PORT_ACTION_L1_CFG :
+                                                FW_PORT_ACTION_L1_CFG32) |
                            FW_LEN16(cmd));
-       cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
+
+       if (fw_caps == FW_CAPS16)
+               cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
+       else
+               cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
 
        return t4_wr_mbox(adap, mbox, &cmd, sizeof(cmd), NULL);
 }
@@ -4278,6 +4322,31 @@ int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
        return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
 }
 
+/**
+ * t4_link_down_rc_str - return a string for a Link Down Reason Code
+ * @link_down_rc: Link Down Reason Code
+ *
+ * Returns a string representation of the Link Down Reason Code.
+ */
+static const char *t4_link_down_rc_str(unsigned char link_down_rc)
+{
+       static const char * const reason[] = {
+               "Link Down",
+               "Remote Fault",
+               "Auto-negotiation Failure",
+               "Reserved",
+               "Insufficient Airflow",
+               "Unable To Determine Reason",
+               "No RX Signal Detected",
+               "Reserved",
+       };
+
+       if (link_down_rc >= ARRAY_SIZE(reason))
+               return "Bad Reason Code";
+
+       return reason[link_down_rc];
+}
+
 /* Return the highest speed set in the port capabilities, in Mb/s. */
 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
 {
@@ -4300,6 +4369,122 @@ static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
        return 0;
 }
 
+/**
+ * t4_handle_get_port_info - process a FW reply message
+ * @pi: the port info
+ * @rpl: start of the FW message
+ *
+ * Processes a GET_PORT_INFO FW reply message.
+ */
+static void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
+{
+       const struct fw_port_cmd *cmd = (const void *)rpl;
+       int action = G_FW_PORT_CMD_ACTION(be32_to_cpu(cmd->action_to_len16));
+       fw_port_cap32_t pcaps, acaps, linkattr;
+       struct link_config *lc = &pi->link_cfg;
+       struct adapter *adapter = pi->adapter;
+       enum fw_port_module_type mod_type;
+       enum fw_port_type port_type;
+       unsigned int speed, fc, fec;
+       int link_ok, linkdnrc;
+
+       /* Extract the various fields from the Port Information message.
+        */
+       switch (action) {
+       case FW_PORT_ACTION_GET_PORT_INFO: {
+               u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
+
+               link_ok = (lstatus & F_FW_PORT_CMD_LSTATUS) != 0;
+               linkdnrc = G_FW_PORT_CMD_LINKDNRC(lstatus);
+               port_type = G_FW_PORT_CMD_PTYPE(lstatus);
+               mod_type = G_FW_PORT_CMD_MODTYPE(lstatus);
+               pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
+               acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
+
+               /* Unfortunately the format of the Link Status in the old
+                * 16-bit Port Information message isn't the same as the
+                * 16-bit Port Capabilities bitfield used everywhere else ...
+                */
+               linkattr = 0;
+               if (lstatus & F_FW_PORT_CMD_RXPAUSE)
+                       linkattr |= FW_PORT_CAP32_FC_RX;
+               if (lstatus & F_FW_PORT_CMD_TXPAUSE)
+                       linkattr |= FW_PORT_CAP32_FC_TX;
+               if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
+                       linkattr |= FW_PORT_CAP32_SPEED_100M;
+               if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
+                       linkattr |= FW_PORT_CAP32_SPEED_1G;
+               if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
+                       linkattr |= FW_PORT_CAP32_SPEED_10G;
+               if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
+                       linkattr |= FW_PORT_CAP32_SPEED_25G;
+               if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
+                       linkattr |= FW_PORT_CAP32_SPEED_40G;
+               if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
+                       linkattr |= FW_PORT_CAP32_SPEED_100G;
+
+               break;
+               }
+
+       case FW_PORT_ACTION_GET_PORT_INFO32: {
+               u32 lstatus32 =
+                       be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
+
+               link_ok = (lstatus32 & F_FW_PORT_CMD_LSTATUS32) != 0;
+               linkdnrc = G_FW_PORT_CMD_LINKDNRC32(lstatus32);
+               port_type = G_FW_PORT_CMD_PORTTYPE32(lstatus32);
+               mod_type = G_FW_PORT_CMD_MODTYPE32(lstatus32);
+               pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
+               acaps = be32_to_cpu(cmd->u.info32.acaps32);
+               linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
+               break;
+               }
+
+       default:
+               dev_warn(adapter, "Handle Port Information: Bad Command/Action %#x\n",
+                        be32_to_cpu(cmd->action_to_len16));
+               return;
+       }
+
+       fec = fwcap_to_cc_fec(acaps);
+
+       fc = fwcap_to_cc_pause(linkattr);
+       speed = fwcap_to_speed(linkattr);
+
+       if (mod_type != pi->mod_type) {
+               lc->auto_fec = fec;
+               pi->port_type = port_type;
+               pi->mod_type = mod_type;
+               t4_os_portmod_changed(adapter, pi->port_id);
+       }
+       if (link_ok != lc->link_ok || speed != lc->speed ||
+           fc != lc->fc || fec != lc->fec) { /* something changed */
+               if (!link_ok && lc->link_ok) {
+                       lc->link_down_rc = linkdnrc;
+                       dev_warn(adap, "Port %d link down, reason: %s\n",
+                                pi->tx_chan, t4_link_down_rc_str(linkdnrc));
+               }
+               lc->link_ok = link_ok;
+               lc->speed = speed;
+               lc->fc = fc;
+               lc->fec = fec;
+               lc->pcaps = pcaps;
+               lc->acaps = acaps & ADVERT_MASK;
+
+               if (lc->acaps & FW_PORT_CAP32_ANEG) {
+                       lc->autoneg = AUTONEG_ENABLE;
+               } else {
+                       /* When Autoneg is disabled, user needs to set
+                        * single speed.
+                        * Similar to cxgb4_ethtool.c: set_link_ksettings
+                        */
+                       lc->acaps = 0;
+                       lc->requested_speed = fwcap_to_speed(acaps);
+                       lc->autoneg = AUTONEG_DISABLE;
+               }
+       }
+}
+
 /**
  * t4_handle_fw_rpl - process a FW reply message
  * @adap: the adapter
@@ -4321,83 +4506,21 @@ int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
        unsigned int action =
                G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
 
-       if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
+       if (opcode == FW_PORT_CMD &&
+           (action == FW_PORT_ACTION_GET_PORT_INFO ||
+            action == FW_PORT_ACTION_GET_PORT_INFO32)) {
                /* link/module state change message */
-               unsigned int speed = 0, fc = 0, i;
                int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
                struct port_info *pi = NULL;
-               struct link_config *lc;
-               u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
-               int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
-               u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
-               unsigned int fec;
-
-               fc = fwcap_to_cc_pause(stat);
-               fec = fwcap_to_cc_fec(stat);
-
-               if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
-                       speed = ETH_SPEED_NUM_100M;
-               else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
-                       speed = ETH_SPEED_NUM_1G;
-               else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
-                       speed = ETH_SPEED_NUM_10G;
-               else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
-                       speed = ETH_SPEED_NUM_25G;
-               else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
-                       speed = ETH_SPEED_NUM_40G;
-               else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
-                       speed = ETH_SPEED_NUM_100G;
+               int i;
 
                for_each_port(adap, i) {
                        pi = adap2pinfo(adap, i);
                        if (pi->tx_chan == chan)
                                break;
                }
-               lc = &pi->link_cfg;
 
-               if (mod != pi->mod_type) {
-                       lc->auto_fec = fec;
-                       pi->mod_type = mod;
-                       t4_os_portmod_changed(adap, i);
-               }
-               if (link_ok != lc->link_ok || speed != lc->speed ||
-                   fc != lc->fc || fec != lc->fec) { /* something changed */
-                       if (!link_ok && lc->link_ok) {
-                               static const char * const reason[] = {
-                                       "Link Down",
-                                       "Remote Fault",
-                                       "Auto-negotiation Failure",
-                                       "Reserved",
-                                       "Insufficient Airflow",
-                                       "Unable To Determine Reason",
-                                       "No RX Signal Detected",
-                                       "Reserved",
-                               };
-                               unsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);
-
-                               dev_warn(adap, "Port %d link down, reason: %s\n",
-                                        chan, reason[rc]);
-                       }
-                       lc->link_ok = link_ok;
-                       lc->speed = speed;
-                       lc->fc = fc;
-                       lc->fec = fec;
-                       lc->pcaps = be16_to_cpu(p->u.info.pcap);
-                       lc->acaps = be16_to_cpu(p->u.info.acap) & ADVERT_MASK;
-                       if (lc->acaps & FW_PORT_CAP32_ANEG) {
-                               lc->autoneg = AUTONEG_ENABLE;
-                       } else {
-                               /* When Autoneg is disabled, user needs to set
-                                * single speed.
-                                */
-                               lc->acaps = 0;
-                               lc->requested_speed =
-                                       be16_to_cpu(p->u.info.acap);
-                               lc->requested_speed =
-                                       fwcap_to_speed(lc->requested_speed);
-                               lc->autoneg = AUTONEG_DISABLE;
-                       }
-               }
+               t4_handle_get_port_info(pi, rpl);
        } else {
                dev_warn(adap, "Unknown firmware reply %d\n", opcode);
                return -EINVAL;
@@ -4426,8 +4549,8 @@ void t4_reset_link_config(struct adapter *adap, int idx)
  * Initializes the SW state maintained for each link, including the link's
  * capabilities and default speed/flow-control/autonegotiation settings.
  */
-static void init_link_config(struct link_config *lc, unsigned int pcaps,
-                            unsigned int acaps)
+static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
+                            fw_port_cap32_t acaps)
 {
        lc->pcaps = pcaps;
        lc->requested_speed = 0;
@@ -4969,46 +5092,95 @@ int t4_init_rss_mode(struct adapter *adap, int mbox)
 
 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
 {
-       u8 addr[6];
+       unsigned int fw_caps = adap->params.fw_caps_support;
+       fw_port_cap32_t pcaps, acaps;
+       enum fw_port_type port_type;
+       struct fw_port_cmd cmd;
        int ret, i, j = 0;
-       struct fw_port_cmd c;
+       int mdio_addr;
+       u32 action;
+       u8 addr[6];
 
-       memset(&c, 0, sizeof(c));
+       memset(&cmd, 0, sizeof(cmd));
 
        for_each_port(adap, i) {
+               struct port_info *pi = adap2pinfo(adap, i);
                unsigned int rss_size = 0;
-               struct port_info *p = adap2pinfo(adap, i);
 
                while ((adap->params.portvec & (1 << j)) == 0)
                        j++;
 
-               c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
-                                            F_FW_CMD_REQUEST | F_FW_CMD_READ |
-                                            V_FW_PORT_CMD_PORTID(j));
-               c.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(
-                                               FW_PORT_ACTION_GET_PORT_INFO) |
-                                               FW_LEN16(c));
-               ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
+               /* If we haven't yet determined whether we're talking to
+                * Firmware which knows the new 32-bit Port Capabilities, it's
+                * time to find out now.  This will also tell new Firmware to
+                * send us Port Status Updates using the new 32-bit Port
+                * Capabilities version of the Port Information message.
+                */
+               if (fw_caps == FW_CAPS_UNKNOWN) {
+                       u32 param, val, caps;
+
+                       caps = FW_PARAMS_PARAM_PFVF_PORT_CAPS32;
+                       param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) |
+                                V_FW_PARAMS_PARAM_X(caps));
+                       val = 1;
+                       ret = t4_set_params(adap, mbox, pf, vf, 1, &param,
+                                           &val);
+                       fw_caps = ret == 0 ? FW_CAPS32 : FW_CAPS16;
+                       adap->params.fw_caps_support = fw_caps;
+               }
+
+               memset(&cmd, 0, sizeof(cmd));
+               cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
+                                              F_FW_CMD_REQUEST |
+                                              F_FW_CMD_READ |
+                                              V_FW_PORT_CMD_PORTID(j));
+               action = fw_caps == FW_CAPS16 ? FW_PORT_ACTION_GET_PORT_INFO :
+                                               FW_PORT_ACTION_GET_PORT_INFO32;
+               cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) |
+                                                 FW_LEN16(cmd));
+               ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
                if (ret)
                        return ret;
 
+               /* Extract the various fields from the Port Information message.
+                */
+               if (fw_caps == FW_CAPS16) {
+                       u32 lstatus =
+                               be32_to_cpu(cmd.u.info.lstatus_to_modtype);
+
+                       port_type = G_FW_PORT_CMD_PTYPE(lstatus);
+                       mdio_addr = (lstatus & F_FW_PORT_CMD_MDIOCAP) ?
+                                   (int)G_FW_PORT_CMD_MDIOADDR(lstatus) : -1;
+                       pcaps = be16_to_cpu(cmd.u.info.pcap);
+                       acaps = be16_to_cpu(cmd.u.info.acap);
+                       pcaps = fwcaps16_to_caps32(pcaps);
+                       acaps = fwcaps16_to_caps32(acaps);
+               } else {
+                       u32 lstatus32 =
+                               be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
+
+                       port_type = G_FW_PORT_CMD_PORTTYPE32(lstatus32);
+                       mdio_addr = (lstatus32 & F_FW_PORT_CMD_MDIOCAP32) ?
+                                   (int)G_FW_PORT_CMD_MDIOADDR32(lstatus32) :
+                                   -1;
+                       pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
+                       acaps = be32_to_cpu(cmd.u.info32.acaps32);
+               }
+
                ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
                if (ret < 0)
                        return ret;
 
-               p->viid = ret;
-               p->tx_chan = j;
-               p->rss_size = rss_size;
+               pi->viid = ret;
+               pi->tx_chan = j;
+               pi->rss_size = rss_size;
                t4_os_set_hw_addr(adap, i, addr);
 
-               ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
-               p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
-                               G_FW_PORT_CMD_MDIOADDR(ret) : -1;
-               p->port_type = G_FW_PORT_CMD_PTYPE(ret);
-               p->mod_type = FW_PORT_MOD_TYPE_NA;
+               pi->port_type = port_type;
+               pi->mdio_addr = mdio_addr;
+               pi->mod_type = FW_PORT_MOD_TYPE_NA;
 
-               init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap),
-                                be16_to_cpu(c.u.info.acap));
+               init_link_config(&pi->link_cfg, pcaps, acaps);
                j++;
        }
        return 0;
index 0e13937..d71c5a4 100644 (file)
@@ -491,7 +491,8 @@ enum fw_params_param_dev {
  * physical and virtual function parameters
  */
 enum fw_params_param_pfvf {
-       FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
+       FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
+       FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A
 };
 
 /*
@@ -1226,6 +1227,8 @@ enum fw_port_mdi32 {
 enum fw_port_action {
        FW_PORT_ACTION_L1_CFG           = 0x0001,
        FW_PORT_ACTION_GET_PORT_INFO    = 0x0003,
+       FW_PORT_ACTION_L1_CFG32         = 0x0009,
+       FW_PORT_ACTION_GET_PORT_INFO32  = 0x000a,
 };
 
 struct fw_port_cmd {
@@ -1314,6 +1317,18 @@ struct fw_port_cmd {
                                __be64 r12;
                        } control;
                } dcb;
+               struct fw_port_l1cfg32 {
+                       __be32 rcap32;
+                       __be32 r;
+               } l1cfg32;
+               struct fw_port_info32 {
+                       __be32 lstatus32_to_cbllen32;
+                       __be32 auxlinfo32_mtu32;
+                       __be32 linkattr32;
+                       __be32 pcaps32;
+                       __be32 acaps32;
+                       __be32 lpacaps32;
+               } info32;
        } u;
 };
 
@@ -1387,6 +1402,36 @@ struct fw_port_cmd {
 #define G_FW_PORT_CMD_MODTYPE(x)       \
        (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
 
+#define S_FW_PORT_CMD_LSTATUS32                31
+#define M_FW_PORT_CMD_LSTATUS32                0x1
+#define V_FW_PORT_CMD_LSTATUS32(x)     ((x) << S_FW_PORT_CMD_LSTATUS32)
+#define F_FW_PORT_CMD_LSTATUS32        V_FW_PORT_CMD_LSTATUS32(1U)
+
+#define S_FW_PORT_CMD_LINKDNRC32       28
+#define M_FW_PORT_CMD_LINKDNRC32       0x7
+#define G_FW_PORT_CMD_LINKDNRC32(x)    \
+       (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
+
+#define S_FW_PORT_CMD_MDIOCAP32                26
+#define M_FW_PORT_CMD_MDIOCAP32                0x1
+#define V_FW_PORT_CMD_MDIOCAP32(x)     ((x) << S_FW_PORT_CMD_MDIOCAP32)
+#define F_FW_PORT_CMD_MDIOCAP32        V_FW_PORT_CMD_MDIOCAP32(1U)
+
+#define S_FW_PORT_CMD_MDIOADDR32       21
+#define M_FW_PORT_CMD_MDIOADDR32       0x1f
+#define G_FW_PORT_CMD_MDIOADDR32(x)    \
+       (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
+
+#define S_FW_PORT_CMD_PORTTYPE32        13
+#define M_FW_PORT_CMD_PORTTYPE32        0xff
+#define G_FW_PORT_CMD_PORTTYPE32(x)     \
+       (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
+
+#define S_FW_PORT_CMD_MODTYPE32                8
+#define M_FW_PORT_CMD_MODTYPE32                0x1f
+#define G_FW_PORT_CMD_MODTYPE32(x)     \
+       (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
+
 /*
  * These are configured into the VPD and hence tools that generate
  * VPD may use this enumeration.