test/barrier: fix for Power CPUs

The memory barrier test fails on IBM Power 9 systems.  Add additional
barriers to accommodate the weakly ordered model used on Power CPUs.

Fixes: 93da5b59afc9 ("test: introduce memory barrier test case")
Cc: stable@dpdk.org
Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>

diff --git a/app/test/test_barrier.c b/app/test/test_barrier.c
index a0b4704..43b5f62 100644 (file)
--- a/app/test/test_barrier.c
+++ b/app/test/test_barrier.c
@@ -92,12 +92,14 @@ plock_lock(struct plock *l, uint32_t self)
        other = self ^ 1;
 
        l->flag[self] = 1;
+       rte_smp_wmb();
        l->victim = self;
 
        store_load_barrier(l->utype);
 
        while (l->flag[other] == 1 && l->victim == self)
                rte_pause();
+       rte_smp_rmb();
 }
 
 static void