net/cxgbe: fix Rx channel map and queue type

Set the Rx channel map and ingress queue type properly to allow firmware
to manage the internal mapping correctly.

Fixes: 6c2809628cd5 ("net/cxgbe: improve latency for slow traffic")
Cc: stable@dpdk.org
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>

diff --git a/drivers/net/cxgbe/base/t4fw_interface.h b/drivers/net/cxgbe/base/t4fw_interface.h
index a17ebea..e80b58a 100644 (file)
--- a/drivers/net/cxgbe/base/t4fw_interface.h
+++ b/drivers/net/cxgbe/base/t4fw_interface.h
@@ -809,6 +809,11 @@ enum fw_iq_type {
        FW_IQ_TYPE_FL_INT_CAP,
 };
 
+enum fw_iq_iqtype {
+       FW_IQ_IQTYPE_NIC = 1,
+       FW_IQ_IQTYPE_OFLD,
+};
+
 struct fw_iq_cmd {
        __be32 op_to_vfn;
        __be32 alloc_to_len16;
@@ -942,6 +947,9 @@ struct fw_iq_cmd {
        (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
 #define F_FW_IQ_CMD_IQFLINTCONGEN      V_FW_IQ_CMD_IQFLINTCONGEN(1U)
 
+#define S_FW_IQ_CMD_IQTYPE     24
+#define V_FW_IQ_CMD_IQTYPE(x)  ((x) << S_FW_IQ_CMD_IQTYPE)
+
 #define S_FW_IQ_CMD_FL0CNGCHMAP                20
 #define M_FW_IQ_CMD_FL0CNGCHMAP                0xf
 #define V_FW_IQ_CMD_FL0CNGCHMAP(x)     ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)

diff --git a/drivers/net/cxgbe/cxgbe_compat.h b/drivers/net/cxgbe/cxgbe_compat.h
index 6091564..5d47c5f 100644 (file)
--- a/drivers/net/cxgbe/cxgbe_compat.h
+++ b/drivers/net/cxgbe/cxgbe_compat.h
@@ -198,15 +198,6 @@ static inline int cxgbe_fls(int x)
        return x ? sizeof(x) * 8 - __builtin_clz(x) : 0;
 }
 
-/**
- * cxgbe_ffs - find first bit set
- * @x: the word to search
- */
-static inline int cxgbe_ffs(int x)
-{
-       return x ? __builtin_ffs(x) : 0;
-}
-
 static inline unsigned long ilog2(unsigned long n)
 {
        unsigned int e = 0;

diff --git a/drivers/net/cxgbe/sge.c b/drivers/net/cxgbe/sge.c
index 357b485..4ea40d1 100644 (file)
--- a/drivers/net/cxgbe/sge.c
+++ b/drivers/net/cxgbe/sge.c
@@ -1889,12 +1889,16 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
                            F_FW_CMD_WRITE | F_FW_CMD_EXEC);
 
        if (is_pf4(adap)) {
-               pciechan = cong > 0 ? cxgbe_ffs(cong) - 1 : pi->tx_chan;
+               pciechan = pi->tx_chan;
                c.op_to_vfn |= htonl(V_FW_IQ_CMD_PFN(adap->pf) |
                                     V_FW_IQ_CMD_VFN(0));
                if (cong >= 0)
-                       c.iqns_to_fl0congen = htonl(F_FW_IQ_CMD_IQFLINTCONGEN |
-                                                   F_FW_IQ_CMD_IQRO);
+                       c.iqns_to_fl0congen =
+                               htonl(F_FW_IQ_CMD_IQFLINTCONGEN |
+                                     V_FW_IQ_CMD_IQTYPE(cong ?
+                                                        FW_IQ_IQTYPE_NIC :
+                                                        FW_IQ_IQTYPE_OFLD) |
+                                     F_FW_IQ_CMD_IQRO);
        } else {
                pciechan = pi->port_id;
        }