bus/fslmc: fix build with clang 3.4
authorHemant Agrawal <hemant.agrawal@nxp.com>
Thu, 19 Apr 2018 12:32:39 +0000 (18:02 +0530)
committerThomas Monjalon <thomas@monjalon.net>
Thu, 19 Apr 2018 16:26:47 +0000 (18:26 +0200)
error: redefinition of typedef 'dma_addr_t' is a C11 feature
[-Werror,-Wtypedef-redefinition]

Fixes: 4bc5ab88dbd6 ("net/dpaa2: fix Tx only mode")
Cc: stable@dpdk.org
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Tested-by: Maxime Coquelin <maxime.coquelin@redhat.com>
drivers/bus/fslmc/qbman/include/fsl_qbman_base.h
drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
drivers/net/dpaa2/dpaa2_rxtx.c

index 96269ed..bb60a98 100644 (file)
@@ -6,8 +6,6 @@
 #ifndef _FSL_QBMAN_BASE_H
 #define _FSL_QBMAN_BASE_H
 
-typedef uint64_t  dma_addr_t;
-
 /**
  * DOC: QBMan basic structures
  *
index 23012e3..3700d70 100644 (file)
@@ -30,6 +30,9 @@
 #include "dpaa2_sec_priv.h"
 #include "dpaa2_sec_logs.h"
 
+/* Required types */
+typedef uint64_t       dma_addr_t;
+
 /* RTA header files */
 #include <hw/desc/ipsec.h>
 #include <hw/desc/algo.h>
index ef3a897..dc0da96 100644 (file)
@@ -481,7 +481,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
                                              q_storage->last_num_pkts);
                qbman_pull_desc_set_fq(&pulldesc, fqid);
                qbman_pull_desc_set_storage(&pulldesc, dq_storage,
-                       (dma_addr_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1);
+                       (uint64_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1);
                if (check_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index)) {
                        while (!qbman_check_command_complete(
                               get_swp_active_dqs(
@@ -517,7 +517,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
        qbman_pull_desc_set_numframes(&pulldesc, DPAA2_DQRR_RING_SIZE);
        qbman_pull_desc_set_fq(&pulldesc, fqid);
        qbman_pull_desc_set_storage(&pulldesc, dq_storage1,
-               (dma_addr_t)(DPAA2_VADDR_TO_IOVA(dq_storage1)), 1);
+               (uint64_t)(DPAA2_VADDR_TO_IOVA(dq_storage1)), 1);
 
        /* Check if the previous issued command is completed.
         * Also seems like the SWP is shared between the Ethernet Driver