net/mlx5: fix MPLS tunnel outer layer overwrite
authorDariusz Sosnowski <dsosnowski@nvidia.com>
Wed, 17 Nov 2021 09:59:33 +0000 (11:59 +0200)
committerRaslan Darawsheh <rasland@nvidia.com>
Wed, 17 Nov 2021 10:48:18 +0000 (11:48 +0100)
mlx5 PMD incorrectly overwrote outer layer fields in MPLS tunnel
rte_flow patterns using defaults for MPLS tunnels. This included
overwriting UDP destination port in MPLSoUDP and GRE protocol field in
MPLSoGRE.

This patch fixes this behavior. If application provides the values in
flow pattern items preceding the MPLS flow item the provided values will
be used, otherwise the defaults will be applied.

Fixes: d1abe664ddde ("net/mlx5: add MPLS to Direct Verbs flow engine")
Cc: stable@dpdk.org
Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
drivers/net/mlx5/mlx5_flow_dv.c

index 7b32c06..d079a52 100644 (file)
@@ -9328,16 +9328,22 @@ flow_dv_translate_item_mpls(void *matcher, void *key,
 
        switch (prev_layer) {
        case MLX5_FLOW_LAYER_OUTER_L4_UDP:
-               MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
-               MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
-                        MLX5_UDP_PORT_MPLS);
+               if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
+                       MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
+                                0xffff);
+                       MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
+                                MLX5_UDP_PORT_MPLS);
+               }
                break;
        case MLX5_FLOW_LAYER_GRE:
                /* Fall-through. */
        case MLX5_FLOW_LAYER_GRE_KEY:
-               MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
-               MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
-                        RTE_ETHER_TYPE_MPLS);
+               if (!MLX5_GET16(fte_match_set_misc, misc_v, gre_protocol)) {
+                       MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
+                                0xffff);
+                       MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
+                                RTE_ETHER_TYPE_MPLS);
+               }
                break;
        default:
                break;