net/cxgbe: fetch max Tx coalesce limit from firmware
authorRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Fri, 27 Sep 2019 20:30:10 +0000 (02:00 +0530)
committerFerruh Yigit <ferruh.yigit@intel.com>
Mon, 7 Oct 2019 13:00:57 +0000 (15:00 +0200)
Query firmware for max number of packets that can be coalesced by
Tx.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
doc/guides/nics/cxgbe.rst
drivers/net/cxgbe/base/common.h
drivers/net/cxgbe/base/t4fw_interface.h
drivers/net/cxgbe/cxgbe_main.c
drivers/net/cxgbe/cxgbe_pfvf.h
drivers/net/cxgbe/cxgbevf_main.c
drivers/net/cxgbe/sge.c

index 76b1a2a..cae78a3 100644 (file)
@@ -70,7 +70,7 @@ in :ref:`t5-nics` and :ref:`t6-nics`.
 Prerequisites
 -------------
 
-- Requires firmware version **1.17.14.0** and higher. Visit
+- Requires firmware version **1.23.4.0** and higher. Visit
   `Chelsio Download Center <http://service.chelsio.com>`_ to get latest firmware
   bundled with the latest Chelsio Unified Wire package.
 
@@ -215,7 +215,7 @@ Unified Wire package for Linux operating system are as follows:
 
    .. code-block:: console
 
-      firmware-version: 1.17.14.0, TP 0.1.4.9
+      firmware-version: 1.23.4.0, TP 0.1.23.2
 
 Running testpmd
 ~~~~~~~~~~~~~~~
@@ -273,7 +273,7 @@ devices managed by librte_pmd_cxgbe in Linux operating system.
       EAL:   PCI memory mapped at 0x7fd7c0200000
       EAL:   PCI memory mapped at 0x7fd77cdfd000
       EAL:   PCI memory mapped at 0x7fd7c10b7000
-      PMD: rte_cxgbe_pmd: fw: 1.17.14.0, TP: 0.1.4.9
+      PMD: rte_cxgbe_pmd: fw: 1.23.4.0, TP: 0.1.23.2
       PMD: rte_cxgbe_pmd: Coming up as MASTER: Initializing adapter
       Interactive-mode selected
       Configuring Port 0 (socket 0)
@@ -379,16 +379,16 @@ virtual functions.
       [...]
       EAL: PCI device 0000:02:01.0 on NUMA socket 0
       EAL:   probe driver: 1425:5803 net_cxgbevf
-      PMD: rte_cxgbe_pmd: Firmware version: 1.17.14.0
-      PMD: rte_cxgbe_pmd: TP Microcode version: 0.1.4.9
+      PMD: rte_cxgbe_pmd: Firmware version: 1.23.4.0
+      PMD: rte_cxgbe_pmd: TP Microcode version: 0.1.23.2
       PMD: rte_cxgbe_pmd: Chelsio rev 0
       PMD: rte_cxgbe_pmd: No bootstrap loaded
       PMD: rte_cxgbe_pmd: No Expansion ROM loaded
       PMD: rte_cxgbe_pmd:  0000:02:01.0 Chelsio rev 0 1G/10GBASE-SFP
       EAL: PCI device 0000:02:01.1 on NUMA socket 0
       EAL:   probe driver: 1425:5803 net_cxgbevf
-      PMD: rte_cxgbe_pmd: Firmware version: 1.17.14.0
-      PMD: rte_cxgbe_pmd: TP Microcode version: 0.1.4.9
+      PMD: rte_cxgbe_pmd: Firmware version: 1.23.4.0
+      PMD: rte_cxgbe_pmd: TP Microcode version: 0.1.23.2
       PMD: rte_cxgbe_pmd: Chelsio rev 0
       PMD: rte_cxgbe_pmd: No bootstrap loaded
       PMD: rte_cxgbe_pmd: No Expansion ROM loaded
@@ -465,7 +465,7 @@ Unified Wire package for FreeBSD operating system are as follows:
 
    .. code-block:: console
 
-      dev.t5nex.0.firmware_version: 1.17.14.0
+      dev.t5nex.0.firmware_version: 1.23.4.0
 
 Running testpmd
 ~~~~~~~~~~~~~~~
@@ -583,7 +583,7 @@ devices managed by librte_pmd_cxgbe in FreeBSD operating system.
       EAL:   PCI memory mapped at 0x8007ec000
       EAL:   PCI memory mapped at 0x842800000
       EAL:   PCI memory mapped at 0x80086c000
-      PMD: rte_cxgbe_pmd: fw: 1.17.14.0, TP: 0.1.4.9
+      PMD: rte_cxgbe_pmd: fw: 1.23.4.0, TP: 0.1.23.2
       PMD: rte_cxgbe_pmd: Coming up as MASTER: Initializing adapter
       Interactive-mode selected
       Configuring Port 0 (socket 0)
index 973d4d7..6047642 100644 (file)
@@ -272,6 +272,7 @@ struct adapter_params {
        bool ulptx_memwrite_dsgl;          /* use of T5 DSGL allowed */
        u8 fw_caps_support;               /* 32-bit Port Capabilities */
        u8 filter2_wr_support;            /* FW support for FILTER2_WR */
+       u32 max_tx_coalesce_num; /* Max # of Tx packets that can be coalesced */
 };
 
 /* Firmware Port Capabilities types.
index 06d3ef3..e992d19 100644 (file)
@@ -692,7 +692,8 @@ enum fw_params_param_pfvf {
        FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
        FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
        FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
-       FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A
+       FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
+       FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D,
 };
 
 /*
index 23b74c7..4701518 100644 (file)
@@ -37,6 +37,7 @@
 #include "base/t4_regs.h"
 #include "base/t4_msg.h"
 #include "cxgbe.h"
+#include "cxgbe_pfvf.h"
 #include "clip_tbl.h"
 #include "l2t.h"
 #include "mps_tcam.h"
@@ -1162,20 +1163,10 @@ static int adap_init0(struct adapter *adap)
        /*
         * Grab some of our basic fundamental operating parameters.
         */
-#define FW_PARAM_DEV(param) \
-       (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
-        V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
-
-#define FW_PARAM_PFVF(param) \
-       (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
-        V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) |  \
-        V_FW_PARAMS_PARAM_Y(0) | \
-        V_FW_PARAMS_PARAM_Z(0))
-
-       params[0] = FW_PARAM_PFVF(L2T_START);
-       params[1] = FW_PARAM_PFVF(L2T_END);
-       params[2] = FW_PARAM_PFVF(FILTER_START);
-       params[3] = FW_PARAM_PFVF(FILTER_END);
+       params[0] = CXGBE_FW_PARAM_PFVF(L2T_START);
+       params[1] = CXGBE_FW_PARAM_PFVF(L2T_END);
+       params[2] = CXGBE_FW_PARAM_PFVF(FILTER_START);
+       params[3] = CXGBE_FW_PARAM_PFVF(FILTER_END);
        ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4, params, val);
        if (ret < 0)
                goto bye;
@@ -1184,8 +1175,8 @@ static int adap_init0(struct adapter *adap)
        adap->tids.ftid_base = val[2];
        adap->tids.nftids = val[3] - val[2] + 1;
 
-       params[0] = FW_PARAM_PFVF(CLIP_START);
-       params[1] = FW_PARAM_PFVF(CLIP_END);
+       params[0] = CXGBE_FW_PARAM_PFVF(CLIP_START);
+       params[1] = CXGBE_FW_PARAM_PFVF(CLIP_END);
        ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
        if (ret < 0)
                goto bye;
@@ -1215,14 +1206,14 @@ static int adap_init0(struct adapter *adap)
        if (is_t4(adap->params.chip)) {
                adap->params.filter2_wr_support = 0;
        } else {
-               params[0] = FW_PARAM_DEV(FILTER2_WR);
+               params[0] = CXGBE_FW_PARAM_DEV(FILTER2_WR);
                ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
                                      1, params, val);
                adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
        }
 
        /* query tid-related parameters */
-       params[0] = FW_PARAM_DEV(NTID);
+       params[0] = CXGBE_FW_PARAM_DEV(NTID);
        ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
                              params, val);
        if (ret < 0)
@@ -1235,7 +1226,7 @@ static int adap_init0(struct adapter *adap)
         * firmware won't understand this and we'll just get
         * unencapsulated messages ...
         */
-       params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
+       params[0] = CXGBE_FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
        val[0] = 1;
        (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
 
@@ -1248,12 +1239,20 @@ static int adap_init0(struct adapter *adap)
        if (is_t4(adap->params.chip)) {
                adap->params.ulptx_memwrite_dsgl = false;
        } else {
-               params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
+               params[0] = CXGBE_FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
                ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
                                      1, params, val);
                adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
        }
 
+       /* Query for max number of packets that can be coalesced for Tx */
+       params[0] = CXGBE_FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR);
+       ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
+       if (!ret && val[0] > 0)
+               adap->params.max_tx_coalesce_num = val[0];
+       else
+               adap->params.max_tx_coalesce_num = ETH_COALESCE_PKT_NUM;
+
        /*
         * The MTU/MSS Table is initialized by now, so load their values.  If
         * we're initializing the adapter, then we'll make any modifications
index 3a6ab41..0b7c52a 100644 (file)
@@ -6,6 +6,16 @@
 #ifndef _CXGBE_PFVF_H_
 #define _CXGBE_PFVF_H_
 
+#define CXGBE_FW_PARAM_DEV(param) \
+       (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
+        V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
+
+#define CXGBE_FW_PARAM_PFVF(param) \
+       (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
+        V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) |  \
+        V_FW_PARAMS_PARAM_Y(0) | \
+        V_FW_PARAMS_PARAM_Z(0))
+
 void cxgbe_dev_rx_queue_release(void *q);
 void cxgbe_dev_tx_queue_release(void *q);
 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev);
index 82f40f3..66fb923 100644 (file)
@@ -11,6 +11,7 @@
 #include "base/t4_regs.h"
 #include "base/t4_msg.h"
 #include "cxgbe.h"
+#include "cxgbe_pfvf.h"
 #include "mps_tcam.h"
 
 /*
@@ -122,11 +123,18 @@ static int adap_init0vf(struct adapter *adapter)
         * firmware won't understand this and we'll just get
         * unencapsulated messages ...
         */
-       param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) |
-               V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP);
+       param = CXGBE_FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
        val = 1;
        t4vf_set_params(adapter, 1, &param, &val);
 
+       /* Query for max number of packets that can be coalesced for Tx */
+       param = CXGBE_FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR);
+       err = t4vf_query_params(adapter, 1, &param, &val);
+       if (!err && val > 0)
+               adapter->params.max_tx_coalesce_num = val;
+       else
+               adapter->params.max_tx_coalesce_num = ETH_COALESCE_VF_PKT_NUM;
+
        /*
         * Grab our Virtual Interface resource allocation, extract the
         * features that we're interested in and do a bit of sanity testing on
index 0df870a..aba85a2 100644 (file)
@@ -1004,8 +1004,6 @@ static inline int tx_do_packet_coalesce(struct sge_eth_txq *txq,
        struct cpl_tx_pkt_core *cpl;
        struct tx_sw_desc *sd;
        unsigned int idx = q->coalesce.idx, len = mbuf->pkt_len;
-       unsigned int max_coal_pkt_num = is_pf4(adap) ? ETH_COALESCE_PKT_NUM :
-                                                      ETH_COALESCE_VF_PKT_NUM;
 
        if (q->coalesce.type == 0) {
                mc = (struct ulp_txpkt *)q->coalesce.ptr;
@@ -1083,7 +1081,7 @@ static inline int tx_do_packet_coalesce(struct sge_eth_txq *txq,
         * for coalescing the next Tx burst and send the packets now.
         */
        q->coalesce.idx++;
-       if (q->coalesce.idx == max_coal_pkt_num ||
+       if (q->coalesce.idx == adap->params.max_tx_coalesce_num ||
            (adap->devargs.tx_mode_latency && q->coalesce.idx >= nb_pkts))
                ship_tx_pkt_coalesce_wr(adap, txq);