{
return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, false);
}
+
+int
+roc_bphy_cgx_fec_supported_get(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+ enum roc_bphy_cgx_eth_link_fec *fec)
+{
+ uint64_t scr1, scr0;
+ int ret;
+
+ if (!roc_cgx || !fec)
+ return -EINVAL;
+
+ if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+ return -EINVAL;
+
+ scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_GET_SUPPORTED_FEC);
+
+ ret = roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+ if (ret)
+ return ret;
+
+ scr0 = FIELD_GET(SCR0_ETH_FEC_TYPES_S_FEC, scr0);
+ *fec = (enum roc_bphy_cgx_eth_link_fec)scr0;
+
+ return 0;
+}
unsigned int lmac);
__roc_api int roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac);
+__roc_api int roc_bphy_cgx_fec_supported_get(struct roc_bphy_cgx *roc_cgx,
+ unsigned int lmac,
+ enum roc_bphy_cgx_eth_link_fec *fec);
#endif /* _ROC_BPHY_CGX_H_ */
ETH_CMD_INTERNAL_LBK = 7,
ETH_CMD_MODE_CHANGE = 11, /* hot plug support */
ETH_CMD_INTF_SHUTDOWN = 12,
+ ETH_CMD_GET_SUPPORTED_FEC = 18,
ETH_CMD_SET_PTP_MODE = 34,
};
#define SCR0_ETH_LNK_STS_S_LMAC_TYPE GENMASK_ULL(35, 28)
#define SCR0_ETH_LNK_STS_S_MODE GENMASK_ULL(43, 36)
+/* struct eth_fec_types_s */
+#define SCR0_ETH_FEC_TYPES_S_FEC GENMASK_ULL(10, 9)
+
/* scratchx(1) CSR used for non-secure SW->ATF communication
* This CSR acts as a command register
*/
roc_ae_fpm_put;
roc_bphy_cgx_dev_fini;
roc_bphy_cgx_dev_init;
+ roc_bphy_cgx_fec_supported_get;
roc_bphy_cgx_get_linkinfo;
roc_bphy_cgx_intlbk_disable;
roc_bphy_cgx_intlbk_enable;