net/octeontx2: fix PTP and HIGIG2 coexistence
authorKiran Kumar K <kirankumark@marvell.com>
Tue, 14 Jan 2020 09:26:22 +0000 (14:56 +0530)
committerFerruh Yigit <ferruh.yigit@intel.com>
Fri, 17 Jan 2020 18:46:26 +0000 (19:46 +0100)
octeontx2 PMD does not support both PTP and HIGIG2 together.
Added a check to enforce this and updated the Rx offload capabilities when
Higig2 mode enabled.

Fixes: 602009ee2dfb ("net/octeontx2: support HIGIG2")
Cc: stable@dpdk.org
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
drivers/net/octeontx2/otx2_ethdev.c
drivers/net/octeontx2/otx2_ptp.c

index 43c6107..268b383 100644 (file)
@@ -18,7 +18,8 @@ nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
 {
        uint64_t capa = NIX_RX_OFFLOAD_CAPA;
 
-       if (otx2_dev_is_vf(dev))
+       if (otx2_dev_is_vf(dev) ||
+           dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG)
                capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
 
        return capa;
@@ -1641,6 +1642,12 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
                goto fail_offloads;
        }
 
+       if (dev->ptp_en &&
+           dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
+               otx2_err("Both PTP and switch header enabled");
+               goto free_nix_lf;
+       }
+
        rc = nix_lf_switch_header_type_enable(dev);
        if (rc) {
                otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
index f34b933..ae5a2b7 100644 (file)
@@ -221,6 +221,11 @@ otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev)
                return -EINVAL;
        }
 
+       if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
+               otx2_err("Both PTP and switch header enabled");
+               return -EINVAL;
+       }
+
        /* Allocating a iova address for tx tstamp */
        const struct rte_memzone *ts;
        ts = rte_eth_dma_zone_reserve(eth_dev, "otx2_ts",