regex/mlx5: add engine status check

This commit checks the engine status.

Signed-off-by: Ori Kam <orika@mellanox.com>

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index a24a10d..f6f4ec0 100644 (file)
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -759,6 +759,10 @@ enum {
        MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
        MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
        MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
+       MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
+       MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
+       MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
+       MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
 };
 
 enum {
@@ -2491,6 +2495,93 @@ struct mlx5_ifc_query_qp_in_bits {
        u8 reserved_at_60[0x20];
 };
 
+struct regexp_params_field_select_bits {
+       u8 reserved_at_0[0x1e];
+       u8 stop_engine[0x1];
+       u8 db_umem_id[0x1];
+};
+
+struct mlx5_ifc_regexp_params_bits {
+       u8 reserved_at_0[0x1f];
+       u8 stop_engine[0x1];
+       u8 db_umem_id[0x20];
+       u8 db_umem_offset[0x40];
+       u8 reserved_at_80[0x100];
+};
+
+struct mlx5_ifc_set_regexp_params_in_bits {
+       u8 opcode[0x10];
+       u8 uid[0x10];
+       u8 reserved_at_20[0x10];
+       u8 op_mod[0x10];
+       u8 reserved_at_40[0x18];
+       u8 engine_id[0x8];
+       struct regexp_params_field_select_bits field_select;
+       struct mlx5_ifc_regexp_params_bits regexp_params;
+};
+
+struct mlx5_ifc_set_regexp_params_out_bits {
+       u8 status[0x8];
+       u8 reserved_at_8[0x18];
+       u8 syndrome[0x20];
+       u8 reserved_at_18[0x40];
+};
+
+struct mlx5_ifc_query_regexp_params_in_bits {
+       u8 opcode[0x10];
+       u8 uid[0x10];
+       u8 reserved_at_20[0x10];
+       u8 op_mod[0x10];
+       u8 reserved_at_40[0x18];
+       u8 engine_id[0x8];
+       u8 reserved[0x20];
+};
+
+struct mlx5_ifc_query_regexp_params_out_bits {
+       u8 status[0x8];
+       u8 reserved_at_8[0x18];
+       u8 syndrome[0x20];
+       u8 reserved[0x40];
+       struct mlx5_ifc_regexp_params_bits regexp_params;
+};
+
+struct mlx5_ifc_set_regexp_register_in_bits {
+       u8 opcode[0x10];
+       u8 uid[0x10];
+       u8 reserved_at_20[0x10];
+       u8 op_mod[0x10];
+       u8 reserved_at_40[0x18];
+       u8 engine_id[0x8];
+       u8 register_address[0x20];
+       u8 register_data[0x20];
+       u8 reserved[0x40];
+};
+
+struct mlx5_ifc_set_regexp_register_out_bits {
+       u8 status[0x8];
+       u8 reserved_at_8[0x18];
+       u8 syndrome[0x20];
+       u8 reserved[0x40];
+};
+
+struct mlx5_ifc_query_regexp_register_in_bits {
+       u8 opcode[0x10];
+       u8 uid[0x10];
+       u8 reserved_at_20[0x10];
+       u8 op_mod[0x10];
+       u8 reserved_at_40[0x18];
+       u8 engine_id[0x8];
+       u8 register_address[0x20];
+};
+
+struct mlx5_ifc_query_regexp_register_out_bits {
+       u8 status[0x8];
+       u8 reserved_at_8[0x18];
+       u8 syndrome[0x20];
+       u8 reserved[0x20];
+       u8 register_data[0x20];
+};
+
 /* CQE format mask. */
 #define MLX5E_CQE_FORMAT_MASK 0xc
 

diff --git a/drivers/regex/mlx5/Makefile b/drivers/regex/mlx5/Makefile
index aea9824..3c1c8bf 100644 (file)
--- a/drivers/regex/mlx5/Makefile
+++ b/drivers/regex/mlx5/Makefile
@@ -9,6 +9,7 @@ LIB = librte_pmd_mlx5_regex.a
 # Sources.
 SRCS-$(CONFIG_RTE_LIBRTE_MLX5_REGEX_PMD) += mlx5_regex.c
 SRCS-$(CONFIG_RTE_LIBRTE_MLX5_REGEX_PMD) += mlx5_rxp.c
+SRCS-$(CONFIG_RTE_LIBRTE_MLX5_REGEX_PMD) += mlx5_regex_devx.c
 
 # Basic CFLAGS.
 CFLAGS += -O3

diff --git a/drivers/regex/mlx5/meson.build b/drivers/regex/mlx5/meson.build
index 0a4d410..dd75fe7 100644 (file)
--- a/drivers/regex/mlx5/meson.build
+++ b/drivers/regex/mlx5/meson.build
@@ -12,6 +12,7 @@ deps += ['common_mlx5', 'bus_pci', 'eal', 'regexdev']
 sources = files(
        'mlx5_regex.c',
        'mlx5_rxp.c',
+       'mlx5_regex_devx.c',
 )
 cflags_options = [
        '-std=c11',

diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c
index ce2216b..89d4fc8 100644 (file)
--- a/drivers/regex/mlx5/mlx5_regex.c
+++ b/drivers/regex/mlx5/mlx5_regex.c
@@ -17,6 +17,7 @@
 
 #include "mlx5_regex.h"
 #include "mlx5_regex_utils.h"
+#include "mlx5_rxp_csrs.h"
 
 int mlx5_regex_logtype;
 
@@ -51,6 +52,28 @@ mlx5_regex_get_ib_device_match(struct rte_pci_addr *addr)
        mlx5_glue->free_device_list(ibv_list);
        return ibv_match;
 }
+static int
+mlx5_regex_engines_status(struct ibv_context *ctx, int num_engines)
+{
+       uint32_t fpga_ident = 0;
+       int err;
+       int i;
+
+       for (i = 0; i < num_engines; i++) {
+               err = mlx5_devx_regex_register_read(ctx, i,
+                                                   MLX5_RXP_CSR_IDENTIFIER,
+                                                   &fpga_ident);
+               fpga_ident = (fpga_ident & (0x0000FFFF));
+               if (err || fpga_ident != MLX5_RXP_IDENTIFIER) {
+                       DRV_LOG(ERR, "Failed setup RXP %d err %d database "
+                               "memory 0x%x", i, err, fpga_ident);
+                       if (!err)
+                               err = EINVAL;
+                       return err;
+               }
+       }
+       return 0;
+}
 
 static void
 mlx5_regex_get_name(char *name, struct rte_pci_device *pci_dev __rte_unused)
@@ -97,6 +120,11 @@ mlx5_regex_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
                rte_errno = ENOTSUP;
                goto error;
        }
+       if (mlx5_regex_engines_status(ctx, 2)) {
+               DRV_LOG(ERR, "RegEx engine error.");
+               rte_errno = ENOMEM;
+               goto error;
+       }
        priv = rte_zmalloc("mlx5 regex device private", sizeof(*priv),
                           RTE_CACHE_LINE_SIZE);
        if (!priv) {

diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h
index 9d0fc16..082d134 100644 (file)
--- a/drivers/regex/mlx5/mlx5_regex.h
+++ b/drivers/regex/mlx5/mlx5_regex.h
@@ -5,6 +5,8 @@
 #ifndef MLX5_REGEX_H
 #define MLX5_REGEX_H
 
+#include <rte_regexdev.h>
+
 struct mlx5_regex_priv {
        TAILQ_ENTRY(mlx5_regex_priv) next;
        struct ibv_context *ctx; /* Device context. */
@@ -16,4 +18,10 @@ struct mlx5_regex_priv {
 int mlx5_regex_info_get(struct rte_regexdev *dev,
                        struct rte_regexdev_info *info);
 
+/* mlx5_regex_devx.c */
+int mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,
+                                  uint32_t addr, uint32_t data);
+int mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,
+                                 uint32_t addr, uint32_t *data);
+
 #endif /* MLX5_REGEX_H */

diff --git a/drivers/regex/mlx5/mlx5_regex_devx.c b/drivers/regex/mlx5/mlx5_regex_devx.c
new file mode 100644 (file)
index 0000000..1ffc008
--- /dev/null
+++ b/drivers/regex/mlx5/mlx5_regex_devx.c
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2020 Mellanox Technologies, Ltd
+ */
+
+#include <rte_errno.h>
+#include <rte_log.h>
+
+#include <mlx5_glue.h>
+#include <mlx5_devx_cmds.h>
+#include <mlx5_prm.h>
+
+#include "mlx5_regex.h"
+#include "mlx5_regex_utils.h"
+
+int
+mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,
+                              uint32_t addr, uint32_t data)
+{
+       uint32_t out[MLX5_ST_SZ_DW(set_regexp_register_out)] = {0};
+       uint32_t in[MLX5_ST_SZ_DW(set_regexp_register_in)] = {0};
+       int ret;
+
+       MLX5_SET(set_regexp_register_in, in, opcode,
+                MLX5_CMD_SET_REGEX_REGISTERS);
+       MLX5_SET(set_regexp_register_in, in, engine_id, engine_id);
+       MLX5_SET(set_regexp_register_in, in, register_address, addr);
+       MLX5_SET(set_regexp_register_in, in, register_data, data);
+
+       ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
+                                         sizeof(out));
+       if (ret) {
+               DRV_LOG(ERR, "Set regexp register failed %d", ret);
+               rte_errno = errno;
+               return -errno;
+       }
+       return 0;
+}
+
+int
+mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,
+                             uint32_t addr, uint32_t *data)
+{
+       uint32_t out[MLX5_ST_SZ_DW(query_regexp_register_out)] = {0};
+       uint32_t in[MLX5_ST_SZ_DW(query_regexp_register_in)] = {0};
+       int ret;
+
+       MLX5_SET(query_regexp_register_in, in, opcode,
+                MLX5_CMD_QUERY_REGEX_REGISTERS);
+       MLX5_SET(query_regexp_register_in, in, engine_id, engine_id);
+       MLX5_SET(query_regexp_register_in, in, register_address, addr);
+
+       ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
+                                         sizeof(out));
+       if (ret) {
+               DRV_LOG(ERR, "Query regexp register failed %d", ret);
+               rte_errno = errno;
+               return -errno;
+       }
+       *data = MLX5_GET(query_regexp_register_out, out, register_data);
+       return 0;
+}

diff --git a/drivers/regex/mlx5/mlx5_rxp_csrs.h b/drivers/regex/mlx5/mlx5_rxp_csrs.h
new file mode 100644 (file)
index 0000000..d92b3ff
--- /dev/null
+++ b/drivers/regex/mlx5/mlx5_rxp_csrs.h
@@ -0,0 +1,339 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2020 Mellanox Technologies, Ltd
+ */
+
+#ifndef _MLX5_RXP_CSRS_H_
+#define _MLX5_RXP_CSRS_H_
+
+/*
+ * Common to all RXP implementations
+ */
+#define MLX5_RXP_CSR_BASE_ADDRESS 0x0000ul
+#define MLX5_RXP_RTRU_CSR_BASE_ADDRESS 0x0100ul
+#define MLX5_RXP_STATS_CSR_BASE_ADDRESS        0x0200ul
+#define MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS 0x0600ul
+
+#define MLX5_RXP_CSR_WIDTH 4
+
+/* This is the identifier we expect to see in the first RXP CSR */
+#define MLX5_RXP_IDENTIFIER 0x5254
+
+/* Hyperion specific BAR0 offsets */
+#define MLX5_RXP_FPGA_BASE_ADDRESS 0x0000ul
+#define MLX5_RXP_PCIE_BASE_ADDRESS 0x1000ul
+#define MLX5_RXP_IDMA_BASE_ADDRESS 0x2000ul
+#define MLX5_RXP_EDMA_BASE_ADDRESS 0x3000ul
+#define MLX5_RXP_SYSMON_BASE_ADDRESS 0xf300ul
+#define MLX5_RXP_ISP_CSR_BASE_ADDRESS 0xf400ul
+
+/* Offset to the RXP common 4K CSR space */
+#define MLX5_RXP_PCIE_CSR_BASE_ADDRESS 0xf000ul
+
+/* FPGA CSRs */
+
+#define MLX5_RXP_FPGA_VERSION (MLX5_RXP_FPGA_BASE_ADDRESS + \
+                              MLX5_RXP_CSR_WIDTH * 0)
+
+/* PCIe CSRs */
+#define MLX5_RXP_PCIE_INIT_ISR (MLX5_RXP_PCIE_BASE_ADDRESS + \
+                               MLX5_RXP_CSR_WIDTH * 0)
+#define MLX5_RXP_PCIE_INIT_IMR (MLX5_RXP_PCIE_BASE_ADDRESS + \
+                               MLX5_RXP_CSR_WIDTH * 1)
+#define MLX5_RXP_PCIE_INIT_CFG_STAT (MLX5_RXP_PCIE_BASE_ADDRESS + \
+                                    MLX5_RXP_CSR_WIDTH * 2)
+#define MLX5_RXP_PCIE_INIT_FLR (MLX5_RXP_PCIE_BASE_ADDRESS + \
+                               MLX5_RXP_CSR_WIDTH * 3)
+#define MLX5_RXP_PCIE_INIT_CTRL        (MLX5_RXP_PCIE_BASE_ADDRESS + \
+                                MLX5_RXP_CSR_WIDTH * 4)
+
+/* IDMA CSRs */
+#define MLX5_RXP_IDMA_ISR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 0)
+#define MLX5_RXP_IDMA_IMR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 1)
+#define MLX5_RXP_IDMA_CSR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 4)
+#define MLX5_RXP_IDMA_CSR_RST_MSK 0x0001
+#define MLX5_RXP_IDMA_CSR_PDONE_MSK 0x0002
+#define MLX5_RXP_IDMA_CSR_INIT_MSK 0x0004
+#define MLX5_RXP_IDMA_CSR_EN_MSK 0x0008
+#define MLX5_RXP_IDMA_QCR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 5)
+#define MLX5_RXP_IDMA_QCR_QAVAIL_MSK 0x00FF
+#define MLX5_RXP_IDMA_QCR_QEN_MSK 0xFF00
+#define MLX5_RXP_IDMA_DCR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 6)
+#define MLX5_RXP_IDMA_DWCTR (MLX5_RXP_IDMA_BASE_ADDRESS + \
+                            MLX5_RXP_CSR_WIDTH * 7)
+#define MLX5_RXP_IDMA_DWTOR (MLX5_RXP_IDMA_BASE_ADDRESS + \
+                            MLX5_RXP_CSR_WIDTH * 8)
+#define MLX5_RXP_IDMA_PADCR (MLX5_RXP_IDMA_BASE_ADDRESS + \
+                            MLX5_RXP_CSR_WIDTH * 9)
+#define MLX5_RXP_IDMA_DFCR (MLX5_RXP_IDMA_BASE_ADDRESS + \
+                           MLX5_RXP_CSR_WIDTH * 10)
+#define MLX5_RXP_IDMA_FOFLR0 (MLX5_RXP_IDMA_BASE_ADDRESS + \
+                             MLX5_RXP_CSR_WIDTH * 16)
+#define MLX5_RXP_IDMA_FOFLR1 (MLX5_RXP_IDMA_BASE_ADDRESS + \
+                             MLX5_RXP_CSR_WIDTH * 17)
+#define MLX5_RXP_IDMA_FOFLR2 (MLX5_RXP_IDMA_BASE_ADDRESS + \
+                             MLX5_RXP_CSR_WIDTH * 18)
+#define MLX5_RXP_IDMA_FUFLR0 (MLX5_RXP_IDMA_BASE_ADDRESS + \
+                             MLX5_RXP_CSR_WIDTH * 24)
+#define MLX5_RXP_IDMA_FUFLR1 (MLX5_RXP_IDMA_BASE_ADDRESS + \
+                             MLX5_RXP_CSR_WIDTH * 25)
+#define MLX5_RXP_IDMA_FUFLR2 (MLX5_RXP_IDMA_BASE_ADDRESS + \
+                             MLX5_RXP_CSR_WIDTH * 26)
+
+#define MLX5_RXP_IDMA_QCSR_BASE        (MLX5_RXP_IDMA_BASE_ADDRESS + \
+                                MLX5_RXP_CSR_WIDTH * 128)
+#define MLX5_RXP_IDMA_QCSR_RST_MSK 0x0001
+#define MLX5_RXP_IDMA_QCSR_PDONE_MSK 0x0002
+#define MLX5_RXP_IDMA_QCSR_INIT_MSK 0x0004
+#define MLX5_RXP_IDMA_QCSR_EN_MSK 0x0008
+#define MLX5_RXP_IDMA_QDPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
+                                 MLX5_RXP_CSR_WIDTH * 192)
+#define MLX5_RXP_IDMA_QTPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
+                                 MLX5_RXP_CSR_WIDTH * 256)
+#define MLX5_RXP_IDMA_QDRPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
+                                  MLX5_RXP_CSR_WIDTH * 320)
+#define MLX5_RXP_IDMA_QDRALR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
+                                  MLX5_RXP_CSR_WIDTH * 384)
+#define MLX5_RXP_IDMA_QDRAHR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
+                                  MLX5_RXP_CSR_WIDTH * 385)
+
+/* EDMA CSRs */
+#define MLX5_RXP_EDMA_ISR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 0)
+#define MLX5_RXP_EDMA_IMR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 1)
+#define MLX5_RXP_EDMA_CSR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 4)
+#define MLX5_RXP_EDMA_CSR_RST_MSK 0x0001
+#define MLX5_RXP_EDMA_CSR_PDONE_MSK 0x0002
+#define MLX5_RXP_EDMA_CSR_INIT_MSK 0x0004
+#define MLX5_RXP_EDMA_CSR_EN_MSK 0x0008
+#define MLX5_RXP_EDMA_QCR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 5)
+#define MLX5_RXP_EDMA_QCR_QAVAIL_MSK 0x00FF
+#define MLX5_RXP_EDMA_QCR_QEN_MSK 0xFF00
+#define MLX5_RXP_EDMA_DCR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 6)
+#define MLX5_RXP_EDMA_DWCTR (MLX5_RXP_EDMA_BASE_ADDRESS + \
+                            MLX5_RXP_CSR_WIDTH * 7)
+#define MLX5_RXP_EDMA_DWTOR (MLX5_RXP_EDMA_BASE_ADDRESS + \
+                            MLX5_RXP_CSR_WIDTH * 8)
+#define MLX5_RXP_EDMA_DFCR (MLX5_RXP_EDMA_BASE_ADDRESS + \
+                           MLX5_RXP_CSR_WIDTH * 10)
+#define MLX5_RXP_EDMA_FOFLR0 (MLX5_RXP_EDMA_BASE_ADDRESS + \
+                             MLX5_RXP_CSR_WIDTH * 16)
+#define MLX5_RXP_EDMA_FOFLR1 (MLX5_RXP_EDMA_BASE_ADDRESS + \
+                             MLX5_RXP_CSR_WIDTH * 17)
+#define MLX5_RXP_EDMA_FOFLR2 (MLX5_RXP_EDMA_BASE_ADDRESS + \
+                             MLX5_RXP_CSR_WIDTH * 18)
+#define MLX5_RXP_EDMA_FUFLR0 (MLX5_RXP_EDMA_BASE_ADDRESS + \
+                             MLX5_RXP_CSR_WIDTH * 24)
+#define MLX5_RXP_EDMA_FUFLR1 (MLX5_RXP_EDMA_BASE_ADDRESS +\
+                             MLX5_RXP_CSR_WIDTH * 25)
+#define MLX5_RXP_EDMA_FUFLR2 (MLX5_RXP_EDMA_BASE_ADDRESS + \
+                             MLX5_RXP_CSR_WIDTH * 26)
+
+#define MLX5_RXP_EDMA_QCSR_BASE        (MLX5_RXP_EDMA_BASE_ADDRESS + \
+                                MLX5_RXP_CSR_WIDTH * 128)
+#define MLX5_RXP_EDMA_QCSR_RST_MSK 0x0001
+#define MLX5_RXP_EDMA_QCSR_PDONE_MSK 0x0002
+#define MLX5_RXP_EDMA_QCSR_INIT_MSK 0x0004
+#define MLX5_RXP_EDMA_QCSR_EN_MSK 0x0008
+#define MLX5_RXP_EDMA_QTPTR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \
+                                 MLX5_RXP_CSR_WIDTH * 256)
+#define MLX5_RXP_EDMA_QDRPTR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \
+                                  MLX5_RXP_CSR_WIDTH * 320)
+#define MLX5_RXP_EDMA_QDRALR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \
+                                  MLX5_RXP_CSR_WIDTH * 384)
+#define MLX5_RXP_EDMA_QDRAHR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \
+                                  MLX5_RXP_CSR_WIDTH * 385)
+
+/* Main CSRs */
+#define MLX5_RXP_CSR_IDENTIFIER        (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                MLX5_RXP_CSR_WIDTH * 0)
+#define MLX5_RXP_CSR_REVISION (MLX5_RXP_CSR_BASE_ADDRESS + \
+                              MLX5_RXP_CSR_WIDTH * 1)
+#define MLX5_RXP_CSR_CAPABILITY_0 (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                  MLX5_RXP_CSR_WIDTH * 2)
+#define MLX5_RXP_CSR_CAPABILITY_1 (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                  MLX5_RXP_CSR_WIDTH * 3)
+#define MLX5_RXP_CSR_CAPABILITY_2 (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                  MLX5_RXP_CSR_WIDTH * 4)
+#define MLX5_RXP_CSR_CAPABILITY_3 (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                  MLX5_RXP_CSR_WIDTH * 5)
+#define MLX5_RXP_CSR_CAPABILITY_4 (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                  MLX5_RXP_CSR_WIDTH * 6)
+#define MLX5_RXP_CSR_CAPABILITY_5 (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                  MLX5_RXP_CSR_WIDTH * 7)
+#define MLX5_RXP_CSR_CAPABILITY_6 (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                  MLX5_RXP_CSR_WIDTH * 8)
+#define MLX5_RXP_CSR_CAPABILITY_7 (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                  MLX5_RXP_CSR_WIDTH * 9)
+#define MLX5_RXP_CSR_STATUS (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                  MLX5_RXP_CSR_WIDTH * 10)
+#define MLX5_RXP_CSR_STATUS_INIT_DONE 0x0001
+#define MLX5_RXP_CSR_STATUS_GOING 0x0008
+#define MLX5_RXP_CSR_STATUS_IDLE 0x0040
+#define MLX5_RXP_CSR_STATUS_TRACKER_OK 0x0080
+#define MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT 0x0100
+#define MLX5_RXP_CSR_FIFO_STATUS_0 (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                   MLX5_RXP_CSR_WIDTH * 11)
+#define MLX5_RXP_CSR_FIFO_STATUS_1 (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                   MLX5_RXP_CSR_WIDTH * 12)
+#define MLX5_RXP_CSR_JOB_DDOS_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                    MLX5_RXP_CSR_WIDTH * 13)
+/* 14 + 15 reserved */
+#define MLX5_RXP_CSR_CORE_CLK_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                    MLX5_RXP_CSR_WIDTH * 16)
+#define MLX5_RXP_CSR_WRITE_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                 MLX5_RXP_CSR_WIDTH * 17)
+#define MLX5_RXP_CSR_JOB_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
+                               MLX5_RXP_CSR_WIDTH * 18)
+#define MLX5_RXP_CSR_JOB_ERROR_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                     MLX5_RXP_CSR_WIDTH * 19)
+#define MLX5_RXP_CSR_JOB_BYTE_COUNT0 (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                     MLX5_RXP_CSR_WIDTH * 20)
+#define MLX5_RXP_CSR_JOB_BYTE_COUNT1 (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                     MLX5_RXP_CSR_WIDTH * 21)
+#define MLX5_RXP_CSR_RESPONSE_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                    MLX5_RXP_CSR_WIDTH * 22)
+#define MLX5_RXP_CSR_MATCH_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                 MLX5_RXP_CSR_WIDTH * 23)
+#define MLX5_RXP_CSR_CTRL (MLX5_RXP_CSR_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 24)
+#define MLX5_RXP_CSR_CTRL_INIT 0x0001
+#define MLX5_RXP_CSR_CTRL_GO 0x0008
+#define MLX5_RXP_CSR_MAX_MATCH (MLX5_RXP_CSR_BASE_ADDRESS + \
+                               MLX5_RXP_CSR_WIDTH * 25)
+#define MLX5_RXP_CSR_MAX_PREFIX        (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                MLX5_RXP_CSR_WIDTH * 26)
+#define MLX5_RXP_CSR_MAX_PRI_THREAD (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                    MLX5_RXP_CSR_WIDTH * 27)
+#define MLX5_RXP_CSR_MAX_LATENCY (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                 MLX5_RXP_CSR_WIDTH * 28)
+#define MLX5_RXP_CSR_SCRATCH_1 (MLX5_RXP_CSR_BASE_ADDRESS + \
+                               MLX5_RXP_CSR_WIDTH * 29)
+#define MLX5_RXP_CSR_CLUSTER_MASK (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                  MLX5_RXP_CSR_WIDTH * 30)
+#define MLX5_RXP_CSR_INTRA_CLUSTER_MASK (MLX5_RXP_CSR_BASE_ADDRESS + \
+                                        MLX5_RXP_CSR_WIDTH * 31)
+
+/* Runtime Rule Update CSRs */
+/* 0 + 1 reserved */
+#define MLX5_RXP_RTRU_CSR_CAPABILITY (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
+                                     MLX5_RXP_CSR_WIDTH * 2)
+/* 3-9 reserved */
+#define MLX5_RXP_RTRU_CSR_STATUS (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
+                                 MLX5_RXP_CSR_WIDTH * 10)
+#define MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE 0x0002
+#define MLX5_RXP_RTRU_CSR_STATUS_IM_INIT_DONE 0x0010
+#define MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE 0x0020
+#define MLX5_RXP_RTRU_CSR_STATUS_L2C_INIT_DONE 0x0040
+#define MLX5_RXP_RTRU_CSR_STATUS_EM_INIT_DONE 0x0080
+#define MLX5_RXP_RTRU_CSR_FIFO_STAT (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
+                                    MLX5_RXP_CSR_WIDTH * 11)
+/* 12-15 reserved */
+#define MLX5_RXP_RTRU_CSR_CHECKSUM_0 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
+                                     MLX5_RXP_CSR_WIDTH * 16)
+#define MLX5_RXP_RTRU_CSR_CHECKSUM_1 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
+                                     MLX5_RXP_CSR_WIDTH * 17)
+#define MLX5_RXP_RTRU_CSR_CHECKSUM_2 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
+                                     MLX5_RXP_CSR_WIDTH * 18)
+/* 19 + 20 reserved */
+#define MLX5_RXP_RTRU_CSR_RTRU_COUNT (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
+                                     MLX5_RXP_CSR_WIDTH * 21)
+#define MLX5_RXP_RTRU_CSR_ROF_REV (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
+                                  MLX5_RXP_CSR_WIDTH * 22)
+/* 23 reserved */
+#define MLX5_RXP_RTRU_CSR_CTRL (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
+                               MLX5_RXP_CSR_WIDTH * 24)
+#define MLX5_RXP_RTRU_CSR_CTRL_INIT 0x0001
+#define MLX5_RXP_RTRU_CSR_CTRL_GO 0x0002
+#define MLX5_RXP_RTRU_CSR_CTRL_SIP 0x0004
+#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_MASK (3 << 4)
+#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2_EM (0 << 4)
+#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2 (1 << 4)
+#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2 (2 << 4)
+#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_EM (3 << 4)
+#define MLX5_RXP_RTRU_CSR_ADDR (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
+                               MLX5_RXP_CSR_WIDTH * 25)
+#define MLX5_RXP_RTRU_CSR_DATA_0 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
+                                 MLX5_RXP_CSR_WIDTH * 26)
+#define MLX5_RXP_RTRU_CSR_DATA_1 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
+                                 MLX5_RXP_CSR_WIDTH * 27)
+/* 28-31 reserved */
+
+/* Statistics CSRs */
+#define MLX5_RXP_STATS_CSR_CLUSTER (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
+                                   MLX5_RXP_CSR_WIDTH * 0)
+#define MLX5_RXP_STATS_CSR_L2_CACHE (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
+                                    MLX5_RXP_CSR_WIDTH * 24)
+#define MLX5_RXP_STATS_CSR_MPFE_FIFO (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
+                                     MLX5_RXP_CSR_WIDTH * 25)
+#define MLX5_RXP_STATS_CSR_PE (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
+                              MLX5_RXP_CSR_WIDTH * 28)
+#define MLX5_RXP_STATS_CSR_CP (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
+                              MLX5_RXP_CSR_WIDTH * 30)
+#define MLX5_RXP_STATS_CSR_DP (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
+                              MLX5_RXP_CSR_WIDTH * 31)
+
+/* Sysmon Stats CSRs */
+#define MLX5_RXP_SYSMON_CSR_T_FPGA (MLX5_RXP_SYSMON_BASE_ADDRESS + \
+                                   MLX5_RXP_CSR_WIDTH * 0)
+#define MLX5_RXP_SYSMON_CSR_V_VCCINT (MLX5_RXP_SYSMON_BASE_ADDRESS + \
+                                     MLX5_RXP_CSR_WIDTH * 1)
+#define MLX5_RXP_SYSMON_CSR_V_VCCAUX (MLX5_RXP_SYSMON_BASE_ADDRESS + \
+                                     MLX5_RXP_CSR_WIDTH * 2)
+#define MLX5_RXP_SYSMON_CSR_T_U1 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
+                                 MLX5_RXP_CSR_WIDTH * 20)
+#define MLX5_RXP_SYSMON_CSR_I_EDG12V (MLX5_RXP_SYSMON_BASE_ADDRESS + \
+                                     MLX5_RXP_CSR_WIDTH * 21)
+#define MLX5_RXP_SYSMON_CSR_I_VCC3V3 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
+                                     MLX5_RXP_CSR_WIDTH * 22)
+#define MLX5_RXP_SYSMON_CSR_I_VCC2V5 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
+                                     MLX5_RXP_CSR_WIDTH * 23)
+#define MLX5_RXP_SYSMON_CSR_T_U2 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
+                                 MLX5_RXP_CSR_WIDTH * 28)
+#define MLX5_RXP_SYSMON_CSR_I_AUX12V (MLX5_RXP_SYSMON_BASE_ADDRESS + \
+                                     MLX5_RXP_CSR_WIDTH * 29)
+#define MLX5_RXP_SYSMON_CSR_I_VCC1V8 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
+                                     MLX5_RXP_CSR_WIDTH * 30)
+#define MLX5_RXP_SYSMON_CSR_I_VDDR3 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
+                                    MLX5_RXP_CSR_WIDTH * 31)
+
+/* In Service Programming CSRs */
+
+/* RXP-F1 and RXP-ZYNQ specific CSRs */
+#define MLX5_RXP_MQ_CP_BASE (0x0500ul)
+#define MLX5_RXP_MQ_CP_CAPABILITY_BASE (MLX5_RXP_MQ_CP_BASE + \
+                                       2 * MLX5_RXP_CSR_WIDTH)
+#define MLX5_RXP_MQ_CP_CAPABILITY_0 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \
+                                    0 * MLX5_RXP_CSR_WIDTH)
+#define MLX5_RXP_MQ_CP_CAPABILITY_1 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \
+                                    1 * MLX5_RXP_CSR_WIDTH)
+#define MLX5_RXP_MQ_CP_CAPABILITY_2 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \
+                                    2 * MLX5_RXP_CSR_WIDTH)
+#define MLX5_RXP_MQ_CP_CAPABILITY_3 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \
+                                    3 * MLX5_RXP_CSR_WIDTH)
+#define MLX5_RXP_MQ_CP_FIFO_STATUS_BASE (MLX5_RXP_MQ_CP_BASE + \
+                                        11 * MLX5_RXP_CSR_WIDTH)
+#define MLX5_RXP_MQ_CP_FIFO_STATUS_C0 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \
+                                      0 * MLX5_RXP_CSR_WIDTH)
+#define MLX5_RXP_MQ_CP_FIFO_STATUS_C1 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \
+                                      1 * MLX5_RXP_CSR_WIDTH)
+#define MLX5_RXP_MQ_CP_FIFO_STATUS_C2 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \
+                                      2 * MLX5_RXP_CSR_WIDTH)
+#define MLX5_RXP_MQ_CP_FIFO_STATUS_C3 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \
+                                      3 * MLX5_RXP_CSR_WIDTH)
+
+/* Royalty tracker / licensing related CSRs */
+#define MLX5_RXPL__CSR_IDENT (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
+                             0 * MLX5_RXP_CSR_WIDTH)
+#define MLX5_RXPL__IDENTIFIER 0x4c505852 /* MLX5_RXPL_ */
+#define MLX5_RXPL__CSR_CAPABILITY (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
+                                  2 * MLX5_RXP_CSR_WIDTH)
+#define MLX5_RXPL__TYPE_MASK 0xFF
+#define MLX5_RXPL__TYPE_NONE 0
+#define MLX5_RXPL__TYPE_MAXIM 1
+#define MLX5_RXPL__TYPE_XILINX_DNA 2
+#define MLX5_RXPL__CSR_STATUS (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
+                              10 * MLX5_RXP_CSR_WIDTH)
+#define MLX5_RXPL__CSR_IDENT_0 (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
+                               16 * MLX5_RXP_CSR_WIDTH)
+#define MLX5_RXPL__CSR_KEY_0 (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
+                             24 * MLX5_RXP_CSR_WIDTH)
+
+#endif /* _MLX5_RXP_CSRS_H_ */