net/qede/base: disable aRFS for NPAR and 100G

Disable accelerated RFS for NPAR and 100G using ECORE_MF_DISABLE_ARFS
multi function mode bit.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>

diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h
index 3b51fc2..dc09847 100644 (file)
--- a/drivers/net/qede/base/ecore.h
+++ b/drivers/net/qede/base/ecore.h
@@ -528,6 +528,8 @@ enum ecore_mf_mode_bit {
 
        /* TODO - if we ever re-utilize any of this logic, we can rename */
        ECORE_MF_UFP_SPECIFIC,
+
+       ECORE_MF_DISABLE_ARFS,
 };
 
 enum ecore_ufp_mode {

diff --git a/drivers/net/qede/base/ecore_cxt.c b/drivers/net/qede/base/ecore_cxt.c
index 3ebeb12..fed7926 100644 (file)
--- a/drivers/net/qede/base/ecore_cxt.c
+++ b/drivers/net/qede/base/ecore_cxt.c
@@ -1991,6 +1991,8 @@ enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
        switch (p_hwfn->hw_info.personality) {
        case ECORE_PCI_ETH:
                {
+               u32 count = 0;
+
                struct ecore_eth_pf_params *p_params =
                            &p_hwfn->pf_params.eth_pf_params;
 
@@ -1999,7 +2001,13 @@ enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
                ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
                                              p_params->num_cons,
                                              p_params->num_vf_cons);
-               p_hwfn->p_cxt_mngr->arfs_count = p_params->num_arfs_filters;
+
+               count = p_params->num_arfs_filters;
+
+               if (!OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS,
+                                  &p_hwfn->p_dev->mf_bits))
+                       p_hwfn->p_cxt_mngr->arfs_count = count;
+
                break;
                }
        default:

diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c
index 0568470..9511110 100644 (file)
--- a/drivers/net/qede/base/ecore_dev.c
+++ b/drivers/net/qede/base/ecore_dev.c
@@ -3501,7 +3501,8 @@ ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
                p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
                                         1 << ECORE_MF_LLH_PROTO_CLSS |
                                         1 << ECORE_MF_LL2_NON_UNICAST |
-                                        1 << ECORE_MF_INTER_PF_SWITCH;
+                                        1 << ECORE_MF_INTER_PF_SWITCH |
+                                        1 << ECORE_MF_DISABLE_ARFS;
                break;
        case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
                p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
@@ -3514,6 +3515,9 @@ ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
        DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
                p_hwfn->p_dev->mf_bits);
 
+       if (ECORE_IS_CMT(p_hwfn->p_dev))
+               p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
+
        /* It's funny since we have another switch, but it's easier
         * to throw this away in linux this way. Long term, it might be
         * better to have have getters for needed ECORE_MF_* fields,

diff --git a/drivers/net/qede/base/ecore_l2.c b/drivers/net/qede/base/ecore_l2.c
index 01fe880..e3afc8a 100644 (file)
--- a/drivers/net/qede/base/ecore_l2.c
+++ b/drivers/net/qede/base/ecore_l2.c
@@ -2072,6 +2072,9 @@ void ecore_arfs_mode_configure(struct ecore_hwfn *p_hwfn,
                               struct ecore_ptt *p_ptt,
                               struct ecore_arfs_config_params *p_cfg_params)
 {
+       if (OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS, &p_hwfn->p_dev->mf_bits))
+               return;
+
        if (p_cfg_params->arfs_enable) {
                ecore_gft_config(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
                                 p_cfg_params->tcp,

diff --git a/drivers/net/qede/qede_if.h b/drivers/net/qede/qede_if.h
index 1f97b59..bf80ccb 100644 (file)
--- a/drivers/net/qede/qede_if.h
+++ b/drivers/net/qede/qede_if.h
@@ -40,6 +40,7 @@ struct qed_dev_info {
 #define QED_MFW_VERSION_3_OFFSET       24
 
        uint32_t flash_size;
+       bool b_arfs_capable;
        bool b_inter_pf_switch;
        bool tx_switching;
        u16 mtu;

diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c
index 2f6a4dc..a0c9e03 100644 (file)
--- a/drivers/net/qede/qede_main.c
+++ b/drivers/net/qede/qede_main.c
@@ -378,6 +378,8 @@ qed_fill_dev_info(struct ecore_dev *edev, struct qed_dev_info *dev_info)
        if (IS_PF(edev)) {
                dev_info->b_inter_pf_switch =
                        OSAL_TEST_BIT(ECORE_MF_INTER_PF_SWITCH, &edev->mf_bits);
+               if (!OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS, &edev->mf_bits))
+                       dev_info->b_arfs_capable = true;
                dev_info->tx_switching = false;
 
                dev_info->smart_an = ecore_mcp_is_smart_an_supported(p_hwfn);