aesni_mb: add AES-CTR
authorFan Zhang <roy.fan.zhang@intel.com>
Fri, 3 Jun 2016 10:11:57 +0000 (11:11 +0100)
committerThomas Monjalon <thomas.monjalon@6wind.com>
Tue, 7 Jun 2016 19:46:55 +0000 (21:46 +0200)
This patch provides counter mode support to AES-NI multi-buffer library.

The following cipher algorithm is enabled:
- RTE_CRYPTO_CIPHER_AES_CTR

Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
app/test/test_cryptodev.c
doc/guides/cryptodevs/aesni_mb.rst
doc/guides/cryptodevs/overview.rst
doc/guides/rel_notes/release_16_07.rst
drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
drivers/crypto/aesni_mb/rte_aesni_mb_pmd_ops.c

index 03d6f02..45e6daa 100644 (file)
@@ -4648,6 +4648,19 @@ static struct unit_test_suite cryptodev_aesni_mb_testsuite  = {
                TEST_CASE_ST(ut_setup, ut_teardown,
                        test_AES_CBC_HMAC_SHA1_encrypt_digest_sessionless),
 
+               TEST_CASE_ST(ut_setup, ut_teardown,
+                               test_AES_CTR_encrypt_digest_case_1),
+               TEST_CASE_ST(ut_setup, ut_teardown,
+                               test_AES_CTR_encrypt_digest_case_2),
+               TEST_CASE_ST(ut_setup, ut_teardown,
+                               test_AES_CTR_encrypt_digest_case_3),
+               TEST_CASE_ST(ut_setup, ut_teardown,
+                               test_AES_CTR_digest_verify_decrypt_case_1),
+               TEST_CASE_ST(ut_setup, ut_teardown,
+                               test_AES_CTR_digest_verify_decrypt_case_2),
+               TEST_CASE_ST(ut_setup, ut_teardown,
+                               test_AES_CTR_digest_verify_decrypt_case_3),
+
                TEST_CASE_ST(ut_setup, ut_teardown,
                        test_not_in_place_crypto),
 
index fd5414d..60a8914 100644 (file)
@@ -48,6 +48,9 @@ Cipher algorithms:
 * RTE_CRYPTO_SYM_CIPHER_AES128_CBC
 * RTE_CRYPTO_SYM_CIPHER_AES192_CBC
 * RTE_CRYPTO_SYM_CIPHER_AES256_CBC
+* RTE_CRYPTO_SYM_CIPHER_AES128_CTR
+* RTE_CRYPTO_SYM_CIPHER_AES192_CTR
+* RTE_CRYPTO_SYM_CIPHER_AES256_CTR
 
 Hash algorithms:
 
index e1f33e1..4a84146 100644 (file)
@@ -55,9 +55,9 @@ Supported Cipher Algorithms
    "AES_CBC_128",x,,x,,
    "AES_CBC_192",x,,x,,
    "AES_CBC_256",x,,x,,
-   "AES_CTR_128",x,,,,
-   "AES_CTR_192",x,,,,
-   "AES_CTR_256",x,,,,
+   "AES_CTR_128",x,,x,,
+   "AES_CTR_192",x,,x,,
+   "AES_CTR_256",x,,x,,
    "SNOW3G_UEA2",x,,,,x
 
 Supported Authentication Algorithms
index 565055e..307e7c4 100644 (file)
@@ -47,6 +47,11 @@ New Features
   * Dropped specific Xen Dom0 code.
   * Dropped specific anonymous mempool code in testpmd.
 
+* **Added AES-CTR support to AESNI MB PMD.**
+
+  Now AESNI MB PMD supports 128/192/256-bit counter mode AES encryption and
+  decryption.
+
 * **Added support of AES counter mode for Intel QuickAssist devices.**
 
   Enabled support for the AES CTR algorithm for Intel QuickAssist devices.
index 31784e1..6554fc4 100644 (file)
@@ -222,6 +222,9 @@ aesni_mb_set_session_cipher_parameters(const struct aesni_mb_ops *mb_ops,
        case RTE_CRYPTO_CIPHER_AES_CBC:
                sess->cipher.mode = CBC;
                break;
+       case RTE_CRYPTO_CIPHER_AES_CTR:
+               sess->cipher.mode = CNTR;
+               break;
        default:
                MB_LOG_ERR("Unsupported cipher mode parameter");
                return -1;
index 3806a66..d3c46ac 100644 (file)
@@ -207,6 +207,26 @@ static const struct rte_cryptodev_capabilities aesni_mb_pmd_capabilities[] = {
                        }, }
                }, }
        },
+       {       /* AES CTR */
+               .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+               {.sym = {
+                       .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+                       {.cipher = {
+                               .algo = RTE_CRYPTO_CIPHER_AES_CTR,
+                               .block_size = 16,
+                               .key_size = {
+                                       .min = 16,
+                                       .max = 32,
+                                       .increment = 8
+                               },
+                               .iv_size = {
+                                       .min = 16,
+                                       .max = 16,
+                                       .increment = 0
+                               }
+                       }, }
+               }, }
+       },
        RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 };