regex/mlx5: check DevX register write
authorMichael Baum <michaelba@nvidia.com>
Wed, 18 Nov 2020 17:00:08 +0000 (17:00 +0000)
committerThomas Monjalon <thomas@monjalon.net>
Sun, 22 Nov 2020 13:50:50 +0000 (14:50 +0100)
The rxp_flush_rules function tries to read and write to the register
several times using DevX API, and when it fails the function returns an
error.
Similarly the rxp_init_eng function also tries to write to the register
several times, and if writing is failed, it returns an error too.

Both functions have one write that the function does not check if it
succeeded, overriding the return value from the write function without
using it.

Add a check for this writing, and return an error in case of failure.

Fixes: b34d816363b5 ("regex/mlx5: support rules import")
Fixes: e3dbbf718ebc ("regex/mlx5: support configuration")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
drivers/regex/mlx5/mlx5_rxp.c

index 41fbae7..ba78cc0 100644 (file)
@@ -194,6 +194,10 @@ rxp_flush_rules(struct ibv_context *ctx, struct mlx5_rxp_rof_entry *rules,
        val |= MLX5_RXP_RTRU_CSR_CTRL_GO;
        ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
                                             val);
+       if (ret) {
+               DRV_LOG(ERR, "CSR write failed!");
+               return -1;
+       }
        ret = rxp_poll_csr_for_value(ctx, &val, MLX5_RXP_RTRU_CSR_STATUS,
                                     MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE,
                                     MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE,
@@ -554,6 +558,8 @@ rxp_init_eng(struct mlx5_regex_priv *priv, uint8_t id)
                return ret;
        ctrl &= ~MLX5_RXP_CSR_CTRL_INIT;
        ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
+       if (ret)
+               return ret;
        rte_delay_us(20000);
        ret = rxp_poll_csr_for_value(ctx, &ctrl, MLX5_RXP_CSR_STATUS,
                                     MLX5_RXP_CSR_STATUS_INIT_DONE,