net/mlx5: fix VLAN inner type matching on DR/DV

The rte_flow_item_vlan has the inner_type, which is missing on
DR/DV flow engine.

By adding this support, the example testpmd commands could be:

 - matching all vlan traffic with id 2:

 testpmd> flow create 0 ingress pattern eth / vlan vid is 2 / end
          actions queue index 2 / end

 - matching all ipv4 traffic in vlan with id 2:

 testpmd> flow create 0 ingress pattern eth / vlan vid is 2
          inner_type is 0x0800 / end actions queue index 2 / end

Fixes: fc2c498ccb94 ("net/mlx5: add Direct Verbs translate items")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 536059d..a7d677f 100644 (file)
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -3469,10 +3469,6 @@ flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
 {
        const struct rte_flow_item_vlan *vlan_m = item->mask;
        const struct rte_flow_item_vlan *vlan_v = item->spec;
-       const struct rte_flow_item_vlan nic_mask = {
-               .tci = RTE_BE16(0x0fff),
-               .inner_type = RTE_BE16(0xffff),
-       };
        void *headers_m;
        void *headers_v;
        uint16_t tci_m;
@@ -3481,7 +3477,7 @@ flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
        if (!vlan_v)
                return;
        if (!vlan_m)
-               vlan_m = &nic_mask;
+               vlan_m = &rte_flow_item_vlan_mask;
        if (inner) {
                headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
                                         inner_headers);
@@ -3507,6 +3503,10 @@ flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
        MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
        MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
        MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
+       MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
+                rte_be_to_cpu_16(vlan_m->inner_type));
+       MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
+                rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
 }
 
 /**