net/mlx5: fix limit of direct rules tables number
authorDekel Peled <dekelp@mellanox.com>
Thu, 1 Aug 2019 13:22:58 +0000 (16:22 +0300)
committerRaslan Darawsheh <rasland@mellanox.com>
Tue, 6 Aug 2019 15:42:12 +0000 (17:42 +0200)
MLX5 PMD limits the number of SW steering tables to 32.
This patch updates the limit to 65535, to allow wide range of values.

Fixes: e2b4925ef7c1 ("net/mlx5: support Direct Rules E-Switch")
Cc: stable@dpdk.org
Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
drivers/net/mlx5/mlx5.h
drivers/net/mlx5/mlx5_flow_dv.c

index caf2491..f559f83 100644 (file)
@@ -513,8 +513,8 @@ struct mlx5_flow_tbl_resource {
        rte_atomic32_t refcnt; /**< Reference counter. */
 };
 
-#define MLX5_MAX_TABLES 1024
-#define MLX5_MAX_TABLES_FDB 32
+#define MLX5_MAX_TABLES 0xffff
+#define MLX5_MAX_TABLES_FDB 0xffff
 #define MLX5_GROUP_FACTOR 1
 
 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
index 9c0a261..14e70ed 100644 (file)
@@ -2817,7 +2817,7 @@ flow_dv_validate_attributes(struct rte_eth_dev *dev,
                                (error, EINVAL,
                                 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,
                                 NULL, "group must be smaller than "
-                                RTE_STR(MLX5_MAX_FDB_TABLES));
+                                RTE_STR(MLX5_MAX_TABLES_FDB));
        }
        if (!(attributes->egress ^ attributes->ingress))
                return rte_flow_error_set(error, ENOTSUP,