event/cnxk: add cn10k crypto adapter fast path

Set crypto adapter enqueue and dequeue operations for CN10K.

Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>

diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst
index 262dc15..b559009 100644 (file)
--- a/doc/guides/rel_notes/release_21_11.rst
+++ b/doc/guides/rel_notes/release_21_11.rst
@@ -68,6 +68,10 @@ New Features
   * Added Transport mode support in lookaside protocol (IPsec) for CN10K.
   * Added UDP encapsulation support in lookaside protocol (IPsec) for CN10K.
 
+* **Added support for event crypto adapter on Marvell CN10K and CN9K.**
+
+  * Added event crypto adapter OP_FORWARD mode support.
+
 
 Removed Items
 -------------

diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c
index 1aacab0..8af273a 100644 (file)
--- a/drivers/event/cnxk/cn10k_eventdev.c
+++ b/drivers/event/cnxk/cn10k_eventdev.c
@@ -316,6 +316,20 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
 #undef R
        };
 
+       const event_dequeue_t sso_hws_deq_ca[2][2][2][2][2][2] = {
+#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
+       [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_##name,
+               NIX_RX_FASTPATH_MODES
+#undef R
+       };
+
+       const event_dequeue_burst_t sso_hws_deq_ca_burst[2][2][2][2][2][2] = {
+#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
+       [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_burst_##name,
+               NIX_RX_FASTPATH_MODES
+#undef R
+       };
+
        const event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2] = {
 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
        [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_##name,
@@ -345,6 +359,21 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
 #undef R
                };
 
+       const event_dequeue_t sso_hws_deq_ca_seg[2][2][2][2][2][2] = {
+#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
+       [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_seg_##name,
+               NIX_RX_FASTPATH_MODES
+#undef R
+       };
+
+       const event_dequeue_burst_t
+               sso_hws_deq_ca_seg_burst[2][2][2][2][2][2] = {
+#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
+       [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_seg_burst_##name,
+                       NIX_RX_FASTPATH_MODES
+#undef R
+       };
+
        /* Tx modes */
        const event_tx_adapter_enqueue
                sso_hws_tx_adptr_enq[2][2][2][2][2][2] = {
@@ -377,6 +406,12 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
                        CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
                                               sso_hws_deq_tmo_seg_burst);
                }
+               if (dev->is_ca_internal_port) {
+                       CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
+                                              sso_hws_deq_ca_seg);
+                       CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
+                                              sso_hws_deq_ca_seg_burst);
+               }
        } else {
                CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
                CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
@@ -387,7 +422,14 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
                        CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
                                               sso_hws_deq_tmo_burst);
                }
+               if (dev->is_ca_internal_port) {
+                       CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
+                                              sso_hws_deq_ca);
+                       CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
+                                              sso_hws_deq_ca_burst);
+               }
        }
+       event_dev->ca_enqueue = cn10k_sso_hws_ca_enq;
 
        if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
                CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
@@ -780,7 +822,8 @@ cn10k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
        CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
        CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 
-       *caps = 0;
+       *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
+               RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
 
        return 0;
 }

diff --git a/drivers/event/cnxk/cn10k_worker.c b/drivers/event/cnxk/cn10k_worker.c
index c71aa37..975a223 100644 (file)
--- a/drivers/event/cnxk/cn10k_worker.c
+++ b/drivers/event/cnxk/cn10k_worker.c
@@ -60,3 +60,14 @@ cn10k_sso_hws_enq_fwd_burst(void *port, const struct rte_event ev[],
 
        return 1;
 }
+
+uint16_t __rte_hot
+cn10k_sso_hws_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events)
+{
+       struct cn10k_sso_hws *ws = port;
+
+       RTE_SET_USED(nb_events);
+
+       return cn10k_cpt_crypto_adapter_enqueue(ws->base + SSOW_LF_GWS_TAG,
+                                               ev->event_ptr);
+}

diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h
index 9cc0992..e5ed043 100644 (file)
--- a/drivers/event/cnxk/cn10k_worker.h
+++ b/drivers/event/cnxk/cn10k_worker.h
@@ -10,6 +10,7 @@
 #include "cnxk_ethdev.h"
 #include "cnxk_eventdev.h"
 #include "cnxk_worker.h"
+#include "cn10k_cryptodev_ops.h"
 
 #include "cn10k_ethdev.h"
 #include "cn10k_rx.h"
@@ -179,8 +180,12 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,
                    (gw.u64[0] & 0xffffffff);
 
        if (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {
-               if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
-                   RTE_EVENT_TYPE_ETHDEV) {
+               if ((flags & CPT_RX_WQE_F) &&
+                   (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
+                    RTE_EVENT_TYPE_CRYPTODEV)) {
+                       gw.u64[1] = cn10k_cpt_crypto_adapter_dequeue(gw.u64[1]);
+               } else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==
+                          RTE_EVENT_TYPE_ETHDEV) {
                        uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);
 
                        gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
@@ -282,6 +287,8 @@ uint16_t __rte_hot cn10k_sso_hws_enq_new_burst(void *port,
 uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port,
                                               const struct rte_event ev[],
                                               uint16_t nb_events);
+uint16_t __rte_hot cn10k_sso_hws_ca_enq(void *port, struct rte_event ev[],
+                                       uint16_t nb_events);
 
 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
        uint16_t __rte_hot cn10k_sso_hws_deq_##name(                           \
@@ -294,6 +301,11 @@ uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port,
        uint16_t __rte_hot cn10k_sso_hws_deq_tmo_burst_##name(                 \
                void *port, struct rte_event ev[], uint16_t nb_events,         \
                uint64_t timeout_ticks);                                       \
+       uint16_t __rte_hot cn10k_sso_hws_deq_ca_##name(                        \
+               void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
+       uint16_t __rte_hot cn10k_sso_hws_deq_ca_burst_##name(                  \
+               void *port, struct rte_event ev[], uint16_t nb_events,         \
+               uint64_t timeout_ticks);                                       \
        uint16_t __rte_hot cn10k_sso_hws_deq_seg_##name(                       \
                void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
        uint16_t __rte_hot cn10k_sso_hws_deq_seg_burst_##name(                 \
@@ -302,6 +314,11 @@ uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port,
        uint16_t __rte_hot cn10k_sso_hws_deq_tmo_seg_##name(                   \
                void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
        uint16_t __rte_hot cn10k_sso_hws_deq_tmo_seg_burst_##name(             \
+               void *port, struct rte_event ev[], uint16_t nb_events,         \
+               uint64_t timeout_ticks);                                       \
+       uint16_t __rte_hot cn10k_sso_hws_deq_ca_seg_##name(                    \
+               void *port, struct rte_event *ev, uint64_t timeout_ticks);     \
+       uint16_t __rte_hot cn10k_sso_hws_deq_ca_seg_burst_##name(              \
                void *port, struct rte_event ev[], uint16_t nb_events,         \
                uint64_t timeout_ticks);
 

diff --git a/drivers/event/cnxk/cn10k_worker_deq_ca.c b/drivers/event/cnxk/cn10k_worker_deq_ca.c
new file mode 100644 (file)
index 0000000..c90f6a9
--- /dev/null
+++ b/drivers/event/cnxk/cn10k_worker_deq_ca.c
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "cn10k_worker.h"
+#include "cnxk_eventdev.h"
+#include "cnxk_worker.h"
+
+#define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
+       uint16_t __rte_hot cn10k_sso_hws_deq_ca_##name(                        \
+               void *port, struct rte_event *ev, uint64_t timeout_ticks)      \
+       {                                                                      \
+               struct cn10k_sso_hws *ws = port;                               \
+                                                                              \
+               RTE_SET_USED(timeout_ticks);                                   \
+                                                                              \
+               if (ws->swtag_req) {                                           \
+                       ws->swtag_req = 0;                                     \
+                       cnxk_sso_hws_swtag_wait(ws->base + SSOW_LF_GWS_WQE0);  \
+                       return 1;                                              \
+               }                                                              \
+                                                                              \
+               return cn10k_sso_hws_get_work(ws, ev, flags | CPT_RX_WQE_F,    \
+                                             ws->lookup_mem);                 \
+       }                                                                      \
+                                                                              \
+       uint16_t __rte_hot cn10k_sso_hws_deq_ca_burst_##name(                  \
+               void *port, struct rte_event ev[], uint16_t nb_events,         \
+               uint64_t timeout_ticks)                                        \
+       {                                                                      \
+               RTE_SET_USED(nb_events);                                       \
+                                                                              \
+               return cn10k_sso_hws_deq_ca_##name(port, ev, timeout_ticks);   \
+       }                                                                      \
+                                                                              \
+       uint16_t __rte_hot cn10k_sso_hws_deq_ca_seg_##name(                    \
+               void *port, struct rte_event *ev, uint64_t timeout_ticks)      \
+       {                                                                      \
+               struct cn10k_sso_hws *ws = port;                               \
+                                                                              \
+               RTE_SET_USED(timeout_ticks);                                   \
+                                                                              \
+               if (ws->swtag_req) {                                           \
+                       ws->swtag_req = 0;                                     \
+                       cnxk_sso_hws_swtag_wait(ws->base + SSOW_LF_GWS_WQE0);  \
+                       return 1;                                              \
+               }                                                              \
+                                                                              \
+               return cn10k_sso_hws_get_work(                                 \
+                       ws, ev, flags | NIX_RX_MULTI_SEG_F | CPT_RX_WQE_F,     \
+                       ws->lookup_mem);                                       \
+       }                                                                      \
+                                                                              \
+       uint16_t __rte_hot cn10k_sso_hws_deq_ca_seg_burst_##name(              \
+               void *port, struct rte_event ev[], uint16_t nb_events,         \
+               uint64_t timeout_ticks)                                        \
+       {                                                                      \
+               RTE_SET_USED(nb_events);                                       \
+                                                                              \
+               return cn10k_sso_hws_deq_ca_seg_##name(port, ev,               \
+                                                      timeout_ticks);         \
+       }
+
+NIX_RX_FASTPATH_MODES
+#undef R

diff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build
index ffbc0ce..6f8b23c 100644 (file)
--- a/drivers/event/cnxk/meson.build
+++ b/drivers/event/cnxk/meson.build
@@ -27,6 +27,7 @@ sources = files(
         'cn10k_worker.c',
         'cn10k_worker_deq.c',
         'cn10k_worker_deq_burst.c',
+        'cn10k_worker_deq_ca.c',
         'cn10k_worker_deq_tmo.c',
         'cn10k_worker_tx_enq.c',
         'cn10k_worker_tx_enq_seg.c',