eal/x86: add more CPU flags

This patch adds CPU flags which will enable the detection of ISA
features available on more recent x86 based CPUs.

The CPUID leaf information can be found in
Table 1-2. "Information Returned by CPUID Instruction" of this document:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

The following CPU flags are added in this patch:
    - AVX-512 doubleword and quadword instructions.
    - AVX-512 integer fused multiply-add instructions.
    - AVX-512 conflict detection instructions.
    - AVX-512 byte and word instructions.
    - AVX-512 vector length instructions.
    - AVX-512 vector bit manipulation instructions.
    - AVX-512 vector bit manipulation 2 instructions.
    - Galois field new instructions.
    - Vector AES instructions.
    - Vector carry-less multiply instructions.
    - AVX-512 vector neural network instructions.
    - AVX-512 for bit algorithm instructions.
    - AVX-512 vector popcount instructions.
    - Cache line demote instructions.
    - Direct store instructions.
    - Direct store 64B instructions.
    - AVX-512 two register intersection instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
Acked-by: Harry van Haaren <harry.van.haaren@intel.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>

diff --git a/devtools/libabigail.abignore b/devtools/libabigail.abignore
index 0326662..587dce1 100644 (file)
--- a/devtools/libabigail.abignore
+++ b/devtools/libabigail.abignore
@@ -35,3 +35,8 @@
         type_kind = enum
         name = rte_eth_event_type
         changed_enumerators = RTE_ETH_EVENT_MAX
+; Ignore this enum update as new flags remain unknown to applications
+[suppress_type]
+       type_kind = enum
+       name = rte_cpu_flag_t
+       changed_enumerators = RTE_CPUFLAG_NUMFLAGS

diff --git a/lib/librte_eal/x86/include/rte_cpuflags.h b/lib/librte_eal/x86/include/rte_cpuflags.h
index 25ba47b..c1d2036 100644 (file)
--- a/lib/librte_eal/x86/include/rte_cpuflags.h
+++ b/lib/librte_eal/x86/include/rte_cpuflags.h
@@ -113,6 +113,25 @@ enum rte_cpu_flag_t {
        /* (EAX 80000007h) EDX features */
        RTE_CPUFLAG_INVTSC,                 /**< INVTSC */
 
+       RTE_CPUFLAG_AVX512DQ,               /**< AVX512 Doubleword and Quadword */
+       RTE_CPUFLAG_AVX512IFMA,             /**< AVX512 Integer Fused Multiply-Add */
+       RTE_CPUFLAG_AVX512CD,               /**< AVX512 Conflict Detection*/
+       RTE_CPUFLAG_AVX512BW,               /**< AVX512 Byte and Word */
+       RTE_CPUFLAG_AVX512VL,               /**< AVX512 Vector Length */
+       RTE_CPUFLAG_AVX512VBMI,             /**< AVX512 Vector Bit Manipulation */
+       RTE_CPUFLAG_AVX512VBMI2,            /**< AVX512 Vector Bit Manipulation 2 */
+       RTE_CPUFLAG_GFNI,                   /**< Galois Field New Instructions */
+       RTE_CPUFLAG_VAES,                   /**< Vector AES */
+       RTE_CPUFLAG_VPCLMULQDQ,             /**< Vector Carry-less Multiply */
+       RTE_CPUFLAG_AVX512VNNI,
+       /**< AVX512 Vector Neural Network Instructions */
+       RTE_CPUFLAG_AVX512BITALG,           /**< AVX512 Bit Algorithms */
+       RTE_CPUFLAG_AVX512VPOPCNTDQ,        /**< AVX512 Vector Popcount */
+       RTE_CPUFLAG_CLDEMOTE,               /**< Cache Line Demote */
+       RTE_CPUFLAG_MOVDIRI,                /**< Direct Store Instructions */
+       RTE_CPUFLAG_MOVDIR64B,              /**< Direct Store Instructions 64B */
+       RTE_CPUFLAG_AVX512VP2INTERSECT,     /**< AVX512 Two Register Intersection */
+
        /* The last item */
        RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
 };

diff --git a/lib/librte_eal/x86/rte_cpuflags.c b/lib/librte_eal/x86/rte_cpuflags.c
index 6492df5..30439e7 100644 (file)
--- a/lib/librte_eal/x86/rte_cpuflags.c
+++ b/lib/librte_eal/x86/rte_cpuflags.c
@@ -120,6 +120,24 @@ const struct feature_entry rte_cpu_feature_table[] = {
        FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)
 
        FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
+
+       FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)
+       FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)
+       FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)
+       FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)
+       FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)
+       FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1)
+       FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6)
+       FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8)
+       FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9)
+       FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)
+       FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)
+       FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)
+       FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX,  14)
+       FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)
+       FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27)
+       FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28)
+       FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8)
 };
 
 int