net/cxgbe: configure PCIe extended tags

Add support to configure minimum and maximum PCIe extended tag.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>

diff --git a/drivers/net/cxgbe/base/adapter.h b/drivers/net/cxgbe/base/adapter.h
index 58c6903..5e5f221 100644 (file)
--- a/drivers/net/cxgbe/base/adapter.h
+++ b/drivers/net/cxgbe/base/adapter.h
@@ -462,6 +462,7 @@ static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,
 #define PCI_CAP_LIST_NEXT       1       /* Next capability in the list */
 #define PCI_EXP_DEVCTL          0x0008  /* Device control */
 #define PCI_EXP_DEVCTL2         40      /* Device Control 2 */
+#define PCI_EXP_DEVCTL_EXT_TAG  0x0100  /* Extended Tag Field Enable */
 #define PCI_EXP_DEVCTL_PAYLOAD  0x00E0  /* Max payload */
 #define PCI_CAP_ID_VPD          0x03    /* Vital Product Data */
 #define PCI_VPD_ADDR            2       /* Address to access (15 bits!) */

diff --git a/drivers/net/cxgbe/base/t4_regs.h b/drivers/net/cxgbe/base/t4_regs.h
index 289c7e4..1100e16 100644 (file)
--- a/drivers/net/cxgbe/base/t4_regs.h
+++ b/drivers/net/cxgbe/base/t4_regs.h
@@ -420,6 +420,26 @@
 #define A_PCIE_FW 0x30b8
 #define A_PCIE_FW_PF 0x30bc
 
+#define A_PCIE_CFG2 0x3018
+
+#define S_TOTMAXTAG    0
+#define M_TOTMAXTAG    0x3U
+#define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG)
+
+#define S_T6_TOTMAXTAG    0
+#define M_T6_TOTMAXTAG    0x7U
+#define V_T6_TOTMAXTAG(x) ((x) << S_T6_TOTMAXTAG)
+
+#define A_PCIE_CMD_CFG 0x5980
+
+#define S_MINTAG       0
+#define M_MINTAG       0xffU
+#define V_MINTAG(x)    ((x) << S_MINTAG)
+
+#define S_T6_MINTAG    0
+#define M_T6_MINTAG    0xffU
+#define V_T6_MINTAG(x) ((x) << S_T6_MINTAG)
+
 /* registers for module CIM */
 #define CIM_BASE_ADDR 0x7b00
 

diff --git a/drivers/net/cxgbe/cxgbe_main.c b/drivers/net/cxgbe/cxgbe_main.c
index 4d95f5d..ac5b48f 100644 (file)
--- a/drivers/net/cxgbe/cxgbe_main.c
+++ b/drivers/net/cxgbe/cxgbe_main.c
@@ -414,6 +414,36 @@ static void print_port_info(struct adapter *adap)
        }
 }
 
+static void configure_pcie_ext_tag(struct adapter *adapter)
+{
+       u16 v;
+       int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
+
+       if (!pos)
+               return;
+
+       if (pos > 0) {
+               t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
+               v |= PCI_EXP_DEVCTL_EXT_TAG;
+               t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
+               if (is_t6(adapter->params.chip)) {
+                       t4_set_reg_field(adapter, A_PCIE_CFG2,
+                                        V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
+                                        V_T6_TOTMAXTAG(7));
+                       t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
+                                        V_T6_MINTAG(M_T6_MINTAG),
+                                        V_T6_MINTAG(8));
+               } else {
+                       t4_set_reg_field(adapter, A_PCIE_CFG2,
+                                        V_TOTMAXTAG(M_TOTMAXTAG),
+                                        V_TOTMAXTAG(3));
+                       t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
+                                        V_MINTAG(M_MINTAG),
+                                        V_MINTAG(8));
+               }
+       }
+}
+
 /*
  * Tweak configuration based on system architecture, etc.  Most of these have
  * defaults assigned to them by Firmware Configuration Files (if we're using
@@ -799,6 +829,7 @@ static int adap_init0(struct adapter *adap)
        }
        t4_init_sge_params(adap);
        t4_init_tp_params(adap);
+       configure_pcie_ext_tag(adap);
 
        adap->params.drv_memwin = MEMWIN_NIC;
        adap->flags |= FW_OK;