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net/mlx5: fix last completed built descriptor
2020-02-21 Viacheslav Ovsiienkonet/mlx5: fix last completed built descriptor
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-02-14 Viacheslav Ovsiienkoapp/testpmd: fix txonly flow generation entropy
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-02-14 Viacheslav Ovsiienkonet/mlx5: fix legacy multi-packet write session
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-02-06 Viacheslav Ovsiienkotest/mbuf: check pinned external buffer
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-02-06 Viacheslav Ovsiienkombuf: fix pinned memory function style
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-02-05 Viacheslav Ovsiienkonet/mlx5: add no-inline Tx flag
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-20 Viacheslav Ovsiienkonet/mlx5: engage free on completion queue
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-20 Viacheslav Ovsiienkonet/mlx5: add free on completion queue
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-20 Viacheslav Ovsiienkonet/mlx5: update Tx error handling routine
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-20 Viacheslav Ovsiienkonet/mlx5: move Tx complete request routine
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-20 Viacheslav Ovsiienkonet/mlx5: allow allocated mbuf with external buffer
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-20 Viacheslav Ovsiienkoapp/testpmd: add mempool with external data buffers
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-20 Viacheslav Ovsiienkombuf: create pool with external memory buffers
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-20 Viacheslav Ovsiienkombuf: detach mbuf with pinned external buffer
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-20 Viacheslav Ovsiienkombuf: introduce routine to get private mbuf pool flags
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-17 Viacheslav Ovsiienkonet/mlx5: fix metadata item endianness conversion
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-17 Viacheslav Ovsiienkonet/mlx5: fix matcher field usage for metadata entities
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-17 Viacheslav Ovsiienkonet/mlx5: fix shared metadata matcher field setup
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-17 Viacheslav Ovsiienkoethdev: fix switching domain allocation
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-17 Viacheslav Ovsiienkonet/mlx5: fix doorbell register offset type
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-17 Viacheslav Ovsiienkonet/mlx5: fix Tx burst routines set
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-27 Viacheslav Ovsiienkonet/mlx5: fix legacy inline multi-packet performance
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-27 Viacheslav Ovsiienkonet/mlx5: fix legacy non-inline multi-packet performance
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-27 Viacheslav Ovsiienkonet/mlx5: fix default mark copy flow
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-26 Viacheslav Ovsiienkonet/mlx5: fix legacy multi-packet Tx descriptors
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-26 Viacheslav Ovsiienkodoc: update metadata feature in mlx5 guide
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-26 Viacheslav Ovsiienkonet/mlx5: fix getting metadata register for E-Switch...
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-20 Viacheslav Ovsiienkonet/mlx5: fix assert in Tx inline settings
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-20 Viacheslav Ovsiienkonet/mlx5: fix port action for LAG
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-20 Viacheslav Ovsiienkonet/mlx5: fix Tx doorbell write memory barrier
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-20 Viacheslav Ovsiienkonet/mlx5: fix vport index in port action
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-20 Viacheslav Ovsiienkonet/mlx5: fix vport id in port id action
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-20 Viacheslav Ovsiienkonet/mlx5: fix environment variable recovery
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-20 Viacheslav Ovsiienkonet/mlx5: fix suffix flow creation in metadata split
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-20 Viacheslav Ovsiienkonet/mlx5: fix query host adapter attributes
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: control transmit doorbell register mapping
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: fix asserts for multi-segment Tx offload...
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: add metadata register copy table
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: split Rx flows to provide metadata copy
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: introduce flow splitters chain
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: add metadata support to Rx datapath
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: extend flow metadata support
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: extend flow mark support
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: support flow tag
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: update metadata register ID query
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: check maximum modify actions number
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: adjust shared register according to mask
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: add devarg for extensive metadata support
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: check metadata registers availability
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: rename structure and function
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: update meta register matcher set
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: update flow functions
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: refactor flow structure
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: add metadata register copy
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: update modify header action translator
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: convert internal tag endianness
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-08 Viacheslav Ovsiienkoethdev: move egress metadata to dynamic field
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-08 Viacheslav Ovsiienkoethdev: extend flow metadata
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-08 Viacheslav Ovsiienkoethdev: add flow tag
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-23 Viacheslav Ovsiienkonet/mlx5: fix Tx packets statistics
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-08 Viacheslav Ovsiienkonet/mlx5: fix direct call to rdma-core library
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-08 Viacheslav Ovsiienkonet/mlx5: fix device scan within switch domain
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-08 Viacheslav Ovsiienkonet/mlx5: adjust inline setting for large Tx queue...
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-08 Viacheslav Ovsiienkonet/mlx5: check sibling device configurations mismatch
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-08 Viacheslav Ovsiienkonet/mlx5: update switch port id in bonding configuration
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-08 Viacheslav Ovsiienkonet/mlx5: extend switch domain searching range
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-08 Viacheslav Ovsiienkonet/mlx5: update source and destination vport translations
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-08 Viacheslav Ovsiienkonet/mlx5: elaborate E-Switch port parameters query
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-07 Viacheslav Ovsiienkonet/mlx5: query vport index match mode and parameters
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-07 Viacheslav Ovsiienkonet/mlx5: check kernel support for VF LAG bonding
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-07 Viacheslav Ovsiienkonet/mlx5: generate bonding device name
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-07 Viacheslav Ovsiienkonet/mlx5: add VF LAG mode bonding device recognition
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-07 Viacheslav Ovsiienkonet/mlx5: allocate device list explicitly
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-07 Viacheslav Ovsiienkonet/mlx5: update PCI address retrieving routine
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-07 Viacheslav Ovsiienkonet/mlx5: move backing PCI device to private context
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-07 Viacheslav Ovsiienkonet/mlx5: fix ConnectX-6 VF type recognition
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-07 Viacheslav Ovsiienkonet/mlx5: fix BlueField VF type recognition
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-07 Viacheslav Ovsiienkonet/mlx5: fix UAR remap initialization for 32-bit systems
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-09-20 Viacheslav Ovsiienkonet/mlx5: fix netlink RDMA socket callback routine
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-09-20 Viacheslav Ovsiienkonet/mlx5: fix Tx descriptor with VLAN insertions
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-08-07 Viacheslav Ovsiienkonet/mlx5: fix completion request for multi-segment
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-08-08 Viacheslav Ovsiienkodoc: add limitation with mlx5 Tx inline settings
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-08-07 Viacheslav Ovsiienkodoc: update Tx inline settings in mlx5 guide
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-08-06 Viacheslav Ovsiienkonet/mlx5: fix memory event callback list
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-08-06 Viacheslav Ovsiienkonet/mlx5: fix completion queue overflow for large burst
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-08-06 Viacheslav Ovsiienkonet/mlx5: fix packet size inline settings
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-08-06 Viacheslav Ovsiienkonet/mlx5: fix inline data settings
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-08-06 Viacheslav Ovsiienkonet/mlx5: fix completion queue drain loop
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-08-06 Viacheslav Ovsiienkonet/mlx5: fix inline data length assert
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-08-06 Viacheslav Ovsiienkonet/mlx5: fix default minimal data inline
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-08-06 Viacheslav Ovsiienkonet/mlx5: add workaround for VLAN in virtual machine
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-07-29 Viacheslav Ovsiienkonet/mlx5: fix Tx completion request generation
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-07-29 Viacheslav Ovsiienkonet/mlx5: fix ConnectX-4LX minimal inline data limit
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-07-29 Viacheslav Ovsiienkonet/mlx5: fix Tx completion descriptors fetching loop
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-07-23 Viacheslav Ovsiienkonet/mlx5: revert Netlink socket sharing
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-07-23 Viacheslav Ovsiienkonet/mlx5: cache associated network device index
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-07-23 Viacheslav Ovsiienkonet/mlx5: report max number of mbuf segments
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-07-23 Viacheslav Ovsiienkonet/mlx5: implement Tx burst template
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-07-23 Viacheslav Ovsiienkonet/mlx5: introduce Tx burst routine template
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-07-23 Viacheslav Ovsiienkonet/mlx5: add Tx configuration and setup
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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