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net/ice: fix queue config in DCF
2021-08-29 Jie Wangnet/ice: fix queue config in DCF
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-29 Yu Wenjunnet/ice: fix deadlock on flow query
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-29 Wenjun Wunet/ice: fix default RSS hash for IP fragments
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-29 Wenjun Wunet/iavf: fix default RSS hash for IP fragments
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-29 Wenjun Wunet/iavf: support flow director for IPv6 fragments
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-29 Wenjun Wunet/iavf: fix flow director L3 field for IPv4 fragments
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-29 Qi Zhangnet/ice: fix RXDID default value in DCF
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-29 Haiyue Wangnet/ice: fix memzone leak after device init failure
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-29 Wenjun Wunet/ice/base: support flow director for IPv6 fragments
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-15 Ting Xunet/ice: fix bandwidth config size in memory copy
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-15 Simei Sunet/ice: fix max entry number for ACL normal priority
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: increase maximum TCAM/PTG per profile
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: fix typo in comment
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: rename and add setter for unicast MAC...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: support flow director for GTPU UL/DL...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: enable jumbo frame during HW init
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: support RSS for IPv4/L4 checksum
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: support flow director for GTPoGRE
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: enable NVM update reset capabilities
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: support RSS for GTPoGRE
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: support flow director for GTPU EH inner...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: support RSS for GRE tunnel
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: support flow director for GRE tunnel
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: support TC nodes PIR configuration
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: refine MAC rule adding
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add new AQ description
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: implement firmware debug dump
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add E810T check function
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: support starting PHY in bypass mode
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: clarify comments on checking PFC mode
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: implement Vernier calibration for E822
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: print human-friendly PHY types
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add accessors to get/set time reference
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add clock initialization function
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add timestamp masks
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: change dummy packets with VLAN
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add ethertype IPv6 check for dummy packet
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add functions for device clock control
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add IEEE 1588 capability probing
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-10 Ruifeng Wangnet/i40e: fix clang warning on non-x86
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-10 Wenjun Wunet/ice: fix priority of DCF switch rule
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-10 Feifei Wangnet/i40e: reduce L1 cache misses in NEON Rx
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2021-08-10 Feifei Wangnet/i40e: increase readability in NEON Rx
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2021-08-10 Feifei Wangdrivers/net: fix vector Rx comments
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2021-08-10 Feifei Wangdrivers/net: fix typo in vector Rx comment
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2021-08-02 Qi Zhangdoc: update matching versions in ice guide
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-27 Alvin Zhangnet/iavf: relax RSS virtual channel commands
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-25 Xiaoyun Linet/iavf: fix Tx threshold check
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2021-07-21 Ting Xunet/ice: fix L3 RSS with IPv6 fragment
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-21 Ting Xunet/ice: clear QoS bandwidth on DCF close
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-16 Ting Xunet/iavf: fix bandwidth unit in TM capability query
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-16 Alvin Zhangnet/ice/base: support MPLS ethertype switch filter
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-16 Simei Sunet/ice: fix ESP flow director with SPI as input set
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-16 Wenjun Wunet/ice/base: revert change of first profile mask
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-16 Joyce Kongnet/i40e: replace SMP barrier with thread fence in Rx
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-16 Wenjun Wunet/iavf: support default RSS for IP fragment
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-16 Lingyu Liunet/iavf: support RSS for GTPoGRE
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-16 Lingyu Liunet/iavf: support flow director for GTPoGRE
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-16 Lingyu Liunet/iavf: support flow pattern for GTPoGRE
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-09 Dapeng Yunet/ixgbe: fix flow entry access after freeing
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2021-07-09 Joyce Kongnet/i40e: fix descriptor scan on Arm
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2021-07-09 Dapeng Yunet/ice: fix VXLAN flow director creation
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-09 Dapeng Yunet/ice/base: fix VXLAN flow director creation
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-09 Ting Xunet/ice: support QoS bandwidth config after VF reset...
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-09 Ting Xunet/ice: fix check for QoS in DCF
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-09 Wenjun Wunet/iavf: simplify flow director rules for IP fragment
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-09 Wenjun Wunet/ice: simplify flow director rules for IP fragment
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-09 David Marchandnet/ice: fix memzone leak when firmware is missing
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2021-07-06 Wenjun Wunet/ice: support default RSS for IP fragment packet
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-06 Dapeng Yunet/i40e: fix multi-process shared data
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-06 Feifei Wangnet/i40e: improve vector Tx performance
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2021-07-06 Feifei Wangnet/i40e: improve scalar Tx performance
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2021-07-06 Haiyue Wangnet/ice: add option for setting HW debug mask
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-06 Beilei Xingnet/i40e: fix flow director input set conflict
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2021-07-06 Ting Xunet/iavf: check Tx packet with correct UP and queue
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-06 Ting Xunet/iavf: query QoS capabilities and set queue TC mapping
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-06 Ting Xunet/ice: support QoS config VF bandwidth in DCF
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-06 Ting Xunet/ice: support DCF link status event handling
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-06 Ting Xunet/ice/base: support DCF query port ETS adminq
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-06 Ting Xucommon/iavf: support ETS-based QoS offload configuration
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-06 Wenzhuo Lunet/ice: add AVX2 offload Rx
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2021-07-06 Wenzhuo Lunet/ice: add AVX2 offload Tx
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2021-07-04 Wenjun Wunet/ice/base: fix first profile mask
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-04 Alvin Zhangnet/i40e: fix L2 payload RSS mask input set
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2021-07-04 Steve Yangnet/i40e: fix available RSS hash function
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2021-07-04 Tudor Corneanet/ice: fix overflow in maximum packet length config
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-04 Dapeng Yunet/i40e: fix data path selection in secondary process
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-04 Wenjun Wunet/iavf: support flow director for GRE tunnel packet
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-04 Wenjun Wunet/iavf: support RSS for GRE tunnel packet
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-04 Wenjun Wucommon/iavf: add GRE header type
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-04 Wenjun Wunet/iavf: support flow pattern for GRE
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-04 Simei Sunet/ice: support ESP/NATT flow director to match outer IP
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-04 Simei Sunet/ice/base: support ESP flow director to match outer IP
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-07-04 Simei Sunet/iavf: support ESP flow director to match outer IP
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-16 Ting Xunet/ice/base: fix ptype bitmap for IP fragment
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-16 Wenjun Wunet/ice: fix RSS for L2 packet
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-10 Beilei Xingnet/iavf: fix scalar Rx
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2021-06-10 Dapeng Yunet/i40e: fix use after free in FDIR release
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-10 Ting Xunet/ice: fix FDIR flow type for IPv4 fragment
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-10 Qi Zhangnet/ice: fix data path in secondary process
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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