1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_82599.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
39 #ident "$Id: ixgbe_82599.c,v 1.301 2012/11/08 11:33:27 jtkirshe Exp $"
41 #define IXGBE_82599_MAX_TX_QUEUES 128
42 #define IXGBE_82599_MAX_RX_QUEUES 128
43 #define IXGBE_82599_RAR_ENTRIES 128
44 #define IXGBE_82599_MC_TBL_SIZE 128
45 #define IXGBE_82599_VFT_TBL_SIZE 128
46 #define IXGBE_82599_RX_PB_SIZE 512
48 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
49 ixgbe_link_speed speed,
51 bool autoneg_wait_to_complete);
52 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
53 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
54 u16 offset, u16 *data);
55 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
56 u16 words, u16 *data);
58 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
60 struct ixgbe_mac_info *mac = &hw->mac;
62 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
64 /* enable the laser control functions for SFP+ fiber */
65 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
66 mac->ops.disable_tx_laser =
67 &ixgbe_disable_tx_laser_multispeed_fiber;
68 mac->ops.enable_tx_laser =
69 &ixgbe_enable_tx_laser_multispeed_fiber;
70 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
73 mac->ops.disable_tx_laser = NULL;
74 mac->ops.enable_tx_laser = NULL;
75 mac->ops.flap_tx_laser = NULL;
78 if (hw->phy.multispeed_fiber) {
79 /* Set up dual speed SFP+ support */
80 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
82 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
83 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
84 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
85 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
86 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
88 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
94 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
95 * @hw: pointer to hardware structure
97 * Initialize any function pointers that were not able to be
98 * set during init_shared_code because the PHY/SFP type was
99 * not known. Perform the SFP init if necessary.
102 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
104 struct ixgbe_mac_info *mac = &hw->mac;
105 struct ixgbe_phy_info *phy = &hw->phy;
106 s32 ret_val = IXGBE_SUCCESS;
108 DEBUGFUNC("ixgbe_init_phy_ops_82599");
110 /* Identify the PHY or SFP module */
111 ret_val = phy->ops.identify(hw);
112 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
113 goto init_phy_ops_out;
115 /* Setup function pointers based on detected SFP module and speeds */
116 ixgbe_init_mac_link_ops_82599(hw);
117 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
118 hw->phy.ops.reset = NULL;
120 /* If copper media, overwrite with copper function pointers */
121 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
122 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
123 mac->ops.get_link_capabilities =
124 &ixgbe_get_copper_link_capabilities_generic;
127 /* Set necessary function pointers based on phy type */
128 switch (hw->phy.type) {
130 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
131 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
132 phy->ops.get_firmware_version =
133 &ixgbe_get_phy_firmware_version_tnx;
142 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
144 s32 ret_val = IXGBE_SUCCESS;
145 u16 list_offset, data_offset, data_value;
146 bool got_lock = false;
148 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
150 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
151 ixgbe_init_mac_link_ops_82599(hw);
153 hw->phy.ops.reset = NULL;
155 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
157 if (ret_val != IXGBE_SUCCESS)
160 /* PHY config will finish before releasing the semaphore */
161 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
162 IXGBE_GSSR_MAC_CSR_SM);
163 if (ret_val != IXGBE_SUCCESS) {
164 ret_val = IXGBE_ERR_SWFW_SYNC;
168 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
169 while (data_value != 0xffff) {
170 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
171 IXGBE_WRITE_FLUSH(hw);
172 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
175 /* Release the semaphore */
176 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
177 /* Delay obtaining semaphore again to allow FW access */
178 msec_delay(hw->eeprom.semaphore_delay);
180 /* Need SW/FW semaphore around AUTOC writes if LESM on,
181 * likewise reset_pipeline requires lock as it also writes
184 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
185 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
186 IXGBE_GSSR_MAC_CSR_SM);
187 if (ret_val != IXGBE_SUCCESS) {
188 ret_val = IXGBE_ERR_SWFW_SYNC;
195 /* Restart DSP and set SFI mode */
196 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
197 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL));
199 ret_val = ixgbe_reset_pipeline_82599(hw);
202 hw->mac.ops.release_swfw_sync(hw,
203 IXGBE_GSSR_MAC_CSR_SM);
208 DEBUGOUT("sfp module setup not complete\n");
209 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
220 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
221 * @hw: pointer to hardware structure
223 * Initialize the function pointers and assign the MAC type for 82599.
224 * Does not touch the hardware.
227 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
229 struct ixgbe_mac_info *mac = &hw->mac;
230 struct ixgbe_phy_info *phy = &hw->phy;
231 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
234 DEBUGFUNC("ixgbe_init_ops_82599");
236 ret_val = ixgbe_init_phy_ops_generic(hw);
237 ret_val = ixgbe_init_ops_generic(hw);
240 phy->ops.identify = &ixgbe_identify_phy_82599;
241 phy->ops.init = &ixgbe_init_phy_ops_82599;
244 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
245 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
246 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
247 mac->ops.get_supported_physical_layer =
248 &ixgbe_get_supported_physical_layer_82599;
249 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
250 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
251 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
252 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
253 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
254 mac->ops.start_hw = &ixgbe_start_hw_82599;
255 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
256 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
257 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
258 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
259 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
261 /* RAR, Multicast, VLAN */
262 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
263 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
264 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
265 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
266 mac->rar_highwater = 1;
267 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
268 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
269 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
270 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
271 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
272 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
273 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
276 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
277 mac->ops.check_link = &ixgbe_check_mac_link_generic;
278 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
279 ixgbe_init_mac_link_ops_82599(hw);
281 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
282 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
283 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
284 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
285 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
286 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
287 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
289 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
290 IXGBE_FWSM_MODE_MASK) ? true : false;
292 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
295 eeprom->ops.read = &ixgbe_read_eeprom_82599;
296 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
298 /* Manageability interface */
299 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
302 mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
308 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
309 * @hw: pointer to hardware structure
310 * @speed: pointer to link speed
311 * @negotiation: true when autoneg or autotry is enabled
313 * Determines the link capabilities by reading the AUTOC register.
315 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
316 ixgbe_link_speed *speed,
319 s32 status = IXGBE_SUCCESS;
322 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
325 /* Check if 1G SFP module. */
326 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
327 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
328 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
329 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
330 *speed = IXGBE_LINK_SPEED_1GB_FULL;
336 * Determine link capabilities based on the stored value of AUTOC,
337 * which represents EEPROM defaults. If AUTOC value has not
338 * been stored, use the current register values.
340 if (hw->mac.orig_link_settings_stored)
341 autoc = hw->mac.orig_autoc;
343 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
345 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
346 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
347 *speed = IXGBE_LINK_SPEED_1GB_FULL;
348 *negotiation = false;
351 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
352 *speed = IXGBE_LINK_SPEED_10GB_FULL;
353 *negotiation = false;
356 case IXGBE_AUTOC_LMS_1G_AN:
357 *speed = IXGBE_LINK_SPEED_1GB_FULL;
361 case IXGBE_AUTOC_LMS_10G_SERIAL:
362 *speed = IXGBE_LINK_SPEED_10GB_FULL;
363 *negotiation = false;
366 case IXGBE_AUTOC_LMS_KX4_KX_KR:
367 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
368 *speed = IXGBE_LINK_SPEED_UNKNOWN;
369 if (autoc & IXGBE_AUTOC_KR_SUPP)
370 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
371 if (autoc & IXGBE_AUTOC_KX4_SUPP)
372 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
373 if (autoc & IXGBE_AUTOC_KX_SUPP)
374 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
378 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
379 *speed = IXGBE_LINK_SPEED_100_FULL;
380 if (autoc & IXGBE_AUTOC_KR_SUPP)
381 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
382 if (autoc & IXGBE_AUTOC_KX4_SUPP)
383 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
384 if (autoc & IXGBE_AUTOC_KX_SUPP)
385 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
389 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
390 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
391 *negotiation = false;
395 status = IXGBE_ERR_LINK_SETUP;
400 if (hw->phy.multispeed_fiber) {
401 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
402 IXGBE_LINK_SPEED_1GB_FULL;
411 * ixgbe_get_media_type_82599 - Get media type
412 * @hw: pointer to hardware structure
414 * Returns the media type (fiber, copper, backplane)
416 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
418 enum ixgbe_media_type media_type;
420 DEBUGFUNC("ixgbe_get_media_type_82599");
422 /* Detect if there is a copper PHY attached. */
423 switch (hw->phy.type) {
424 case ixgbe_phy_cu_unknown:
426 media_type = ixgbe_media_type_copper;
432 switch (hw->device_id) {
433 case IXGBE_DEV_ID_82599_KX4:
434 case IXGBE_DEV_ID_82599_KX4_MEZZ:
435 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
436 case IXGBE_DEV_ID_82599_KR:
437 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
438 case IXGBE_DEV_ID_82599_XAUI_LOM:
439 /* Default device ID is mezzanine card KX/KX4 */
440 media_type = ixgbe_media_type_backplane;
442 case IXGBE_DEV_ID_82599_SFP:
443 case IXGBE_DEV_ID_82599_SFP_FCOE:
444 case IXGBE_DEV_ID_82599_SFP_EM:
445 case IXGBE_DEV_ID_82599_SFP_SF2:
446 case IXGBE_DEV_ID_82599_SFP_SF_QP:
447 case IXGBE_DEV_ID_82599EN_SFP:
448 #ifdef RTE_NIC_BYPASS
449 case IXGBE_DEV_ID_82599_BYPASS:
451 media_type = ixgbe_media_type_fiber;
453 case IXGBE_DEV_ID_82599_CX4:
454 media_type = ixgbe_media_type_cx4;
456 case IXGBE_DEV_ID_82599_T3_LOM:
457 media_type = ixgbe_media_type_copper;
460 media_type = ixgbe_media_type_unknown;
468 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
469 * @hw: pointer to hardware structure
471 * Disables link during D3 power down sequence.
474 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
476 u32 autoc2_reg, fwsm;
479 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
480 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
482 /* Check to see if MNG FW could be enabled */
483 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
485 if (((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) &&
487 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
488 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
489 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
490 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
495 * ixgbe_start_mac_link_82599 - Setup MAC link settings
496 * @hw: pointer to hardware structure
497 * @autoneg_wait_to_complete: true when waiting for completion is needed
499 * Configures link settings based on values in the ixgbe_hw struct.
500 * Restarts the link. Performs autonegotiation if needed.
502 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
503 bool autoneg_wait_to_complete)
508 s32 status = IXGBE_SUCCESS;
509 bool got_lock = false;
511 DEBUGFUNC("ixgbe_start_mac_link_82599");
514 /* reset_pipeline requires us to hold this lock as it writes to
517 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
518 status = hw->mac.ops.acquire_swfw_sync(hw,
519 IXGBE_GSSR_MAC_CSR_SM);
520 if (status != IXGBE_SUCCESS)
527 ixgbe_reset_pipeline_82599(hw);
530 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
532 /* Only poll for autoneg to complete if specified to do so */
533 if (autoneg_wait_to_complete) {
534 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
535 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
536 IXGBE_AUTOC_LMS_KX4_KX_KR ||
537 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
538 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
539 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
540 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
541 links_reg = 0; /* Just in case Autoneg time = 0 */
542 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
543 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
544 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
548 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
549 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
550 DEBUGOUT("Autoneg did not complete.\n");
555 /* Add delay to filter out noises during initial link setup */
563 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
564 * @hw: pointer to hardware structure
566 * The base drivers may require better control over SFP+ module
567 * PHY states. This includes selectively shutting down the Tx
568 * laser on the PHY, effectively halting physical link.
570 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
572 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
574 /* Disable tx laser; allow 100us to go dark per spec */
575 esdp_reg |= IXGBE_ESDP_SDP3;
576 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
577 IXGBE_WRITE_FLUSH(hw);
582 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
583 * @hw: pointer to hardware structure
585 * The base drivers may require better control over SFP+ module
586 * PHY states. This includes selectively turning on the Tx
587 * laser on the PHY, effectively starting physical link.
589 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
591 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
593 /* Enable tx laser; allow 100ms to light up */
594 esdp_reg &= ~IXGBE_ESDP_SDP3;
595 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
596 IXGBE_WRITE_FLUSH(hw);
601 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
602 * @hw: pointer to hardware structure
604 * When the driver changes the link speeds that it can support,
605 * it sets autotry_restart to true to indicate that we need to
606 * initiate a new autotry session with the link partner. To do
607 * so, we set the speed then disable and re-enable the tx laser, to
608 * alert the link partner that it also needs to restart autotry on its
609 * end. This is consistent with true clause 37 autoneg, which also
610 * involves a loss of signal.
612 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
614 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
616 if (hw->mac.autotry_restart) {
617 ixgbe_disable_tx_laser_multispeed_fiber(hw);
618 ixgbe_enable_tx_laser_multispeed_fiber(hw);
619 hw->mac.autotry_restart = false;
624 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
625 * @hw: pointer to hardware structure
626 * @speed: new link speed
627 * @autoneg: true if autonegotiation enabled
628 * @autoneg_wait_to_complete: true when waiting for completion is needed
630 * Set the link speed in the AUTOC register and restarts link.
632 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
633 ixgbe_link_speed speed, bool autoneg,
634 bool autoneg_wait_to_complete)
636 s32 status = IXGBE_SUCCESS;
637 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
638 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
640 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
642 bool link_up = false;
645 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
647 /* Mask off requested but non-supported speeds */
648 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);
649 if (status != IXGBE_SUCCESS)
655 * Try each speed one by one, highest priority first. We do this in
656 * software because 10gb fiber doesn't support speed autonegotiation.
658 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
660 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
662 /* If we already have link at this speed, just jump out */
663 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
664 if (status != IXGBE_SUCCESS)
667 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
670 /* Set the module link speed */
671 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
672 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
673 IXGBE_WRITE_FLUSH(hw);
675 /* Allow module to change analog characteristics (1G->10G) */
678 status = ixgbe_setup_mac_link_82599(hw,
679 IXGBE_LINK_SPEED_10GB_FULL,
681 autoneg_wait_to_complete);
682 if (status != IXGBE_SUCCESS)
685 /* Flap the tx laser if it has not already been done */
686 ixgbe_flap_tx_laser(hw);
689 * Wait for the controller to acquire link. Per IEEE 802.3ap,
690 * Section 73.10.2, we may have to wait up to 500ms if KR is
691 * attempted. 82599 uses the same timing for 10g SFI.
693 for (i = 0; i < 5; i++) {
694 /* Wait for the link partner to also set speed */
697 /* If we have link, just jump out */
698 status = ixgbe_check_link(hw, &link_speed,
700 if (status != IXGBE_SUCCESS)
708 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
710 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
711 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
713 /* If we already have link at this speed, just jump out */
714 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
715 if (status != IXGBE_SUCCESS)
718 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
721 /* Set the module link speed */
722 esdp_reg &= ~IXGBE_ESDP_SDP5;
723 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
724 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
725 IXGBE_WRITE_FLUSH(hw);
727 /* Allow module to change analog characteristics (10G->1G) */
730 status = ixgbe_setup_mac_link_82599(hw,
731 IXGBE_LINK_SPEED_1GB_FULL,
733 autoneg_wait_to_complete);
734 if (status != IXGBE_SUCCESS)
737 /* Flap the tx laser if it has not already been done */
738 ixgbe_flap_tx_laser(hw);
740 /* Wait for the link partner to also set speed */
743 /* If we have link, just jump out */
744 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
745 if (status != IXGBE_SUCCESS)
753 * We didn't get link. Configure back to the highest speed we tried,
754 * (if there was more than one). We call ourselves back with just the
755 * single highest speed that the user requested.
758 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
759 highest_link_speed, autoneg, autoneg_wait_to_complete);
762 /* Set autoneg_advertised value based on input link speed */
763 hw->phy.autoneg_advertised = 0;
765 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
766 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
768 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
769 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
775 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
776 * @hw: pointer to hardware structure
777 * @speed: new link speed
778 * @autoneg: true if autonegotiation enabled
779 * @autoneg_wait_to_complete: true when waiting for completion is needed
781 * Implements the Intel SmartSpeed algorithm.
783 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
784 ixgbe_link_speed speed, bool autoneg,
785 bool autoneg_wait_to_complete)
787 s32 status = IXGBE_SUCCESS;
788 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
790 bool link_up = false;
791 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
793 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
795 /* Set autoneg_advertised value based on input link speed */
796 hw->phy.autoneg_advertised = 0;
798 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
799 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
801 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
802 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
804 if (speed & IXGBE_LINK_SPEED_100_FULL)
805 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
808 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
809 * autoneg advertisement if link is unable to be established at the
810 * highest negotiated rate. This can sometimes happen due to integrity
811 * issues with the physical media connection.
814 /* First, try to get link with full advertisement */
815 hw->phy.smart_speed_active = false;
816 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
817 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
818 autoneg_wait_to_complete);
819 if (status != IXGBE_SUCCESS)
823 * Wait for the controller to acquire link. Per IEEE 802.3ap,
824 * Section 73.10.2, we may have to wait up to 500ms if KR is
825 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
826 * Table 9 in the AN MAS.
828 for (i = 0; i < 5; i++) {
831 /* If we have link, just jump out */
832 status = ixgbe_check_link(hw, &link_speed, &link_up,
834 if (status != IXGBE_SUCCESS)
843 * We didn't get link. If we advertised KR plus one of KX4/KX
844 * (or BX4/BX), then disable KR and try again.
846 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
847 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
850 /* Turn SmartSpeed on to disable KR support */
851 hw->phy.smart_speed_active = true;
852 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
853 autoneg_wait_to_complete);
854 if (status != IXGBE_SUCCESS)
858 * Wait for the controller to acquire link. 600ms will allow for
859 * the AN link_fail_inhibit_timer as well for multiple cycles of
860 * parallel detect, both 10g and 1g. This allows for the maximum
861 * connect attempts as defined in the AN MAS table 73-7.
863 for (i = 0; i < 6; i++) {
866 /* If we have link, just jump out */
867 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
868 if (status != IXGBE_SUCCESS)
875 /* We didn't get link. Turn SmartSpeed back off. */
876 hw->phy.smart_speed_active = false;
877 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
878 autoneg_wait_to_complete);
881 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
882 DEBUGOUT("Smartspeed has downgraded the link speed "
883 "from the maximum advertised\n");
888 * ixgbe_setup_mac_link_82599 - Set MAC link speed
889 * @hw: pointer to hardware structure
890 * @speed: new link speed
891 * @autoneg: true if autonegotiation enabled
892 * @autoneg_wait_to_complete: true when waiting for completion is needed
894 * Set the link speed in the AUTOC register and restarts link.
896 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
897 ixgbe_link_speed speed, bool autoneg,
898 bool autoneg_wait_to_complete)
900 s32 status = IXGBE_SUCCESS;
901 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
902 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
903 u32 start_autoc = autoc;
905 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
906 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
907 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
910 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
911 bool got_lock = false;
913 DEBUGFUNC("ixgbe_setup_mac_link_82599");
915 /* Check to see if speed passed in is supported. */
916 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
920 speed &= link_capabilities;
922 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
923 status = IXGBE_ERR_LINK_SETUP;
927 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
928 if (hw->mac.orig_link_settings_stored)
929 orig_autoc = hw->mac.orig_autoc;
933 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
934 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
935 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
936 /* Set KX4/KX/KR support according to speed requested */
937 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
938 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
939 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
940 autoc |= IXGBE_AUTOC_KX4_SUPP;
941 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
942 (hw->phy.smart_speed_active == false))
943 autoc |= IXGBE_AUTOC_KR_SUPP;
945 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
946 autoc |= IXGBE_AUTOC_KX_SUPP;
947 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
948 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
949 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
950 /* Switch from 1G SFI to 10G SFI if requested */
951 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
952 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
953 autoc &= ~IXGBE_AUTOC_LMS_MASK;
954 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
956 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
957 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
958 /* Switch from 10G SFI to 1G SFI if requested */
959 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
960 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
961 autoc &= ~IXGBE_AUTOC_LMS_MASK;
963 autoc |= IXGBE_AUTOC_LMS_1G_AN;
965 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
969 if (autoc != start_autoc) {
970 /* Need SW/FW semaphore around AUTOC writes if LESM is on,
971 * likewise reset_pipeline requires us to hold this lock as
972 * it also writes to AUTOC.
974 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
975 status = hw->mac.ops.acquire_swfw_sync(hw,
976 IXGBE_GSSR_MAC_CSR_SM);
977 if (status != IXGBE_SUCCESS) {
978 status = IXGBE_ERR_SWFW_SYNC;
986 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
987 ixgbe_reset_pipeline_82599(hw);
990 hw->mac.ops.release_swfw_sync(hw,
991 IXGBE_GSSR_MAC_CSR_SM);
995 /* Only poll for autoneg to complete if specified to do so */
996 if (autoneg_wait_to_complete) {
997 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
998 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
999 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1000 links_reg = 0; /*Just in case Autoneg time=0*/
1001 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1003 IXGBE_READ_REG(hw, IXGBE_LINKS);
1004 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
1008 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
1010 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
1011 DEBUGOUT("Autoneg did not complete.\n");
1016 /* Add delay to filter out noises during initial link setup */
1025 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
1026 * @hw: pointer to hardware structure
1027 * @speed: new link speed
1028 * @autoneg: true if autonegotiation enabled
1029 * @autoneg_wait_to_complete: true if waiting is needed to complete
1031 * Restarts link on PHY and MAC based on settings passed in.
1033 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1034 ixgbe_link_speed speed,
1036 bool autoneg_wait_to_complete)
1040 DEBUGFUNC("ixgbe_setup_copper_link_82599");
1042 /* Setup the PHY according to input speed */
1043 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
1044 autoneg_wait_to_complete);
1046 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1052 * ixgbe_reset_hw_82599 - Perform hardware reset
1053 * @hw: pointer to hardware structure
1055 * Resets the hardware by resetting the transmit and receive units, masks
1056 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1059 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1061 ixgbe_link_speed link_speed;
1063 u32 ctrl, i, autoc, autoc2;
1064 bool link_up = false;
1066 DEBUGFUNC("ixgbe_reset_hw_82599");
1068 /* Call adapter stop to disable tx/rx and clear interrupts */
1069 status = hw->mac.ops.stop_adapter(hw);
1070 if (status != IXGBE_SUCCESS)
1073 /* flush pending Tx transactions */
1074 ixgbe_clear_tx_pending(hw);
1076 /* PHY ops must be identified and initialized prior to reset */
1078 /* Identify PHY and related function pointers */
1079 status = hw->phy.ops.init(hw);
1081 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1084 /* Setup SFP module if there is one present. */
1085 if (hw->phy.sfp_setup_needed) {
1086 status = hw->mac.ops.setup_sfp(hw);
1087 hw->phy.sfp_setup_needed = false;
1090 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1094 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1095 hw->phy.ops.reset(hw);
1099 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1100 * If link reset is used when link is up, it might reset the PHY when
1101 * mng is using it. If link is down or the flag to force full link
1102 * reset is set, then perform link reset.
1104 ctrl = IXGBE_CTRL_LNK_RST;
1105 if (!hw->force_full_reset) {
1106 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1108 ctrl = IXGBE_CTRL_RST;
1111 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1112 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1113 IXGBE_WRITE_FLUSH(hw);
1115 /* Poll for reset bit to self-clear meaning reset is complete */
1116 for (i = 0; i < 10; i++) {
1118 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1119 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1123 if (ctrl & IXGBE_CTRL_RST_MASK) {
1124 status = IXGBE_ERR_RESET_FAILED;
1125 DEBUGOUT("Reset polling failed to complete.\n");
1131 * Double resets are required for recovery from certain error
1132 * conditions. Between resets, it is necessary to stall to
1133 * allow time for any pending HW events to complete.
1135 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1136 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1141 * Store the original AUTOC/AUTOC2 values if they have not been
1142 * stored off yet. Otherwise restore the stored original
1143 * values since the reset operation sets back to defaults.
1145 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1146 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1148 /* Enable link if disabled in NVM */
1149 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1150 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1151 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1152 IXGBE_WRITE_FLUSH(hw);
1155 if (hw->mac.orig_link_settings_stored == false) {
1156 hw->mac.orig_autoc = autoc;
1157 hw->mac.orig_autoc2 = autoc2;
1158 hw->mac.orig_link_settings_stored = true;
1160 if (autoc != hw->mac.orig_autoc) {
1161 /* Need SW/FW semaphore around AUTOC writes if LESM is
1162 * on, likewise reset_pipeline requires us to hold
1163 * this lock as it also writes to AUTOC.
1165 bool got_lock = false;
1166 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1167 status = hw->mac.ops.acquire_swfw_sync(hw,
1168 IXGBE_GSSR_MAC_CSR_SM);
1169 if (status != IXGBE_SUCCESS) {
1170 status = IXGBE_ERR_SWFW_SYNC;
1177 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
1178 ixgbe_reset_pipeline_82599(hw);
1181 hw->mac.ops.release_swfw_sync(hw,
1182 IXGBE_GSSR_MAC_CSR_SM);
1185 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1186 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1187 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1188 autoc2 |= (hw->mac.orig_autoc2 &
1189 IXGBE_AUTOC2_UPPER_MASK);
1190 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1194 /* Store the permanent mac address */
1195 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1198 * Store MAC address from RAR0, clear receive address registers, and
1199 * clear the multicast table. Also reset num_rar_entries to 128,
1200 * since we modify this value when programming the SAN MAC address.
1202 hw->mac.num_rar_entries = 128;
1203 hw->mac.ops.init_rx_addrs(hw);
1205 /* Store the permanent SAN mac address */
1206 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1208 /* Add the SAN MAC address to the RAR only if it's a valid address */
1209 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1210 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1211 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1213 /* Save the SAN MAC RAR index */
1214 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1216 /* Reserve the last RAR for the SAN MAC address */
1217 hw->mac.num_rar_entries--;
1220 /* Store the alternative WWNN/WWPN prefix */
1221 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1222 &hw->mac.wwpn_prefix);
1229 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1230 * @hw: pointer to hardware structure
1232 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1235 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1236 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1238 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1241 * Before starting reinitialization process,
1242 * FDIRCMD.CMD must be zero.
1244 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1245 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1246 IXGBE_FDIRCMD_CMD_MASK))
1250 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1251 DEBUGOUT("Flow Director previous command isn't complete, "
1252 "aborting table re-initialization.\n");
1253 return IXGBE_ERR_FDIR_REINIT_FAILED;
1256 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1257 IXGBE_WRITE_FLUSH(hw);
1259 * 82599 adapters flow director init flow cannot be restarted,
1260 * Workaround 82599 silicon errata by performing the following steps
1261 * before re-writing the FDIRCTRL control register with the same value.
1262 * - write 1 to bit 8 of FDIRCMD register &
1263 * - write 0 to bit 8 of FDIRCMD register
1265 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1266 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1267 IXGBE_FDIRCMD_CLEARHT));
1268 IXGBE_WRITE_FLUSH(hw);
1269 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1270 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1271 ~IXGBE_FDIRCMD_CLEARHT));
1272 IXGBE_WRITE_FLUSH(hw);
1274 * Clear FDIR Hash register to clear any leftover hashes
1275 * waiting to be programmed.
1277 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1278 IXGBE_WRITE_FLUSH(hw);
1280 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1281 IXGBE_WRITE_FLUSH(hw);
1283 /* Poll init-done after we write FDIRCTRL register */
1284 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1285 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1286 IXGBE_FDIRCTRL_INIT_DONE)
1290 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1291 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1292 return IXGBE_ERR_FDIR_REINIT_FAILED;
1295 /* Clear FDIR statistics registers (read to clear) */
1296 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1297 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1298 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1299 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1300 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1302 return IXGBE_SUCCESS;
1306 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1307 * @hw: pointer to hardware structure
1308 * @fdirctrl: value to write to flow director control register
1310 STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1314 DEBUGFUNC("ixgbe_fdir_enable_82599");
1316 /* Prime the keys for hashing */
1317 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1318 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1321 * Poll init-done after we write the register. Estimated times:
1322 * 10G: PBALLOC = 11b, timing is 60us
1323 * 1G: PBALLOC = 11b, timing is 600us
1324 * 100M: PBALLOC = 11b, timing is 6ms
1326 * Multiple these timings by 4 if under full Rx load
1328 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1329 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1330 * this might not finish in our poll time, but we can live with that
1333 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1334 IXGBE_WRITE_FLUSH(hw);
1335 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1336 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1337 IXGBE_FDIRCTRL_INIT_DONE)
1342 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1343 DEBUGOUT("Flow Director poll time exceeded!\n");
1347 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1348 * @hw: pointer to hardware structure
1349 * @fdirctrl: value to write to flow director control register, initially
1350 * contains just the value of the Rx packet buffer allocation
1352 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1354 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1357 * Continue setup of fdirctrl register bits:
1358 * Move the flexible bytes to use the ethertype - shift 6 words
1359 * Set the maximum length per hash bucket to 0xA filters
1360 * Send interrupt when 64 filters are left
1362 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1363 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1364 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1366 /* write hashes and fdirctrl register, poll for completion */
1367 ixgbe_fdir_enable_82599(hw, fdirctrl);
1369 return IXGBE_SUCCESS;
1373 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1374 * @hw: pointer to hardware structure
1375 * @fdirctrl: value to write to flow director control register, initially
1376 * contains just the value of the Rx packet buffer allocation
1378 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1380 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1383 * Continue setup of fdirctrl register bits:
1384 * Turn perfect match filtering on
1385 * Report hash in RSS field of Rx wb descriptor
1386 * Initialize the drop queue
1387 * Move the flexible bytes to use the ethertype - shift 6 words
1388 * Set the maximum length per hash bucket to 0xA filters
1389 * Send interrupt when 64 (0x4 * 16) filters are left
1391 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1392 IXGBE_FDIRCTRL_REPORT_STATUS |
1393 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1394 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1395 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1396 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1399 /* write hashes and fdirctrl register, poll for completion */
1400 ixgbe_fdir_enable_82599(hw, fdirctrl);
1402 return IXGBE_SUCCESS;
1406 * These defines allow us to quickly generate all of the necessary instructions
1407 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1408 * for values 0 through 15
1410 #define IXGBE_ATR_COMMON_HASH_KEY \
1411 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1412 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1415 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1416 common_hash ^= lo_hash_dword >> n; \
1417 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1418 bucket_hash ^= lo_hash_dword >> n; \
1419 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1420 sig_hash ^= lo_hash_dword << (16 - n); \
1421 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1422 common_hash ^= hi_hash_dword >> n; \
1423 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1424 bucket_hash ^= hi_hash_dword >> n; \
1425 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1426 sig_hash ^= hi_hash_dword << (16 - n); \
1430 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1431 * @stream: input bitstream to compute the hash on
1433 * This function is almost identical to the function above but contains
1434 * several optomizations such as unwinding all of the loops, letting the
1435 * compiler work out all of the conditional ifs since the keys are static
1436 * defines, and computing two keys at once since the hashed dword stream
1437 * will be the same for both keys.
1439 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1440 union ixgbe_atr_hash_dword common)
1442 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1443 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1445 /* record the flow_vm_vlan bits as they are a key part to the hash */
1446 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1448 /* generate common hash dword */
1449 hi_hash_dword = IXGBE_NTOHL(common.dword);
1451 /* low dword is word swapped version of common */
1452 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1454 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1455 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1457 /* Process bits 0 and 16 */
1458 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1461 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1462 * delay this because bit 0 of the stream should not be processed
1463 * so we do not add the vlan until after bit 0 was processed
1465 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1467 /* Process remaining 30 bit of the key */
1468 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1469 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1470 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1471 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1472 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1473 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1474 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1475 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1476 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1477 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1478 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1479 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1480 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1481 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1482 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1484 /* combine common_hash result with signature and bucket hashes */
1485 bucket_hash ^= common_hash;
1486 bucket_hash &= IXGBE_ATR_HASH_MASK;
1488 sig_hash ^= common_hash << 16;
1489 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1491 /* return completed signature hash */
1492 return sig_hash ^ bucket_hash;
1496 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1497 * @hw: pointer to hardware structure
1498 * @input: unique input dword
1499 * @common: compressed common input dword
1500 * @queue: queue index to direct traffic to
1502 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1503 union ixgbe_atr_hash_dword input,
1504 union ixgbe_atr_hash_dword common,
1510 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1513 * Get the flow_type in order to program FDIRCMD properly
1514 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1515 * fifth is FDIRCMD.TUNNEL_FILTER
1517 switch (input.formatted.flow_type) {
1518 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1519 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1520 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1521 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1522 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1523 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1526 DEBUGOUT(" Error on flow type input\n");
1527 return IXGBE_ERR_CONFIG;
1530 /* configure FDIRCMD register */
1531 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1532 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1533 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1534 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1537 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1538 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1540 fdirhashcmd = (u64)fdircmd << 32;
1541 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1542 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1544 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1546 return IXGBE_SUCCESS;
1549 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1552 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1553 bucket_hash ^= lo_hash_dword >> n; \
1554 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1555 bucket_hash ^= hi_hash_dword >> n; \
1559 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1560 * @atr_input: input bitstream to compute the hash on
1561 * @input_mask: mask for the input bitstream
1563 * This function serves two main purposes. First it applys the input_mask
1564 * to the atr_input resulting in a cleaned up atr_input data stream.
1565 * Secondly it computes the hash and stores it in the bkt_hash field at
1566 * the end of the input byte stream. This way it will be available for
1567 * future use without needing to recompute the hash.
1569 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1570 union ixgbe_atr_input *input_mask)
1573 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1574 u32 bucket_hash = 0;
1576 /* Apply masks to input data */
1577 input->dword_stream[0] &= input_mask->dword_stream[0];
1578 input->dword_stream[1] &= input_mask->dword_stream[1];
1579 input->dword_stream[2] &= input_mask->dword_stream[2];
1580 input->dword_stream[3] &= input_mask->dword_stream[3];
1581 input->dword_stream[4] &= input_mask->dword_stream[4];
1582 input->dword_stream[5] &= input_mask->dword_stream[5];
1583 input->dword_stream[6] &= input_mask->dword_stream[6];
1584 input->dword_stream[7] &= input_mask->dword_stream[7];
1585 input->dword_stream[8] &= input_mask->dword_stream[8];
1586 input->dword_stream[9] &= input_mask->dword_stream[9];
1587 input->dword_stream[10] &= input_mask->dword_stream[10];
1589 /* record the flow_vm_vlan bits as they are a key part to the hash */
1590 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1592 /* generate common hash dword */
1593 hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
1594 input->dword_stream[2] ^
1595 input->dword_stream[3] ^
1596 input->dword_stream[4] ^
1597 input->dword_stream[5] ^
1598 input->dword_stream[6] ^
1599 input->dword_stream[7] ^
1600 input->dword_stream[8] ^
1601 input->dword_stream[9] ^
1602 input->dword_stream[10]);
1604 /* low dword is word swapped version of common */
1605 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1607 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1608 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1610 /* Process bits 0 and 16 */
1611 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1614 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1615 * delay this because bit 0 of the stream should not be processed
1616 * so we do not add the vlan until after bit 0 was processed
1618 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1620 /* Process remaining 30 bit of the key */
1621 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1622 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1623 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1624 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1625 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1626 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1627 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1628 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1629 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1630 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1631 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1632 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1633 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1634 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1635 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1638 * Limit hash to 13 bits since max bucket count is 8K.
1639 * Store result at the end of the input stream.
1641 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1645 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1646 * @input_mask: mask to be bit swapped
1648 * The source and destination port masks for flow director are bit swapped
1649 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1650 * generate a correctly swapped value we need to bit swap the mask and that
1651 * is what is accomplished by this function.
1653 STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1655 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1656 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1657 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1658 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1659 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1660 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1661 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1665 * These two macros are meant to address the fact that we have registers
1666 * that are either all or in part big-endian. As a result on big-endian
1667 * systems we will end up byte swapping the value to little-endian before
1668 * it is byte swapped again and written to the hardware in the original
1669 * big-endian format.
1671 #define IXGBE_STORE_AS_BE32(_value) \
1672 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1673 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1675 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1676 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1678 #define IXGBE_STORE_AS_BE16(_value) \
1679 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1681 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1682 union ixgbe_atr_input *input_mask)
1684 /* mask IPv6 since it is currently not supported */
1685 u32 fdirm = IXGBE_FDIRM_DIPv6;
1687 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1690 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1691 * are zero, then assume a full mask for that field. Also assume that
1692 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1693 * cannot be masked out in this implementation.
1695 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1699 /* verify bucket hash is cleared on hash generation */
1700 if (input_mask->formatted.bkt_hash)
1701 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1703 /* Program FDIRM and verify partial masks */
1704 switch (input_mask->formatted.vm_pool & 0x7F) {
1706 fdirm |= IXGBE_FDIRM_POOL;
1710 DEBUGOUT(" Error on vm pool mask\n");
1711 return IXGBE_ERR_CONFIG;
1714 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1716 fdirm |= IXGBE_FDIRM_L4P;
1717 if (input_mask->formatted.dst_port ||
1718 input_mask->formatted.src_port) {
1719 DEBUGOUT(" Error on src/dst port mask\n");
1720 return IXGBE_ERR_CONFIG;
1722 case IXGBE_ATR_L4TYPE_MASK:
1725 DEBUGOUT(" Error on flow type mask\n");
1726 return IXGBE_ERR_CONFIG;
1729 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1731 /* mask VLAN ID, fall through to mask VLAN priority */
1732 fdirm |= IXGBE_FDIRM_VLANID;
1734 /* mask VLAN priority */
1735 fdirm |= IXGBE_FDIRM_VLANP;
1738 /* mask VLAN ID only, fall through */
1739 fdirm |= IXGBE_FDIRM_VLANID;
1741 /* no VLAN fields masked */
1744 DEBUGOUT(" Error on VLAN mask\n");
1745 return IXGBE_ERR_CONFIG;
1748 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1750 /* Mask Flex Bytes, fall through */
1751 fdirm |= IXGBE_FDIRM_FLEX;
1755 DEBUGOUT(" Error on flexible byte mask\n");
1756 return IXGBE_ERR_CONFIG;
1760 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1761 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1763 /* store the TCP/UDP port masks, bit reversed from port layout */
1764 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1766 /* write both the same so that UDP and TCP use the same mask */
1767 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1768 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1770 /* store source and destination IP masks (big-enian) */
1771 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1772 ~input_mask->formatted.src_ip[0]);
1773 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1774 ~input_mask->formatted.dst_ip[0]);
1776 return IXGBE_SUCCESS;
1779 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1780 union ixgbe_atr_input *input,
1781 u16 soft_id, u8 queue)
1783 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1785 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1787 /* currently IPv6 is not supported, must be programmed with 0 */
1788 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1789 input->formatted.src_ip[0]);
1790 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1791 input->formatted.src_ip[1]);
1792 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1793 input->formatted.src_ip[2]);
1795 /* record the source address (big-endian) */
1796 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1798 /* record the first 32 bits of the destination address (big-endian) */
1799 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1801 /* record source and destination port (little-endian)*/
1802 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1803 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1804 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1805 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1807 /* record vlan (little-endian) and flex_bytes(big-endian) */
1808 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1809 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1810 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1811 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1814 /* configure FDIRHASH register */
1815 fdirhash = input->formatted.bkt_hash;
1816 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1817 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1820 * flush all previous writes to make certain registers are
1821 * programmed prior to issuing the command
1823 IXGBE_WRITE_FLUSH(hw);
1825 /* configure FDIRCMD register */
1826 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1827 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1828 if (queue == IXGBE_FDIR_DROP_QUEUE)
1829 fdircmd |= IXGBE_FDIRCMD_DROP;
1830 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1831 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1832 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1834 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1836 return IXGBE_SUCCESS;
1839 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1840 union ixgbe_atr_input *input,
1846 s32 err = IXGBE_SUCCESS;
1848 /* configure FDIRHASH register */
1849 fdirhash = input->formatted.bkt_hash;
1850 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1851 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1853 /* flush hash to HW */
1854 IXGBE_WRITE_FLUSH(hw);
1856 /* Query if filter is present */
1857 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1859 for (retry_count = 10; retry_count; retry_count--) {
1860 /* allow 10us for query to process */
1862 /* verify query completed successfully */
1863 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1864 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1869 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1871 /* if filter exists in hardware then remove it */
1872 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1873 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1874 IXGBE_WRITE_FLUSH(hw);
1875 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1876 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1883 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1884 * @hw: pointer to hardware structure
1885 * @input: input bitstream
1886 * @input_mask: mask for the input bitstream
1887 * @soft_id: software index for the filters
1888 * @queue: queue index to direct traffic to
1890 * Note that the caller to this function must lock before calling, since the
1891 * hardware writes must be protected from one another.
1893 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1894 union ixgbe_atr_input *input,
1895 union ixgbe_atr_input *input_mask,
1896 u16 soft_id, u8 queue)
1898 s32 err = IXGBE_ERR_CONFIG;
1900 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1903 * Check flow_type formatting, and bail out before we touch the hardware
1904 * if there's a configuration issue
1906 switch (input->formatted.flow_type) {
1907 case IXGBE_ATR_FLOW_TYPE_IPV4:
1908 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
1909 if (input->formatted.dst_port || input->formatted.src_port) {
1910 DEBUGOUT(" Error on src/dst port\n");
1911 return IXGBE_ERR_CONFIG;
1914 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1915 if (input->formatted.dst_port || input->formatted.src_port) {
1916 DEBUGOUT(" Error on src/dst port\n");
1917 return IXGBE_ERR_CONFIG;
1919 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1920 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1921 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
1922 IXGBE_ATR_L4TYPE_MASK;
1925 DEBUGOUT(" Error on flow type input\n");
1929 /* program input mask into the HW */
1930 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
1934 /* apply mask and compute/store hash */
1935 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
1937 /* program filters to filter memory */
1938 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
1943 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1944 * @hw: pointer to hardware structure
1945 * @reg: analog register to read
1948 * Performs read operation to Omer analog register specified.
1950 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1954 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
1956 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1958 IXGBE_WRITE_FLUSH(hw);
1960 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1961 *val = (u8)core_ctl;
1963 return IXGBE_SUCCESS;
1967 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1968 * @hw: pointer to hardware structure
1969 * @reg: atlas register to write
1970 * @val: value to write
1972 * Performs write operation to Omer analog register specified.
1974 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1978 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
1980 core_ctl = (reg << 8) | val;
1981 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1982 IXGBE_WRITE_FLUSH(hw);
1985 return IXGBE_SUCCESS;
1989 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1990 * @hw: pointer to hardware structure
1992 * Starts the hardware using the generic start_hw function
1993 * and the generation start_hw function.
1994 * Then performs revision-specific operations, if any.
1996 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1998 s32 ret_val = IXGBE_SUCCESS;
2000 DEBUGFUNC("ixgbe_start_hw_82599");
2002 ret_val = ixgbe_start_hw_generic(hw);
2003 if (ret_val != IXGBE_SUCCESS)
2006 ret_val = ixgbe_start_hw_gen2(hw);
2007 if (ret_val != IXGBE_SUCCESS)
2010 /* We need to run link autotry after the driver loads */
2011 hw->mac.autotry_restart = true;
2013 if (ret_val == IXGBE_SUCCESS)
2014 ret_val = ixgbe_verify_fw_version_82599(hw);
2020 * ixgbe_identify_phy_82599 - Get physical layer module
2021 * @hw: pointer to hardware structure
2023 * Determines the physical layer module found on the current adapter.
2024 * If PHY already detected, maintains current PHY type in hw struct,
2025 * otherwise executes the PHY detection routine.
2027 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2031 DEBUGFUNC("ixgbe_identify_phy_82599");
2033 /* Detect PHY if not unknown - returns success if already detected. */
2034 status = ixgbe_identify_phy_generic(hw);
2035 if (status != IXGBE_SUCCESS) {
2036 /* 82599 10GBASE-T requires an external PHY */
2037 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2040 status = ixgbe_identify_module_generic(hw);
2043 /* Set PHY type none if no PHY detected */
2044 if (hw->phy.type == ixgbe_phy_unknown) {
2045 hw->phy.type = ixgbe_phy_none;
2046 status = IXGBE_SUCCESS;
2049 /* Return error if SFP module has been detected but is not supported */
2050 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2051 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
2058 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2059 * @hw: pointer to hardware structure
2061 * Determines physical layer capabilities of the current configuration.
2063 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2065 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2066 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2067 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2068 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2069 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2070 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2071 u16 ext_ability = 0;
2072 u8 comp_codes_10g = 0;
2073 u8 comp_codes_1g = 0;
2075 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
2077 hw->phy.ops.identify(hw);
2079 switch (hw->phy.type) {
2081 case ixgbe_phy_cu_unknown:
2082 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2083 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
2084 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2085 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2086 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2087 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2088 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
2089 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2095 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2096 case IXGBE_AUTOC_LMS_1G_AN:
2097 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2098 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2099 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2100 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2103 /* SFI mode so read SFP module */
2106 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2107 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2108 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2109 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2110 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2111 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2112 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2115 case IXGBE_AUTOC_LMS_10G_SERIAL:
2116 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2117 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2119 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2122 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2123 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2124 if (autoc & IXGBE_AUTOC_KX_SUPP)
2125 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2126 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2127 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2128 if (autoc & IXGBE_AUTOC_KR_SUPP)
2129 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2138 /* SFP check must be done last since DA modules are sometimes used to
2139 * test KR mode - we need to id KR mode correctly before SFP module.
2140 * Call identify_sfp because the pluggable module may have changed */
2141 hw->phy.ops.identify_sfp(hw);
2142 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2145 switch (hw->phy.type) {
2146 case ixgbe_phy_sfp_passive_tyco:
2147 case ixgbe_phy_sfp_passive_unknown:
2148 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2150 case ixgbe_phy_sfp_ftl_active:
2151 case ixgbe_phy_sfp_active_unknown:
2152 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2154 case ixgbe_phy_sfp_avago:
2155 case ixgbe_phy_sfp_ftl:
2156 case ixgbe_phy_sfp_intel:
2157 case ixgbe_phy_sfp_unknown:
2158 hw->phy.ops.read_i2c_eeprom(hw,
2159 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2160 hw->phy.ops.read_i2c_eeprom(hw,
2161 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2162 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2163 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2164 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2165 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2166 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2167 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2168 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
2169 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
2176 return physical_layer;
2180 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2181 * @hw: pointer to hardware structure
2182 * @regval: register value to write to RXCTRL
2184 * Enables the Rx DMA unit for 82599
2186 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2189 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2192 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2193 * If traffic is incoming before we enable the Rx unit, it could hang
2194 * the Rx DMA unit. Therefore, make sure the security engine is
2195 * completely disabled prior to enabling the Rx unit.
2198 hw->mac.ops.disable_sec_rx_path(hw);
2200 if (regval & IXGBE_RXCTRL_RXEN)
2201 ixgbe_enable_rx(hw);
2203 ixgbe_disable_rx(hw);
2205 hw->mac.ops.enable_sec_rx_path(hw);
2207 return IXGBE_SUCCESS;
2211 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2212 * @hw: pointer to hardware structure
2214 * Verifies that installed the firmware version is 0.6 or higher
2215 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2217 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2218 * if the FW version is not supported.
2220 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2222 s32 status = IXGBE_ERR_EEPROM_VERSION;
2223 u16 fw_offset, fw_ptp_cfg_offset;
2226 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2228 /* firmware check is only necessary for SFI devices */
2229 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2230 status = IXGBE_SUCCESS;
2231 goto fw_version_out;
2234 /* get the offset to the Firmware Module block */
2235 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
2236 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2237 "eeprom read at offset %d failed", IXGBE_FW_PTR);
2238 return IXGBE_ERR_EEPROM_VERSION;
2241 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2242 goto fw_version_out;
2244 /* get the offset to the Pass Through Patch Configuration block */
2245 if (hw->eeprom.ops.read(hw, (fw_offset +
2246 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2247 &fw_ptp_cfg_offset)) {
2248 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2249 "eeprom read at offset %d failed",
2251 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR);
2252 return IXGBE_ERR_EEPROM_VERSION;
2255 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2256 goto fw_version_out;
2258 /* get the firmware version */
2259 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2260 IXGBE_FW_PATCH_VERSION_4), &fw_version)) {
2261 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2262 "eeprom read at offset %d failed",
2263 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4);
2264 return IXGBE_ERR_EEPROM_VERSION;
2267 if (fw_version > 0x5)
2268 status = IXGBE_SUCCESS;
2275 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2276 * @hw: pointer to hardware structure
2278 * Returns true if the LESM FW module is present and enabled. Otherwise
2279 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2281 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2283 bool lesm_enabled = false;
2284 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2287 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2289 /* get the offset to the Firmware Module block */
2290 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2292 if ((status != IXGBE_SUCCESS) ||
2293 (fw_offset == 0) || (fw_offset == 0xFFFF))
2296 /* get the offset to the LESM Parameters block */
2297 status = hw->eeprom.ops.read(hw, (fw_offset +
2298 IXGBE_FW_LESM_PARAMETERS_PTR),
2299 &fw_lesm_param_offset);
2301 if ((status != IXGBE_SUCCESS) ||
2302 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2305 /* get the lesm state word */
2306 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2307 IXGBE_FW_LESM_STATE_1),
2310 if ((status == IXGBE_SUCCESS) &&
2311 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2312 lesm_enabled = true;
2315 return lesm_enabled;
2319 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2320 * fastest available method
2322 * @hw: pointer to hardware structure
2323 * @offset: offset of word in EEPROM to read
2324 * @words: number of words
2325 * @data: word(s) read from the EEPROM
2327 * Retrieves 16 bit word(s) read from EEPROM
2329 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2330 u16 words, u16 *data)
2332 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2333 s32 ret_val = IXGBE_ERR_CONFIG;
2335 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2338 * If EEPROM is detected and can be addressed using 14 bits,
2339 * use EERD otherwise use bit bang
2341 if ((eeprom->type == ixgbe_eeprom_spi) &&
2342 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2343 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2346 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2354 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2355 * fastest available method
2357 * @hw: pointer to hardware structure
2358 * @offset: offset of word in the EEPROM to read
2359 * @data: word read from the EEPROM
2361 * Reads a 16 bit word from the EEPROM
2363 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2364 u16 offset, u16 *data)
2366 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2367 s32 ret_val = IXGBE_ERR_CONFIG;
2369 DEBUGFUNC("ixgbe_read_eeprom_82599");
2372 * If EEPROM is detected and can be addressed using 14 bits,
2373 * use EERD otherwise use bit bang
2375 if ((eeprom->type == ixgbe_eeprom_spi) &&
2376 (offset <= IXGBE_EERD_MAX_ADDR))
2377 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2379 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2385 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2387 * @hw: pointer to hardware structure
2389 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2390 * full pipeline reset
2392 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2394 s32 i, autoc_reg, autoc2_reg, ret_val;
2397 /* Enable link if disabled in NVM */
2398 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2399 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2400 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2401 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2402 IXGBE_WRITE_FLUSH(hw);
2405 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2406 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2407 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2408 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN);
2409 /* Wait for AN to leave state 0 */
2410 for (i = 0; i < 10; i++) {
2412 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2413 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2417 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2418 DEBUGOUT("auto negotiation not completed\n");
2419 ret_val = IXGBE_ERR_RESET_FAILED;
2420 goto reset_pipeline_out;
2423 ret_val = IXGBE_SUCCESS;
2426 /* Write AUTOC register with original LMS field and Restart_AN */
2427 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2428 IXGBE_WRITE_FLUSH(hw);