net/ixgbe/base: add bit for enabling L3/L4 filtering

Add a L3/L4 filtering definition of Multiple Receive Queues Command
(MRQC) register for the future use.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h
index bb1f85b0b1a43c0e6581f0db3d4b8e378e177daa..6acd966d95414c66d5e3bd314b2cd1f5cd80df16 100644 (file)
--- a/drivers/net/ixgbe/base/ixgbe_type.h
+++ b/drivers/net/ixgbe/base/ixgbe_type.h
@@ -2622,6 +2622,7 @@ enum {
 #define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */
 #define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
 #define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */
+#define IXGBE_MRQC_L3L4TXSWEN  0x00008000 /* Enable L3/L4 Tx switch */
 #define IXGBE_MRQC_RSS_FIELD_MASK      0xFFFF0000
 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP  0x00010000
 #define IXGBE_MRQC_RSS_FIELD_IPV4      0x00020000