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34 #ifndef _DPAA2_HW_PVT_H_
35 #define _DPAA2_HW_PVT_H_
37 #include <mc/fsl_mc_sys.h>
38 #include <fsl_qbman_portal.h>
46 #define lower_32_bits(x) ((uint32_t)(x))
47 #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))
49 #define SVR_LS1080A 0x87030000
50 #define SVR_LS2080A 0x87010000
51 #define SVR_LS2088A 0x87090000
54 #define ETH_VLAN_HLEN 4 /** < Vlan Header Length */
57 #define MAX_TX_RING_SLOTS 8
58 /** <Maximum number of slots available in TX ring*/
60 #define DPAA2_DQRR_RING_SIZE 16
61 /** <Maximum number of slots available in RX ring*/
63 #define MC_PORTAL_INDEX 0
64 #define NUM_DPIO_REGIONS 2
65 #define NUM_DQS_PER_QUEUE 2
67 /* Maximum release/acquire from QBMAN */
68 #define DPAA2_MBUF_MAX_ACQ_REL 7
71 #define DPAA2_MBUF_HW_ANNOTATION 64
72 #define DPAA2_FD_PTA_SIZE 0
74 #if (DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > RTE_PKTMBUF_HEADROOM
75 #error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM"
78 /* we will re-use the HEADROOM for annotation in RX */
79 #define DPAA2_HW_BUF_RESERVE 0
80 #define DPAA2_PACKET_LAYOUT_ALIGN 64 /*changing from 256 */
82 struct dpaa2_dpio_dev {
83 TAILQ_ENTRY(dpaa2_dpio_dev) next;
84 /**< Pointer to Next device instance */
85 uint16_t index; /**< Index of a instance in the list */
86 rte_atomic16_t ref_count;
87 /**< How many thread contexts are sharing this.*/
88 struct fsl_mc_io *dpio; /** handle to DPIO portal object */
90 struct qbman_swp *sw_portal; /** SW portal object */
91 const struct qbman_result *dqrr[4];
92 /**< DQRR Entry for this SW portal */
93 void *mc_portal; /**< MC Portal for configuring this device */
94 uintptr_t qbman_portal_ce_paddr;
95 /**< Physical address of Cache Enabled Area */
96 uintptr_t ce_size; /**< Size of the CE region */
97 uintptr_t qbman_portal_ci_paddr;
98 /**< Physical address of Cache Inhibit Area */
99 uintptr_t ci_size; /**< Size of the CI region */
100 int32_t vfio_fd; /**< File descriptor received via VFIO */
101 int32_t hw_id; /**< An unique ID of this DPIO device instance */
104 struct dpaa2_dpbp_dev {
105 TAILQ_ENTRY(dpaa2_dpbp_dev) next;
106 /**< Pointer to Next device instance */
107 struct fsl_mc_io dpbp; /** handle to DPBP portal object */
109 rte_atomic16_t in_use;
110 uint32_t dpbp_id; /*HW ID for DPBP object */
113 struct queue_storage_info_t {
114 struct qbman_result *dq_storage[NUM_DQS_PER_QUEUE];
115 struct qbman_result *active_dqs;
121 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
123 int32_t eventfd; /*!< Event Fd of this queue */
124 uint32_t fqid; /*!< Unique ID of this queue */
125 uint8_t tc_index; /*!< traffic class identifier */
126 uint16_t flow_id; /*!< To be used by DPAA2 frmework */
131 struct queue_storage_info_t *q_storage;
132 struct qbman_result *cscn;
136 struct swp_active_dqs {
137 struct qbman_result *global_active_dqs;
138 uint64_t reserved[7];
141 #define NUM_MAX_SWP 64
143 extern struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
145 /*! Global MCP list */
146 extern void *(*rte_mcp_ptr_list);
148 /* Refer to Table 7-3 in SEC BG */
153 /* FMT must be 00, MSB is final bit */
154 uint32_t fin_bpid_offset;
156 uint32_t reserved[3]; /* Not used currently */
159 /*Macros to define operations on FD*/
160 #define DPAA2_SET_FD_ADDR(fd, addr) do { \
161 fd->simple.addr_lo = lower_32_bits((uint64_t)(addr)); \
162 fd->simple.addr_hi = upper_32_bits((uint64_t)(addr)); \
164 #define DPAA2_SET_FD_LEN(fd, length) (fd)->simple.len = length
165 #define DPAA2_SET_FD_BPID(fd, bpid) ((fd)->simple.bpid_offset |= bpid)
166 #define DPAA2_SET_FD_IVP(fd) ((fd->simple.bpid_offset |= 0x00004000))
167 #define DPAA2_SET_FD_OFFSET(fd, offset) \
168 ((fd->simple.bpid_offset |= (uint32_t)(offset) << 16))
169 #define DPAA2_SET_FD_INTERNAL_JD(fd, len) fd->simple.frc = (0x80000000 | (len))
170 #define DPAA2_SET_FD_FRC(fd, frc) fd->simple.frc = frc
171 #define DPAA2_RESET_FD_CTRL(fd) (fd)->simple.ctrl = 0
173 #define DPAA2_SET_FD_ASAL(fd, asal) ((fd)->simple.ctrl |= (asal << 16))
174 #define DPAA2_SET_FD_FLC(fd, addr) do { \
175 fd->simple.flc_lo = lower_32_bits((uint64_t)(addr)); \
176 fd->simple.flc_hi = upper_32_bits((uint64_t)(addr)); \
178 #define DPAA2_SET_FLE_INTERNAL_JD(fle, len) (fle->frc = (0x80000000 | (len)))
179 #define DPAA2_GET_FLE_ADDR(fle) \
180 (uint64_t)((((uint64_t)(fle->addr_hi)) << 32) + fle->addr_lo)
181 #define DPAA2_SET_FLE_ADDR(fle, addr) do { \
182 fle->addr_lo = lower_32_bits((uint64_t)addr); \
183 fle->addr_hi = upper_32_bits((uint64_t)addr); \
185 #define DPAA2_SET_FLE_OFFSET(fle, offset) \
186 ((fle)->fin_bpid_offset |= (uint32_t)(offset) << 16)
187 #define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (uint64_t)bpid)
188 #define DPAA2_GET_FLE_BPID(fle, bpid) (fle->fin_bpid_offset & 0x000000ff)
189 #define DPAA2_SET_FLE_FIN(fle) (fle->fin_bpid_offset |= (uint64_t)1 << 31)
190 #define DPAA2_SET_FLE_IVP(fle) (((fle)->fin_bpid_offset |= 0x00004000))
191 #define DPAA2_SET_FD_COMPOUND_FMT(fd) \
192 (fd->simple.bpid_offset |= (uint32_t)1 << 28)
193 #define DPAA2_GET_FD_ADDR(fd) \
194 ((uint64_t)((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo))
196 #define DPAA2_GET_FD_LEN(fd) ((fd)->simple.len)
197 #define DPAA2_GET_FD_BPID(fd) (((fd)->simple.bpid_offset & 0x00003FFF))
198 #define DPAA2_GET_FD_IVP(fd) ((fd->simple.bpid_offset & 0x00004000) >> 14)
199 #define DPAA2_GET_FD_OFFSET(fd) (((fd)->simple.bpid_offset & 0x0FFF0000) >> 16)
200 #define DPAA2_SET_FLE_SG_EXT(fle) (fle->fin_bpid_offset |= (uint64_t)1 << 29)
201 #define DPAA2_IS_SET_FLE_SG_EXT(fle) \
202 ((fle->fin_bpid_offset & ((uint64_t)1 << 29)) ? 1 : 0)
204 #define DPAA2_INLINE_MBUF_FROM_BUF(buf, meta_data_size) \
205 ((struct rte_mbuf *)((uint64_t)(buf) - (meta_data_size)))
207 #define DPAA2_ASAL_VAL (DPAA2_MBUF_HW_ANNOTATION / 64)
209 /* Only Enqueue Error responses will be
210 * pushed on FQID_ERR of Enqueue FQ
212 #define DPAA2_EQ_RESP_ERR_FQ 0
213 /* All Enqueue responses will be pushed on address
214 * set with qbman_eq_desc_set_response
216 #define DPAA2_EQ_RESP_ALWAYS 1
218 #ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
219 static void *dpaa2_mem_ptov(phys_addr_t paddr) __attribute__((unused));
220 /* todo - this is costly, need to write a fast coversion routine */
221 static void *dpaa2_mem_ptov(phys_addr_t paddr)
223 const struct rte_memseg *memseg = rte_eal_get_physmem_layout();
226 for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
227 if (paddr >= memseg[i].phys_addr &&
228 (char *)paddr < (char *)memseg[i].phys_addr + memseg[i].len)
229 return (void *)(memseg[i].addr_64
230 + (paddr - memseg[i].phys_addr));
235 static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) __attribute__((unused));
236 static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
238 const struct rte_memseg *memseg = rte_eal_get_physmem_layout();
241 for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
242 if (vaddr >= memseg[i].addr_64 &&
243 vaddr < memseg[i].addr_64 + memseg[i].len)
244 return memseg[i].phys_addr
245 + (vaddr - memseg[i].addr_64);
247 return (phys_addr_t)(NULL);
251 * When we are using Physical addresses as IO Virtual Addresses,
252 * Need to call conversion routines dpaa2_mem_vtop & dpaa2_mem_ptov
253 * whereever required.
254 * These routines are called with help of below MACRO's
257 #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_physaddr)
258 #define DPAA2_OP_VADDR_TO_IOVA(op) (op->phys_addr)
261 * macro to convert Virtual address to IOVA
263 #define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((uint64_t)(_vaddr))
266 * macro to convert IOVA to Virtual address
268 #define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((phys_addr_t)(_iova))
271 * macro to convert modify the memory containing IOVA to Virtual address
273 #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type) \
274 {_mem = (_type)(dpaa2_mem_ptov((phys_addr_t)(_mem))); }
276 #else /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
278 #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_addr)
279 #define DPAA2_OP_VADDR_TO_IOVA(op) (op)
280 #define DPAA2_VADDR_TO_IOVA(_vaddr) (_vaddr)
281 #define DPAA2_IOVA_TO_VADDR(_iova) (_iova)
282 #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type)
284 #endif /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
287 int check_swp_active_dqs(uint16_t dpio_index)
289 if (rte_global_active_dqs_list[dpio_index].global_active_dqs != NULL)
295 void clear_swp_active_dqs(uint16_t dpio_index)
297 rte_global_active_dqs_list[dpio_index].global_active_dqs = NULL;
301 struct qbman_result *get_swp_active_dqs(uint16_t dpio_index)
303 return rte_global_active_dqs_list[dpio_index].global_active_dqs;
307 void set_swp_active_dqs(uint16_t dpio_index, struct qbman_result *dqs)
309 rte_global_active_dqs_list[dpio_index].global_active_dqs = dqs;
311 struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void);
312 void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp);