drivers/crypto/qat/qat_crypto.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *       * Redistributions of source code must retain the above copyright
  12  *         notice, this list of conditions and the following disclaimer.
  13  *       * Redistributions in binary form must reproduce the above copyright
  14  *         notice, this list of conditions and the following disclaimer in
  15  *         the documentation and/or other materials provided with the
  16  *         distribution.
  17  *       * Neither the name of Intel Corporation nor the names of its
  18  *         contributors may be used to endorse or promote products derived
  19  *         from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <strings.h>
  37 #include <string.h>
  38 #include <inttypes.h>
  39 #include <errno.h>
  40 #include <sys/queue.h>
  41 #include <stdarg.h>
  42
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_memory.h>
  47 #include <rte_memzone.h>
  48 #include <rte_tailq.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_launch.h>
  52 #include <rte_eal.h>
  53 #include <rte_per_lcore.h>
  54 #include <rte_lcore.h>
  55 #include <rte_atomic.h>
  56 #include <rte_branch_prediction.h>
  57 #include <rte_mempool.h>
  58 #include <rte_mbuf.h>
  59 #include <rte_string_fns.h>
  60 #include <rte_spinlock.h>
  61 #include <rte_hexdump.h>
  62 #include <rte_crypto_sym.h>
  63 #include <rte_cryptodev_pci.h>
  64 #include <openssl/evp.h>
  65
  66 #include "qat_logs.h"
  67 #include "qat_algs.h"
  68 #include "qat_crypto.h"
  69 #include "adf_transport_access_macros.h"
  70
  71 #define BYTE_LENGTH    8
  72
  73 static int
  74 qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,
  75                 struct qat_pmd_private *internals) {
  76         int i = 0;
  77         const struct rte_cryptodev_capabilities *capability;
  78
  79         while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
  80                         RTE_CRYPTO_OP_TYPE_UNDEFINED) {
  81                 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
  82                         continue;
  83
  84                 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)
  85                         continue;
  86
  87                 if (capability->sym.cipher.algo == algo)
  88                         return 1;
  89         }
  90         return 0;
  91 }
  92
  93 static int
  94 qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,
  95                 struct qat_pmd_private *internals) {
  96         int i = 0;
  97         const struct rte_cryptodev_capabilities *capability;
  98
  99         while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
 100                         RTE_CRYPTO_OP_TYPE_UNDEFINED) {
 101                 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
 102                         continue;
 103
 104                 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)
 105                         continue;
 106
 107                 if (capability->sym.auth.algo == algo)
 108                         return 1;
 109         }
 110         return 0;
 111 }
 112
 113 /** Encrypt a single partial block
 114  *  Depends on openssl libcrypto
 115  *  Uses ECB+XOR to do CFB encryption, same result, more performant
 116  */
 117 static inline int
 118 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
 119                 uint8_t *iv, int ivlen, int srclen,
 120                 void *bpi_ctx)
 121 {
 122         EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
 123         int encrypted_ivlen;
 124         uint8_t encrypted_iv[16];
 125         int i;
 126
 127         /* ECB method: encrypt the IV, then XOR this with plaintext */
 128         if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
 129                                                                 <= 0)
 130                 goto cipher_encrypt_err;
 131
 132         for (i = 0; i < srclen; i++)
 133                 *(dst+i) = *(src+i)^(encrypted_iv[i]);
 134
 135         return 0;
 136
 137 cipher_encrypt_err:
 138         PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
 139         return -EINVAL;
 140 }
 141
 142 /** Decrypt a single partial block
 143  *  Depends on openssl libcrypto
 144  *  Uses ECB+XOR to do CFB encryption, same result, more performant
 145  */
 146 static inline int
 147 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
 148                 uint8_t *iv, int ivlen, int srclen,
 149                 void *bpi_ctx)
 150 {
 151         EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
 152         int encrypted_ivlen;
 153         uint8_t encrypted_iv[16];
 154         int i;
 155
 156         /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
 157         if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
 158                                                                 <= 0)
 159                 goto cipher_decrypt_err;
 160
 161         for (i = 0; i < srclen; i++)
 162                 *(dst+i) = *(src+i)^(encrypted_iv[i]);
 163
 164         return 0;
 165
 166 cipher_decrypt_err:
 167         PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt for BPI IV failed");
 168         return -EINVAL;
 169 }
 170
 171 /** Creates a context in either AES or DES in ECB mode
 172  *  Depends on openssl libcrypto
 173  */
 174 static void *
 175 bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,
 176                 enum rte_crypto_cipher_operation direction __rte_unused,
 177                                         uint8_t *key)
 178 {
 179         const EVP_CIPHER *algo = NULL;
 180         EVP_CIPHER_CTX *ctx = EVP_CIPHER_CTX_new();
 181
 182         if (ctx == NULL)
 183                 goto ctx_init_err;
 184
 185         if (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)
 186                 algo = EVP_des_ecb();
 187         else
 188                 algo = EVP_aes_128_ecb();
 189
 190         /* IV will be ECB encrypted whether direction is encrypt or decrypt*/
 191         if (EVP_EncryptInit_ex(ctx, algo, NULL, key, 0) != 1)
 192                 goto ctx_init_err;
 193
 194         return ctx;
 195
 196 ctx_init_err:
 197         if (ctx != NULL)
 198                 EVP_CIPHER_CTX_free(ctx);
 199         return NULL;
 200 }
 201
 202 /** Frees a context previously created
 203  *  Depends on openssl libcrypto
 204  */
 205 static void
 206 bpi_cipher_ctx_free(void *bpi_ctx)
 207 {
 208         if (bpi_ctx != NULL)
 209                 EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);
 210 }
 211
 212 static inline uint32_t
 213 adf_modulo(uint32_t data, uint32_t shift);
 214
 215 static inline int
 216 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
 217                 struct qat_crypto_op_cookie *qat_op_cookie);
 218
 219 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
 220                 void *session)
 221 {
 222         struct qat_session *sess = session;
 223         phys_addr_t cd_paddr;
 224
 225         PMD_INIT_FUNC_TRACE();
 226         if (sess) {
 227                 if (sess->bpi_ctx) {
 228                         bpi_cipher_ctx_free(sess->bpi_ctx);
 229                         sess->bpi_ctx = NULL;
 230                 }
 231                 cd_paddr = sess->cd_paddr;
 232                 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
 233                 sess->cd_paddr = cd_paddr;
 234         } else
 235                 PMD_DRV_LOG(ERR, "NULL session");
 236 }
 237
 238 static int
 239 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
 240 {
 241         /* Cipher Only */
 242         if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
 243                 return ICP_QAT_FW_LA_CMD_CIPHER;
 244
 245         /* Authentication Only */
 246         if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
 247                 return ICP_QAT_FW_LA_CMD_AUTH;
 248
 249         if (xform->next == NULL)
 250                 return -1;
 251
 252         /* Cipher then Authenticate */
 253         if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
 254                         xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
 255                 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
 256
 257         /* Authenticate then Cipher */
 258         if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
 259                         xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
 260                 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
 261
 262         return -1;
 263 }
 264
 265 static struct rte_crypto_auth_xform *
 266 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
 267 {
 268         do {
 269                 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
 270                         return &xform->auth;
 271
 272                 xform = xform->next;
 273         } while (xform);
 274
 275         return NULL;
 276 }
 277
 278 static struct rte_crypto_cipher_xform *
 279 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
 280 {
 281         do {
 282                 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
 283                         return &xform->cipher;
 284
 285                 xform = xform->next;
 286         } while (xform);
 287
 288         return NULL;
 289 }
 290 void *
 291 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
 292                 struct rte_crypto_sym_xform *xform, void *session_private)
 293 {
 294         struct qat_session *session = session_private;
 295         struct qat_pmd_private *internals = dev->data->dev_private;
 296         struct rte_crypto_cipher_xform *cipher_xform = NULL;
 297
 298         /* Get cipher xform from crypto xform chain */
 299         cipher_xform = qat_get_cipher_xform(xform);
 300
 301         session->cipher_iv.offset = cipher_xform->iv.offset;
 302         session->cipher_iv.length = cipher_xform->iv.length;
 303
 304         switch (cipher_xform->algo) {
 305         case RTE_CRYPTO_CIPHER_AES_CBC:
 306                 if (qat_alg_validate_aes_key(cipher_xform->key.length,
 307                                 &session->qat_cipher_alg) != 0) {
 308                         PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
 309                         goto error_out;
 310                 }
 311                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 312                 break;
 313         case RTE_CRYPTO_CIPHER_AES_GCM:
 314                 if (qat_alg_validate_aes_key(cipher_xform->key.length,
 315                                 &session->qat_cipher_alg) != 0) {
 316                         PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
 317                         goto error_out;
 318                 }
 319                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 320                 break;
 321         case RTE_CRYPTO_CIPHER_AES_CTR:
 322                 if (qat_alg_validate_aes_key(cipher_xform->key.length,
 323                                 &session->qat_cipher_alg) != 0) {
 324                         PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
 325                         goto error_out;
 326                 }
 327                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 328                 break;
 329         case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
 330                 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
 331                                         &session->qat_cipher_alg) != 0) {
 332                         PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
 333                         goto error_out;
 334                 }
 335                 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
 336                 break;
 337         case RTE_CRYPTO_CIPHER_NULL:
 338                 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
 339                 break;
 340         case RTE_CRYPTO_CIPHER_KASUMI_F8:
 341                 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
 342                                         &session->qat_cipher_alg) != 0) {
 343                         PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
 344                         goto error_out;
 345                 }
 346                 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
 347                 break;
 348         case RTE_CRYPTO_CIPHER_3DES_CBC:
 349                 if (qat_alg_validate_3des_key(cipher_xform->key.length,
 350                                 &session->qat_cipher_alg) != 0) {
 351                         PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
 352                         goto error_out;
 353                 }
 354                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 355                 break;
 356         case RTE_CRYPTO_CIPHER_DES_CBC:
 357                 if (qat_alg_validate_des_key(cipher_xform->key.length,
 358                                 &session->qat_cipher_alg) != 0) {
 359                         PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
 360                         goto error_out;
 361                 }
 362                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 363                 break;
 364         case RTE_CRYPTO_CIPHER_3DES_CTR:
 365                 if (qat_alg_validate_3des_key(cipher_xform->key.length,
 366                                 &session->qat_cipher_alg) != 0) {
 367                         PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
 368                         goto error_out;
 369                 }
 370                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 371                 break;
 372         case RTE_CRYPTO_CIPHER_DES_DOCSISBPI:
 373                 session->bpi_ctx = bpi_cipher_ctx_init(
 374                                         cipher_xform->algo,
 375                                         cipher_xform->op,
 376                                         cipher_xform->key.data);
 377                 if (session->bpi_ctx == NULL) {
 378                         PMD_DRV_LOG(ERR, "failed to create DES BPI ctx");
 379                         goto error_out;
 380                 }
 381                 if (qat_alg_validate_des_key(cipher_xform->key.length,
 382                                 &session->qat_cipher_alg) != 0) {
 383                         PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
 384                         goto error_out;
 385                 }
 386                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 387                 break;
 388         case RTE_CRYPTO_CIPHER_AES_DOCSISBPI:
 389                 session->bpi_ctx = bpi_cipher_ctx_init(
 390                                         cipher_xform->algo,
 391                                         cipher_xform->op,
 392                                         cipher_xform->key.data);
 393                 if (session->bpi_ctx == NULL) {
 394                         PMD_DRV_LOG(ERR, "failed to create AES BPI ctx");
 395                         goto error_out;
 396                 }
 397                 if (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,
 398                                 &session->qat_cipher_alg) != 0) {
 399                         PMD_DRV_LOG(ERR, "Invalid AES DOCSISBPI key size");
 400                         goto error_out;
 401                 }
 402                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 403                 break;
 404         case RTE_CRYPTO_CIPHER_ZUC_EEA3:
 405                 if (!qat_is_cipher_alg_supported(
 406                         cipher_xform->algo, internals)) {
 407                         PMD_DRV_LOG(ERR, "%s not supported on this device",
 408                                 rte_crypto_cipher_algorithm_strings
 409                                         [cipher_xform->algo]);
 410                         goto error_out;
 411                 }
 412                 if (qat_alg_validate_zuc_key(cipher_xform->key.length,
 413                                 &session->qat_cipher_alg) != 0) {
 414                         PMD_DRV_LOG(ERR, "Invalid ZUC cipher key size");
 415                         goto error_out;
 416                 }
 417                 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
 418                 break;
 419         case RTE_CRYPTO_CIPHER_3DES_ECB:
 420         case RTE_CRYPTO_CIPHER_AES_ECB:
 421         case RTE_CRYPTO_CIPHER_AES_CCM:
 422         case RTE_CRYPTO_CIPHER_AES_F8:
 423         case RTE_CRYPTO_CIPHER_AES_XTS:
 424         case RTE_CRYPTO_CIPHER_ARC4:
 425                 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
 426                                 cipher_xform->algo);
 427                 goto error_out;
 428         default:
 429                 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
 430                                 cipher_xform->algo);
 431                 goto error_out;
 432         }
 433
 434         if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
 435                 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
 436         else
 437                 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
 438
 439         if (qat_alg_aead_session_create_content_desc_cipher(session,
 440                                                 cipher_xform->key.data,
 441                                                 cipher_xform->key.length))
 442                 goto error_out;
 443
 444         return session;
 445
 446 error_out:
 447         if (session->bpi_ctx) {
 448                 bpi_cipher_ctx_free(session->bpi_ctx);
 449                 session->bpi_ctx = NULL;
 450         }
 451         return NULL;
 452 }
 453
 454
 455 void *
 456 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
 457                 struct rte_crypto_sym_xform *xform, void *session_private)
 458 {
 459         struct qat_session *session = session_private;
 460
 461         int qat_cmd_id;
 462         PMD_INIT_FUNC_TRACE();
 463
 464         /* Get requested QAT command id */
 465         qat_cmd_id = qat_get_cmd_id(xform);
 466         if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
 467                 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
 468                 goto error_out;
 469         }
 470         session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
 471         switch (session->qat_cmd) {
 472         case ICP_QAT_FW_LA_CMD_CIPHER:
 473         session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
 474                 break;
 475         case ICP_QAT_FW_LA_CMD_AUTH:
 476         session = qat_crypto_sym_configure_session_auth(dev, xform, session);
 477                 break;
 478         case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
 479         session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
 480         session = qat_crypto_sym_configure_session_auth(dev, xform, session);
 481                 break;
 482         case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
 483         session = qat_crypto_sym_configure_session_auth(dev, xform, session);
 484         session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
 485                 break;
 486         case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
 487         case ICP_QAT_FW_LA_CMD_TRNG_TEST:
 488         case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
 489         case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
 490         case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
 491         case ICP_QAT_FW_LA_CMD_MGF1:
 492         case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
 493         case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
 494         case ICP_QAT_FW_LA_CMD_DELIMITER:
 495         PMD_DRV_LOG(ERR, "Unsupported Service %u",
 496                 session->qat_cmd);
 497                 goto error_out;
 498         default:
 499         PMD_DRV_LOG(ERR, "Unsupported Service %u",
 500                 session->qat_cmd);
 501                 goto error_out;
 502         }
 503
 504         return session;
 505
 506 error_out:
 507         return NULL;
 508 }
 509
 510 struct qat_session *
 511 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
 512                                 struct rte_crypto_sym_xform *xform,
 513                                 struct qat_session *session_private)
 514 {
 515
 516         struct qat_session *session = session_private;
 517         struct rte_crypto_auth_xform *auth_xform = NULL;
 518         struct rte_crypto_cipher_xform *cipher_xform = NULL;
 519         struct qat_pmd_private *internals = dev->data->dev_private;
 520         auth_xform = qat_get_auth_xform(xform);
 521
 522         switch (auth_xform->algo) {
 523         case RTE_CRYPTO_AUTH_SHA1_HMAC:
 524                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
 525                 break;
 526         case RTE_CRYPTO_AUTH_SHA224_HMAC:
 527                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
 528                 break;
 529         case RTE_CRYPTO_AUTH_SHA256_HMAC:
 530                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
 531                 break;
 532         case RTE_CRYPTO_AUTH_SHA384_HMAC:
 533                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
 534                 break;
 535         case RTE_CRYPTO_AUTH_SHA512_HMAC:
 536                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
 537                 break;
 538         case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
 539                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
 540                 break;
 541         case RTE_CRYPTO_AUTH_AES_GCM:
 542                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
 543                 break;
 544         case RTE_CRYPTO_AUTH_AES_GMAC:
 545                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
 546                 break;
 547         case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
 548                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
 549                 break;
 550         case RTE_CRYPTO_AUTH_MD5_HMAC:
 551                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
 552                 break;
 553         case RTE_CRYPTO_AUTH_NULL:
 554                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
 555                 break;
 556         case RTE_CRYPTO_AUTH_KASUMI_F9:
 557                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
 558                 break;
 559         case RTE_CRYPTO_AUTH_ZUC_EIA3:
 560                 if (!qat_is_auth_alg_supported(auth_xform->algo, internals)) {
 561                         PMD_DRV_LOG(ERR, "%s not supported on this device",
 562                                 rte_crypto_auth_algorithm_strings
 563                                 [auth_xform->algo]);
 564                         goto error_out;
 565                 }
 566                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;
 567                 break;
 568         case RTE_CRYPTO_AUTH_SHA1:
 569         case RTE_CRYPTO_AUTH_SHA256:
 570         case RTE_CRYPTO_AUTH_SHA512:
 571         case RTE_CRYPTO_AUTH_SHA224:
 572         case RTE_CRYPTO_AUTH_SHA384:
 573         case RTE_CRYPTO_AUTH_MD5:
 574         case RTE_CRYPTO_AUTH_AES_CCM:
 575         case RTE_CRYPTO_AUTH_AES_CMAC:
 576         case RTE_CRYPTO_AUTH_AES_CBC_MAC:
 577                 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
 578                                 auth_xform->algo);
 579                 goto error_out;
 580         default:
 581                 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
 582                                 auth_xform->algo);
 583                 goto error_out;
 584         }
 585         cipher_xform = qat_get_cipher_xform(xform);
 586
 587         session->auth_iv.offset = auth_xform->iv.offset;
 588         session->auth_iv.length = auth_xform->iv.length;
 589
 590         if ((session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
 591                         (session->qat_hash_alg ==
 592                                 ICP_QAT_HW_AUTH_ALGO_GALOIS_64))  {
 593                 if (qat_alg_aead_session_create_content_desc_auth(session,
 594                                 cipher_xform->key.data,
 595                                 cipher_xform->key.length,
 596                                 auth_xform->add_auth_data_length,
 597                                 auth_xform->digest_length,
 598                                 auth_xform->op))
 599                         goto error_out;
 600         } else {
 601                 if (qat_alg_aead_session_create_content_desc_auth(session,
 602                                 auth_xform->key.data,
 603                                 auth_xform->key.length,
 604                                 auth_xform->add_auth_data_length,
 605                                 auth_xform->digest_length,
 606                                 auth_xform->op))
 607                         goto error_out;
 608         }
 609         return session;
 610
 611 error_out:
 612         return NULL;
 613 }
 614
 615 unsigned qat_crypto_sym_get_session_private_size(
 616                 struct rte_cryptodev *dev __rte_unused)
 617 {
 618         return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
 619 }
 620
 621 static inline uint32_t
 622 qat_bpicipher_preprocess(struct qat_session *ctx,
 623                                 struct rte_crypto_op *op)
 624 {
 625         uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
 626         struct rte_crypto_sym_op *sym_op = op->sym;
 627         uint8_t last_block_len = sym_op->cipher.data.length % block_len;
 628
 629         if (last_block_len &&
 630                         ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
 631
 632                 /* Decrypt last block */
 633                 uint8_t *last_block, *dst, *iv;
 634                 uint32_t last_block_offset = sym_op->cipher.data.offset +
 635                                 sym_op->cipher.data.length - last_block_len;
 636                 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
 637                                 uint8_t *, last_block_offset);
 638
 639                 if (unlikely(sym_op->m_dst != NULL))
 640                         /* out-of-place operation (OOP) */
 641                         dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
 642                                                 uint8_t *, last_block_offset);
 643                 else
 644                         dst = last_block;
 645
 646                 if (last_block_len < sym_op->cipher.data.length)
 647                         /* use previous block ciphertext as IV */
 648                         iv = last_block - block_len;
 649                 else
 650                         /* runt block, i.e. less than one full block */
 651                         iv = rte_crypto_op_ctod_offset(op, uint8_t *,
 652                                         ctx->cipher_iv.offset);
 653
 654 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 655                 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
 656                         last_block_len);
 657                 if (sym_op->m_dst != NULL)
 658                         rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
 659                                 last_block_len);
 660 #endif
 661                 bpi_cipher_decrypt(last_block, dst, iv, block_len,
 662                                 last_block_len, ctx->bpi_ctx);
 663 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 664                 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
 665                         last_block_len);
 666                 if (sym_op->m_dst != NULL)
 667                         rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
 668                                 last_block_len);
 669 #endif
 670         }
 671
 672         return sym_op->cipher.data.length - last_block_len;
 673 }
 674
 675 static inline uint32_t
 676 qat_bpicipher_postprocess(struct qat_session *ctx,
 677                                 struct rte_crypto_op *op)
 678 {
 679         uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
 680         struct rte_crypto_sym_op *sym_op = op->sym;
 681         uint8_t last_block_len = sym_op->cipher.data.length % block_len;
 682
 683         if (last_block_len > 0 &&
 684                         ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
 685
 686                 /* Encrypt last block */
 687                 uint8_t *last_block, *dst, *iv;
 688                 uint32_t last_block_offset;
 689
 690                 last_block_offset = sym_op->cipher.data.offset +
 691                                 sym_op->cipher.data.length - last_block_len;
 692                 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
 693                                 uint8_t *, last_block_offset);
 694
 695                 if (unlikely(sym_op->m_dst != NULL))
 696                         /* out-of-place operation (OOP) */
 697                         dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
 698                                                 uint8_t *, last_block_offset);
 699                 else
 700                         dst = last_block;
 701
 702                 if (last_block_len < sym_op->cipher.data.length)
 703                         /* use previous block ciphertext as IV */
 704                         iv = dst - block_len;
 705                 else
 706                         /* runt block, i.e. less than one full block */
 707                         iv = rte_crypto_op_ctod_offset(op, uint8_t *,
 708                                         ctx->cipher_iv.offset);
 709
 710 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 711                 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
 712                         last_block_len);
 713                 if (sym_op->m_dst != NULL)
 714                         rte_hexdump(stdout, "BPI: dst before post-process:",
 715                                         dst, last_block_len);
 716 #endif
 717                 bpi_cipher_encrypt(last_block, dst, iv, block_len,
 718                                 last_block_len, ctx->bpi_ctx);
 719 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 720                 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
 721                         last_block_len);
 722                 if (sym_op->m_dst != NULL)
 723                         rte_hexdump(stdout, "BPI: dst after post-process:", dst,
 724                                 last_block_len);
 725 #endif
 726         }
 727         return sym_op->cipher.data.length - last_block_len;
 728 }
 729
 730 uint16_t
 731 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
 732                 uint16_t nb_ops)
 733 {
 734         register struct qat_queue *queue;
 735         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 736         register uint32_t nb_ops_sent = 0;
 737         register struct rte_crypto_op **cur_op = ops;
 738         register int ret;
 739         uint16_t nb_ops_possible = nb_ops;
 740         register uint8_t *base_addr;
 741         register uint32_t tail;
 742         int overflow;
 743
 744         if (unlikely(nb_ops == 0))
 745                 return 0;
 746
 747         /* read params used a lot in main loop into registers */
 748         queue = &(tmp_qp->tx_q);
 749         base_addr = (uint8_t *)queue->base_addr;
 750         tail = queue->tail;
 751
 752         /* Find how many can actually fit on the ring */
 753         overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
 754                                 - queue->max_inflights;
 755         if (overflow > 0) {
 756                 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
 757                 nb_ops_possible = nb_ops - overflow;
 758                 if (nb_ops_possible == 0)
 759                         return 0;
 760         }
 761
 762         while (nb_ops_sent != nb_ops_possible) {
 763                 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
 764                                 tmp_qp->op_cookies[tail / queue->msg_size]);
 765                 if (ret != 0) {
 766                         tmp_qp->stats.enqueue_err_count++;
 767                         /*
 768                          * This message cannot be enqueued,
 769                          * decrease number of ops that wasn't sent
 770                          */
 771                         rte_atomic16_sub(&tmp_qp->inflights16,
 772                                         nb_ops_possible - nb_ops_sent);
 773                         if (nb_ops_sent == 0)
 774                                 return 0;
 775                         goto kick_tail;
 776                 }
 777
 778                 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
 779                 nb_ops_sent++;
 780                 cur_op++;
 781         }
 782 kick_tail:
 783         WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
 784                         queue->hw_queue_number, tail);
 785         queue->tail = tail;
 786         tmp_qp->stats.enqueued_count += nb_ops_sent;
 787         return nb_ops_sent;
 788 }
 789
 790 uint16_t
 791 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
 792                 uint16_t nb_ops)
 793 {
 794         struct qat_queue *queue;
 795         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 796         uint32_t msg_counter = 0;
 797         struct rte_crypto_op *rx_op;
 798         struct icp_qat_fw_comn_resp *resp_msg;
 799
 800         queue = &(tmp_qp->rx_q);
 801         resp_msg = (struct icp_qat_fw_comn_resp *)
 802                         ((uint8_t *)queue->base_addr + queue->head);
 803
 804         while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
 805                         msg_counter != nb_ops) {
 806                 rx_op = (struct rte_crypto_op *)(uintptr_t)
 807                                 (resp_msg->opaque_data);
 808
 809 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 810                 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
 811                         sizeof(struct icp_qat_fw_comn_resp));
 812
 813 #endif
 814                 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
 815                                 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
 816                                         resp_msg->comn_hdr.comn_status)) {
 817                         rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
 818                 } else {
 819                         struct qat_session *sess = (struct qat_session *)
 820                                                 (rx_op->sym->session->_private);
 821                         if (sess->bpi_ctx)
 822                                 qat_bpicipher_postprocess(sess, rx_op);
 823                         rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
 824                 }
 825
 826                 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
 827                 queue->head = adf_modulo(queue->head +
 828                                 queue->msg_size,
 829                                 ADF_RING_SIZE_MODULO(queue->queue_size));
 830                 resp_msg = (struct icp_qat_fw_comn_resp *)
 831                                         ((uint8_t *)queue->base_addr +
 832                                                         queue->head);
 833                 *ops = rx_op;
 834                 ops++;
 835                 msg_counter++;
 836         }
 837         if (msg_counter > 0) {
 838                 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
 839                                         queue->hw_bundle_number,
 840                                         queue->hw_queue_number, queue->head);
 841                 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
 842                 tmp_qp->stats.dequeued_count += msg_counter;
 843         }
 844         return msg_counter;
 845 }
 846
 847 static inline int
 848 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
 849                 struct qat_alg_buf_list *list, uint32_t data_len)
 850 {
 851         int nr = 1;
 852
 853         uint32_t buf_len = rte_pktmbuf_mtophys(buf) -
 854                         buff_start + rte_pktmbuf_data_len(buf);
 855
 856         list->bufers[0].addr = buff_start;
 857         list->bufers[0].resrvd = 0;
 858         list->bufers[0].len = buf_len;
 859
 860         if (data_len <= buf_len) {
 861                 list->num_bufs = nr;
 862                 list->bufers[0].len = data_len;
 863                 return 0;
 864         }
 865
 866         buf = buf->next;
 867         while (buf) {
 868                 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
 869                         PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
 870                                         " entry(%u)",
 871                                         QAT_SGL_MAX_NUMBER);
 872                         return -EINVAL;
 873                 }
 874
 875                 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
 876                 list->bufers[nr].resrvd = 0;
 877                 list->bufers[nr].addr = rte_pktmbuf_mtophys(buf);
 878
 879                 buf_len += list->bufers[nr].len;
 880                 buf = buf->next;
 881
 882                 if (buf_len > data_len) {
 883                         list->bufers[nr].len -=
 884                                 buf_len - data_len;
 885                         buf = NULL;
 886                 }
 887                 ++nr;
 888         }
 889         list->num_bufs = nr;
 890
 891         return 0;
 892 }
 893
 894 static inline int
 895 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
 896                 struct qat_crypto_op_cookie *qat_op_cookie)
 897 {
 898         int ret = 0;
 899         struct qat_session *ctx;
 900         struct icp_qat_fw_la_cipher_req_params *cipher_param;
 901         struct icp_qat_fw_la_auth_req_params *auth_param;
 902         register struct icp_qat_fw_la_bulk_req *qat_req;
 903         uint8_t do_auth = 0, do_cipher = 0;
 904         uint32_t cipher_len = 0, cipher_ofs = 0;
 905         uint32_t auth_len = 0, auth_ofs = 0;
 906         uint32_t min_ofs = 0;
 907         uint64_t src_buf_start = 0, dst_buf_start = 0;
 908         uint8_t do_sgl = 0;
 909         uint8_t *cipher_iv_ptr = NULL;
 910
 911 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 912         if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
 913                 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
 914                                 "operation requests, op (%p) is not a "
 915                                 "symmetric operation.", op);
 916                 return -EINVAL;
 917         }
 918 #endif
 919         if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
 920                 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
 921                                 " requests, op (%p) is sessionless.", op);
 922                 return -EINVAL;
 923         }
 924
 925         if (unlikely(op->sym->session->dev_type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
 926                 PMD_DRV_LOG(ERR, "Session was not created for this device");
 927                 return -EINVAL;
 928         }
 929
 930         ctx = (struct qat_session *)op->sym->session->_private;
 931         qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
 932         rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
 933         qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
 934         cipher_param = (void *)&qat_req->serv_specif_rqpars;
 935         auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
 936
 937         if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
 938                 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
 939                 do_auth = 1;
 940                 do_cipher = 1;
 941         } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
 942                 do_auth = 1;
 943                 do_cipher = 0;
 944         } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
 945                 do_auth = 0;
 946                 do_cipher = 1;
 947         }
 948
 949         if (do_cipher) {
 950
 951                 if (ctx->qat_cipher_alg ==
 952                                          ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
 953                         ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
 954                         ctx->qat_cipher_alg ==
 955                                 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
 956
 957                         if (unlikely(
 958                                 (cipher_param->cipher_length % BYTE_LENGTH != 0)
 959                                  || (cipher_param->cipher_offset
 960                                                         % BYTE_LENGTH != 0))) {
 961                                 PMD_DRV_LOG(ERR,
 962                   "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
 963                                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
 964                                 return -EINVAL;
 965                         }
 966                         cipher_len = op->sym->cipher.data.length >> 3;
 967                         cipher_ofs = op->sym->cipher.data.offset >> 3;
 968
 969                 } else if (ctx->bpi_ctx) {
 970                         /* DOCSIS - only send complete blocks to device
 971                          * Process any partial block using CFB mode.
 972                          * Even if 0 complete blocks, still send this to device
 973                          * to get into rx queue for post-process and dequeuing
 974                          */
 975                         cipher_len = qat_bpicipher_preprocess(ctx, op);
 976                         cipher_ofs = op->sym->cipher.data.offset;
 977                 } else {
 978                         cipher_len = op->sym->cipher.data.length;
 979                         cipher_ofs = op->sym->cipher.data.offset;
 980                 }
 981
 982                 cipher_iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
 983                                         ctx->cipher_iv.offset);
 984                 /* copy IV into request if it fits */
 985                 if (ctx->cipher_iv.length <=
 986                                 sizeof(cipher_param->u.cipher_IV_array)) {
 987                         rte_memcpy(cipher_param->u.cipher_IV_array,
 988                                         cipher_iv_ptr,
 989                                         ctx->cipher_iv.length);
 990                 } else {
 991                         ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
 992                                         qat_req->comn_hdr.serv_specif_flags,
 993                                         ICP_QAT_FW_CIPH_IV_64BIT_PTR);
 994                         cipher_param->u.s.cipher_IV_ptr =
 995                                         rte_crypto_op_ctophys_offset(op,
 996                                                 ctx->cipher_iv.offset);
 997                 }
 998                 min_ofs = cipher_ofs;
 999         }
1000
1001         if (do_auth) {
1002
1003                 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
1004                         ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
1005                         ctx->qat_hash_alg ==
1006                                 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
1007                         if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
1008                                 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
1009                                 PMD_DRV_LOG(ERR,
1010                 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
1011                                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1012                                 return -EINVAL;
1013                         }
1014                         auth_ofs = op->sym->auth.data.offset >> 3;
1015                         auth_len = op->sym->auth.data.length >> 3;
1016
1017                         if (ctx->qat_hash_alg ==
1018                                         ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) {
1019                                 if (do_cipher) {
1020                                         auth_len = auth_len + auth_ofs + 1 -
1021                                                 ICP_QAT_HW_KASUMI_BLK_SZ;
1022                                         auth_ofs = ICP_QAT_HW_KASUMI_BLK_SZ;
1023                                 } else {
1024                                         auth_len = auth_len + auth_ofs + 1;
1025                                         auth_ofs = 0;
1026                                 }
1027                         } else
1028                                 auth_param->u1.aad_adr =
1029                                         rte_crypto_op_ctophys_offset(op,
1030                                                         ctx->auth_iv.offset);
1031
1032                 } else if (ctx->qat_hash_alg ==
1033                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1034                                 ctx->qat_hash_alg ==
1035                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1036                         auth_ofs = op->sym->cipher.data.offset;
1037                         auth_len = op->sym->cipher.data.length;
1038
1039                         auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
1040                 } else {
1041                         auth_ofs = op->sym->auth.data.offset;
1042                         auth_len = op->sym->auth.data.length;
1043
1044                 }
1045                 min_ofs = auth_ofs;
1046
1047                 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
1048
1049         }
1050
1051         if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
1052                 do_sgl = 1;
1053
1054         /* adjust for chain case */
1055         if (do_cipher && do_auth)
1056                 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
1057
1058         if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
1059                 min_ofs = 0;
1060
1061         if (unlikely(op->sym->m_dst != NULL)) {
1062                 /* Out-of-place operation (OOP)
1063                  * Don't align DMA start. DMA the minimum data-set
1064                  * so as not to overwrite data in dest buffer
1065                  */
1066                 src_buf_start =
1067                         rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs);
1068                 dst_buf_start =
1069                         rte_pktmbuf_mtophys_offset(op->sym->m_dst, min_ofs);
1070
1071         } else {
1072                 /* In-place operation
1073                  * Start DMA at nearest aligned address below min_ofs
1074                  */
1075                 src_buf_start =
1076                         rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs)
1077                                                 & QAT_64_BTYE_ALIGN_MASK;
1078
1079                 if (unlikely((rte_pktmbuf_mtophys(op->sym->m_src) -
1080                                         rte_pktmbuf_headroom(op->sym->m_src))
1081                                                         > src_buf_start)) {
1082                         /* alignment has pushed addr ahead of start of mbuf
1083                          * so revert and take the performance hit
1084                          */
1085                         src_buf_start =
1086                                 rte_pktmbuf_mtophys_offset(op->sym->m_src,
1087                                                                 min_ofs);
1088                 }
1089                 dst_buf_start = src_buf_start;
1090         }
1091
1092         if (do_cipher) {
1093                 cipher_param->cipher_offset =
1094                                 (uint32_t)rte_pktmbuf_mtophys_offset(
1095                                 op->sym->m_src, cipher_ofs) - src_buf_start;
1096                 cipher_param->cipher_length = cipher_len;
1097         } else {
1098                 cipher_param->cipher_offset = 0;
1099                 cipher_param->cipher_length = 0;
1100         }
1101         if (do_auth) {
1102                 auth_param->auth_off = (uint32_t)rte_pktmbuf_mtophys_offset(
1103                                 op->sym->m_src, auth_ofs) - src_buf_start;
1104                 auth_param->auth_len = auth_len;
1105         } else {
1106                 auth_param->auth_off = 0;
1107                 auth_param->auth_len = 0;
1108         }
1109         qat_req->comn_mid.dst_length =
1110                 qat_req->comn_mid.src_length =
1111                 (cipher_param->cipher_offset + cipher_param->cipher_length)
1112                 > (auth_param->auth_off + auth_param->auth_len) ?
1113                 (cipher_param->cipher_offset + cipher_param->cipher_length)
1114                 : (auth_param->auth_off + auth_param->auth_len);
1115
1116         if (do_sgl) {
1117
1118                 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
1119                                 QAT_COMN_PTR_TYPE_SGL);
1120                 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
1121                                 &qat_op_cookie->qat_sgl_list_src,
1122                                 qat_req->comn_mid.src_length);
1123                 if (ret) {
1124                         PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
1125                         return ret;
1126                 }
1127
1128                 if (likely(op->sym->m_dst == NULL))
1129                         qat_req->comn_mid.dest_data_addr =
1130                                 qat_req->comn_mid.src_data_addr =
1131                                 qat_op_cookie->qat_sgl_src_phys_addr;
1132                 else {
1133                         ret = qat_sgl_fill_array(op->sym->m_dst,
1134                                         dst_buf_start,
1135                                         &qat_op_cookie->qat_sgl_list_dst,
1136                                                 qat_req->comn_mid.dst_length);
1137
1138                         if (ret) {
1139                                 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
1140                                                 "fill sgl array");
1141                                 return ret;
1142                         }
1143
1144                         qat_req->comn_mid.src_data_addr =
1145                                 qat_op_cookie->qat_sgl_src_phys_addr;
1146                         qat_req->comn_mid.dest_data_addr =
1147                                         qat_op_cookie->qat_sgl_dst_phys_addr;
1148                 }
1149         } else {
1150                 qat_req->comn_mid.src_data_addr = src_buf_start;
1151                 qat_req->comn_mid.dest_data_addr = dst_buf_start;
1152         }
1153
1154         if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1155                         ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1156                 if (ctx->cipher_iv.length == 12) {
1157                         /*
1158                          * For GCM a 12 byte IV is allowed,
1159                          * but we need to inform the f/w
1160                          */
1161                         ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1162                                 qat_req->comn_hdr.serv_specif_flags,
1163                                 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1164                 }
1165                 if (op->sym->cipher.data.length == 0) {
1166                         /*
1167                          * GMAC
1168                          */
1169                         qat_req->comn_mid.dest_data_addr =
1170                                 qat_req->comn_mid.src_data_addr =
1171                                                 op->sym->auth.aad.phys_addr;
1172                         qat_req->comn_mid.dst_length =
1173                                 qat_req->comn_mid.src_length =
1174                                         rte_pktmbuf_data_len(op->sym->m_src);
1175                         cipher_param->cipher_length = 0;
1176                         cipher_param->cipher_offset = 0;
1177                         auth_param->u1.aad_adr = 0;
1178                         auth_param->auth_len = op->sym->auth.aad.length;
1179                         auth_param->auth_off = op->sym->auth.data.offset;
1180                         auth_param->u2.aad_sz = 0;
1181                 }
1182         }
1183
1184 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1185         rte_hexdump(stdout, "qat_req:", qat_req,
1186                         sizeof(struct icp_qat_fw_la_bulk_req));
1187         rte_hexdump(stdout, "src_data:",
1188                         rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1189                         rte_pktmbuf_data_len(op->sym->m_src));
1190         if (do_cipher)
1191                 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
1192                                 ctx->cipher_iv.length);
1193
1194         if (do_auth) {
1195                 if (ctx->auth_iv.length) {
1196                         uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
1197                                                         uint8_t *,
1198                                                         ctx->auth_iv.offset);
1199                         rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
1200                                                 ctx->auth_iv.length);
1201                 }
1202                 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1203                                 op->sym->auth.digest.length);
1204                 rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
1205                                 op->sym->auth.aad.length);
1206         }
1207 #endif
1208         return 0;
1209 }
1210
1211 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1212 {
1213         uint32_t div = data >> shift;
1214         uint32_t mult = div << shift;
1215
1216         return data - mult;
1217 }
1218
1219 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *sym_sess)
1220 {
1221         struct rte_cryptodev_sym_session *sess = sym_sess;
1222         struct qat_session *s = (void *)sess->_private;
1223
1224         PMD_INIT_FUNC_TRACE();
1225         s->cd_paddr = rte_mempool_virt2phy(mp, sess) +
1226                 offsetof(struct qat_session, cd) +
1227                 offsetof(struct rte_cryptodev_sym_session, _private);
1228 }
1229
1230 int qat_dev_config(__rte_unused struct rte_cryptodev *dev,
1231                 __rte_unused struct rte_cryptodev_config *config)
1232 {
1233         PMD_INIT_FUNC_TRACE();
1234         return 0;
1235 }
1236
1237 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1238 {
1239         PMD_INIT_FUNC_TRACE();
1240         return 0;
1241 }
1242
1243 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1244 {
1245         PMD_INIT_FUNC_TRACE();
1246 }
1247
1248 int qat_dev_close(struct rte_cryptodev *dev)
1249 {
1250         int i, ret;
1251
1252         PMD_INIT_FUNC_TRACE();
1253
1254         for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1255                 ret = qat_crypto_sym_qp_release(dev, i);
1256                 if (ret < 0)
1257                         return ret;
1258         }
1259
1260         return 0;
1261 }
1262
1263 void qat_dev_info_get(struct rte_cryptodev *dev,
1264                         struct rte_cryptodev_info *info)
1265 {
1266         struct qat_pmd_private *internals = dev->data->dev_private;
1267
1268         PMD_INIT_FUNC_TRACE();
1269         if (info != NULL) {
1270                 info->max_nb_queue_pairs =
1271                                 ADF_NUM_SYM_QPS_PER_BUNDLE *
1272                                 ADF_NUM_BUNDLES_PER_DEV;
1273                 info->feature_flags = dev->feature_flags;
1274                 info->capabilities = internals->qat_dev_capabilities;
1275                 info->sym.max_nb_sessions = internals->max_nb_sessions;
1276                 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
1277                 info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1278         }
1279 }
1280
1281 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1282                 struct rte_cryptodev_stats *stats)
1283 {
1284         int i;
1285         struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1286
1287         PMD_INIT_FUNC_TRACE();
1288         if (stats == NULL) {
1289                 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1290                 return;
1291         }
1292         for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1293                 if (qp[i] == NULL) {
1294                         PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1295                         continue;
1296                 }
1297
1298                 stats->enqueued_count += qp[i]->stats.enqueued_count;
1299                 stats->dequeued_count += qp[i]->stats.dequeued_count;
1300                 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1301                 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
1302         }
1303 }
1304
1305 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1306 {
1307         int i;
1308         struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1309
1310         PMD_INIT_FUNC_TRACE();
1311         for (i = 0; i < dev->data->nb_queue_pairs; i++)
1312                 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1313         PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");
1314 }