drivers/crypto/qat/qat_crypto.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *       * Redistributions of source code must retain the above copyright
  12  *         notice, this list of conditions and the following disclaimer.
  13  *       * Redistributions in binary form must reproduce the above copyright
  14  *         notice, this list of conditions and the following disclaimer in
  15  *         the documentation and/or other materials provided with the
  16  *         distribution.
  17  *       * Neither the name of Intel Corporation nor the names of its
  18  *         contributors may be used to endorse or promote products derived
  19  *         from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <strings.h>
  37 #include <string.h>
  38 #include <inttypes.h>
  39 #include <errno.h>
  40 #include <sys/queue.h>
  41 #include <stdarg.h>
  42
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_memory.h>
  47 #include <rte_memzone.h>
  48 #include <rte_tailq.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_launch.h>
  52 #include <rte_eal.h>
  53 #include <rte_per_lcore.h>
  54 #include <rte_lcore.h>
  55 #include <rte_atomic.h>
  56 #include <rte_branch_prediction.h>
  57 #include <rte_mempool.h>
  58 #include <rte_mbuf.h>
  59 #include <rte_string_fns.h>
  60 #include <rte_spinlock.h>
  61 #include <rte_hexdump.h>
  62 #include <rte_crypto_sym.h>
  63 #include <rte_cryptodev_pci.h>
  64 #include <openssl/evp.h>
  65
  66 #include "qat_logs.h"
  67 #include "qat_algs.h"
  68 #include "qat_crypto.h"
  69 #include "adf_transport_access_macros.h"
  70
  71 #define BYTE_LENGTH    8
  72
  73 static int
  74 qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,
  75                 struct qat_pmd_private *internals) {
  76         int i = 0;
  77         const struct rte_cryptodev_capabilities *capability;
  78
  79         while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
  80                         RTE_CRYPTO_OP_TYPE_UNDEFINED) {
  81                 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
  82                         continue;
  83
  84                 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)
  85                         continue;
  86
  87                 if (capability->sym.cipher.algo == algo)
  88                         return 1;
  89         }
  90         return 0;
  91 }
  92
  93 static int
  94 qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,
  95                 struct qat_pmd_private *internals) {
  96         int i = 0;
  97         const struct rte_cryptodev_capabilities *capability;
  98
  99         while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
 100                         RTE_CRYPTO_OP_TYPE_UNDEFINED) {
 101                 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
 102                         continue;
 103
 104                 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)
 105                         continue;
 106
 107                 if (capability->sym.auth.algo == algo)
 108                         return 1;
 109         }
 110         return 0;
 111 }
 112
 113 /** Encrypt a single partial block
 114  *  Depends on openssl libcrypto
 115  *  Uses ECB+XOR to do CFB encryption, same result, more performant
 116  */
 117 static inline int
 118 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
 119                 uint8_t *iv, int ivlen, int srclen,
 120                 void *bpi_ctx)
 121 {
 122         EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
 123         int encrypted_ivlen;
 124         uint8_t encrypted_iv[16];
 125         int i;
 126
 127         /* ECB method: encrypt the IV, then XOR this with plaintext */
 128         if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
 129                                                                 <= 0)
 130                 goto cipher_encrypt_err;
 131
 132         for (i = 0; i < srclen; i++)
 133                 *(dst+i) = *(src+i)^(encrypted_iv[i]);
 134
 135         return 0;
 136
 137 cipher_encrypt_err:
 138         PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
 139         return -EINVAL;
 140 }
 141
 142 /** Decrypt a single partial block
 143  *  Depends on openssl libcrypto
 144  *  Uses ECB+XOR to do CFB encryption, same result, more performant
 145  */
 146 static inline int
 147 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
 148                 uint8_t *iv, int ivlen, int srclen,
 149                 void *bpi_ctx)
 150 {
 151         EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
 152         int encrypted_ivlen;
 153         uint8_t encrypted_iv[16];
 154         int i;
 155
 156         /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
 157         if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
 158                                                                 <= 0)
 159                 goto cipher_decrypt_err;
 160
 161         for (i = 0; i < srclen; i++)
 162                 *(dst+i) = *(src+i)^(encrypted_iv[i]);
 163
 164         return 0;
 165
 166 cipher_decrypt_err:
 167         PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt for BPI IV failed");
 168         return -EINVAL;
 169 }
 170
 171 /** Creates a context in either AES or DES in ECB mode
 172  *  Depends on openssl libcrypto
 173  */
 174 static void *
 175 bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,
 176                 enum rte_crypto_cipher_operation direction __rte_unused,
 177                                         uint8_t *key)
 178 {
 179         const EVP_CIPHER *algo = NULL;
 180         EVP_CIPHER_CTX *ctx = EVP_CIPHER_CTX_new();
 181
 182         if (ctx == NULL)
 183                 goto ctx_init_err;
 184
 185         if (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)
 186                 algo = EVP_des_ecb();
 187         else
 188                 algo = EVP_aes_128_ecb();
 189
 190         /* IV will be ECB encrypted whether direction is encrypt or decrypt*/
 191         if (EVP_EncryptInit_ex(ctx, algo, NULL, key, 0) != 1)
 192                 goto ctx_init_err;
 193
 194         return ctx;
 195
 196 ctx_init_err:
 197         if (ctx != NULL)
 198                 EVP_CIPHER_CTX_free(ctx);
 199         return NULL;
 200 }
 201
 202 /** Frees a context previously created
 203  *  Depends on openssl libcrypto
 204  */
 205 static void
 206 bpi_cipher_ctx_free(void *bpi_ctx)
 207 {
 208         if (bpi_ctx != NULL)
 209                 EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);
 210 }
 211
 212 static inline uint32_t
 213 adf_modulo(uint32_t data, uint32_t shift);
 214
 215 static inline int
 216 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
 217                 struct qat_crypto_op_cookie *qat_op_cookie);
 218
 219 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
 220                 void *session)
 221 {
 222         struct qat_session *sess = session;
 223         phys_addr_t cd_paddr;
 224
 225         PMD_INIT_FUNC_TRACE();
 226         if (sess) {
 227                 if (sess->bpi_ctx) {
 228                         bpi_cipher_ctx_free(sess->bpi_ctx);
 229                         sess->bpi_ctx = NULL;
 230                 }
 231                 cd_paddr = sess->cd_paddr;
 232                 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
 233                 sess->cd_paddr = cd_paddr;
 234         } else
 235                 PMD_DRV_LOG(ERR, "NULL session");
 236 }
 237
 238 static int
 239 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
 240 {
 241         /* Cipher Only */
 242         if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
 243                 return ICP_QAT_FW_LA_CMD_CIPHER;
 244
 245         /* Authentication Only */
 246         if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
 247                 return ICP_QAT_FW_LA_CMD_AUTH;
 248
 249         if (xform->next == NULL)
 250                 return -1;
 251
 252         /* Cipher then Authenticate */
 253         if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
 254                         xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
 255                 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
 256
 257         /* Authenticate then Cipher */
 258         if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
 259                         xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
 260                 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
 261
 262         return -1;
 263 }
 264
 265 static struct rte_crypto_auth_xform *
 266 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
 267 {
 268         do {
 269                 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
 270                         return &xform->auth;
 271
 272                 xform = xform->next;
 273         } while (xform);
 274
 275         return NULL;
 276 }
 277
 278 static struct rte_crypto_cipher_xform *
 279 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
 280 {
 281         do {
 282                 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
 283                         return &xform->cipher;
 284
 285                 xform = xform->next;
 286         } while (xform);
 287
 288         return NULL;
 289 }
 290 void *
 291 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
 292                 struct rte_crypto_sym_xform *xform, void *session_private)
 293 {
 294         struct qat_session *session = session_private;
 295         struct qat_pmd_private *internals = dev->data->dev_private;
 296         struct rte_crypto_cipher_xform *cipher_xform = NULL;
 297
 298         /* Get cipher xform from crypto xform chain */
 299         cipher_xform = qat_get_cipher_xform(xform);
 300
 301         session->iv.offset = cipher_xform->iv.offset;
 302         session->iv.length = cipher_xform->iv.length;
 303
 304         switch (cipher_xform->algo) {
 305         case RTE_CRYPTO_CIPHER_AES_CBC:
 306                 if (qat_alg_validate_aes_key(cipher_xform->key.length,
 307                                 &session->qat_cipher_alg) != 0) {
 308                         PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
 309                         goto error_out;
 310                 }
 311                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 312                 break;
 313         case RTE_CRYPTO_CIPHER_AES_GCM:
 314                 if (qat_alg_validate_aes_key(cipher_xform->key.length,
 315                                 &session->qat_cipher_alg) != 0) {
 316                         PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
 317                         goto error_out;
 318                 }
 319                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 320                 break;
 321         case RTE_CRYPTO_CIPHER_AES_CTR:
 322                 if (qat_alg_validate_aes_key(cipher_xform->key.length,
 323                                 &session->qat_cipher_alg) != 0) {
 324                         PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
 325                         goto error_out;
 326                 }
 327                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 328                 break;
 329         case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
 330                 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
 331                                         &session->qat_cipher_alg) != 0) {
 332                         PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
 333                         goto error_out;
 334                 }
 335                 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
 336                 break;
 337         case RTE_CRYPTO_CIPHER_NULL:
 338                 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
 339                 break;
 340         case RTE_CRYPTO_CIPHER_KASUMI_F8:
 341                 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
 342                                         &session->qat_cipher_alg) != 0) {
 343                         PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
 344                         goto error_out;
 345                 }
 346                 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
 347                 break;
 348         case RTE_CRYPTO_CIPHER_3DES_CBC:
 349                 if (qat_alg_validate_3des_key(cipher_xform->key.length,
 350                                 &session->qat_cipher_alg) != 0) {
 351                         PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
 352                         goto error_out;
 353                 }
 354                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 355                 break;
 356         case RTE_CRYPTO_CIPHER_DES_CBC:
 357                 if (qat_alg_validate_des_key(cipher_xform->key.length,
 358                                 &session->qat_cipher_alg) != 0) {
 359                         PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
 360                         goto error_out;
 361                 }
 362                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 363                 break;
 364         case RTE_CRYPTO_CIPHER_3DES_CTR:
 365                 if (qat_alg_validate_3des_key(cipher_xform->key.length,
 366                                 &session->qat_cipher_alg) != 0) {
 367                         PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
 368                         goto error_out;
 369                 }
 370                 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 371                 break;
 372         case RTE_CRYPTO_CIPHER_DES_DOCSISBPI:
 373                 session->bpi_ctx = bpi_cipher_ctx_init(
 374                                         cipher_xform->algo,
 375                                         cipher_xform->op,
 376                                         cipher_xform->key.data);
 377                 if (session->bpi_ctx == NULL) {
 378                         PMD_DRV_LOG(ERR, "failed to create DES BPI ctx");
 379                         goto error_out;
 380                 }
 381                 if (qat_alg_validate_des_key(cipher_xform->key.length,
 382                                 &session->qat_cipher_alg) != 0) {
 383                         PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
 384                         goto error_out;
 385                 }
 386                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 387                 break;
 388         case RTE_CRYPTO_CIPHER_AES_DOCSISBPI:
 389                 session->bpi_ctx = bpi_cipher_ctx_init(
 390                                         cipher_xform->algo,
 391                                         cipher_xform->op,
 392                                         cipher_xform->key.data);
 393                 if (session->bpi_ctx == NULL) {
 394                         PMD_DRV_LOG(ERR, "failed to create AES BPI ctx");
 395                         goto error_out;
 396                 }
 397                 if (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,
 398                                 &session->qat_cipher_alg) != 0) {
 399                         PMD_DRV_LOG(ERR, "Invalid AES DOCSISBPI key size");
 400                         goto error_out;
 401                 }
 402                 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
 403                 break;
 404         case RTE_CRYPTO_CIPHER_ZUC_EEA3:
 405                 if (!qat_is_cipher_alg_supported(
 406                         cipher_xform->algo, internals)) {
 407                         PMD_DRV_LOG(ERR, "%s not supported on this device",
 408                                 rte_crypto_cipher_algorithm_strings
 409                                         [cipher_xform->algo]);
 410                         goto error_out;
 411                 }
 412                 if (qat_alg_validate_zuc_key(cipher_xform->key.length,
 413                                 &session->qat_cipher_alg) != 0) {
 414                         PMD_DRV_LOG(ERR, "Invalid ZUC cipher key size");
 415                         goto error_out;
 416                 }
 417                 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
 418                 break;
 419         case RTE_CRYPTO_CIPHER_3DES_ECB:
 420         case RTE_CRYPTO_CIPHER_AES_ECB:
 421         case RTE_CRYPTO_CIPHER_AES_CCM:
 422         case RTE_CRYPTO_CIPHER_AES_F8:
 423         case RTE_CRYPTO_CIPHER_AES_XTS:
 424         case RTE_CRYPTO_CIPHER_ARC4:
 425                 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
 426                                 cipher_xform->algo);
 427                 goto error_out;
 428         default:
 429                 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
 430                                 cipher_xform->algo);
 431                 goto error_out;
 432         }
 433
 434         if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
 435                 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
 436         else
 437                 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
 438
 439         if (qat_alg_aead_session_create_content_desc_cipher(session,
 440                                                 cipher_xform->key.data,
 441                                                 cipher_xform->key.length))
 442                 goto error_out;
 443
 444         return session;
 445
 446 error_out:
 447         if (session->bpi_ctx) {
 448                 bpi_cipher_ctx_free(session->bpi_ctx);
 449                 session->bpi_ctx = NULL;
 450         }
 451         return NULL;
 452 }
 453
 454
 455 void *
 456 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
 457                 struct rte_crypto_sym_xform *xform, void *session_private)
 458 {
 459         struct qat_session *session = session_private;
 460
 461         int qat_cmd_id;
 462         PMD_INIT_FUNC_TRACE();
 463
 464         /* Get requested QAT command id */
 465         qat_cmd_id = qat_get_cmd_id(xform);
 466         if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
 467                 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
 468                 goto error_out;
 469         }
 470         session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
 471         switch (session->qat_cmd) {
 472         case ICP_QAT_FW_LA_CMD_CIPHER:
 473         session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
 474                 break;
 475         case ICP_QAT_FW_LA_CMD_AUTH:
 476         session = qat_crypto_sym_configure_session_auth(dev, xform, session);
 477                 break;
 478         case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
 479         session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
 480         session = qat_crypto_sym_configure_session_auth(dev, xform, session);
 481                 break;
 482         case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
 483         session = qat_crypto_sym_configure_session_auth(dev, xform, session);
 484         session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
 485                 break;
 486         case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
 487         case ICP_QAT_FW_LA_CMD_TRNG_TEST:
 488         case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
 489         case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
 490         case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
 491         case ICP_QAT_FW_LA_CMD_MGF1:
 492         case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
 493         case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
 494         case ICP_QAT_FW_LA_CMD_DELIMITER:
 495         PMD_DRV_LOG(ERR, "Unsupported Service %u",
 496                 session->qat_cmd);
 497                 goto error_out;
 498         default:
 499         PMD_DRV_LOG(ERR, "Unsupported Service %u",
 500                 session->qat_cmd);
 501                 goto error_out;
 502         }
 503
 504         return session;
 505
 506 error_out:
 507         return NULL;
 508 }
 509
 510 struct qat_session *
 511 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
 512                                 struct rte_crypto_sym_xform *xform,
 513                                 struct qat_session *session_private)
 514 {
 515
 516         struct qat_session *session = session_private;
 517         struct rte_crypto_auth_xform *auth_xform = NULL;
 518         struct rte_crypto_cipher_xform *cipher_xform = NULL;
 519         struct qat_pmd_private *internals = dev->data->dev_private;
 520         auth_xform = qat_get_auth_xform(xform);
 521
 522         switch (auth_xform->algo) {
 523         case RTE_CRYPTO_AUTH_SHA1_HMAC:
 524                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
 525                 break;
 526         case RTE_CRYPTO_AUTH_SHA224_HMAC:
 527                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
 528                 break;
 529         case RTE_CRYPTO_AUTH_SHA256_HMAC:
 530                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
 531                 break;
 532         case RTE_CRYPTO_AUTH_SHA384_HMAC:
 533                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
 534                 break;
 535         case RTE_CRYPTO_AUTH_SHA512_HMAC:
 536                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
 537                 break;
 538         case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
 539                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
 540                 break;
 541         case RTE_CRYPTO_AUTH_AES_GCM:
 542                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
 543                 break;
 544         case RTE_CRYPTO_AUTH_AES_GMAC:
 545                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
 546                 break;
 547         case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
 548                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
 549                 break;
 550         case RTE_CRYPTO_AUTH_MD5_HMAC:
 551                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
 552                 break;
 553         case RTE_CRYPTO_AUTH_NULL:
 554                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
 555                 break;
 556         case RTE_CRYPTO_AUTH_KASUMI_F9:
 557                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
 558                 break;
 559         case RTE_CRYPTO_AUTH_ZUC_EIA3:
 560                 if (!qat_is_auth_alg_supported(auth_xform->algo, internals)) {
 561                         PMD_DRV_LOG(ERR, "%s not supported on this device",
 562                                 rte_crypto_auth_algorithm_strings
 563                                 [auth_xform->algo]);
 564                         goto error_out;
 565                 }
 566                 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;
 567                 break;
 568         case RTE_CRYPTO_AUTH_SHA1:
 569         case RTE_CRYPTO_AUTH_SHA256:
 570         case RTE_CRYPTO_AUTH_SHA512:
 571         case RTE_CRYPTO_AUTH_SHA224:
 572         case RTE_CRYPTO_AUTH_SHA384:
 573         case RTE_CRYPTO_AUTH_MD5:
 574         case RTE_CRYPTO_AUTH_AES_CCM:
 575         case RTE_CRYPTO_AUTH_AES_CMAC:
 576         case RTE_CRYPTO_AUTH_AES_CBC_MAC:
 577                 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
 578                                 auth_xform->algo);
 579                 goto error_out;
 580         default:
 581                 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
 582                                 auth_xform->algo);
 583                 goto error_out;
 584         }
 585         cipher_xform = qat_get_cipher_xform(xform);
 586
 587         if ((session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
 588                         (session->qat_hash_alg ==
 589                                 ICP_QAT_HW_AUTH_ALGO_GALOIS_64))  {
 590                 if (qat_alg_aead_session_create_content_desc_auth(session,
 591                                 cipher_xform->key.data,
 592                                 cipher_xform->key.length,
 593                                 auth_xform->add_auth_data_length,
 594                                 auth_xform->digest_length,
 595                                 auth_xform->op))
 596                         goto error_out;
 597         } else {
 598                 if (qat_alg_aead_session_create_content_desc_auth(session,
 599                                 auth_xform->key.data,
 600                                 auth_xform->key.length,
 601                                 auth_xform->add_auth_data_length,
 602                                 auth_xform->digest_length,
 603                                 auth_xform->op))
 604                         goto error_out;
 605         }
 606         return session;
 607
 608 error_out:
 609         return NULL;
 610 }
 611
 612 unsigned qat_crypto_sym_get_session_private_size(
 613                 struct rte_cryptodev *dev __rte_unused)
 614 {
 615         return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
 616 }
 617
 618 static inline uint32_t
 619 qat_bpicipher_preprocess(struct qat_session *ctx,
 620                                 struct rte_crypto_op *op)
 621 {
 622         uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
 623         struct rte_crypto_sym_op *sym_op = op->sym;
 624         uint8_t last_block_len = sym_op->cipher.data.length % block_len;
 625
 626         if (last_block_len &&
 627                         ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
 628
 629                 /* Decrypt last block */
 630                 uint8_t *last_block, *dst, *iv;
 631                 uint32_t last_block_offset = sym_op->cipher.data.offset +
 632                                 sym_op->cipher.data.length - last_block_len;
 633                 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
 634                                 uint8_t *, last_block_offset);
 635
 636                 if (unlikely(sym_op->m_dst != NULL))
 637                         /* out-of-place operation (OOP) */
 638                         dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
 639                                                 uint8_t *, last_block_offset);
 640                 else
 641                         dst = last_block;
 642
 643                 if (last_block_len < sym_op->cipher.data.length)
 644                         /* use previous block ciphertext as IV */
 645                         iv = last_block - block_len;
 646                 else
 647                         /* runt block, i.e. less than one full block */
 648                         iv = rte_crypto_op_ctod_offset(op, uint8_t *,
 649                                         ctx->iv.offset);
 650
 651 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 652                 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
 653                         last_block_len);
 654                 if (sym_op->m_dst != NULL)
 655                         rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
 656                                 last_block_len);
 657 #endif
 658                 bpi_cipher_decrypt(last_block, dst, iv, block_len,
 659                                 last_block_len, ctx->bpi_ctx);
 660 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 661                 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
 662                         last_block_len);
 663                 if (sym_op->m_dst != NULL)
 664                         rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
 665                                 last_block_len);
 666 #endif
 667         }
 668
 669         return sym_op->cipher.data.length - last_block_len;
 670 }
 671
 672 static inline uint32_t
 673 qat_bpicipher_postprocess(struct qat_session *ctx,
 674                                 struct rte_crypto_op *op)
 675 {
 676         uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
 677         struct rte_crypto_sym_op *sym_op = op->sym;
 678         uint8_t last_block_len = sym_op->cipher.data.length % block_len;
 679
 680         if (last_block_len > 0 &&
 681                         ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
 682
 683                 /* Encrypt last block */
 684                 uint8_t *last_block, *dst, *iv;
 685                 uint32_t last_block_offset;
 686
 687                 last_block_offset = sym_op->cipher.data.offset +
 688                                 sym_op->cipher.data.length - last_block_len;
 689                 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
 690                                 uint8_t *, last_block_offset);
 691
 692                 if (unlikely(sym_op->m_dst != NULL))
 693                         /* out-of-place operation (OOP) */
 694                         dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
 695                                                 uint8_t *, last_block_offset);
 696                 else
 697                         dst = last_block;
 698
 699                 if (last_block_len < sym_op->cipher.data.length)
 700                         /* use previous block ciphertext as IV */
 701                         iv = dst - block_len;
 702                 else
 703                         /* runt block, i.e. less than one full block */
 704                         iv = rte_crypto_op_ctod_offset(op, uint8_t *,
 705                                         ctx->iv.offset);
 706
 707 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 708                 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
 709                         last_block_len);
 710                 if (sym_op->m_dst != NULL)
 711                         rte_hexdump(stdout, "BPI: dst before post-process:",
 712                                         dst, last_block_len);
 713 #endif
 714                 bpi_cipher_encrypt(last_block, dst, iv, block_len,
 715                                 last_block_len, ctx->bpi_ctx);
 716 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 717                 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
 718                         last_block_len);
 719                 if (sym_op->m_dst != NULL)
 720                         rte_hexdump(stdout, "BPI: dst after post-process:", dst,
 721                                 last_block_len);
 722 #endif
 723         }
 724         return sym_op->cipher.data.length - last_block_len;
 725 }
 726
 727 uint16_t
 728 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
 729                 uint16_t nb_ops)
 730 {
 731         register struct qat_queue *queue;
 732         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 733         register uint32_t nb_ops_sent = 0;
 734         register struct rte_crypto_op **cur_op = ops;
 735         register int ret;
 736         uint16_t nb_ops_possible = nb_ops;
 737         register uint8_t *base_addr;
 738         register uint32_t tail;
 739         int overflow;
 740
 741         if (unlikely(nb_ops == 0))
 742                 return 0;
 743
 744         /* read params used a lot in main loop into registers */
 745         queue = &(tmp_qp->tx_q);
 746         base_addr = (uint8_t *)queue->base_addr;
 747         tail = queue->tail;
 748
 749         /* Find how many can actually fit on the ring */
 750         overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
 751                                 - queue->max_inflights;
 752         if (overflow > 0) {
 753                 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
 754                 nb_ops_possible = nb_ops - overflow;
 755                 if (nb_ops_possible == 0)
 756                         return 0;
 757         }
 758
 759         while (nb_ops_sent != nb_ops_possible) {
 760                 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
 761                                 tmp_qp->op_cookies[tail / queue->msg_size]);
 762                 if (ret != 0) {
 763                         tmp_qp->stats.enqueue_err_count++;
 764                         /*
 765                          * This message cannot be enqueued,
 766                          * decrease number of ops that wasn't sent
 767                          */
 768                         rte_atomic16_sub(&tmp_qp->inflights16,
 769                                         nb_ops_possible - nb_ops_sent);
 770                         if (nb_ops_sent == 0)
 771                                 return 0;
 772                         goto kick_tail;
 773                 }
 774
 775                 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
 776                 nb_ops_sent++;
 777                 cur_op++;
 778         }
 779 kick_tail:
 780         WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
 781                         queue->hw_queue_number, tail);
 782         queue->tail = tail;
 783         tmp_qp->stats.enqueued_count += nb_ops_sent;
 784         return nb_ops_sent;
 785 }
 786
 787 uint16_t
 788 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
 789                 uint16_t nb_ops)
 790 {
 791         struct qat_queue *queue;
 792         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 793         uint32_t msg_counter = 0;
 794         struct rte_crypto_op *rx_op;
 795         struct icp_qat_fw_comn_resp *resp_msg;
 796
 797         queue = &(tmp_qp->rx_q);
 798         resp_msg = (struct icp_qat_fw_comn_resp *)
 799                         ((uint8_t *)queue->base_addr + queue->head);
 800
 801         while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
 802                         msg_counter != nb_ops) {
 803                 rx_op = (struct rte_crypto_op *)(uintptr_t)
 804                                 (resp_msg->opaque_data);
 805
 806 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 807                 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
 808                         sizeof(struct icp_qat_fw_comn_resp));
 809
 810 #endif
 811                 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
 812                                 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
 813                                         resp_msg->comn_hdr.comn_status)) {
 814                         rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
 815                 } else {
 816                         struct qat_session *sess = (struct qat_session *)
 817                                                 (rx_op->sym->session->_private);
 818                         if (sess->bpi_ctx)
 819                                 qat_bpicipher_postprocess(sess, rx_op);
 820                         rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
 821                 }
 822
 823                 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
 824                 queue->head = adf_modulo(queue->head +
 825                                 queue->msg_size,
 826                                 ADF_RING_SIZE_MODULO(queue->queue_size));
 827                 resp_msg = (struct icp_qat_fw_comn_resp *)
 828                                         ((uint8_t *)queue->base_addr +
 829                                                         queue->head);
 830                 *ops = rx_op;
 831                 ops++;
 832                 msg_counter++;
 833         }
 834         if (msg_counter > 0) {
 835                 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
 836                                         queue->hw_bundle_number,
 837                                         queue->hw_queue_number, queue->head);
 838                 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
 839                 tmp_qp->stats.dequeued_count += msg_counter;
 840         }
 841         return msg_counter;
 842 }
 843
 844 static inline int
 845 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
 846                 struct qat_alg_buf_list *list, uint32_t data_len)
 847 {
 848         int nr = 1;
 849
 850         uint32_t buf_len = rte_pktmbuf_mtophys(buf) -
 851                         buff_start + rte_pktmbuf_data_len(buf);
 852
 853         list->bufers[0].addr = buff_start;
 854         list->bufers[0].resrvd = 0;
 855         list->bufers[0].len = buf_len;
 856
 857         if (data_len <= buf_len) {
 858                 list->num_bufs = nr;
 859                 list->bufers[0].len = data_len;
 860                 return 0;
 861         }
 862
 863         buf = buf->next;
 864         while (buf) {
 865                 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
 866                         PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
 867                                         " entry(%u)",
 868                                         QAT_SGL_MAX_NUMBER);
 869                         return -EINVAL;
 870                 }
 871
 872                 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
 873                 list->bufers[nr].resrvd = 0;
 874                 list->bufers[nr].addr = rte_pktmbuf_mtophys(buf);
 875
 876                 buf_len += list->bufers[nr].len;
 877                 buf = buf->next;
 878
 879                 if (buf_len > data_len) {
 880                         list->bufers[nr].len -=
 881                                 buf_len - data_len;
 882                         buf = NULL;
 883                 }
 884                 ++nr;
 885         }
 886         list->num_bufs = nr;
 887
 888         return 0;
 889 }
 890
 891 static inline int
 892 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
 893                 struct qat_crypto_op_cookie *qat_op_cookie)
 894 {
 895         int ret = 0;
 896         struct qat_session *ctx;
 897         struct icp_qat_fw_la_cipher_req_params *cipher_param;
 898         struct icp_qat_fw_la_auth_req_params *auth_param;
 899         register struct icp_qat_fw_la_bulk_req *qat_req;
 900         uint8_t do_auth = 0, do_cipher = 0;
 901         uint32_t cipher_len = 0, cipher_ofs = 0;
 902         uint32_t auth_len = 0, auth_ofs = 0;
 903         uint32_t min_ofs = 0;
 904         uint64_t src_buf_start = 0, dst_buf_start = 0;
 905         uint8_t do_sgl = 0;
 906         uint8_t *iv_ptr;
 907
 908
 909 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 910         if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
 911                 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
 912                                 "operation requests, op (%p) is not a "
 913                                 "symmetric operation.", op);
 914                 return -EINVAL;
 915         }
 916 #endif
 917         if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
 918                 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
 919                                 " requests, op (%p) is sessionless.", op);
 920                 return -EINVAL;
 921         }
 922
 923         if (unlikely(op->sym->session->dev_type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
 924                 PMD_DRV_LOG(ERR, "Session was not created for this device");
 925                 return -EINVAL;
 926         }
 927
 928         ctx = (struct qat_session *)op->sym->session->_private;
 929         qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
 930         rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
 931         qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
 932         cipher_param = (void *)&qat_req->serv_specif_rqpars;
 933         auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
 934
 935         if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
 936                 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
 937                 do_auth = 1;
 938                 do_cipher = 1;
 939         } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
 940                 do_auth = 1;
 941                 do_cipher = 0;
 942         } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
 943                 do_auth = 0;
 944                 do_cipher = 1;
 945         }
 946
 947         if (do_cipher) {
 948
 949                 if (ctx->qat_cipher_alg ==
 950                                          ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
 951                         ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
 952                         ctx->qat_cipher_alg ==
 953                                 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
 954
 955                         if (unlikely(
 956                                 (cipher_param->cipher_length % BYTE_LENGTH != 0)
 957                                  || (cipher_param->cipher_offset
 958                                                         % BYTE_LENGTH != 0))) {
 959                                 PMD_DRV_LOG(ERR,
 960                   "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
 961                                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
 962                                 return -EINVAL;
 963                         }
 964                         cipher_len = op->sym->cipher.data.length >> 3;
 965                         cipher_ofs = op->sym->cipher.data.offset >> 3;
 966
 967                 } else if (ctx->bpi_ctx) {
 968                         /* DOCSIS - only send complete blocks to device
 969                          * Process any partial block using CFB mode.
 970                          * Even if 0 complete blocks, still send this to device
 971                          * to get into rx queue for post-process and dequeuing
 972                          */
 973                         cipher_len = qat_bpicipher_preprocess(ctx, op);
 974                         cipher_ofs = op->sym->cipher.data.offset;
 975                 } else {
 976                         cipher_len = op->sym->cipher.data.length;
 977                         cipher_ofs = op->sym->cipher.data.offset;
 978                 }
 979
 980                 iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
 981                                         ctx->iv.offset);
 982                 /* copy IV into request if it fits */
 983                 if (ctx->iv.length <=
 984                                 sizeof(cipher_param->u.cipher_IV_array)) {
 985                         rte_memcpy(cipher_param->u.cipher_IV_array,
 986                                         iv_ptr,
 987                                         ctx->iv.length);
 988                 } else {
 989                         ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
 990                                         qat_req->comn_hdr.serv_specif_flags,
 991                                         ICP_QAT_FW_CIPH_IV_64BIT_PTR);
 992                         cipher_param->u.s.cipher_IV_ptr =
 993                                         rte_crypto_op_ctophys_offset(op,
 994                                                 ctx->iv.offset);
 995                 }
 996                 min_ofs = cipher_ofs;
 997         }
 998
 999         if (do_auth) {
1000
1001                 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
1002                         ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
1003                         ctx->qat_hash_alg ==
1004                                 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
1005                         if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
1006                                 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
1007                                 PMD_DRV_LOG(ERR,
1008                 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
1009                                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1010                                 return -EINVAL;
1011                         }
1012                         auth_ofs = op->sym->auth.data.offset >> 3;
1013                         auth_len = op->sym->auth.data.length >> 3;
1014
1015                         if (ctx->qat_hash_alg ==
1016                                         ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) {
1017                                 if (do_cipher) {
1018                                         auth_len = auth_len + auth_ofs + 1 -
1019                                                 ICP_QAT_HW_KASUMI_BLK_SZ;
1020                                         auth_ofs = ICP_QAT_HW_KASUMI_BLK_SZ;
1021                                 } else {
1022                                         auth_len = auth_len + auth_ofs + 1;
1023                                         auth_ofs = 0;
1024                                 }
1025                         }
1026
1027                 } else if (ctx->qat_hash_alg ==
1028                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1029                                 ctx->qat_hash_alg ==
1030                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1031                         auth_ofs = op->sym->cipher.data.offset;
1032                         auth_len = op->sym->cipher.data.length;
1033                 } else {
1034                         auth_ofs = op->sym->auth.data.offset;
1035                         auth_len = op->sym->auth.data.length;
1036                 }
1037                 min_ofs = auth_ofs;
1038
1039                 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
1040
1041                 auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
1042
1043         }
1044
1045         if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
1046                 do_sgl = 1;
1047
1048         /* adjust for chain case */
1049         if (do_cipher && do_auth)
1050                 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
1051
1052         if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
1053                 min_ofs = 0;
1054
1055         if (unlikely(op->sym->m_dst != NULL)) {
1056                 /* Out-of-place operation (OOP)
1057                  * Don't align DMA start. DMA the minimum data-set
1058                  * so as not to overwrite data in dest buffer
1059                  */
1060                 src_buf_start =
1061                         rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs);
1062                 dst_buf_start =
1063                         rte_pktmbuf_mtophys_offset(op->sym->m_dst, min_ofs);
1064
1065         } else {
1066                 /* In-place operation
1067                  * Start DMA at nearest aligned address below min_ofs
1068                  */
1069                 src_buf_start =
1070                         rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs)
1071                                                 & QAT_64_BTYE_ALIGN_MASK;
1072
1073                 if (unlikely((rte_pktmbuf_mtophys(op->sym->m_src) -
1074                                         rte_pktmbuf_headroom(op->sym->m_src))
1075                                                         > src_buf_start)) {
1076                         /* alignment has pushed addr ahead of start of mbuf
1077                          * so revert and take the performance hit
1078                          */
1079                         src_buf_start =
1080                                 rte_pktmbuf_mtophys_offset(op->sym->m_src,
1081                                                                 min_ofs);
1082                 }
1083                 dst_buf_start = src_buf_start;
1084         }
1085
1086         if (do_cipher) {
1087                 cipher_param->cipher_offset =
1088                                 (uint32_t)rte_pktmbuf_mtophys_offset(
1089                                 op->sym->m_src, cipher_ofs) - src_buf_start;
1090                 cipher_param->cipher_length = cipher_len;
1091         } else {
1092                 cipher_param->cipher_offset = 0;
1093                 cipher_param->cipher_length = 0;
1094         }
1095         if (do_auth) {
1096                 auth_param->auth_off = (uint32_t)rte_pktmbuf_mtophys_offset(
1097                                 op->sym->m_src, auth_ofs) - src_buf_start;
1098                 auth_param->auth_len = auth_len;
1099         } else {
1100                 auth_param->auth_off = 0;
1101                 auth_param->auth_len = 0;
1102         }
1103         qat_req->comn_mid.dst_length =
1104                 qat_req->comn_mid.src_length =
1105                 (cipher_param->cipher_offset + cipher_param->cipher_length)
1106                 > (auth_param->auth_off + auth_param->auth_len) ?
1107                 (cipher_param->cipher_offset + cipher_param->cipher_length)
1108                 : (auth_param->auth_off + auth_param->auth_len);
1109
1110         if (do_sgl) {
1111
1112                 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
1113                                 QAT_COMN_PTR_TYPE_SGL);
1114                 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
1115                                 &qat_op_cookie->qat_sgl_list_src,
1116                                 qat_req->comn_mid.src_length);
1117                 if (ret) {
1118                         PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
1119                         return ret;
1120                 }
1121
1122                 if (likely(op->sym->m_dst == NULL))
1123                         qat_req->comn_mid.dest_data_addr =
1124                                 qat_req->comn_mid.src_data_addr =
1125                                 qat_op_cookie->qat_sgl_src_phys_addr;
1126                 else {
1127                         ret = qat_sgl_fill_array(op->sym->m_dst,
1128                                         dst_buf_start,
1129                                         &qat_op_cookie->qat_sgl_list_dst,
1130                                                 qat_req->comn_mid.dst_length);
1131
1132                         if (ret) {
1133                                 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
1134                                                 "fill sgl array");
1135                                 return ret;
1136                         }
1137
1138                         qat_req->comn_mid.src_data_addr =
1139                                 qat_op_cookie->qat_sgl_src_phys_addr;
1140                         qat_req->comn_mid.dest_data_addr =
1141                                         qat_op_cookie->qat_sgl_dst_phys_addr;
1142                 }
1143         } else {
1144                 qat_req->comn_mid.src_data_addr = src_buf_start;
1145                 qat_req->comn_mid.dest_data_addr = dst_buf_start;
1146         }
1147
1148         if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1149                         ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1150                 if (ctx->iv.length == 12) {
1151                         /*
1152                          * For GCM a 12 byte IV is allowed,
1153                          * but we need to inform the f/w
1154                          */
1155                         ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1156                                 qat_req->comn_hdr.serv_specif_flags,
1157                                 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1158                 }
1159                 if (op->sym->cipher.data.length == 0) {
1160                         /*
1161                          * GMAC
1162                          */
1163                         qat_req->comn_mid.dest_data_addr =
1164                                 qat_req->comn_mid.src_data_addr =
1165                                                 op->sym->auth.aad.phys_addr;
1166                         qat_req->comn_mid.dst_length =
1167                                 qat_req->comn_mid.src_length =
1168                                         rte_pktmbuf_data_len(op->sym->m_src);
1169                         cipher_param->cipher_length = 0;
1170                         cipher_param->cipher_offset = 0;
1171                         auth_param->u1.aad_adr = 0;
1172                         auth_param->auth_len = op->sym->auth.aad.length;
1173                         auth_param->auth_off = op->sym->auth.data.offset;
1174                         auth_param->u2.aad_sz = 0;
1175                 }
1176         }
1177
1178 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1179         rte_hexdump(stdout, "qat_req:", qat_req,
1180                         sizeof(struct icp_qat_fw_la_bulk_req));
1181         rte_hexdump(stdout, "src_data:",
1182                         rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1183                         rte_pktmbuf_data_len(op->sym->m_src));
1184         if (do_cipher)
1185                 rte_hexdump(stdout, "iv:", iv_ptr,
1186                                 ctx->iv.length);
1187
1188         if (do_auth) {
1189                 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1190                                 op->sym->auth.digest.length);
1191                 rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
1192                                 op->sym->auth.aad.length);
1193         }
1194 #endif
1195         return 0;
1196 }
1197
1198 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1199 {
1200         uint32_t div = data >> shift;
1201         uint32_t mult = div << shift;
1202
1203         return data - mult;
1204 }
1205
1206 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *sym_sess)
1207 {
1208         struct rte_cryptodev_sym_session *sess = sym_sess;
1209         struct qat_session *s = (void *)sess->_private;
1210
1211         PMD_INIT_FUNC_TRACE();
1212         s->cd_paddr = rte_mempool_virt2phy(mp, sess) +
1213                 offsetof(struct qat_session, cd) +
1214                 offsetof(struct rte_cryptodev_sym_session, _private);
1215 }
1216
1217 int qat_dev_config(__rte_unused struct rte_cryptodev *dev,
1218                 __rte_unused struct rte_cryptodev_config *config)
1219 {
1220         PMD_INIT_FUNC_TRACE();
1221         return 0;
1222 }
1223
1224 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1225 {
1226         PMD_INIT_FUNC_TRACE();
1227         return 0;
1228 }
1229
1230 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1231 {
1232         PMD_INIT_FUNC_TRACE();
1233 }
1234
1235 int qat_dev_close(struct rte_cryptodev *dev)
1236 {
1237         int i, ret;
1238
1239         PMD_INIT_FUNC_TRACE();
1240
1241         for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1242                 ret = qat_crypto_sym_qp_release(dev, i);
1243                 if (ret < 0)
1244                         return ret;
1245         }
1246
1247         return 0;
1248 }
1249
1250 void qat_dev_info_get(struct rte_cryptodev *dev,
1251                         struct rte_cryptodev_info *info)
1252 {
1253         struct qat_pmd_private *internals = dev->data->dev_private;
1254
1255         PMD_INIT_FUNC_TRACE();
1256         if (info != NULL) {
1257                 info->max_nb_queue_pairs =
1258                                 ADF_NUM_SYM_QPS_PER_BUNDLE *
1259                                 ADF_NUM_BUNDLES_PER_DEV;
1260                 info->feature_flags = dev->feature_flags;
1261                 info->capabilities = internals->qat_dev_capabilities;
1262                 info->sym.max_nb_sessions = internals->max_nb_sessions;
1263                 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
1264                 info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1265         }
1266 }
1267
1268 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1269                 struct rte_cryptodev_stats *stats)
1270 {
1271         int i;
1272         struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1273
1274         PMD_INIT_FUNC_TRACE();
1275         if (stats == NULL) {
1276                 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1277                 return;
1278         }
1279         for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1280                 if (qp[i] == NULL) {
1281                         PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1282                         continue;
1283                 }
1284
1285                 stats->enqueued_count += qp[i]->stats.enqueued_count;
1286                 stats->dequeued_count += qp[i]->stats.dequeued_count;
1287                 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1288                 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
1289         }
1290 }
1291
1292 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1293 {
1294         int i;
1295         struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1296
1297         PMD_INIT_FUNC_TRACE();
1298         for (i = 0; i < dev->data->nb_queue_pairs; i++)
1299                 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1300         PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");
1301 }