drivers/net: do not use ethdev driver
[dpdk.git] / drivers / net / bnxt / bnxt_ethdev.c
1 /*-
2  *   BSD LICENSE
3  *
4  *   Copyright(c) Broadcom Limited.
5  *   All rights reserved.
6  *
7  *   Redistribution and use in source and binary forms, with or without
8  *   modification, are permitted provided that the following conditions
9  *   are met:
10  *
11  *     * Redistributions of source code must retain the above copyright
12  *       notice, this list of conditions and the following disclaimer.
13  *     * Redistributions in binary form must reproduce the above copyright
14  *       notice, this list of conditions and the following disclaimer in
15  *       the documentation and/or other materials provided with the
16  *       distribution.
17  *     * Neither the name of Broadcom Corporation nor the names of its
18  *       contributors may be used to endorse or promote products derived
19  *       from this software without specific prior written permission.
20  *
21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33
34 #include <inttypes.h>
35 #include <stdbool.h>
36
37 #include <rte_dev.h>
38 #include <rte_ethdev.h>
39 #include <rte_ethdev_pci.h>
40 #include <rte_malloc.h>
41 #include <rte_cycles.h>
42
43 #include "bnxt.h"
44 #include "bnxt_cpr.h"
45 #include "bnxt_filter.h"
46 #include "bnxt_hwrm.h"
47 #include "bnxt_irq.h"
48 #include "bnxt_ring.h"
49 #include "bnxt_rxq.h"
50 #include "bnxt_rxr.h"
51 #include "bnxt_stats.h"
52 #include "bnxt_txq.h"
53 #include "bnxt_txr.h"
54 #include "bnxt_vnic.h"
55 #include "hsi_struct_def_dpdk.h"
56
57 #define DRV_MODULE_NAME         "bnxt"
58 static const char bnxt_version[] =
59         "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
60
61 #define PCI_VENDOR_ID_BROADCOM 0x14E4
62
63 #define BROADCOM_DEV_ID_57301 0x16c8
64 #define BROADCOM_DEV_ID_57302 0x16c9
65 #define BROADCOM_DEV_ID_57304_PF 0x16ca
66 #define BROADCOM_DEV_ID_57304_VF 0x16cb
67 #define BROADCOM_DEV_ID_57417_MF 0x16cc
68 #define BROADCOM_DEV_ID_NS2 0x16cd
69 #define BROADCOM_DEV_ID_57311 0x16ce
70 #define BROADCOM_DEV_ID_57312 0x16cf
71 #define BROADCOM_DEV_ID_57402 0x16d0
72 #define BROADCOM_DEV_ID_57404 0x16d1
73 #define BROADCOM_DEV_ID_57406_PF 0x16d2
74 #define BROADCOM_DEV_ID_57406_VF 0x16d3
75 #define BROADCOM_DEV_ID_57402_MF 0x16d4
76 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
77 #define BROADCOM_DEV_ID_57412 0x16d6
78 #define BROADCOM_DEV_ID_57414 0x16d7
79 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
80 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
81 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
82 #define BROADCOM_DEV_ID_57412_MF 0x16de
83 #define BROADCOM_DEV_ID_57314 0x16df
84 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
85 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
86 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
87 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
88 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
89 #define BROADCOM_DEV_ID_57404_MF 0x16e7
90 #define BROADCOM_DEV_ID_57406_MF 0x16e8
91 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
92 #define BROADCOM_DEV_ID_57407_MF 0x16ea
93 #define BROADCOM_DEV_ID_57414_MF 0x16ec
94 #define BROADCOM_DEV_ID_57416_MF 0x16ee
95
96 static const struct rte_pci_id bnxt_pci_id_map[] = {
97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
129         { .vendor_id = 0, /* sentinel */ },
130 };
131
132 #define BNXT_ETH_RSS_SUPPORT (  \
133         ETH_RSS_IPV4 |          \
134         ETH_RSS_NONFRAG_IPV4_TCP |      \
135         ETH_RSS_NONFRAG_IPV4_UDP |      \
136         ETH_RSS_IPV6 |          \
137         ETH_RSS_NONFRAG_IPV6_TCP |      \
138         ETH_RSS_NONFRAG_IPV6_UDP)
139
140 /***********************/
141
142 /*
143  * High level utility functions
144  */
145
146 static void bnxt_free_mem(struct bnxt *bp)
147 {
148         bnxt_free_filter_mem(bp);
149         bnxt_free_vnic_attributes(bp);
150         bnxt_free_vnic_mem(bp);
151
152         bnxt_free_stats(bp);
153         bnxt_free_tx_rings(bp);
154         bnxt_free_rx_rings(bp);
155         bnxt_free_def_cp_ring(bp);
156 }
157
158 static int bnxt_alloc_mem(struct bnxt *bp)
159 {
160         int rc;
161
162         /* Default completion ring */
163         rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
164         if (rc)
165                 goto alloc_mem_err;
166
167         rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
168                               bp->def_cp_ring, "def_cp");
169         if (rc)
170                 goto alloc_mem_err;
171
172         rc = bnxt_alloc_vnic_mem(bp);
173         if (rc)
174                 goto alloc_mem_err;
175
176         rc = bnxt_alloc_vnic_attributes(bp);
177         if (rc)
178                 goto alloc_mem_err;
179
180         rc = bnxt_alloc_filter_mem(bp);
181         if (rc)
182                 goto alloc_mem_err;
183
184         return 0;
185
186 alloc_mem_err:
187         bnxt_free_mem(bp);
188         return rc;
189 }
190
191 static int bnxt_init_chip(struct bnxt *bp)
192 {
193         unsigned int i, rss_idx, fw_idx;
194         struct rte_eth_link new;
195         int rc;
196
197         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
198         if (rc) {
199                 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
200                 goto err_out;
201         }
202
203         rc = bnxt_alloc_hwrm_rings(bp);
204         if (rc) {
205                 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
206                 goto err_out;
207         }
208
209         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
210         if (rc) {
211                 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
212                 goto err_out;
213         }
214
215         rc = bnxt_mq_rx_configure(bp);
216         if (rc) {
217                 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
218                 goto err_out;
219         }
220
221         /* VNIC configuration */
222         for (i = 0; i < bp->nr_vnics; i++) {
223                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
224
225                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
226                 if (rc) {
227                         RTE_LOG(ERR, PMD, "HWRM vnic alloc failure rc: %x\n",
228                                 rc);
229                         goto err_out;
230                 }
231
232                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
233                 if (rc) {
234                         RTE_LOG(ERR, PMD,
235                                 "HWRM vnic ctx alloc failure rc: %x\n", rc);
236                         goto err_out;
237                 }
238
239                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
240                 if (rc) {
241                         RTE_LOG(ERR, PMD, "HWRM vnic cfg failure rc: %x\n", rc);
242                         goto err_out;
243                 }
244
245                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
246                 if (rc) {
247                         RTE_LOG(ERR, PMD, "HWRM vnic filter failure rc: %x\n",
248                                 rc);
249                         goto err_out;
250                 }
251                 if (vnic->rss_table && vnic->hash_type) {
252                         /*
253                          * Fill the RSS hash & redirection table with
254                          * ring group ids for all VNICs
255                          */
256                         for (rss_idx = 0, fw_idx = 0;
257                              rss_idx < HW_HASH_INDEX_SIZE;
258                              rss_idx++, fw_idx++) {
259                                 if (vnic->fw_grp_ids[fw_idx] ==
260                                     INVALID_HW_RING_ID)
261                                         fw_idx = 0;
262                                 vnic->rss_table[rss_idx] =
263                                                 vnic->fw_grp_ids[fw_idx];
264                         }
265                         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
266                         if (rc) {
267                                 RTE_LOG(ERR, PMD,
268                                         "HWRM vnic set RSS failure rc: %x\n",
269                                         rc);
270                                 goto err_out;
271                         }
272                 }
273         }
274         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0]);
275         if (rc) {
276                 RTE_LOG(ERR, PMD,
277                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
278                 goto err_out;
279         }
280
281         rc = bnxt_get_hwrm_link_config(bp, &new);
282         if (rc) {
283                 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
284                 goto err_out;
285         }
286
287         if (!bp->link_info.link_up) {
288                 rc = bnxt_set_hwrm_link_config(bp, true);
289                 if (rc) {
290                         RTE_LOG(ERR, PMD,
291                                 "HWRM link config failure rc: %x\n", rc);
292                         goto err_out;
293                 }
294         }
295
296         return 0;
297
298 err_out:
299         bnxt_free_all_hwrm_resources(bp);
300
301         return rc;
302 }
303
304 static int bnxt_shutdown_nic(struct bnxt *bp)
305 {
306         bnxt_free_all_hwrm_resources(bp);
307         bnxt_free_all_filters(bp);
308         bnxt_free_all_vnics(bp);
309         return 0;
310 }
311
312 static int bnxt_init_nic(struct bnxt *bp)
313 {
314         int rc;
315
316         bnxt_init_ring_grps(bp);
317         bnxt_init_vnics(bp);
318         bnxt_init_filters(bp);
319
320         rc = bnxt_init_chip(bp);
321         if (rc)
322                 return rc;
323
324         return 0;
325 }
326
327 /*
328  * Device configuration and status function
329  */
330
331 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
332                                   struct rte_eth_dev_info *dev_info)
333 {
334         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
335         uint16_t max_vnics, i, j, vpool, vrxq;
336
337         dev_info->pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
338
339         /* MAC Specifics */
340         dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
341         dev_info->max_hash_mac_addrs = 0;
342
343         /* PF/VF specifics */
344         if (BNXT_PF(bp)) {
345                 dev_info->max_rx_queues = bp->pf.max_rx_rings;
346                 dev_info->max_tx_queues = bp->pf.max_tx_rings;
347                 dev_info->max_vfs = bp->pf.active_vfs;
348                 dev_info->reta_size = bp->pf.max_rsscos_ctx;
349                 max_vnics = bp->pf.max_vnics;
350         } else {
351                 dev_info->max_rx_queues = bp->vf.max_rx_rings;
352                 dev_info->max_tx_queues = bp->vf.max_tx_rings;
353                 dev_info->reta_size = bp->vf.max_rsscos_ctx;
354                 max_vnics = bp->vf.max_vnics;
355         }
356
357         /* Fast path specifics */
358         dev_info->min_rx_bufsize = 1;
359         dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
360                                   + VLAN_TAG_SIZE;
361         dev_info->rx_offload_capa = 0;
362         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
363                                         DEV_TX_OFFLOAD_TCP_CKSUM |
364                                         DEV_TX_OFFLOAD_UDP_CKSUM |
365                                         DEV_TX_OFFLOAD_TCP_TSO;
366
367         /* *INDENT-OFF* */
368         dev_info->default_rxconf = (struct rte_eth_rxconf) {
369                 .rx_thresh = {
370                         .pthresh = 8,
371                         .hthresh = 8,
372                         .wthresh = 0,
373                 },
374                 .rx_free_thresh = 32,
375                 .rx_drop_en = 0,
376         };
377
378         dev_info->default_txconf = (struct rte_eth_txconf) {
379                 .tx_thresh = {
380                         .pthresh = 32,
381                         .hthresh = 0,
382                         .wthresh = 0,
383                 },
384                 .tx_free_thresh = 32,
385                 .tx_rs_thresh = 32,
386                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
387                              ETH_TXQ_FLAGS_NOOFFLOADS,
388         };
389         eth_dev->data->dev_conf.intr_conf.lsc = 1;
390
391         /* *INDENT-ON* */
392
393         /*
394          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
395          *       need further investigation.
396          */
397
398         /* VMDq resources */
399         vpool = 64; /* ETH_64_POOLS */
400         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
401         for (i = 0; i < 4; vpool >>= 1, i++) {
402                 if (max_vnics > vpool) {
403                         for (j = 0; j < 5; vrxq >>= 1, j++) {
404                                 if (dev_info->max_rx_queues > vrxq) {
405                                         if (vpool > vrxq)
406                                                 vpool = vrxq;
407                                         goto found;
408                                 }
409                         }
410                         /* Not enough resources to support VMDq */
411                         break;
412                 }
413         }
414         /* Not enough resources to support VMDq */
415         vpool = 0;
416         vrxq = 0;
417 found:
418         dev_info->max_vmdq_pools = vpool;
419         dev_info->vmdq_queue_num = vrxq;
420
421         dev_info->vmdq_pool_base = 0;
422         dev_info->vmdq_queue_base = 0;
423 }
424
425 /* Configure the device based on the configuration provided */
426 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
427 {
428         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
429
430         bp->rx_queues = (void *)eth_dev->data->rx_queues;
431         bp->tx_queues = (void *)eth_dev->data->tx_queues;
432
433         /* Inherit new configurations */
434         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
435         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
436         bp->rx_cp_nr_rings = bp->rx_nr_rings;
437         bp->tx_cp_nr_rings = bp->tx_nr_rings;
438
439         if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
440                 eth_dev->data->mtu =
441                                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
442                                 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
443         return 0;
444 }
445
446 static inline int
447 rte_bnxt_atomic_write_link_status(struct rte_eth_dev *eth_dev,
448                                 struct rte_eth_link *link)
449 {
450         struct rte_eth_link *dst = &eth_dev->data->dev_link;
451         struct rte_eth_link *src = link;
452
453         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
454                                         *(uint64_t *)src) == 0)
455                 return 1;
456
457         return 0;
458 }
459
460 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
461 {
462         struct rte_eth_link *link = &eth_dev->data->dev_link;
463
464         if (link->link_status)
465                 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
466                         (uint8_t)(eth_dev->data->port_id),
467                         (uint32_t)link->link_speed,
468                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
469                         ("full-duplex") : ("half-duplex\n"));
470         else
471                 RTE_LOG(INFO, PMD, "Port %d Link Down\n",
472                         (uint8_t)(eth_dev->data->port_id));
473 }
474
475 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
476 {
477         bnxt_print_link_info(eth_dev);
478         return 0;
479 }
480
481 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
482 {
483         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
484         int rc;
485
486         bp->dev_stopped = 0;
487         rc = bnxt_hwrm_func_reset(bp);
488         if (rc) {
489                 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
490                 rc = -1;
491                 goto error;
492         }
493
494         rc = bnxt_setup_int(bp);
495         if (rc)
496                 goto error;
497
498         rc = bnxt_alloc_mem(bp);
499         if (rc)
500                 goto error;
501
502         rc = bnxt_request_int(bp);
503         if (rc)
504                 goto error;
505
506         rc = bnxt_init_nic(bp);
507         if (rc)
508                 goto error;
509
510         bnxt_enable_int(bp);
511
512         bnxt_link_update_op(eth_dev, 0);
513         return 0;
514
515 error:
516         bnxt_shutdown_nic(bp);
517         bnxt_disable_int(bp);
518         bnxt_free_int(bp);
519         bnxt_free_tx_mbufs(bp);
520         bnxt_free_rx_mbufs(bp);
521         bnxt_free_mem(bp);
522         return rc;
523 }
524
525 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
526 {
527         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
528
529         eth_dev->data->dev_link.link_status = 1;
530         bnxt_set_hwrm_link_config(bp, true);
531         return 0;
532 }
533
534 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
535 {
536         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
537
538         eth_dev->data->dev_link.link_status = 0;
539         bnxt_set_hwrm_link_config(bp, false);
540         return 0;
541 }
542
543 /* Unload the driver, release resources */
544 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
545 {
546         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
547
548         if (bp->eth_dev->data->dev_started) {
549                 /* TBD: STOP HW queues DMA */
550                 eth_dev->data->dev_link.link_status = 0;
551         }
552         bnxt_set_hwrm_link_config(bp, false);
553         bnxt_disable_int(bp);
554         bnxt_free_int(bp);
555         bnxt_shutdown_nic(bp);
556         bp->dev_stopped = 1;
557 }
558
559 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
560 {
561         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
562
563         if (bp->dev_stopped == 0)
564                 bnxt_dev_stop_op(eth_dev);
565
566         bnxt_free_tx_mbufs(bp);
567         bnxt_free_rx_mbufs(bp);
568         bnxt_free_mem(bp);
569         if (eth_dev->data->mac_addrs != NULL) {
570                 rte_free(eth_dev->data->mac_addrs);
571                 eth_dev->data->mac_addrs = NULL;
572         }
573         if (bp->grp_info != NULL) {
574                 rte_free(bp->grp_info);
575                 bp->grp_info = NULL;
576         }
577 }
578
579 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
580                                     uint32_t index)
581 {
582         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
583         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
584         struct bnxt_vnic_info *vnic;
585         struct bnxt_filter_info *filter, *temp_filter;
586         int i;
587
588         /*
589          * Loop through all VNICs from the specified filter flow pools to
590          * remove the corresponding MAC addr filter
591          */
592         for (i = 0; i < MAX_FF_POOLS; i++) {
593                 if (!(pool_mask & (1ULL << i)))
594                         continue;
595
596                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
597                         filter = STAILQ_FIRST(&vnic->filter);
598                         while (filter) {
599                                 temp_filter = STAILQ_NEXT(filter, next);
600                                 if (filter->mac_index == index) {
601                                         STAILQ_REMOVE(&vnic->filter, filter,
602                                                       bnxt_filter_info, next);
603                                         bnxt_hwrm_clear_filter(bp, filter);
604                                         filter->mac_index = INVALID_MAC_INDEX;
605                                         memset(&filter->l2_addr, 0,
606                                                ETHER_ADDR_LEN);
607                                         STAILQ_INSERT_TAIL(
608                                                         &bp->free_filter_list,
609                                                         filter, next);
610                                 }
611                                 filter = temp_filter;
612                         }
613                 }
614         }
615 }
616
617 static void bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
618                                  struct ether_addr *mac_addr,
619                                  uint32_t index, uint32_t pool)
620 {
621         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
622         struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
623         struct bnxt_filter_info *filter;
624
625         if (BNXT_VF(bp)) {
626                 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
627                 return;
628         }
629
630         if (!vnic) {
631                 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
632                 return;
633         }
634         /* Attach requested MAC address to the new l2_filter */
635         STAILQ_FOREACH(filter, &vnic->filter, next) {
636                 if (filter->mac_index == index) {
637                         RTE_LOG(ERR, PMD,
638                                 "MAC addr already existed for pool %d\n", pool);
639                         return;
640                 }
641         }
642         filter = bnxt_alloc_filter(bp);
643         if (!filter) {
644                 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
645                 return;
646         }
647         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
648         filter->mac_index = index;
649         memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
650         bnxt_hwrm_set_filter(bp, vnic, filter);
651 }
652
653 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
654 {
655         int rc = 0;
656         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
657         struct rte_eth_link new;
658         unsigned int cnt = BNXT_LINK_WAIT_CNT;
659
660         memset(&new, 0, sizeof(new));
661         do {
662                 /* Retrieve link info from hardware */
663                 rc = bnxt_get_hwrm_link_config(bp, &new);
664                 if (rc) {
665                         new.link_speed = ETH_LINK_SPEED_100M;
666                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
667                         RTE_LOG(ERR, PMD,
668                                 "Failed to retrieve link rc = 0x%x!", rc);
669                         goto out;
670                 }
671                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
672
673                 if (!wait_to_complete)
674                         break;
675         } while (!new.link_status && cnt--);
676
677 out:
678         /* Timed out or success */
679         if (new.link_status != eth_dev->data->dev_link.link_status ||
680         new.link_speed != eth_dev->data->dev_link.link_speed) {
681                 rte_bnxt_atomic_write_link_status(eth_dev, &new);
682                 bnxt_print_link_info(eth_dev);
683         }
684
685         return rc;
686 }
687
688 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
689 {
690         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
691         struct bnxt_vnic_info *vnic;
692
693         if (bp->vnic_info == NULL)
694                 return;
695
696         vnic = &bp->vnic_info[0];
697
698         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
699         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
700 }
701
702 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
703 {
704         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
705         struct bnxt_vnic_info *vnic;
706
707         if (bp->vnic_info == NULL)
708                 return;
709
710         vnic = &bp->vnic_info[0];
711
712         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
713         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
714 }
715
716 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
717 {
718         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
719         struct bnxt_vnic_info *vnic;
720
721         if (bp->vnic_info == NULL)
722                 return;
723
724         vnic = &bp->vnic_info[0];
725
726         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
727         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
728 }
729
730 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
731 {
732         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
733         struct bnxt_vnic_info *vnic;
734
735         if (bp->vnic_info == NULL)
736                 return;
737
738         vnic = &bp->vnic_info[0];
739
740         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
741         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
742 }
743
744 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
745                             struct rte_eth_rss_reta_entry64 *reta_conf,
746                             uint16_t reta_size)
747 {
748         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
749         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
750         struct bnxt_vnic_info *vnic;
751         int i;
752
753         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
754                 return -EINVAL;
755
756         if (reta_size != HW_HASH_INDEX_SIZE) {
757                 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
758                         "(%d) must equal the size supported by the hardware "
759                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
760                 return -EINVAL;
761         }
762         /* Update the RSS VNIC(s) */
763         for (i = 0; i < MAX_FF_POOLS; i++) {
764                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
765                         memcpy(vnic->rss_table, reta_conf, reta_size);
766
767                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
768                 }
769         }
770         return 0;
771 }
772
773 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
774                               struct rte_eth_rss_reta_entry64 *reta_conf,
775                               uint16_t reta_size)
776 {
777         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
778         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
779         struct rte_intr_handle *intr_handle
780                 = &bp->pdev->intr_handle;
781
782         /* Retrieve from the default VNIC */
783         if (!vnic)
784                 return -EINVAL;
785         if (!vnic->rss_table)
786                 return -EINVAL;
787
788         if (reta_size != HW_HASH_INDEX_SIZE) {
789                 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
790                         "(%d) must equal the size supported by the hardware "
791                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
792                 return -EINVAL;
793         }
794         /* EW - need to revisit here copying from u64 to u16 */
795         memcpy(reta_conf, vnic->rss_table, reta_size);
796
797         if (rte_intr_allow_others(intr_handle)) {
798                 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
799                         bnxt_dev_lsc_intr_setup(eth_dev);
800         }
801
802         return 0;
803 }
804
805 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
806                                    struct rte_eth_rss_conf *rss_conf)
807 {
808         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
809         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
810         struct bnxt_vnic_info *vnic;
811         uint16_t hash_type = 0;
812         int i;
813
814         /*
815          * If RSS enablement were different than dev_configure,
816          * then return -EINVAL
817          */
818         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
819                 if (!rss_conf->rss_hf)
820                         return -EINVAL;
821         } else {
822                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
823                         return -EINVAL;
824         }
825         if (rss_conf->rss_hf & ETH_RSS_IPV4)
826                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
827         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
828                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
829         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
830                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
831         if (rss_conf->rss_hf & ETH_RSS_IPV6)
832                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
833         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
834                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
835         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
836                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
837
838         /* Update the RSS VNIC(s) */
839         for (i = 0; i < MAX_FF_POOLS; i++) {
840                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
841                         vnic->hash_type = hash_type;
842
843                         /*
844                          * Use the supplied key if the key length is
845                          * acceptable and the rss_key is not NULL
846                          */
847                         if (rss_conf->rss_key &&
848                             rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
849                                 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
850                                        rss_conf->rss_key_len);
851
852                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
853                 }
854         }
855         return 0;
856 }
857
858 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
859                                      struct rte_eth_rss_conf *rss_conf)
860 {
861         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
862         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
863         int len;
864         uint32_t hash_types;
865
866         /* RSS configuration is the same for all VNICs */
867         if (vnic && vnic->rss_hash_key) {
868                 if (rss_conf->rss_key) {
869                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
870                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
871                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
872                 }
873
874                 hash_types = vnic->hash_type;
875                 rss_conf->rss_hf = 0;
876                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
877                         rss_conf->rss_hf |= ETH_RSS_IPV4;
878                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
879                 }
880                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
881                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
882                         hash_types &=
883                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
884                 }
885                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
886                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
887                         hash_types &=
888                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
889                 }
890                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
891                         rss_conf->rss_hf |= ETH_RSS_IPV6;
892                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
893                 }
894                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
895                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
896                         hash_types &=
897                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
898                 }
899                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
900                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
901                         hash_types &=
902                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
903                 }
904                 if (hash_types) {
905                         RTE_LOG(ERR, PMD,
906                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
907                                 vnic->hash_type);
908                         return -ENOTSUP;
909                 }
910         } else {
911                 rss_conf->rss_hf = 0;
912         }
913         return 0;
914 }
915
916 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
917                                struct rte_eth_fc_conf *fc_conf __rte_unused)
918 {
919         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
920         struct rte_eth_link link_info;
921         int rc;
922
923         rc = bnxt_get_hwrm_link_config(bp, &link_info);
924         if (rc)
925                 return rc;
926
927         memset(fc_conf, 0, sizeof(*fc_conf));
928         if (bp->link_info.auto_pause)
929                 fc_conf->autoneg = 1;
930         switch (bp->link_info.pause) {
931         case 0:
932                 fc_conf->mode = RTE_FC_NONE;
933                 break;
934         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
935                 fc_conf->mode = RTE_FC_TX_PAUSE;
936                 break;
937         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
938                 fc_conf->mode = RTE_FC_RX_PAUSE;
939                 break;
940         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
941                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
942                 fc_conf->mode = RTE_FC_FULL;
943                 break;
944         }
945         return 0;
946 }
947
948 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
949                                struct rte_eth_fc_conf *fc_conf)
950 {
951         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
952
953         if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
954                 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
955                 return -ENOTSUP;
956         }
957
958         switch (fc_conf->mode) {
959         case RTE_FC_NONE:
960                 bp->link_info.auto_pause = 0;
961                 bp->link_info.force_pause = 0;
962                 break;
963         case RTE_FC_RX_PAUSE:
964                 if (fc_conf->autoneg) {
965                         bp->link_info.auto_pause =
966                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
967                         bp->link_info.force_pause = 0;
968                 } else {
969                         bp->link_info.auto_pause = 0;
970                         bp->link_info.force_pause =
971                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
972                 }
973                 break;
974         case RTE_FC_TX_PAUSE:
975                 if (fc_conf->autoneg) {
976                         bp->link_info.auto_pause =
977                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
978                         bp->link_info.force_pause = 0;
979                 } else {
980                         bp->link_info.auto_pause = 0;
981                         bp->link_info.force_pause =
982                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
983                 }
984                 break;
985         case RTE_FC_FULL:
986                 if (fc_conf->autoneg) {
987                         bp->link_info.auto_pause =
988                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
989                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
990                         bp->link_info.force_pause = 0;
991                 } else {
992                         bp->link_info.auto_pause = 0;
993                         bp->link_info.force_pause =
994                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
995                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
996                 }
997                 break;
998         }
999         return bnxt_set_hwrm_link_config(bp, true);
1000 }
1001
1002 /*
1003  * Initialization
1004  */
1005
1006 static const struct eth_dev_ops bnxt_dev_ops = {
1007         .dev_infos_get = bnxt_dev_info_get_op,
1008         .dev_close = bnxt_dev_close_op,
1009         .dev_configure = bnxt_dev_configure_op,
1010         .dev_start = bnxt_dev_start_op,
1011         .dev_stop = bnxt_dev_stop_op,
1012         .dev_set_link_up = bnxt_dev_set_link_up_op,
1013         .dev_set_link_down = bnxt_dev_set_link_down_op,
1014         .stats_get = bnxt_stats_get_op,
1015         .stats_reset = bnxt_stats_reset_op,
1016         .rx_queue_setup = bnxt_rx_queue_setup_op,
1017         .rx_queue_release = bnxt_rx_queue_release_op,
1018         .tx_queue_setup = bnxt_tx_queue_setup_op,
1019         .tx_queue_release = bnxt_tx_queue_release_op,
1020         .reta_update = bnxt_reta_update_op,
1021         .reta_query = bnxt_reta_query_op,
1022         .rss_hash_update = bnxt_rss_hash_update_op,
1023         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
1024         .link_update = bnxt_link_update_op,
1025         .promiscuous_enable = bnxt_promiscuous_enable_op,
1026         .promiscuous_disable = bnxt_promiscuous_disable_op,
1027         .allmulticast_enable = bnxt_allmulticast_enable_op,
1028         .allmulticast_disable = bnxt_allmulticast_disable_op,
1029         .mac_addr_add = bnxt_mac_addr_add_op,
1030         .mac_addr_remove = bnxt_mac_addr_remove_op,
1031         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
1032         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
1033 };
1034
1035 static bool bnxt_vf_pciid(uint16_t id)
1036 {
1037         if (id == BROADCOM_DEV_ID_57304_VF ||
1038             id == BROADCOM_DEV_ID_57406_VF ||
1039             id == BROADCOM_DEV_ID_5731X_VF ||
1040             id == BROADCOM_DEV_ID_5741X_VF)
1041                 return true;
1042         return false;
1043 }
1044
1045 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
1046 {
1047         struct bnxt *bp = eth_dev->data->dev_private;
1048         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1049         int rc;
1050
1051         /* enable device (incl. PCI PM wakeup), and bus-mastering */
1052         if (!pci_dev->mem_resource[0].addr) {
1053                 RTE_LOG(ERR, PMD,
1054                         "Cannot find PCI device base address, aborting\n");
1055                 rc = -ENODEV;
1056                 goto init_err_disable;
1057         }
1058
1059         bp->eth_dev = eth_dev;
1060         bp->pdev = pci_dev;
1061
1062         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
1063         if (!bp->bar0) {
1064                 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
1065                 rc = -ENOMEM;
1066                 goto init_err_release;
1067         }
1068         return 0;
1069
1070 init_err_release:
1071         if (bp->bar0)
1072                 bp->bar0 = NULL;
1073
1074 init_err_disable:
1075
1076         return rc;
1077 }
1078
1079 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
1080
1081 static int
1082 bnxt_dev_init(struct rte_eth_dev *eth_dev)
1083 {
1084         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1085         static int version_printed;
1086         struct bnxt *bp;
1087         int rc;
1088
1089         if (version_printed++ == 0)
1090                 RTE_LOG(INFO, PMD, "%s", bnxt_version);
1091
1092         rte_eth_copy_pci_info(eth_dev, pci_dev);
1093         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1094
1095         bp = eth_dev->data->dev_private;
1096
1097         if (bnxt_vf_pciid(pci_dev->id.device_id))
1098                 bp->flags |= BNXT_FLAG_VF;
1099
1100         rc = bnxt_init_board(eth_dev);
1101         if (rc) {
1102                 RTE_LOG(ERR, PMD,
1103                         "Board initialization failed rc: %x\n", rc);
1104                 goto error;
1105         }
1106         eth_dev->dev_ops = &bnxt_dev_ops;
1107         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
1108         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
1109
1110         rc = bnxt_alloc_hwrm_resources(bp);
1111         if (rc) {
1112                 RTE_LOG(ERR, PMD,
1113                         "hwrm resource allocation failure rc: %x\n", rc);
1114                 goto error_free;
1115         }
1116         rc = bnxt_hwrm_ver_get(bp);
1117         if (rc)
1118                 goto error_free;
1119         bnxt_hwrm_queue_qportcfg(bp);
1120
1121         bnxt_hwrm_func_qcfg(bp);
1122
1123         /* Get the MAX capabilities for this function */
1124         rc = bnxt_hwrm_func_qcaps(bp);
1125         if (rc) {
1126                 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
1127                 goto error_free;
1128         }
1129         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
1130                                         ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
1131         if (eth_dev->data->mac_addrs == NULL) {
1132                 RTE_LOG(ERR, PMD,
1133                         "Failed to alloc %u bytes needed to store MAC addr tbl",
1134                         ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
1135                 rc = -ENOMEM;
1136                 goto error_free;
1137         }
1138         /* Copy the permanent MAC from the qcap response address now. */
1139         if (BNXT_PF(bp))
1140                 memcpy(bp->mac_addr, bp->pf.mac_addr, sizeof(bp->mac_addr));
1141         else
1142                 memcpy(bp->mac_addr, bp->vf.mac_addr, sizeof(bp->mac_addr));
1143         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1144         bp->grp_info = rte_zmalloc("bnxt_grp_info",
1145                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
1146         if (!bp->grp_info) {
1147                 RTE_LOG(ERR, PMD,
1148                         "Failed to alloc %zu bytes needed to store group info table\n",
1149                         sizeof(*bp->grp_info) * bp->max_ring_grps);
1150                 rc = -ENOMEM;
1151                 goto error_free;
1152         }
1153
1154         rc = bnxt_hwrm_func_driver_register(bp, 0,
1155                                             bp->pf.vf_req_fwd);
1156         if (rc) {
1157                 RTE_LOG(ERR, PMD,
1158                         "Failed to register driver");
1159                 rc = -EBUSY;
1160                 goto error_free;
1161         }
1162
1163         RTE_LOG(INFO, PMD,
1164                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
1165                 pci_dev->mem_resource[0].phys_addr,
1166                 pci_dev->mem_resource[0].addr);
1167
1168         bp->dev_stopped = 0;
1169
1170         return 0;
1171
1172 error_free:
1173         bnxt_dev_uninit(eth_dev);
1174 error:
1175         return rc;
1176 }
1177
1178 static int
1179 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
1180         struct bnxt *bp = eth_dev->data->dev_private;
1181         int rc;
1182
1183         if (eth_dev->data->mac_addrs != NULL) {
1184                 rte_free(eth_dev->data->mac_addrs);
1185                 eth_dev->data->mac_addrs = NULL;
1186         }
1187         if (bp->grp_info != NULL) {
1188                 rte_free(bp->grp_info);
1189                 bp->grp_info = NULL;
1190         }
1191         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
1192         bnxt_free_hwrm_resources(bp);
1193         if (bp->dev_stopped == 0)
1194                 bnxt_dev_close_op(eth_dev);
1195         eth_dev->dev_ops = NULL;
1196         eth_dev->rx_pkt_burst = NULL;
1197         eth_dev->tx_pkt_burst = NULL;
1198
1199         return rc;
1200 }
1201
1202 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1203         struct rte_pci_device *pci_dev)
1204 {
1205         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
1206                 bnxt_dev_init);
1207 }
1208
1209 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
1210 {
1211         return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
1212 }
1213
1214 static struct rte_pci_driver bnxt_rte_pmd = {
1215         .id_table = bnxt_pci_id_map,
1216         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
1217                 RTE_PCI_DRV_INTR_LSC,
1218         .probe = bnxt_pci_probe,
1219         .remove = bnxt_pci_remove,
1220 };
1221
1222 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
1223 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
1224 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio");