4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_byteorder.h>
39 #include <rte_common.h>
40 #include <rte_cycles.h>
41 #include <rte_malloc.h>
42 #include <rte_memzone.h>
43 #include <rte_version.h>
47 #include "bnxt_filter.h"
48 #include "bnxt_hwrm.h"
51 #include "bnxt_ring.h"
54 #include "bnxt_vnic.h"
55 #include "hsi_struct_def_dpdk.h"
59 #define HWRM_CMD_TIMEOUT 2000
61 struct bnxt_plcmodes_cfg {
63 uint16_t jumbo_thresh;
65 uint16_t hds_threshold;
68 static int page_getenum(size_t size)
84 RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
85 return sizeof(void *) * 8 - 1;
88 static int page_roundup(size_t size)
90 return 1 << page_getenum(size);
94 * HWRM Functions (sent to HWRM)
95 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
96 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
97 * command was failed by the ChiMP.
100 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
104 struct input *req = msg;
105 struct output *resp = bp->hwrm_cmd_resp_addr;
106 uint32_t *data = msg;
110 /* Write request msg to hwrm channel */
111 for (i = 0; i < msg_len; i += 4) {
112 bar = (uint8_t *)bp->bar0 + i;
113 rte_write32(*data, bar);
117 /* Zero the rest of the request space */
118 for (; i < bp->max_req_len; i += 4) {
119 bar = (uint8_t *)bp->bar0 + i;
123 /* Ring channel doorbell */
124 bar = (uint8_t *)bp->bar0 + 0x100;
127 /* Poll for the valid bit */
128 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
129 /* Sanity check on the resp->resp_len */
131 if (resp->resp_len && resp->resp_len <=
133 /* Last byte of resp contains the valid key */
134 valid = (uint8_t *)resp + resp->resp_len - 1;
135 if (*valid == HWRM_RESP_VALID_KEY)
141 if (i >= HWRM_CMD_TIMEOUT) {
142 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
152 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
156 rte_spinlock_lock(&bp->hwrm_lock);
157 rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
158 rte_spinlock_unlock(&bp->hwrm_lock);
162 #define HWRM_PREP(req, type, cr, resp) \
163 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
164 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
165 req.cmpl_ring = rte_cpu_to_le_16(cr); \
166 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
167 req.target_id = rte_cpu_to_le_16(0xffff); \
168 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
170 #define HWRM_CHECK_RESULT \
173 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
177 if (resp->error_code) { \
178 rc = rte_le_to_cpu_16(resp->error_code); \
179 if (resp->resp_len >= 16) { \
180 struct hwrm_err_output *tmp_hwrm_err_op = \
183 "%s error %d:%d:%08x:%04x\n", \
185 rc, tmp_hwrm_err_op->cmd_err, \
187 tmp_hwrm_err_op->opaque_0), \
189 tmp_hwrm_err_op->opaque_1)); \
193 "%s error %d\n", __func__, rc); \
199 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
202 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
203 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
205 HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
206 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
209 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
216 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
219 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
220 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
223 HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
224 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
226 /* FIXME add multicast flag, when multicast adding options is supported
229 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
230 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
231 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
232 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
233 if (vnic->mc_addr_cnt) {
234 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
235 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
236 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
238 req.mask = rte_cpu_to_le_32(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST |
241 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
248 int bnxt_hwrm_clear_filter(struct bnxt *bp,
249 struct bnxt_filter_info *filter)
252 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
253 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
255 HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
257 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
259 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
263 filter->fw_l2_filter_id = -1;
268 int bnxt_hwrm_set_filter(struct bnxt *bp,
270 struct bnxt_filter_info *filter)
273 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
274 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
275 uint32_t enables = 0;
277 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
279 req.flags = rte_cpu_to_le_32(filter->flags);
281 enables = filter->enables |
282 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
283 req.dst_id = rte_cpu_to_le_16(dst_id);
286 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
287 memcpy(req.l2_addr, filter->l2_addr,
290 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
291 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
294 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
295 req.l2_ovlan = filter->l2_ovlan;
297 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
298 req.l2_ovlan_mask = filter->l2_ovlan_mask;
300 req.enables = rte_cpu_to_le_32(enables);
302 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
306 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
311 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
314 struct hwrm_func_qcaps_input req = {.req_type = 0 };
315 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
316 uint16_t new_max_vfs;
319 HWRM_PREP(req, FUNC_QCAPS, -1, resp);
321 req.fid = rte_cpu_to_le_16(0xffff);
323 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
327 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
329 bp->pf.port_id = resp->port_id;
330 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
331 new_max_vfs = bp->pdev->max_vfs;
332 if (new_max_vfs != bp->pf.max_vfs) {
334 rte_free(bp->pf.vf_info);
335 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
336 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
337 bp->pf.max_vfs = new_max_vfs;
338 for (i = 0; i < new_max_vfs; i++) {
339 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
340 bp->pf.vf_info[i].vlan_table =
341 rte_zmalloc("VF VLAN table",
344 if (bp->pf.vf_info[i].vlan_table == NULL)
346 "Fail to alloc VLAN table for VF %d\n",
350 bp->pf.vf_info[i].vlan_table);
351 STAILQ_INIT(&bp->pf.vf_info[i].filter);
356 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
357 memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
358 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
359 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
360 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
361 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
362 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
363 /* TODO: For now, do not support VMDq/RFS on VFs. */
368 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
372 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
374 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
379 int bnxt_hwrm_func_reset(struct bnxt *bp)
382 struct hwrm_func_reset_input req = {.req_type = 0 };
383 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
385 HWRM_PREP(req, FUNC_RESET, -1, resp);
387 req.enables = rte_cpu_to_le_32(0);
389 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
396 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
399 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
400 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
402 if (bp->flags & BNXT_FLAG_REGISTERED)
405 HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
406 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
407 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
408 req.ver_maj = RTE_VER_YEAR;
409 req.ver_min = RTE_VER_MONTH;
410 req.ver_upd = RTE_VER_MINOR;
413 req.enables |= rte_cpu_to_le_32(
414 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
415 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
416 RTE_MIN(sizeof(req.vf_req_fwd),
417 sizeof(bp->pf.vf_req_fwd)));
420 req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1); /* TODO: Use MACRO */
421 memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
423 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
427 bp->flags |= BNXT_FLAG_REGISTERED;
432 int bnxt_hwrm_ver_get(struct bnxt *bp)
435 struct hwrm_ver_get_input req = {.req_type = 0 };
436 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
439 uint16_t max_resp_len;
440 char type[RTE_MEMZONE_NAMESIZE];
442 HWRM_PREP(req, VER_GET, -1, resp);
444 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
445 req.hwrm_intf_min = HWRM_VERSION_MINOR;
446 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
449 * Hold the lock since we may be adjusting the response pointers.
451 rte_spinlock_lock(&bp->hwrm_lock);
452 rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
456 RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
457 resp->hwrm_intf_maj, resp->hwrm_intf_min,
459 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
460 bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
461 (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
462 RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
463 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
465 my_version = HWRM_VERSION_MAJOR << 16;
466 my_version |= HWRM_VERSION_MINOR << 8;
467 my_version |= HWRM_VERSION_UPDATE;
469 fw_version = resp->hwrm_intf_maj << 16;
470 fw_version |= resp->hwrm_intf_min << 8;
471 fw_version |= resp->hwrm_intf_upd;
473 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
474 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
479 if (my_version != fw_version) {
480 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
481 if (my_version < fw_version) {
483 "Firmware API version is newer than driver.\n");
485 "The driver may be missing features.\n");
488 "Firmware API version is older than driver.\n");
490 "Not all driver features may be functional.\n");
494 if (bp->max_req_len > resp->max_req_win_len) {
495 RTE_LOG(ERR, PMD, "Unsupported request length\n");
498 bp->max_req_len = resp->max_req_win_len;
499 max_resp_len = resp->max_resp_len;
500 if (bp->max_resp_len != max_resp_len) {
501 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
502 bp->pdev->addr.domain, bp->pdev->addr.bus,
503 bp->pdev->addr.devid, bp->pdev->addr.function);
505 rte_free(bp->hwrm_cmd_resp_addr);
507 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
508 if (bp->hwrm_cmd_resp_addr == NULL) {
512 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
513 bp->hwrm_cmd_resp_dma_addr =
514 rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
515 if (bp->hwrm_cmd_resp_dma_addr == 0) {
517 "Unable to map response buffer to physical memory.\n");
521 bp->max_resp_len = max_resp_len;
525 rte_spinlock_unlock(&bp->hwrm_lock);
529 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
532 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
533 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
535 if (!(bp->flags & BNXT_FLAG_REGISTERED))
538 HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
541 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
545 bp->flags &= ~BNXT_FLAG_REGISTERED;
550 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
553 struct hwrm_port_phy_cfg_input req = {0};
554 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
555 uint32_t enables = 0;
557 HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
560 req.flags = rte_cpu_to_le_32(conf->phy_flags);
561 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
563 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
564 * any auto mode, even "none".
566 if (!conf->link_speed) {
567 req.auto_mode |= conf->auto_mode;
568 enables = HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
569 req.auto_link_speed_mask = conf->auto_link_speed_mask;
571 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
572 req.auto_link_speed = bp->link_info.auto_link_speed;
574 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
576 req.auto_duplex = conf->duplex;
577 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
578 req.auto_pause = conf->auto_pause;
579 req.force_pause = conf->force_pause;
580 /* Set force_pause if there is no auto or if there is a force */
581 if (req.auto_pause && !req.force_pause)
582 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
584 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
586 req.enables = rte_cpu_to_le_32(enables);
589 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
590 RTE_LOG(INFO, PMD, "Force Link Down\n");
593 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
600 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
601 struct bnxt_link_info *link_info)
604 struct hwrm_port_phy_qcfg_input req = {0};
605 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
607 HWRM_PREP(req, PORT_PHY_QCFG, -1, resp);
609 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
613 link_info->phy_link_status = resp->link;
614 if (link_info->phy_link_status != HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK) {
615 link_info->link_up = 1;
616 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
618 link_info->link_up = 0;
619 link_info->link_speed = 0;
621 link_info->duplex = resp->duplex;
622 link_info->pause = resp->pause;
623 link_info->auto_pause = resp->auto_pause;
624 link_info->force_pause = resp->force_pause;
625 link_info->auto_mode = resp->auto_mode;
627 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
628 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
629 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
630 link_info->phy_ver[0] = resp->phy_maj;
631 link_info->phy_ver[1] = resp->phy_min;
632 link_info->phy_ver[2] = resp->phy_bld;
637 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
640 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
641 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
643 HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
645 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
649 #define GET_QUEUE_INFO(x) \
650 bp->cos_queue[x].id = resp->queue_id##x; \
651 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
665 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
666 struct bnxt_ring *ring,
667 uint32_t ring_type, uint32_t map_index,
668 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
671 uint32_t enables = 0;
672 struct hwrm_ring_alloc_input req = {.req_type = 0 };
673 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
675 HWRM_PREP(req, RING_ALLOC, -1, resp);
677 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
678 req.fbo = rte_cpu_to_le_32(0);
679 /* Association of ring index with doorbell index */
680 req.logical_id = rte_cpu_to_le_16(map_index);
681 req.length = rte_cpu_to_le_32(ring->ring_size);
684 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
685 req.queue_id = bp->cos_queue[0].id;
687 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
688 req.ring_type = ring_type;
689 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
690 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
691 if (stats_ctx_id != INVALID_STATS_CTX_ID)
693 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
695 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
696 req.ring_type = ring_type;
698 * TODO: Some HWRM versions crash with
699 * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
701 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
704 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
708 req.enables = rte_cpu_to_le_32(enables);
710 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
712 if (rc || resp->error_code) {
713 if (rc == 0 && resp->error_code)
714 rc = rte_le_to_cpu_16(resp->error_code);
716 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
718 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
720 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
722 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
724 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
726 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
729 RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
734 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
738 int bnxt_hwrm_ring_free(struct bnxt *bp,
739 struct bnxt_ring *ring, uint32_t ring_type)
742 struct hwrm_ring_free_input req = {.req_type = 0 };
743 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
745 HWRM_PREP(req, RING_FREE, -1, resp);
747 req.ring_type = ring_type;
748 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
750 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
752 if (rc || resp->error_code) {
753 if (rc == 0 && resp->error_code)
754 rc = rte_le_to_cpu_16(resp->error_code);
757 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
758 RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
761 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
762 RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
765 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
766 RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
770 RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
777 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
780 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
781 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
783 HWRM_PREP(req, RING_GRP_ALLOC, -1, resp);
785 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
786 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
787 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
788 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
790 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
794 bp->grp_info[idx].fw_grp_id =
795 rte_le_to_cpu_16(resp->ring_group_id);
800 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
803 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
804 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
806 HWRM_PREP(req, RING_GRP_FREE, -1, resp);
808 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
810 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
814 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
818 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
821 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
822 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
824 HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
826 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
829 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
830 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
832 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
839 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
840 unsigned int idx __rte_unused)
843 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
844 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
846 HWRM_PREP(req, STAT_CTX_ALLOC, -1, resp);
848 req.update_period_ms = rte_cpu_to_le_32(1000);
850 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
852 rte_cpu_to_le_64(cpr->hw_stats_map);
854 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
858 cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
863 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
864 unsigned int idx __rte_unused)
867 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
868 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
870 HWRM_PREP(req, STAT_CTX_FREE, -1, resp);
872 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
873 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
875 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
882 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
885 struct hwrm_vnic_alloc_input req = { 0 };
886 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
888 /* map ring groups to this vnic */
889 RTE_LOG(DEBUG, PMD, "Alloc VNIC. Start %x, End %x\n",
890 vnic->start_grp_id, vnic->end_grp_id);
891 for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
892 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
893 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
894 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
895 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
896 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
897 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
898 ETHER_CRC_LEN + VLAN_TAG_SIZE;
899 HWRM_PREP(req, VNIC_ALLOC, -1, resp);
901 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
905 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
909 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
910 struct bnxt_vnic_info *vnic,
911 struct bnxt_plcmodes_cfg *pmode)
914 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
915 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
917 HWRM_PREP(req, VNIC_PLCMODES_QCFG, -1, resp);
919 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
921 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
925 pmode->flags = rte_le_to_cpu_32(resp->flags);
926 /* dflt_vnic bit doesn't exist in the _cfg command */
927 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
928 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
929 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
930 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
935 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
936 struct bnxt_vnic_info *vnic,
937 struct bnxt_plcmodes_cfg *pmode)
940 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
941 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
943 HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp);
945 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
946 req.flags = rte_cpu_to_le_32(pmode->flags);
947 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
948 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
949 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
950 req.enables = rte_cpu_to_le_32(
951 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
952 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
953 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
956 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
963 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
966 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
967 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
968 uint32_t ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
969 struct bnxt_plcmodes_cfg pmodes;
971 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
975 HWRM_PREP(req, VNIC_CFG, -1, resp);
977 /* Only RSS support for now TBD: COS & LB */
979 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP |
980 HWRM_VNIC_CFG_INPUT_ENABLES_MRU);
981 if (vnic->lb_rule != 0xffff)
982 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
983 if (vnic->cos_rule != 0xffff)
984 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
985 if (vnic->rss_rule != 0xffff)
986 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
987 req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
988 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
989 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
990 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
991 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
992 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
993 req.mru = rte_cpu_to_le_16(vnic->mru);
994 if (vnic->func_default)
996 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
997 if (vnic->vlan_strip)
999 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1002 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1003 if (vnic->roce_dual)
1004 req.flags |= rte_cpu_to_le_32(
1005 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1006 if (vnic->roce_only)
1007 req.flags |= rte_cpu_to_le_32(
1008 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1009 if (vnic->rss_dflt_cr)
1010 req.flags |= rte_cpu_to_le_32(
1011 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1013 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1017 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1022 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1026 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1027 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1029 HWRM_PREP(req, VNIC_QCFG, -1, resp);
1032 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1033 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1034 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1036 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1040 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1041 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1042 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1043 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1044 vnic->mru = rte_le_to_cpu_16(resp->mru);
1045 vnic->func_default = rte_le_to_cpu_32(
1046 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1047 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1048 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1049 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1050 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1051 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1052 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1053 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1054 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1055 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1056 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1061 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1064 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1065 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1066 bp->hwrm_cmd_resp_addr;
1068 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, -1, resp);
1070 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1074 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1079 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1082 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1083 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1084 bp->hwrm_cmd_resp_addr;
1086 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, -1, resp);
1088 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1090 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1094 vnic->rss_rule = INVALID_HW_RING_ID;
1099 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1102 struct hwrm_vnic_free_input req = {.req_type = 0 };
1103 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1105 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
1108 HWRM_PREP(req, VNIC_FREE, -1, resp);
1110 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1112 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1116 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1120 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1121 struct bnxt_vnic_info *vnic)
1124 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1125 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1127 HWRM_PREP(req, VNIC_RSS_CFG, -1, resp);
1129 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1131 req.ring_grp_tbl_addr =
1132 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1133 req.hash_key_tbl_addr =
1134 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1135 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1137 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1144 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1145 struct bnxt_vnic_info *vnic)
1148 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1149 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1152 HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp);
1154 req.flags = rte_cpu_to_le_32(
1155 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1157 req.enables = rte_cpu_to_le_32(
1158 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1160 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1161 size -= RTE_PKTMBUF_HEADROOM;
1163 req.jumbo_thresh = rte_cpu_to_le_16(size);
1164 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1166 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1173 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1175 struct hwrm_func_cfg_input req = {0};
1176 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1179 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1180 req.enables = rte_cpu_to_le_32(
1181 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1182 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1183 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1185 HWRM_PREP(req, FUNC_CFG, -1, resp);
1187 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1190 bp->pf.vf_info[vf].random_mac = false;
1196 * HWRM utility functions
1199 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1204 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1205 struct bnxt_tx_queue *txq;
1206 struct bnxt_rx_queue *rxq;
1207 struct bnxt_cp_ring_info *cpr;
1209 if (i >= bp->rx_cp_nr_rings) {
1210 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1213 rxq = bp->rx_queues[i];
1217 rc = bnxt_hwrm_stat_clear(bp, cpr);
1224 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1228 struct bnxt_cp_ring_info *cpr;
1230 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1232 if (i >= bp->rx_cp_nr_rings)
1233 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1235 cpr = bp->rx_queues[i]->cp_ring;
1236 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1237 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1238 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1240 * TODO. Need a better way to reset grp_info.stats_ctx
1241 * for Rx rings only. stats_ctx is not saved for Tx
1244 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
1252 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1257 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1258 struct bnxt_tx_queue *txq;
1259 struct bnxt_rx_queue *rxq;
1260 struct bnxt_cp_ring_info *cpr;
1262 if (i >= bp->rx_cp_nr_rings) {
1263 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1266 rxq = bp->rx_queues[i];
1270 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1278 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1283 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1285 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID) {
1287 "Attempt to free invalid ring group %d\n",
1292 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1300 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1301 unsigned int idx __rte_unused)
1303 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1305 bnxt_hwrm_ring_free(bp, cp_ring,
1306 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1307 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1308 bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1309 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1310 sizeof(*cpr->cp_desc_ring));
1311 cpr->cp_raw_cons = 0;
1314 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1319 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1320 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1321 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1322 struct bnxt_ring *ring = txr->tx_ring_struct;
1323 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1324 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1326 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1327 bnxt_hwrm_ring_free(bp, ring,
1328 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1329 ring->fw_ring_id = INVALID_HW_RING_ID;
1330 memset(txr->tx_desc_ring, 0,
1331 txr->tx_ring_struct->ring_size *
1332 sizeof(*txr->tx_desc_ring));
1333 memset(txr->tx_buf_ring, 0,
1334 txr->tx_ring_struct->ring_size *
1335 sizeof(*txr->tx_buf_ring));
1339 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1340 bnxt_free_cp_ring(bp, cpr, idx);
1341 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1345 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1346 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1347 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1348 struct bnxt_ring *ring = rxr->rx_ring_struct;
1349 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1350 unsigned int idx = i + 1;
1352 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1353 bnxt_hwrm_ring_free(bp, ring,
1354 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1355 ring->fw_ring_id = INVALID_HW_RING_ID;
1356 bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1357 memset(rxr->rx_desc_ring, 0,
1358 rxr->rx_ring_struct->ring_size *
1359 sizeof(*rxr->rx_desc_ring));
1360 memset(rxr->rx_buf_ring, 0,
1361 rxr->rx_ring_struct->ring_size *
1362 sizeof(*rxr->rx_buf_ring));
1364 memset(rxr->ag_buf_ring, 0,
1365 rxr->ag_ring_struct->ring_size *
1366 sizeof(*rxr->ag_buf_ring));
1369 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1370 bnxt_free_cp_ring(bp, cpr, idx);
1371 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1372 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1376 /* Default completion ring */
1378 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1380 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1381 bnxt_free_cp_ring(bp, cpr, 0);
1382 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1389 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1394 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1395 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1402 void bnxt_free_hwrm_resources(struct bnxt *bp)
1404 /* Release memzone */
1405 rte_free(bp->hwrm_cmd_resp_addr);
1406 bp->hwrm_cmd_resp_addr = NULL;
1407 bp->hwrm_cmd_resp_dma_addr = 0;
1410 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1412 struct rte_pci_device *pdev = bp->pdev;
1413 char type[RTE_MEMZONE_NAMESIZE];
1415 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1416 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1417 bp->max_req_len = HWRM_MAX_REQ_LEN;
1418 bp->max_resp_len = HWRM_MAX_RESP_LEN;
1419 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1420 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1421 if (bp->hwrm_cmd_resp_addr == NULL)
1423 bp->hwrm_cmd_resp_dma_addr =
1424 rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
1425 if (bp->hwrm_cmd_resp_dma_addr == 0) {
1427 "unable to map response address to physical memory\n");
1430 rte_spinlock_init(&bp->hwrm_lock);
1435 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1437 struct bnxt_filter_info *filter;
1440 STAILQ_FOREACH(filter, &vnic->filter, next) {
1441 rc = bnxt_hwrm_clear_filter(bp, filter);
1448 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1450 struct bnxt_filter_info *filter;
1453 STAILQ_FOREACH(filter, &vnic->filter, next) {
1454 rc = bnxt_hwrm_set_filter(bp, vnic->fw_vnic_id, filter);
1461 void bnxt_free_tunnel_ports(struct bnxt *bp)
1463 if (bp->vxlan_port_cnt)
1464 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1465 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1467 if (bp->geneve_port_cnt)
1468 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1469 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1470 bp->geneve_port = 0;
1473 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1475 struct bnxt_vnic_info *vnic;
1478 if (bp->vnic_info == NULL)
1481 vnic = &bp->vnic_info[0];
1483 bnxt_hwrm_cfa_l2_clear_rx_mask(bp, vnic);
1485 /* VNIC resources */
1486 for (i = 0; i < bp->nr_vnics; i++) {
1487 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1489 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1491 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1492 bnxt_hwrm_vnic_free(bp, vnic);
1494 /* Ring resources */
1495 bnxt_free_all_hwrm_rings(bp);
1496 bnxt_free_all_hwrm_ring_grps(bp);
1497 bnxt_free_all_hwrm_stat_ctxs(bp);
1498 bnxt_free_tunnel_ports(bp);
1501 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1503 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1505 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1506 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1508 switch (conf_link_speed) {
1509 case ETH_LINK_SPEED_10M_HD:
1510 case ETH_LINK_SPEED_100M_HD:
1511 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1513 return hw_link_duplex;
1516 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1518 uint16_t eth_link_speed = 0;
1520 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1521 return ETH_LINK_SPEED_AUTONEG;
1523 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1524 case ETH_LINK_SPEED_100M:
1525 case ETH_LINK_SPEED_100M_HD:
1527 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1529 case ETH_LINK_SPEED_1G:
1531 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1533 case ETH_LINK_SPEED_2_5G:
1535 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1537 case ETH_LINK_SPEED_10G:
1539 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1541 case ETH_LINK_SPEED_20G:
1543 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1545 case ETH_LINK_SPEED_25G:
1547 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1549 case ETH_LINK_SPEED_40G:
1551 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1553 case ETH_LINK_SPEED_50G:
1555 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1559 "Unsupported link speed %d; default to AUTO\n",
1563 return eth_link_speed;
1566 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1567 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1568 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1569 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1571 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
1575 if (link_speed == ETH_LINK_SPEED_AUTONEG)
1578 if (link_speed & ETH_LINK_SPEED_FIXED) {
1579 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1581 if (one_speed & (one_speed - 1)) {
1583 "Invalid advertised speeds (%u) for port %u\n",
1584 link_speed, port_id);
1587 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1589 "Unsupported advertised speed (%u) for port %u\n",
1590 link_speed, port_id);
1594 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1596 "Unsupported advertised speeds (%u) for port %u\n",
1597 link_speed, port_id);
1604 static uint16_t bnxt_parse_eth_link_speed_mask(uint32_t link_speed)
1608 if (link_speed == ETH_LINK_SPEED_AUTONEG)
1609 link_speed = BNXT_SUPPORTED_SPEEDS;
1611 if (link_speed & ETH_LINK_SPEED_100M)
1612 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1613 if (link_speed & ETH_LINK_SPEED_100M_HD)
1614 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1615 if (link_speed & ETH_LINK_SPEED_1G)
1616 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1617 if (link_speed & ETH_LINK_SPEED_2_5G)
1618 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1619 if (link_speed & ETH_LINK_SPEED_10G)
1620 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1621 if (link_speed & ETH_LINK_SPEED_20G)
1622 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1623 if (link_speed & ETH_LINK_SPEED_25G)
1624 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1625 if (link_speed & ETH_LINK_SPEED_40G)
1626 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1627 if (link_speed & ETH_LINK_SPEED_50G)
1628 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1632 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
1634 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
1636 switch (hw_link_speed) {
1637 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
1638 eth_link_speed = ETH_SPEED_NUM_100M;
1640 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
1641 eth_link_speed = ETH_SPEED_NUM_1G;
1643 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
1644 eth_link_speed = ETH_SPEED_NUM_2_5G;
1646 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
1647 eth_link_speed = ETH_SPEED_NUM_10G;
1649 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
1650 eth_link_speed = ETH_SPEED_NUM_20G;
1652 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
1653 eth_link_speed = ETH_SPEED_NUM_25G;
1655 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
1656 eth_link_speed = ETH_SPEED_NUM_40G;
1658 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
1659 eth_link_speed = ETH_SPEED_NUM_50G;
1661 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
1663 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
1667 return eth_link_speed;
1670 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
1672 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1674 switch (hw_link_duplex) {
1675 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
1676 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
1677 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1679 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
1680 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
1683 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
1687 return eth_link_duplex;
1690 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
1693 struct bnxt_link_info *link_info = &bp->link_info;
1695 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
1698 "Get link config failed with rc %d\n", rc);
1701 if (link_info->link_up)
1703 bnxt_parse_hw_link_speed(link_info->link_speed);
1705 link->link_speed = ETH_LINK_SPEED_10M;
1706 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
1707 link->link_status = link_info->link_up;
1708 link->link_autoneg = link_info->auto_mode ==
1709 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
1710 ETH_LINK_SPEED_FIXED : ETH_LINK_SPEED_AUTONEG;
1715 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
1718 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1719 struct bnxt_link_info link_req;
1722 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
1725 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
1726 bp->eth_dev->data->port_id);
1730 memset(&link_req, 0, sizeof(link_req));
1731 link_req.link_up = link_up;
1735 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
1736 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
1738 link_req.phy_flags |=
1739 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
1740 link_req.auto_mode =
1741 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1742 link_req.auto_link_speed_mask =
1743 bnxt_parse_eth_link_speed_mask(dev_conf->link_speeds);
1745 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
1746 link_req.link_speed = speed;
1747 RTE_LOG(INFO, PMD, "Set Link Speed %x\n", speed);
1749 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
1750 link_req.auto_pause = bp->link_info.auto_pause;
1751 link_req.force_pause = bp->link_info.force_pause;
1754 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
1757 "Set link config failed with rc %d\n", rc);
1760 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1766 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
1768 struct hwrm_func_qcfg_input req = {0};
1769 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1772 HWRM_PREP(req, FUNC_QCFG, -1, resp);
1773 req.fid = rte_cpu_to_le_16(0xffff);
1775 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1779 /* Hard Coded.. 0xfff VLAN ID mask */
1780 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
1782 switch (resp->port_partition_type) {
1783 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
1784 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
1785 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
1786 bp->port_partition_type = resp->port_partition_type;
1789 bp->port_partition_type = 0;
1796 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
1797 struct hwrm_func_qcaps_output *qcaps)
1799 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
1800 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
1801 sizeof(qcaps->mac_address));
1802 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
1803 qcaps->max_rx_rings = fcfg->num_rx_rings;
1804 qcaps->max_tx_rings = fcfg->num_tx_rings;
1805 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
1806 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
1808 qcaps->first_vf_id = 0;
1809 qcaps->max_vnics = fcfg->num_vnics;
1810 qcaps->max_decap_records = 0;
1811 qcaps->max_encap_records = 0;
1812 qcaps->max_tx_wm_flows = 0;
1813 qcaps->max_tx_em_flows = 0;
1814 qcaps->max_rx_wm_flows = 0;
1815 qcaps->max_rx_em_flows = 0;
1816 qcaps->max_flow_id = 0;
1817 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
1818 qcaps->max_sp_tx_rings = 0;
1819 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
1822 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
1824 struct hwrm_func_cfg_input req = {0};
1825 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1828 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
1829 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
1830 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
1831 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
1832 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1833 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
1834 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
1835 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1836 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
1837 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
1838 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
1839 req.mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1840 ETHER_CRC_LEN + VLAN_TAG_SIZE);
1841 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1842 ETHER_CRC_LEN + VLAN_TAG_SIZE);
1843 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1844 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
1845 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
1846 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
1847 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
1848 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
1849 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
1850 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
1851 req.fid = rte_cpu_to_le_16(0xffff);
1853 HWRM_PREP(req, FUNC_CFG, -1, resp);
1855 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1861 static void populate_vf_func_cfg_req(struct bnxt *bp,
1862 struct hwrm_func_cfg_input *req,
1865 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
1866 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
1867 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
1868 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
1869 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1870 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
1871 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
1872 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1873 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
1874 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
1876 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1877 ETHER_CRC_LEN + VLAN_TAG_SIZE);
1878 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1879 ETHER_CRC_LEN + VLAN_TAG_SIZE);
1880 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
1882 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
1883 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
1885 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
1886 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
1887 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
1888 /* TODO: For now, do not support VMDq/RFS on VFs. */
1889 req->num_vnics = rte_cpu_to_le_16(1);
1890 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
1894 static void add_random_mac_if_needed(struct bnxt *bp,
1895 struct hwrm_func_cfg_input *cfg_req,
1898 struct ether_addr mac;
1900 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
1903 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
1905 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1906 eth_random_addr(cfg_req->dflt_mac_addr);
1907 bp->pf.vf_info[vf].random_mac = true;
1909 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
1913 static void reserve_resources_from_vf(struct bnxt *bp,
1914 struct hwrm_func_cfg_input *cfg_req,
1917 struct hwrm_func_qcaps_input req = {0};
1918 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1921 /* Get the actual allocated values now */
1922 HWRM_PREP(req, FUNC_QCAPS, -1, resp);
1923 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1924 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1927 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
1928 copy_func_cfg_to_qcaps(cfg_req, resp);
1929 } else if (resp->error_code) {
1930 rc = rte_le_to_cpu_16(resp->error_code);
1931 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
1932 copy_func_cfg_to_qcaps(cfg_req, resp);
1935 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
1936 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
1937 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
1938 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
1939 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
1940 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
1942 * TODO: While not supporting VMDq with VFs, max_vnics is always
1943 * forced to 1 in this case
1945 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
1946 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
1949 static int update_pf_resource_max(struct bnxt *bp)
1951 struct hwrm_func_qcfg_input req = {0};
1952 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1955 /* And copy the allocated numbers into the pf struct */
1956 HWRM_PREP(req, FUNC_QCFG, -1, resp);
1957 req.fid = rte_cpu_to_le_16(0xffff);
1958 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1961 /* Only TX ring value reflects actual allocation? TODO */
1962 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
1963 bp->pf.evb_mode = resp->evb_mode;
1968 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
1973 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
1977 rc = bnxt_hwrm_func_qcaps(bp);
1981 bp->pf.func_cfg_flags &=
1982 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
1983 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
1984 bp->pf.func_cfg_flags |=
1985 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
1986 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
1990 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
1992 struct hwrm_func_cfg_input req = {0};
1993 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2000 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2004 rc = bnxt_hwrm_func_qcaps(bp);
2009 bp->pf.active_vfs = num_vfs;
2012 * First, configure the PF to only use one TX ring. This ensures that
2013 * there are enough rings for all VFs.
2015 * If we don't do this, when we call func_alloc() later, we will lock
2016 * extra rings to the PF that won't be available during func_cfg() of
2019 * This has been fixed with firmware versions above 20.6.54
2021 bp->pf.func_cfg_flags &=
2022 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2023 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2024 bp->pf.func_cfg_flags |=
2025 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2026 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2031 * Now, create and register a buffer to hold forwarded VF requests
2033 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2034 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2035 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2036 if (bp->pf.vf_req_buf == NULL) {
2040 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2041 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2042 for (i = 0; i < num_vfs; i++)
2043 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2044 (i * HWRM_MAX_REQ_LEN);
2046 rc = bnxt_hwrm_func_buf_rgtr(bp);
2050 populate_vf_func_cfg_req(bp, &req, num_vfs);
2052 bp->pf.active_vfs = 0;
2053 for (i = 0; i < num_vfs; i++) {
2054 add_random_mac_if_needed(bp, &req, i);
2056 HWRM_PREP(req, FUNC_CFG, -1, resp);
2057 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2058 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2059 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2061 /* Clear enable flag for next pass */
2062 req.enables &= ~rte_cpu_to_le_32(
2063 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2065 if (rc || resp->error_code) {
2067 "Failed to initizlie VF %d\n", i);
2069 "Not all VFs available. (%d, %d)\n",
2070 rc, resp->error_code);
2074 reserve_resources_from_vf(bp, &req, i);
2075 bp->pf.active_vfs++;
2079 * Now configure the PF to use "the rest" of the resources
2080 * We're using STD_TX_RING_MODE here though which will limit the TX
2081 * rings. This will allow QoS to function properly. Not setting this
2082 * will cause PF rings to break bandwidth settings.
2084 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2088 rc = update_pf_resource_max(bp);
2095 bnxt_hwrm_func_buf_unrgtr(bp);
2099 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2100 uint8_t tunnel_type)
2102 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2103 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2106 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, -1, resp);
2107 req.tunnel_type = tunnel_type;
2108 req.tunnel_dst_port_val = port;
2109 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2112 switch (tunnel_type) {
2113 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2114 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2115 bp->vxlan_port = port;
2117 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2118 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2119 bp->geneve_port = port;
2127 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2128 uint8_t tunnel_type)
2130 struct hwrm_tunnel_dst_port_free_input req = {0};
2131 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2134 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, -1, resp);
2135 req.tunnel_type = tunnel_type;
2136 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2137 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2143 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2146 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2147 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2149 HWRM_PREP(req, FUNC_BUF_RGTR, -1, resp);
2151 req.req_buf_num_pages = rte_cpu_to_le_16(1);
2152 req.req_buf_page_size = rte_cpu_to_le_16(
2153 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2154 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2155 req.req_buf_page_addr[0] =
2156 rte_cpu_to_le_64(rte_mem_virt2phy(bp->pf.vf_req_buf));
2157 if (req.req_buf_page_addr[0] == 0) {
2159 "unable to map buffer address to physical memory\n");
2163 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2170 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2173 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2174 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2176 HWRM_PREP(req, FUNC_BUF_UNRGTR, -1, resp);
2178 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2185 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2187 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2188 struct hwrm_func_cfg_input req = {0};
2191 HWRM_PREP(req, FUNC_CFG, -1, resp);
2192 req.fid = rte_cpu_to_le_16(0xffff);
2193 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2194 req.enables = rte_cpu_to_le_32(
2195 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2196 req.async_event_cr = rte_cpu_to_le_16(
2197 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2198 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2204 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2206 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2207 struct hwrm_func_vf_cfg_input req = {0};
2210 HWRM_PREP(req, FUNC_VF_CFG, -1, resp);
2211 req.enables = rte_cpu_to_le_32(
2212 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2213 req.async_event_cr = rte_cpu_to_le_16(
2214 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2215 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2221 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2222 void *encaped, size_t ec_size)
2225 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2226 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2228 if (ec_size > sizeof(req.encap_request))
2231 HWRM_PREP(req, REJECT_FWD_RESP, -1, resp);
2233 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2234 memcpy(req.encap_request, encaped, ec_size);
2236 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2243 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2244 struct ether_addr *mac)
2246 struct hwrm_func_qcfg_input req = {0};
2247 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2250 HWRM_PREP(req, FUNC_QCFG, -1, resp);
2251 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2252 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2256 memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2260 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2261 void *encaped, size_t ec_size)
2264 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2265 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2267 if (ec_size > sizeof(req.encap_request))
2270 HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
2272 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2273 memcpy(req.encap_request, encaped, ec_size);
2275 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2282 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2284 struct hwrm_port_qstats_input req = {0};
2285 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2286 struct bnxt_pf_info *pf = &bp->pf;
2289 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2292 HWRM_PREP(req, PORT_QSTATS, -1, resp);
2293 req.port_id = rte_cpu_to_le_16(pf->port_id);
2294 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
2295 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
2296 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2301 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
2303 struct hwrm_port_clr_stats_input req = {0};
2304 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2305 struct bnxt_pf_info *pf = &bp->pf;
2308 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2311 HWRM_PREP(req, PORT_CLR_STATS, -1, resp);
2312 req.port_id = rte_cpu_to_le_16(pf->port_id);
2313 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));