drivers/net/bnxt/bnxt_hwrm.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <rte_byteorder.h>
  35 #include <rte_common.h>
  36 #include <rte_cycles.h>
  37 #include <rte_malloc.h>
  38 #include <rte_memzone.h>
  39 #include <rte_version.h>
  40
  41 #include "bnxt.h"
  42 #include "bnxt_cpr.h"
  43 #include "bnxt_filter.h"
  44 #include "bnxt_hwrm.h"
  45 #include "bnxt_rxq.h"
  46 #include "bnxt_ring.h"
  47 #include "bnxt_txq.h"
  48 #include "bnxt_vnic.h"
  49 #include "hsi_struct_def_dpdk.h"
  50
  51 #define HWRM_CMD_TIMEOUT                2000
  52
  53 /*
  54  * HWRM Functions (sent to HWRM)
  55  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  56  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  57  * command was failed by the ChiMP.
  58  */
  59
  60 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
  61                                         uint32_t msg_len)
  62 {
  63         unsigned int i;
  64         struct input *req = msg;
  65         struct output *resp = bp->hwrm_cmd_resp_addr;
  66         uint32_t *data = msg;
  67         uint8_t *bar;
  68         uint8_t *valid;
  69
  70         /* Write request msg to hwrm channel */
  71         for (i = 0; i < msg_len; i += 4) {
  72                 bar = (uint8_t *)bp->bar0 + i;
  73                 *(volatile uint32_t *)bar = *data;
  74                 data++;
  75         }
  76
  77         /* Zero the rest of the request space */
  78         for (; i < bp->max_req_len; i += 4) {
  79                 bar = (uint8_t *)bp->bar0 + i;
  80                 *(volatile uint32_t *)bar = 0;
  81         }
  82
  83         /* Ring channel doorbell */
  84         bar = (uint8_t *)bp->bar0 + 0x100;
  85         *(volatile uint32_t *)bar = 1;
  86
  87         /* Poll for the valid bit */
  88         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
  89                 /* Sanity check on the resp->resp_len */
  90                 rte_rmb();
  91                 if (resp->resp_len && resp->resp_len <=
  92                                 bp->max_resp_len) {
  93                         /* Last byte of resp contains the valid key */
  94                         valid = (uint8_t *)resp + resp->resp_len - 1;
  95                         if (*valid == HWRM_RESP_VALID_KEY)
  96                                 break;
  97                 }
  98                 rte_delay_us(600);
  99         }
 100
 101         if (i >= HWRM_CMD_TIMEOUT) {
 102                 RTE_LOG(ERR, PMD, "Error sending msg %x\n",
 103                         req->req_type);
 104                 goto err_ret;
 105         }
 106         return 0;
 107
 108 err_ret:
 109         return -1;
 110 }
 111
 112 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
 113 {
 114         int rc;
 115
 116         rte_spinlock_lock(&bp->hwrm_lock);
 117         rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
 118         rte_spinlock_unlock(&bp->hwrm_lock);
 119         return rc;
 120 }
 121
 122 #define HWRM_PREP(req, type, cr, resp) \
 123         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 124         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 125         req.cmpl_ring = rte_cpu_to_le_16(cr); \
 126         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 127         req.target_id = rte_cpu_to_le_16(0xffff); \
 128         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
 129
 130 #define HWRM_CHECK_RESULT \
 131         { \
 132                 if (rc) { \
 133                         RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
 134                                 __func__, rc); \
 135                         return rc; \
 136                 } \
 137                 if (resp->error_code) { \
 138                         rc = rte_le_to_cpu_16(resp->error_code); \
 139                         RTE_LOG(ERR, PMD, "%s error %d\n", __func__, rc); \
 140                         return rc; \
 141                 } \
 142         }
 143
 144 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 145 {
 146         int rc = 0;
 147         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 148         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 149
 150         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
 151         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 152         req.mask = 0;
 153
 154         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 155
 156         HWRM_CHECK_RESULT;
 157
 158         return rc;
 159 }
 160
 161 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 162 {
 163         int rc = 0;
 164         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 165         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 166         uint32_t mask = 0;
 167
 168         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
 169         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 170
 171         /* FIXME add multicast flag, when multicast adding options is supported
 172          * by ethtool.
 173          */
 174         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 175                 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 176         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 177                 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 178         req.mask = rte_cpu_to_le_32(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST |
 179                                     HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST |
 180                                     mask);
 181
 182         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 183
 184         HWRM_CHECK_RESULT;
 185
 186         return rc;
 187 }
 188
 189 int bnxt_hwrm_clear_filter(struct bnxt *bp,
 190                            struct bnxt_filter_info *filter)
 191 {
 192         int rc = 0;
 193         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 194         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 195
 196         HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
 197
 198         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 199
 200         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 201
 202         HWRM_CHECK_RESULT;
 203
 204         filter->fw_l2_filter_id = -1;
 205
 206         return 0;
 207 }
 208
 209 int bnxt_hwrm_set_filter(struct bnxt *bp,
 210                          struct bnxt_vnic_info *vnic,
 211                          struct bnxt_filter_info *filter)
 212 {
 213         int rc = 0;
 214         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 215         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 216         uint32_t enables = 0;
 217
 218         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
 219
 220         req.flags = rte_cpu_to_le_32(filter->flags);
 221
 222         enables = filter->enables |
 223               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 224         req.dst_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 225
 226         if (enables &
 227             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 228                 memcpy(req.l2_addr, filter->l2_addr,
 229                        ETHER_ADDR_LEN);
 230         if (enables &
 231             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 232                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 233                        ETHER_ADDR_LEN);
 234         if (enables &
 235             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 236                 req.l2_ovlan = filter->l2_ovlan;
 237         if (enables &
 238             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 239                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 240
 241         req.enables = rte_cpu_to_le_32(enables);
 242
 243         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 244
 245         HWRM_CHECK_RESULT;
 246
 247         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 248
 249         return rc;
 250 }
 251
 252 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, void *fwd_cmd)
 253 {
 254         int rc;
 255         struct hwrm_exec_fwd_resp_input req = {.req_type = 0 };
 256         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
 257
 258         HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
 259
 260         memcpy(req.encap_request, fwd_cmd,
 261                sizeof(req.encap_request));
 262
 263         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 264
 265         HWRM_CHECK_RESULT;
 266
 267         return rc;
 268 }
 269
 270 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 271 {
 272         int rc = 0;
 273         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 274         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 275
 276         HWRM_PREP(req, FUNC_QCAPS, -1, resp);
 277
 278         req.fid = rte_cpu_to_le_16(0xffff);
 279
 280         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 281
 282         HWRM_CHECK_RESULT;
 283
 284         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 285         if (BNXT_PF(bp)) {
 286                 struct bnxt_pf_info *pf = &bp->pf;
 287
 288                 pf->fw_fid = rte_le_to_cpu_32(resp->fid);
 289                 pf->port_id = resp->port_id;
 290                 memcpy(pf->mac_addr, resp->perm_mac_address, ETHER_ADDR_LEN);
 291                 pf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 292                 pf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 293                 pf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 294                 pf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 295                 pf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 296                 pf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 297                 pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 298                 pf->max_vfs = rte_le_to_cpu_16(resp->max_vfs);
 299         } else {
 300                 struct bnxt_vf_info *vf = &bp->vf;
 301
 302                 vf->fw_fid = rte_le_to_cpu_32(resp->fid);
 303                 memcpy(vf->mac_addr, &resp->perm_mac_address, ETHER_ADDR_LEN);
 304                 vf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 305                 vf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 306                 vf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 307                 vf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 308                 vf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 309                 vf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 310         }
 311
 312         return rc;
 313 }
 314
 315 int bnxt_hwrm_func_reset(struct bnxt *bp)
 316 {
 317         int rc = 0;
 318         struct hwrm_func_reset_input req = {.req_type = 0 };
 319         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 320
 321         HWRM_PREP(req, FUNC_RESET, -1, resp);
 322
 323         req.enables = rte_cpu_to_le_32(0);
 324
 325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 326
 327         HWRM_CHECK_RESULT;
 328
 329         return rc;
 330 }
 331
 332 int bnxt_hwrm_func_driver_register(struct bnxt *bp, uint32_t flags,
 333                                    uint32_t *vf_req_fwd)
 334 {
 335         int rc;
 336         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 337         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 338
 339         if (bp->flags & BNXT_FLAG_REGISTERED)
 340                 return 0;
 341
 342         HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
 343         req.flags = flags;
 344         req.enables = HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER;
 345         req.ver_maj = RTE_VER_YEAR;
 346         req.ver_min = RTE_VER_MONTH;
 347         req.ver_upd = RTE_VER_MINOR;
 348
 349         memcpy(req.vf_req_fwd, vf_req_fwd, sizeof(req.vf_req_fwd));
 350
 351         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 352
 353         HWRM_CHECK_RESULT;
 354
 355         bp->flags |= BNXT_FLAG_REGISTERED;
 356
 357         return rc;
 358 }
 359
 360 int bnxt_hwrm_ver_get(struct bnxt *bp)
 361 {
 362         int rc = 0;
 363         struct hwrm_ver_get_input req = {.req_type = 0 };
 364         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 365         uint32_t my_version;
 366         uint32_t fw_version;
 367         uint16_t max_resp_len;
 368         char type[RTE_MEMZONE_NAMESIZE];
 369
 370         HWRM_PREP(req, VER_GET, -1, resp);
 371
 372         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 373         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 374         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 375
 376         /*
 377          * Hold the lock since we may be adjusting the response pointers.
 378          */
 379         rte_spinlock_lock(&bp->hwrm_lock);
 380         rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
 381
 382         HWRM_CHECK_RESULT;
 383
 384         RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
 385                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
 386                 resp->hwrm_intf_upd,
 387                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
 388
 389         my_version = HWRM_VERSION_MAJOR << 16;
 390         my_version |= HWRM_VERSION_MINOR << 8;
 391         my_version |= HWRM_VERSION_UPDATE;
 392
 393         fw_version = resp->hwrm_intf_maj << 16;
 394         fw_version |= resp->hwrm_intf_min << 8;
 395         fw_version |= resp->hwrm_intf_upd;
 396
 397         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
 398                 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
 399                 rc = -EINVAL;
 400                 goto error;
 401         }
 402
 403         if (my_version != fw_version) {
 404                 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
 405                 if (my_version < fw_version) {
 406                         RTE_LOG(INFO, PMD,
 407                                 "Firmware API version is newer than driver.\n");
 408                         RTE_LOG(INFO, PMD,
 409                                 "The driver may be missing features.\n");
 410                 } else {
 411                         RTE_LOG(INFO, PMD,
 412                                 "Firmware API version is older than driver.\n");
 413                         RTE_LOG(INFO, PMD,
 414                                 "Not all driver features may be functional.\n");
 415                 }
 416         }
 417
 418         if (bp->max_req_len > resp->max_req_win_len) {
 419                 RTE_LOG(ERR, PMD, "Unsupported request length\n");
 420                 rc = -EINVAL;
 421         }
 422         bp->max_req_len = resp->max_req_win_len;
 423         max_resp_len = resp->max_resp_len;
 424         if (bp->max_resp_len != max_resp_len) {
 425                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 426                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 427                         bp->pdev->addr.devid, bp->pdev->addr.function);
 428
 429                 rte_free(bp->hwrm_cmd_resp_addr);
 430
 431                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 432                 if (bp->hwrm_cmd_resp_addr == NULL) {
 433                         rc = -ENOMEM;
 434                         goto error;
 435                 }
 436                 bp->hwrm_cmd_resp_dma_addr =
 437                         rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
 438                 bp->max_resp_len = max_resp_len;
 439         }
 440
 441 error:
 442         rte_spinlock_unlock(&bp->hwrm_lock);
 443         return rc;
 444 }
 445
 446 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 447 {
 448         int rc;
 449         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 450         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 451
 452         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 453                 return 0;
 454
 455         HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
 456         req.flags = flags;
 457
 458         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 459
 460         HWRM_CHECK_RESULT;
 461
 462         bp->flags &= ~BNXT_FLAG_REGISTERED;
 463
 464         return rc;
 465 }
 466
 467 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 468 {
 469         int rc = 0;
 470         struct hwrm_port_phy_cfg_input req = {.req_type = 0};
 471         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 472
 473         HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
 474
 475         req.flags = conf->phy_flags;
 476         if (conf->link_up) {
 477                 req.force_link_speed = conf->link_speed;
 478                 /*
 479                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 480                  * any auto mode, even "none".
 481                  */
 482                 if (req.auto_mode == HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE) {
 483                         req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
 484                 } else {
 485                         req.auto_mode = conf->auto_mode;
 486                         req.enables |=
 487                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 488                         req.auto_link_speed_mask = conf->auto_link_speed_mask;
 489                         req.enables |=
 490                            HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 491                         req.auto_link_speed = conf->auto_link_speed;
 492                         req.enables |=
 493                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
 494                 }
 495                 req.auto_duplex = conf->duplex;
 496                 req.enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 497                 req.auto_pause = conf->auto_pause;
 498                 /* Set force_pause if there is no auto or if there is a force */
 499                 if (req.auto_pause)
 500                         req.enables |=
 501                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 502                 else
 503                         req.enables |=
 504                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 505                 req.force_pause = conf->force_pause;
 506                 if (req.force_pause)
 507                         req.enables |=
 508                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 509         } else {
 510                 req.flags &= ~HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
 511                 req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN;
 512                 req.force_link_speed = 0;
 513         }
 514
 515         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 516
 517         HWRM_CHECK_RESULT;
 518
 519         return rc;
 520 }
 521
 522 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 523 {
 524         int rc = 0;
 525         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 526         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 527
 528         HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
 529
 530         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 531
 532         HWRM_CHECK_RESULT;
 533
 534 #define GET_QUEUE_INFO(x) \
 535         bp->cos_queue[x].id = resp->queue_id##x; \
 536         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 537
 538         GET_QUEUE_INFO(0);
 539         GET_QUEUE_INFO(1);
 540         GET_QUEUE_INFO(2);
 541         GET_QUEUE_INFO(3);
 542         GET_QUEUE_INFO(4);
 543         GET_QUEUE_INFO(5);
 544         GET_QUEUE_INFO(6);
 545         GET_QUEUE_INFO(7);
 546
 547         return rc;
 548 }
 549
 550 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
 551                          struct bnxt_ring *ring,
 552                          uint32_t ring_type, uint32_t map_index,
 553                          uint32_t stats_ctx_id)
 554 {
 555         int rc = 0;
 556         struct hwrm_ring_alloc_input req = {.req_type = 0 };
 557         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 558
 559         HWRM_PREP(req, RING_ALLOC, -1, resp);
 560
 561         req.enables = rte_cpu_to_le_32(0);
 562
 563         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
 564         req.fbo = rte_cpu_to_le_32(0);
 565         /* Association of ring index with doorbell index */
 566         req.logical_id = rte_cpu_to_le_16(map_index);
 567
 568         switch (ring_type) {
 569         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
 570                 req.queue_id = bp->cos_queue[0].id;
 571         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
 572                 req.ring_type = ring_type;
 573                 req.cmpl_ring_id =
 574                     rte_cpu_to_le_16(bp->grp_info[map_index].cp_fw_ring_id);
 575                 req.length = rte_cpu_to_le_32(ring->ring_size);
 576                 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
 577                 req.enables = rte_cpu_to_le_32(rte_le_to_cpu_32(req.enables) |
 578                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID);
 579                 break;
 580         case HWRM_RING_ALLOC_INPUT_RING_TYPE_CMPL:
 581                 req.ring_type = ring_type;
 582                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_POLL;
 583                 req.length = rte_cpu_to_le_32(ring->ring_size);
 584                 break;
 585         default:
 586                 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
 587                         ring_type);
 588                 return -1;
 589         }
 590
 591         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 592
 593         if (rc || resp->error_code) {
 594                 if (rc == 0 && resp->error_code)
 595                         rc = rte_le_to_cpu_16(resp->error_code);
 596                 switch (ring_type) {
 597                 case HWRM_RING_FREE_INPUT_RING_TYPE_CMPL:
 598                         RTE_LOG(ERR, PMD,
 599                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
 600                         return rc;
 601                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 602                         RTE_LOG(ERR, PMD,
 603                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
 604                         return rc;
 605                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 606                         RTE_LOG(ERR, PMD,
 607                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
 608                         return rc;
 609                 default:
 610                         RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
 611                         return rc;
 612                 }
 613         }
 614
 615         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
 616         return rc;
 617 }
 618
 619 int bnxt_hwrm_ring_free(struct bnxt *bp,
 620                         struct bnxt_ring *ring, uint32_t ring_type)
 621 {
 622         int rc;
 623         struct hwrm_ring_free_input req = {.req_type = 0 };
 624         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
 625
 626         HWRM_PREP(req, RING_FREE, -1, resp);
 627
 628         req.ring_type = ring_type;
 629         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
 630
 631         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 632
 633         if (rc || resp->error_code) {
 634                 if (rc == 0 && resp->error_code)
 635                         rc = rte_le_to_cpu_16(resp->error_code);
 636
 637                 switch (ring_type) {
 638                 case HWRM_RING_FREE_INPUT_RING_TYPE_CMPL:
 639                         RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
 640                                 rc);
 641                         return rc;
 642                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 643                         RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
 644                                 rc);
 645                         return rc;
 646                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 647                         RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
 648                                 rc);
 649                         return rc;
 650                 default:
 651                         RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
 652                         return rc;
 653                 }
 654         }
 655         return 0;
 656 }
 657
 658 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
 659 {
 660         int rc = 0;
 661         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
 662         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 663
 664         HWRM_PREP(req, RING_GRP_ALLOC, -1, resp);
 665
 666         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
 667         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
 668         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
 669         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
 670
 671         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 672
 673         HWRM_CHECK_RESULT;
 674
 675         bp->grp_info[idx].fw_grp_id =
 676             rte_le_to_cpu_16(resp->ring_group_id);
 677
 678         return rc;
 679 }
 680
 681 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
 682 {
 683         int rc;
 684         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
 685         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
 686
 687         HWRM_PREP(req, RING_GRP_FREE, -1, resp);
 688
 689         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
 690
 691         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 692
 693         HWRM_CHECK_RESULT;
 694
 695         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
 696         return rc;
 697 }
 698
 699 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
 700 {
 701         int rc = 0;
 702         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
 703         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
 704
 705         HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
 706
 707         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
 708                 return rc;
 709
 710         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
 711         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
 712
 713         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 714
 715         HWRM_CHECK_RESULT;
 716
 717         return rc;
 718 }
 719
 720 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp,
 721                              struct bnxt_cp_ring_info *cpr, unsigned int idx)
 722 {
 723         int rc;
 724         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
 725         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 726
 727         HWRM_PREP(req, STAT_CTX_ALLOC, -1, resp);
 728
 729         req.update_period_ms = rte_cpu_to_le_32(1000);
 730
 731         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
 732         req.stats_dma_addr =
 733             rte_cpu_to_le_64(cpr->hw_stats_map);
 734
 735         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 736
 737         HWRM_CHECK_RESULT;
 738
 739         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
 740         bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
 741
 742         return rc;
 743 }
 744
 745 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp,
 746                             struct bnxt_cp_ring_info *cpr, unsigned int idx)
 747 {
 748         int rc;
 749         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
 750         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
 751
 752         HWRM_PREP(req, STAT_CTX_FREE, -1, resp);
 753
 754         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
 755         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
 756
 757         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 758
 759         HWRM_CHECK_RESULT;
 760
 761         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
 762         bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
 763
 764         return rc;
 765 }
 766
 767 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 768 {
 769         int rc = 0, i, j;
 770         struct hwrm_vnic_alloc_input req = {.req_type = 0 };
 771         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 772
 773         /* map ring groups to this vnic */
 774         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++) {
 775                 if (bp->grp_info[i].fw_grp_id == (uint16_t)HWRM_NA_SIGNATURE) {
 776                         RTE_LOG(ERR, PMD,
 777                                 "Not enough ring groups avail:%x req:%x\n", j,
 778                                 (vnic->end_grp_id - vnic->start_grp_id) + 1);
 779                         break;
 780                 }
 781                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
 782         }
 783
 784         vnic->fw_rss_cos_lb_ctx = (uint16_t)HWRM_NA_SIGNATURE;
 785         vnic->ctx_is_rss_cos_lb = HW_CONTEXT_NONE;
 786
 787         HWRM_PREP(req, VNIC_ALLOC, -1, resp);
 788
 789         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 790
 791         HWRM_CHECK_RESULT;
 792
 793         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
 794         return rc;
 795 }
 796
 797 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 798 {
 799         int rc = 0;
 800         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
 801         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 802
 803         HWRM_PREP(req, VNIC_CFG, -1, resp);
 804
 805         /* Only RSS support for now TBD: COS & LB */
 806         req.enables =
 807             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP |
 808                              HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE |
 809                              HWRM_VNIC_CFG_INPUT_ENABLES_MRU);
 810         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 811         req.dflt_ring_grp =
 812                 rte_cpu_to_le_16(bp->grp_info[vnic->start_grp_id].fw_grp_id);
 813         req.rss_rule = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
 814         req.cos_rule = rte_cpu_to_le_16(0xffff);
 815         req.lb_rule = rte_cpu_to_le_16(0xffff);
 816         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
 817                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
 818         if (vnic->func_default)
 819                 req.flags = 1;
 820         if (vnic->vlan_strip)
 821                 req.flags |=
 822                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
 823
 824         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 825
 826         HWRM_CHECK_RESULT;
 827
 828         return rc;
 829 }
 830
 831 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 832 {
 833         int rc = 0;
 834         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
 835         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
 836                                                 bp->hwrm_cmd_resp_addr;
 837
 838         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, -1, resp);
 839
 840         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 841
 842         HWRM_CHECK_RESULT;
 843
 844         vnic->fw_rss_cos_lb_ctx = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
 845
 846         return rc;
 847 }
 848
 849 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 850 {
 851         int rc = 0;
 852         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
 853         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
 854                                                 bp->hwrm_cmd_resp_addr;
 855
 856         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, -1, resp);
 857
 858         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
 859
 860         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 861
 862         HWRM_CHECK_RESULT;
 863
 864         vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
 865
 866         return rc;
 867 }
 868
 869 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 870 {
 871         int rc = 0;
 872         struct hwrm_vnic_free_input req = {.req_type = 0 };
 873         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
 874
 875         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 876                 return rc;
 877
 878         HWRM_PREP(req, VNIC_FREE, -1, resp);
 879
 880         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 881
 882         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 883
 884         HWRM_CHECK_RESULT;
 885
 886         vnic->fw_vnic_id = INVALID_HW_RING_ID;
 887         return rc;
 888 }
 889
 890 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
 891                            struct bnxt_vnic_info *vnic)
 892 {
 893         int rc = 0;
 894         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
 895         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 896
 897         HWRM_PREP(req, VNIC_RSS_CFG, -1, resp);
 898
 899         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
 900
 901         req.ring_grp_tbl_addr =
 902             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
 903         req.hash_key_tbl_addr =
 904             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
 905         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
 906
 907         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 908
 909         HWRM_CHECK_RESULT;
 910
 911         return rc;
 912 }
 913
 914 /*
 915  * HWRM utility functions
 916  */
 917
 918 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
 919 {
 920         unsigned int i;
 921         int rc = 0;
 922
 923         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
 924                 struct bnxt_tx_queue *txq;
 925                 struct bnxt_rx_queue *rxq;
 926                 struct bnxt_cp_ring_info *cpr;
 927
 928                 if (i >= bp->rx_cp_nr_rings) {
 929                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
 930                         cpr = txq->cp_ring;
 931                 } else {
 932                         rxq = bp->rx_queues[i];
 933                         cpr = rxq->cp_ring;
 934                 }
 935
 936                 rc = bnxt_hwrm_stat_clear(bp, cpr);
 937                 if (rc)
 938                         return rc;
 939         }
 940         return 0;
 941 }
 942
 943 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
 944 {
 945         int rc;
 946         unsigned int i;
 947         struct bnxt_cp_ring_info *cpr;
 948
 949         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
 950                 unsigned int idx = i + 1;
 951
 952                 if (i >= bp->rx_cp_nr_rings)
 953                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
 954                 else
 955                         cpr = bp->rx_queues[i]->cp_ring;
 956                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
 957                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, idx);
 958                         if (rc)
 959                                 return rc;
 960                 }
 961         }
 962         return 0;
 963 }
 964
 965 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
 966 {
 967         unsigned int i;
 968         int rc = 0;
 969
 970         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
 971                 struct bnxt_tx_queue *txq;
 972                 struct bnxt_rx_queue *rxq;
 973                 struct bnxt_cp_ring_info *cpr;
 974                 unsigned int idx = i + 1;
 975
 976                 if (i >= bp->rx_cp_nr_rings) {
 977                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
 978                         cpr = txq->cp_ring;
 979                 } else {
 980                         rxq = bp->rx_queues[i];
 981                         cpr = rxq->cp_ring;
 982                 }
 983
 984                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, idx);
 985
 986                 if (rc)
 987                         return rc;
 988         }
 989         return rc;
 990 }
 991
 992 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
 993 {
 994         uint16_t i;
 995         uint32_t rc = 0;
 996
 997         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
 998                 unsigned int idx = i + 1;
 999
1000                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID) {
1001                         RTE_LOG(ERR, PMD,
1002                                 "Attempt to free invalid ring group %d\n",
1003                                 idx);
1004                         continue;
1005                 }
1006
1007                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1008
1009                 if (rc)
1010                         return rc;
1011         }
1012         return rc;
1013 }
1014
1015 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1016 {
1017         uint16_t i;
1018         uint32_t rc = 0;
1019
1020         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1021                 unsigned int idx = i + 1;
1022
1023                 if (bp->grp_info[idx].cp_fw_ring_id == INVALID_HW_RING_ID ||
1024                     bp->grp_info[idx].rx_fw_ring_id == INVALID_HW_RING_ID)
1025                         continue;
1026
1027                 rc = bnxt_hwrm_ring_grp_alloc(bp, idx);
1028
1029                 if (rc)
1030                         return rc;
1031         }
1032         return rc;
1033 }
1034
1035 void bnxt_free_hwrm_resources(struct bnxt *bp)
1036 {
1037         /* Release memzone */
1038         rte_free(bp->hwrm_cmd_resp_addr);
1039         bp->hwrm_cmd_resp_addr = NULL;
1040         bp->hwrm_cmd_resp_dma_addr = 0;
1041 }
1042
1043 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1044 {
1045         struct rte_pci_device *pdev = bp->pdev;
1046         char type[RTE_MEMZONE_NAMESIZE];
1047
1048         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1049                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1050         bp->max_req_len = HWRM_MAX_REQ_LEN;
1051         bp->max_resp_len = HWRM_MAX_RESP_LEN;
1052         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1053         if (bp->hwrm_cmd_resp_addr == NULL)
1054                 return -ENOMEM;
1055         bp->hwrm_cmd_resp_dma_addr =
1056                 rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
1057         rte_spinlock_init(&bp->hwrm_lock);
1058
1059         return 0;
1060 }
1061
1062 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1063 {
1064         struct bnxt_filter_info *filter;
1065         int rc = 0;
1066
1067         STAILQ_FOREACH(filter, &vnic->filter, next) {
1068                 rc = bnxt_hwrm_clear_filter(bp, filter);
1069                 if (rc)
1070                         break;
1071         }
1072         return rc;
1073 }
1074
1075 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1076 {
1077         struct bnxt_filter_info *filter;
1078         int rc = 0;
1079
1080         STAILQ_FOREACH(filter, &vnic->filter, next) {
1081                 rc = bnxt_hwrm_set_filter(bp, vnic, filter);
1082                 if (rc)
1083                         break;
1084         }
1085         return rc;
1086 }
1087
1088 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1089 {
1090         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1091
1092         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1093                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1094
1095         switch (conf_link_speed) {
1096         case ETH_LINK_SPEED_10M_HD:
1097         case ETH_LINK_SPEED_100M_HD:
1098                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1099         }
1100         return hw_link_duplex;
1101 }
1102
1103 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1104 {
1105         uint16_t eth_link_speed = 0;
1106
1107         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1108                 return ETH_LINK_SPEED_AUTONEG;
1109
1110         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1111         case ETH_LINK_SPEED_100M:
1112         case ETH_LINK_SPEED_100M_HD:
1113                 eth_link_speed =
1114                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB;
1115                 break;
1116         case ETH_LINK_SPEED_1G:
1117                 eth_link_speed =
1118                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1119                 break;
1120         case ETH_LINK_SPEED_2_5G:
1121                 eth_link_speed =
1122                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1123                 break;
1124         case ETH_LINK_SPEED_10G:
1125                 eth_link_speed =
1126                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1127                 break;
1128         case ETH_LINK_SPEED_20G:
1129                 eth_link_speed =
1130                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1131                 break;
1132         case ETH_LINK_SPEED_25G:
1133                 eth_link_speed =
1134                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1135                 break;
1136         case ETH_LINK_SPEED_40G:
1137                 eth_link_speed =
1138                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1139                 break;
1140         case ETH_LINK_SPEED_50G:
1141                 eth_link_speed =
1142                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1143                 break;
1144         default:
1145                 RTE_LOG(ERR, PMD,
1146                         "Unsupported link speed %d; default to AUTO\n",
1147                         conf_link_speed);
1148                 break;
1149         }
1150         return eth_link_speed;
1151 }
1152
1153 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1154                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1155                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1156                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1157
1158 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
1159 {
1160         uint32_t one_speed;
1161
1162         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1163                 return 0;
1164
1165         if (link_speed & ETH_LINK_SPEED_FIXED) {
1166                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1167
1168                 if (one_speed & (one_speed - 1)) {
1169                         RTE_LOG(ERR, PMD,
1170                                 "Invalid advertised speeds (%u) for port %u\n",
1171                                 link_speed, port_id);
1172                         return -EINVAL;
1173                 }
1174                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1175                         RTE_LOG(ERR, PMD,
1176                                 "Unsupported advertised speed (%u) for port %u\n",
1177                                 link_speed, port_id);
1178                         return -EINVAL;
1179                 }
1180         } else {
1181                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1182                         RTE_LOG(ERR, PMD,
1183                                 "Unsupported advertised speeds (%u) for port %u\n",
1184                                 link_speed, port_id);
1185                         return -EINVAL;
1186                 }
1187         }
1188         return 0;
1189 }
1190
1191 static uint16_t bnxt_parse_eth_link_speed_mask(uint32_t link_speed)
1192 {
1193         uint16_t ret = 0;
1194
1195         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1196                 link_speed = BNXT_SUPPORTED_SPEEDS;
1197
1198         if (link_speed & ETH_LINK_SPEED_100M)
1199                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1200         if (link_speed & ETH_LINK_SPEED_100M_HD)
1201                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1202         if (link_speed & ETH_LINK_SPEED_1G)
1203                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1204         if (link_speed & ETH_LINK_SPEED_2_5G)
1205                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1206         if (link_speed & ETH_LINK_SPEED_10G)
1207                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1208         if (link_speed & ETH_LINK_SPEED_20G)
1209                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1210         if (link_speed & ETH_LINK_SPEED_25G)
1211                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1212         if (link_speed & ETH_LINK_SPEED_40G)
1213                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1214         if (link_speed & ETH_LINK_SPEED_50G)
1215                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1216         return ret;
1217 }
1218
1219 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
1220 {
1221         int rc = 0;
1222         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1223         struct bnxt_link_info link_req;
1224         uint16_t speed;
1225
1226         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
1227                         bp->eth_dev->data->port_id);
1228         if (rc)
1229                 goto error;
1230
1231         memset(&link_req, 0, sizeof(link_req));
1232         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
1233         link_req.link_up = link_up;
1234         if (speed == 0) {
1235                 link_req.phy_flags =
1236                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
1237                 link_req.auto_mode =
1238                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW;
1239                 link_req.auto_link_speed_mask =
1240                         bnxt_parse_eth_link_speed_mask(dev_conf->link_speeds);
1241                 link_req.auto_link_speed =
1242                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB;
1243         } else {
1244                 link_req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1245                 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE |
1246                         HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
1247                 link_req.link_speed = speed;
1248         }
1249         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
1250         link_req.auto_pause = bp->link_info.auto_pause;
1251         link_req.force_pause = bp->link_info.force_pause;
1252
1253         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
1254         if (rc) {
1255                 RTE_LOG(ERR, PMD,
1256                         "Set link config failed with rc %d\n", rc);
1257         }
1258
1259 error:
1260         return rc;
1261 }