drivers/net/bnxt/bnxt_hwrm.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <unistd.h>
  35
  36 #include <unistd.h>
  37
  38 #include <rte_byteorder.h>
  39 #include <rte_common.h>
  40 #include <rte_cycles.h>
  41 #include <rte_malloc.h>
  42 #include <rte_memzone.h>
  43 #include <rte_version.h>
  44
  45 #include "bnxt.h"
  46 #include "bnxt_cpr.h"
  47 #include "bnxt_filter.h"
  48 #include "bnxt_hwrm.h"
  49 #include "bnxt_rxq.h"
  50 #include "bnxt_rxr.h"
  51 #include "bnxt_ring.h"
  52 #include "bnxt_txq.h"
  53 #include "bnxt_txr.h"
  54 #include "bnxt_vnic.h"
  55 #include "hsi_struct_def_dpdk.h"
  56
  57 #include <rte_io.h>
  58
  59 #define HWRM_CMD_TIMEOUT                2000
  60
  61 struct bnxt_plcmodes_cfg {
  62         uint32_t        flags;
  63         uint16_t        jumbo_thresh;
  64         uint16_t        hds_offset;
  65         uint16_t        hds_threshold;
  66 };
  67
  68 static int page_getenum(size_t size)
  69 {
  70         if (size <= 1 << 4)
  71                 return 4;
  72         if (size <= 1 << 12)
  73                 return 12;
  74         if (size <= 1 << 13)
  75                 return 13;
  76         if (size <= 1 << 16)
  77                 return 16;
  78         if (size <= 1 << 21)
  79                 return 21;
  80         if (size <= 1 << 22)
  81                 return 22;
  82         if (size <= 1 << 30)
  83                 return 30;
  84         RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
  85         return sizeof(void *) * 8 - 1;
  86 }
  87
  88 static int page_roundup(size_t size)
  89 {
  90         return 1 << page_getenum(size);
  91 }
  92
  93 /*
  94  * HWRM Functions (sent to HWRM)
  95  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  96  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  97  * command was failed by the ChiMP.
  98  */
  99
 100 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
 101                                         uint32_t msg_len)
 102 {
 103         unsigned int i;
 104         struct input *req = msg;
 105         struct output *resp = bp->hwrm_cmd_resp_addr;
 106         uint32_t *data = msg;
 107         uint8_t *bar;
 108         uint8_t *valid;
 109
 110         /* Write request msg to hwrm channel */
 111         for (i = 0; i < msg_len; i += 4) {
 112                 bar = (uint8_t *)bp->bar0 + i;
 113                 rte_write32(*data, bar);
 114                 data++;
 115         }
 116
 117         /* Zero the rest of the request space */
 118         for (; i < bp->max_req_len; i += 4) {
 119                 bar = (uint8_t *)bp->bar0 + i;
 120                 rte_write32(0, bar);
 121         }
 122
 123         /* Ring channel doorbell */
 124         bar = (uint8_t *)bp->bar0 + 0x100;
 125         rte_write32(1, bar);
 126
 127         /* Poll for the valid bit */
 128         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 129                 /* Sanity check on the resp->resp_len */
 130                 rte_rmb();
 131                 if (resp->resp_len && resp->resp_len <=
 132                                 bp->max_resp_len) {
 133                         /* Last byte of resp contains the valid key */
 134                         valid = (uint8_t *)resp + resp->resp_len - 1;
 135                         if (*valid == HWRM_RESP_VALID_KEY)
 136                                 break;
 137                 }
 138                 rte_delay_us(600);
 139         }
 140
 141         if (i >= HWRM_CMD_TIMEOUT) {
 142                 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
 143                         req->req_type);
 144                 goto err_ret;
 145         }
 146         return 0;
 147
 148 err_ret:
 149         return -1;
 150 }
 151
 152 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
 153 {
 154         int rc;
 155
 156         rte_spinlock_lock(&bp->hwrm_lock);
 157         rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
 158         rte_spinlock_unlock(&bp->hwrm_lock);
 159         return rc;
 160 }
 161
 162 #define HWRM_PREP(req, type, cr, resp) \
 163         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 164         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 165         req.cmpl_ring = rte_cpu_to_le_16(cr); \
 166         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 167         req.target_id = rte_cpu_to_le_16(0xffff); \
 168         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
 169
 170 #define HWRM_CHECK_RESULT \
 171         { \
 172                 if (rc) { \
 173                         RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
 174                                 __func__, rc); \
 175                         return rc; \
 176                 } \
 177                 if (resp->error_code) { \
 178                         rc = rte_le_to_cpu_16(resp->error_code); \
 179                         if (resp->resp_len >= 16) { \
 180                                 struct hwrm_err_output *tmp_hwrm_err_op = \
 181                                                         (void *)resp; \
 182                                 RTE_LOG(ERR, PMD, \
 183                                         "%s error %d:%d:%08x:%04x\n", \
 184                                         __func__, \
 185                                         rc, tmp_hwrm_err_op->cmd_err, \
 186                                         rte_le_to_cpu_32(\
 187                                                 tmp_hwrm_err_op->opaque_0), \
 188                                         rte_le_to_cpu_16(\
 189                                                 tmp_hwrm_err_op->opaque_1)); \
 190                         } \
 191                         else { \
 192                                 RTE_LOG(ERR, PMD, \
 193                                         "%s error %d\n", __func__, rc); \
 194                         } \
 195                         return rc; \
 196                 } \
 197         }
 198
 199 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 200 {
 201         int rc = 0;
 202         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 203         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 204
 205         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
 206         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 207         req.mask = 0;
 208
 209         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 210
 211         HWRM_CHECK_RESULT;
 212
 213         return rc;
 214 }
 215
 216 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 217 {
 218         int rc = 0;
 219         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 220         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 221         uint32_t mask = 0;
 222
 223         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
 224         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 225
 226         /* FIXME add multicast flag, when multicast adding options is supported
 227          * by ethtool.
 228          */
 229         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 230                 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 231         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 232                 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 233         req.mask = rte_cpu_to_le_32(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST |
 234                                     mask);
 235
 236         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 237
 238         HWRM_CHECK_RESULT;
 239
 240         return rc;
 241 }
 242
 243 int bnxt_hwrm_clear_filter(struct bnxt *bp,
 244                            struct bnxt_filter_info *filter)
 245 {
 246         int rc = 0;
 247         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 248         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 249
 250         HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
 251
 252         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 253
 254         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 255
 256         HWRM_CHECK_RESULT;
 257
 258         filter->fw_l2_filter_id = -1;
 259
 260         return 0;
 261 }
 262
 263 int bnxt_hwrm_set_filter(struct bnxt *bp,
 264                          struct bnxt_vnic_info *vnic,
 265                          struct bnxt_filter_info *filter)
 266 {
 267         int rc = 0;
 268         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 269         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 270         uint32_t enables = 0;
 271
 272         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
 273
 274         req.flags = rte_cpu_to_le_32(filter->flags);
 275
 276         enables = filter->enables |
 277               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 278         req.dst_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 279
 280         if (enables &
 281             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 282                 memcpy(req.l2_addr, filter->l2_addr,
 283                        ETHER_ADDR_LEN);
 284         if (enables &
 285             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 286                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 287                        ETHER_ADDR_LEN);
 288         if (enables &
 289             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 290                 req.l2_ovlan = filter->l2_ovlan;
 291         if (enables &
 292             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 293                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 294
 295         req.enables = rte_cpu_to_le_32(enables);
 296
 297         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 298
 299         HWRM_CHECK_RESULT;
 300
 301         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 302
 303         return rc;
 304 }
 305
 306 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 307 {
 308         int rc = 0;
 309         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 310         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 311         uint16_t new_max_vfs;
 312         int i;
 313
 314         HWRM_PREP(req, FUNC_QCAPS, -1, resp);
 315
 316         req.fid = rte_cpu_to_le_16(0xffff);
 317
 318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 319
 320         HWRM_CHECK_RESULT;
 321
 322         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 323         if (BNXT_PF(bp)) {
 324                 bp->pf.port_id = resp->port_id;
 325                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 326                 new_max_vfs = bp->pdev->max_vfs;
 327                 if (new_max_vfs != bp->pf.max_vfs) {
 328                         if (bp->pf.vf_info)
 329                                 rte_free(bp->pf.vf_info);
 330                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 331                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 332                         bp->pf.max_vfs = new_max_vfs;
 333                         for (i = 0; i < new_max_vfs; i++) {
 334                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 335                                 bp->pf.vf_info[i].vlan_table =
 336                                         rte_zmalloc("VF VLAN table",
 337                                                     getpagesize(),
 338                                                     getpagesize());
 339                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 340                                         RTE_LOG(ERR, PMD,
 341                                         "Fail to alloc VLAN table for VF %d\n",
 342                                         i);
 343                                 else
 344                                         rte_mem_lock_page(
 345                                                 bp->pf.vf_info[i].vlan_table);
 346                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 347                         }
 348                 }
 349         }
 350
 351         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 352         memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
 353         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 354         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 355         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 356         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 357         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 358         /* TODO: For now, do not support VMDq/RFS on VFs. */
 359         if (BNXT_PF(bp)) {
 360                 if (bp->pf.max_vfs)
 361                         bp->max_vnics = 1;
 362                 else
 363                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 364         } else {
 365                 bp->max_vnics = 1;
 366         }
 367         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 368         if (BNXT_PF(bp))
 369                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 370
 371         return rc;
 372 }
 373
 374 int bnxt_hwrm_func_reset(struct bnxt *bp)
 375 {
 376         int rc = 0;
 377         struct hwrm_func_reset_input req = {.req_type = 0 };
 378         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 379
 380         HWRM_PREP(req, FUNC_RESET, -1, resp);
 381
 382         req.enables = rte_cpu_to_le_32(0);
 383
 384         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 385
 386         HWRM_CHECK_RESULT;
 387
 388         return rc;
 389 }
 390
 391 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 392 {
 393         int rc;
 394         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 395         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 396
 397         if (bp->flags & BNXT_FLAG_REGISTERED)
 398                 return 0;
 399
 400         HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
 401         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 402                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 403         req.ver_maj = RTE_VER_YEAR;
 404         req.ver_min = RTE_VER_MONTH;
 405         req.ver_upd = RTE_VER_MINOR;
 406
 407         if (BNXT_PF(bp)) {
 408                 req.enables |= rte_cpu_to_le_32(
 409                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
 410                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 411                        RTE_MIN(sizeof(req.vf_req_fwd),
 412                                sizeof(bp->pf.vf_req_fwd)));
 413         }
 414
 415         req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1);   /* TODO: Use MACRO */
 416         memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
 417
 418         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 419
 420         HWRM_CHECK_RESULT;
 421
 422         bp->flags |= BNXT_FLAG_REGISTERED;
 423
 424         return rc;
 425 }
 426
 427 int bnxt_hwrm_ver_get(struct bnxt *bp)
 428 {
 429         int rc = 0;
 430         struct hwrm_ver_get_input req = {.req_type = 0 };
 431         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 432         uint32_t my_version;
 433         uint32_t fw_version;
 434         uint16_t max_resp_len;
 435         char type[RTE_MEMZONE_NAMESIZE];
 436
 437         HWRM_PREP(req, VER_GET, -1, resp);
 438
 439         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 440         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 441         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 442
 443         /*
 444          * Hold the lock since we may be adjusting the response pointers.
 445          */
 446         rte_spinlock_lock(&bp->hwrm_lock);
 447         rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
 448
 449         HWRM_CHECK_RESULT;
 450
 451         RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
 452                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
 453                 resp->hwrm_intf_upd,
 454                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
 455         bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
 456                         (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
 457         RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
 458                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 459
 460         my_version = HWRM_VERSION_MAJOR << 16;
 461         my_version |= HWRM_VERSION_MINOR << 8;
 462         my_version |= HWRM_VERSION_UPDATE;
 463
 464         fw_version = resp->hwrm_intf_maj << 16;
 465         fw_version |= resp->hwrm_intf_min << 8;
 466         fw_version |= resp->hwrm_intf_upd;
 467
 468         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
 469                 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
 470                 rc = -EINVAL;
 471                 goto error;
 472         }
 473
 474         if (my_version != fw_version) {
 475                 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
 476                 if (my_version < fw_version) {
 477                         RTE_LOG(INFO, PMD,
 478                                 "Firmware API version is newer than driver.\n");
 479                         RTE_LOG(INFO, PMD,
 480                                 "The driver may be missing features.\n");
 481                 } else {
 482                         RTE_LOG(INFO, PMD,
 483                                 "Firmware API version is older than driver.\n");
 484                         RTE_LOG(INFO, PMD,
 485                                 "Not all driver features may be functional.\n");
 486                 }
 487         }
 488
 489         if (bp->max_req_len > resp->max_req_win_len) {
 490                 RTE_LOG(ERR, PMD, "Unsupported request length\n");
 491                 rc = -EINVAL;
 492         }
 493         bp->max_req_len = resp->max_req_win_len;
 494         max_resp_len = resp->max_resp_len;
 495         if (bp->max_resp_len != max_resp_len) {
 496                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 497                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 498                         bp->pdev->addr.devid, bp->pdev->addr.function);
 499
 500                 rte_free(bp->hwrm_cmd_resp_addr);
 501
 502                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 503                 if (bp->hwrm_cmd_resp_addr == NULL) {
 504                         rc = -ENOMEM;
 505                         goto error;
 506                 }
 507                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 508                 bp->hwrm_cmd_resp_dma_addr =
 509                         rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
 510                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 511                         RTE_LOG(ERR, PMD,
 512                         "Unable to map response buffer to physical memory.\n");
 513                         rc = -ENOMEM;
 514                         goto error;
 515                 }
 516                 bp->max_resp_len = max_resp_len;
 517         }
 518
 519 error:
 520         rte_spinlock_unlock(&bp->hwrm_lock);
 521         return rc;
 522 }
 523
 524 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 525 {
 526         int rc;
 527         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 528         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 529
 530         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 531                 return 0;
 532
 533         HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
 534         req.flags = flags;
 535
 536         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 537
 538         HWRM_CHECK_RESULT;
 539
 540         bp->flags &= ~BNXT_FLAG_REGISTERED;
 541
 542         return rc;
 543 }
 544
 545 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 546 {
 547         int rc = 0;
 548         struct hwrm_port_phy_cfg_input req = {0};
 549         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 550         uint32_t enables = 0;
 551
 552         HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
 553
 554         if (conf->link_up) {
 555                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 556                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 557                 /*
 558                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 559                  * any auto mode, even "none".
 560                  */
 561                 if (!conf->link_speed) {
 562                         req.auto_mode |= conf->auto_mode;
 563                         enables = HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 564                         req.auto_link_speed_mask = conf->auto_link_speed_mask;
 565                         enables |=
 566                            HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 567                         req.auto_link_speed = bp->link_info.auto_link_speed;
 568                         enables |=
 569                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
 570                 }
 571                 req.auto_duplex = conf->duplex;
 572                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 573                 req.auto_pause = conf->auto_pause;
 574                 req.force_pause = conf->force_pause;
 575                 /* Set force_pause if there is no auto or if there is a force */
 576                 if (req.auto_pause && !req.force_pause)
 577                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 578                 else
 579                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 580
 581                 req.enables = rte_cpu_to_le_32(enables);
 582         } else {
 583                 req.flags =
 584                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
 585                 RTE_LOG(INFO, PMD, "Force Link Down\n");
 586         }
 587
 588         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 589
 590         HWRM_CHECK_RESULT;
 591
 592         return rc;
 593 }
 594
 595 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
 596                                    struct bnxt_link_info *link_info)
 597 {
 598         int rc = 0;
 599         struct hwrm_port_phy_qcfg_input req = {0};
 600         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 601
 602         HWRM_PREP(req, PORT_PHY_QCFG, -1, resp);
 603
 604         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 605
 606         HWRM_CHECK_RESULT;
 607
 608         link_info->phy_link_status = resp->link;
 609         if (link_info->phy_link_status != HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK) {
 610                 link_info->link_up = 1;
 611                 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
 612         } else {
 613                 link_info->link_up = 0;
 614                 link_info->link_speed = 0;
 615         }
 616         link_info->duplex = resp->duplex;
 617         link_info->pause = resp->pause;
 618         link_info->auto_pause = resp->auto_pause;
 619         link_info->force_pause = resp->force_pause;
 620         link_info->auto_mode = resp->auto_mode;
 621
 622         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
 623         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
 624         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
 625         link_info->phy_ver[0] = resp->phy_maj;
 626         link_info->phy_ver[1] = resp->phy_min;
 627         link_info->phy_ver[2] = resp->phy_bld;
 628
 629         return rc;
 630 }
 631
 632 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 633 {
 634         int rc = 0;
 635         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 636         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 637
 638         HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
 639
 640         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 641
 642         HWRM_CHECK_RESULT;
 643
 644 #define GET_QUEUE_INFO(x) \
 645         bp->cos_queue[x].id = resp->queue_id##x; \
 646         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 647
 648         GET_QUEUE_INFO(0);
 649         GET_QUEUE_INFO(1);
 650         GET_QUEUE_INFO(2);
 651         GET_QUEUE_INFO(3);
 652         GET_QUEUE_INFO(4);
 653         GET_QUEUE_INFO(5);
 654         GET_QUEUE_INFO(6);
 655         GET_QUEUE_INFO(7);
 656
 657         return rc;
 658 }
 659
 660 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
 661                          struct bnxt_ring *ring,
 662                          uint32_t ring_type, uint32_t map_index,
 663                          uint32_t stats_ctx_id)
 664 {
 665         int rc = 0;
 666         struct hwrm_ring_alloc_input req = {.req_type = 0 };
 667         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 668
 669         HWRM_PREP(req, RING_ALLOC, -1, resp);
 670
 671         req.enables = rte_cpu_to_le_32(0);
 672
 673         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
 674         req.fbo = rte_cpu_to_le_32(0);
 675         /* Association of ring index with doorbell index */
 676         req.logical_id = rte_cpu_to_le_16(map_index);
 677
 678         switch (ring_type) {
 679         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
 680                 req.queue_id = bp->cos_queue[0].id;
 681                 /* FALLTHROUGH */
 682         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
 683                 req.ring_type = ring_type;
 684                 req.cmpl_ring_id =
 685                     rte_cpu_to_le_16(bp->grp_info[map_index].cp_fw_ring_id);
 686                 req.length = rte_cpu_to_le_32(ring->ring_size);
 687                 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
 688                 req.enables = rte_cpu_to_le_32(rte_le_to_cpu_32(req.enables) |
 689                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID);
 690                 break;
 691         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
 692                 req.ring_type = ring_type;
 693                 /*
 694                  * TODO: Some HWRM versions crash with
 695                  * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
 696                  */
 697                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
 698                 req.length = rte_cpu_to_le_32(ring->ring_size);
 699                 break;
 700         default:
 701                 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
 702                         ring_type);
 703                 return -1;
 704         }
 705
 706         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 707
 708         if (rc || resp->error_code) {
 709                 if (rc == 0 && resp->error_code)
 710                         rc = rte_le_to_cpu_16(resp->error_code);
 711                 switch (ring_type) {
 712                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 713                         RTE_LOG(ERR, PMD,
 714                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
 715                         return rc;
 716                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 717                         RTE_LOG(ERR, PMD,
 718                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
 719                         return rc;
 720                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 721                         RTE_LOG(ERR, PMD,
 722                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
 723                         return rc;
 724                 default:
 725                         RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
 726                         return rc;
 727                 }
 728         }
 729
 730         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
 731         return rc;
 732 }
 733
 734 int bnxt_hwrm_ring_free(struct bnxt *bp,
 735                         struct bnxt_ring *ring, uint32_t ring_type)
 736 {
 737         int rc;
 738         struct hwrm_ring_free_input req = {.req_type = 0 };
 739         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
 740
 741         HWRM_PREP(req, RING_FREE, -1, resp);
 742
 743         req.ring_type = ring_type;
 744         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
 745
 746         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 747
 748         if (rc || resp->error_code) {
 749                 if (rc == 0 && resp->error_code)
 750                         rc = rte_le_to_cpu_16(resp->error_code);
 751
 752                 switch (ring_type) {
 753                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 754                         RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
 755                                 rc);
 756                         return rc;
 757                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 758                         RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
 759                                 rc);
 760                         return rc;
 761                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 762                         RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
 763                                 rc);
 764                         return rc;
 765                 default:
 766                         RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
 767                         return rc;
 768                 }
 769         }
 770         return 0;
 771 }
 772
 773 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
 774 {
 775         int rc = 0;
 776         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
 777         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 778
 779         HWRM_PREP(req, RING_GRP_ALLOC, -1, resp);
 780
 781         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
 782         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
 783         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
 784         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
 785
 786         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 787
 788         HWRM_CHECK_RESULT;
 789
 790         bp->grp_info[idx].fw_grp_id =
 791             rte_le_to_cpu_16(resp->ring_group_id);
 792
 793         return rc;
 794 }
 795
 796 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
 797 {
 798         int rc;
 799         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
 800         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
 801
 802         HWRM_PREP(req, RING_GRP_FREE, -1, resp);
 803
 804         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
 805
 806         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 807
 808         HWRM_CHECK_RESULT;
 809
 810         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
 811         return rc;
 812 }
 813
 814 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
 815 {
 816         int rc = 0;
 817         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
 818         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
 819
 820         HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
 821
 822         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
 823                 return rc;
 824
 825         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
 826         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
 827
 828         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 829
 830         HWRM_CHECK_RESULT;
 831
 832         return rc;
 833 }
 834
 835 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp,
 836                              struct bnxt_cp_ring_info *cpr, unsigned int idx)
 837 {
 838         int rc;
 839         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
 840         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 841
 842         HWRM_PREP(req, STAT_CTX_ALLOC, -1, resp);
 843
 844         req.update_period_ms = rte_cpu_to_le_32(1000);
 845
 846         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
 847         req.stats_dma_addr =
 848             rte_cpu_to_le_64(cpr->hw_stats_map);
 849
 850         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 851
 852         HWRM_CHECK_RESULT;
 853
 854         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
 855         bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
 856
 857         return rc;
 858 }
 859
 860 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp,
 861                             struct bnxt_cp_ring_info *cpr, unsigned int idx)
 862 {
 863         int rc;
 864         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
 865         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
 866
 867         HWRM_PREP(req, STAT_CTX_FREE, -1, resp);
 868
 869         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
 870         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
 871
 872         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 873
 874         HWRM_CHECK_RESULT;
 875
 876         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
 877         bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
 878
 879         return rc;
 880 }
 881
 882 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 883 {
 884         int rc = 0, i, j;
 885         struct hwrm_vnic_alloc_input req = { 0 };
 886         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 887
 888         /* map ring groups to this vnic */
 889         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++) {
 890                 if (bp->grp_info[i].fw_grp_id == (uint16_t)HWRM_NA_SIGNATURE) {
 891                         RTE_LOG(ERR, PMD,
 892                                 "Not enough ring groups avail:%x req:%x\n", j,
 893                                 (vnic->end_grp_id - vnic->start_grp_id) + 1);
 894                         break;
 895                 }
 896                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
 897         }
 898         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
 899         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
 900         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
 901         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
 902         vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
 903                                 ETHER_CRC_LEN + VLAN_TAG_SIZE;
 904         HWRM_PREP(req, VNIC_ALLOC, -1, resp);
 905
 906         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 907
 908         HWRM_CHECK_RESULT;
 909
 910         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
 911         return rc;
 912 }
 913
 914 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
 915                                         struct bnxt_vnic_info *vnic,
 916                                         struct bnxt_plcmodes_cfg *pmode)
 917 {
 918         int rc = 0;
 919         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
 920         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 921
 922         HWRM_PREP(req, VNIC_PLCMODES_QCFG, -1, resp);
 923
 924         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
 925
 926         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 927
 928         HWRM_CHECK_RESULT;
 929
 930         pmode->flags = rte_le_to_cpu_32(resp->flags);
 931         /* dflt_vnic bit doesn't exist in the _cfg command */
 932         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
 933         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
 934         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
 935         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
 936
 937         return rc;
 938 }
 939
 940 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
 941                                        struct bnxt_vnic_info *vnic,
 942                                        struct bnxt_plcmodes_cfg *pmode)
 943 {
 944         int rc = 0;
 945         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
 946         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 947
 948         HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp);
 949
 950         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
 951         req.flags = rte_cpu_to_le_32(pmode->flags);
 952         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
 953         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
 954         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
 955         req.enables = rte_cpu_to_le_32(
 956             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
 957             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
 958             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
 959         );
 960
 961         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 962
 963         HWRM_CHECK_RESULT;
 964
 965         return rc;
 966 }
 967
 968 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 969 {
 970         int rc = 0;
 971         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
 972         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 973         uint32_t ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
 974         struct bnxt_plcmodes_cfg pmodes;
 975
 976         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
 977         if (rc)
 978                 return rc;
 979
 980         HWRM_PREP(req, VNIC_CFG, -1, resp);
 981
 982         /* Only RSS support for now TBD: COS & LB */
 983         req.enables =
 984             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP |
 985                              HWRM_VNIC_CFG_INPUT_ENABLES_MRU);
 986         if (vnic->lb_rule != 0xffff)
 987                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
 988         if (vnic->cos_rule != 0xffff)
 989                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
 990         if (vnic->rss_rule != 0xffff)
 991                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
 992         req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
 993         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 994         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
 995         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
 996         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
 997         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
 998         req.mru = rte_cpu_to_le_16(vnic->mru);
 999         if (vnic->func_default)
1000                 req.flags |=
1001                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1002         if (vnic->vlan_strip)
1003                 req.flags |=
1004                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1005         if (vnic->bd_stall)
1006                 req.flags |=
1007                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1008         if (vnic->roce_dual)
1009                 req.flags |= rte_cpu_to_le_32(
1010                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1011         if (vnic->roce_only)
1012                 req.flags |= rte_cpu_to_le_32(
1013                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1014         if (vnic->rss_dflt_cr)
1015                 req.flags |= rte_cpu_to_le_32(
1016                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1017
1018         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1019
1020         HWRM_CHECK_RESULT;
1021
1022         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1023
1024         return rc;
1025 }
1026
1027 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1028                 int16_t fw_vf_id)
1029 {
1030         int rc = 0;
1031         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1032         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1033
1034         HWRM_PREP(req, VNIC_QCFG, -1, resp);
1035
1036         req.enables =
1037                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1038         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1039         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1040
1041         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1042
1043         HWRM_CHECK_RESULT;
1044
1045         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1046         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1047         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1048         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1049         vnic->mru = rte_le_to_cpu_16(resp->mru);
1050         vnic->func_default = rte_le_to_cpu_32(
1051                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1052         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1053                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1054         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1055                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1056         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1057                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1058         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1059                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1060         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1061                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1062
1063         return rc;
1064 }
1065
1066 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1067 {
1068         int rc = 0;
1069         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1070         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1071                                                 bp->hwrm_cmd_resp_addr;
1072
1073         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, -1, resp);
1074
1075         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1076
1077         HWRM_CHECK_RESULT;
1078
1079         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1080
1081         return rc;
1082 }
1083
1084 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1085 {
1086         int rc = 0;
1087         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1088         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1089                                                 bp->hwrm_cmd_resp_addr;
1090
1091         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, -1, resp);
1092
1093         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1094
1095         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1096
1097         HWRM_CHECK_RESULT;
1098
1099         vnic->rss_rule = INVALID_HW_RING_ID;
1100
1101         return rc;
1102 }
1103
1104 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1105 {
1106         int rc = 0;
1107         struct hwrm_vnic_free_input req = {.req_type = 0 };
1108         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1109
1110         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
1111                 return rc;
1112
1113         HWRM_PREP(req, VNIC_FREE, -1, resp);
1114
1115         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1116
1117         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1118
1119         HWRM_CHECK_RESULT;
1120
1121         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1122         return rc;
1123 }
1124
1125 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1126                            struct bnxt_vnic_info *vnic)
1127 {
1128         int rc = 0;
1129         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1130         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1131
1132         HWRM_PREP(req, VNIC_RSS_CFG, -1, resp);
1133
1134         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1135
1136         req.ring_grp_tbl_addr =
1137             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1138         req.hash_key_tbl_addr =
1139             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1140         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1141
1142         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1143
1144         HWRM_CHECK_RESULT;
1145
1146         return rc;
1147 }
1148
1149 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1150 {
1151         struct hwrm_func_cfg_input req = {0};
1152         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1153         int rc;
1154
1155         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1156         req.enables = rte_cpu_to_le_32(
1157                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1158         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1159         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1160
1161         HWRM_PREP(req, FUNC_CFG, -1, resp);
1162
1163         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1164         HWRM_CHECK_RESULT;
1165
1166         bp->pf.vf_info[vf].random_mac = false;
1167
1168         return rc;
1169 }
1170
1171 /*
1172  * HWRM utility functions
1173  */
1174
1175 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1176 {
1177         unsigned int i;
1178         int rc = 0;
1179
1180         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1181                 struct bnxt_tx_queue *txq;
1182                 struct bnxt_rx_queue *rxq;
1183                 struct bnxt_cp_ring_info *cpr;
1184
1185                 if (i >= bp->rx_cp_nr_rings) {
1186                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1187                         cpr = txq->cp_ring;
1188                 } else {
1189                         rxq = bp->rx_queues[i];
1190                         cpr = rxq->cp_ring;
1191                 }
1192
1193                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1194                 if (rc)
1195                         return rc;
1196         }
1197         return 0;
1198 }
1199
1200 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1201 {
1202         int rc;
1203         unsigned int i;
1204         struct bnxt_cp_ring_info *cpr;
1205
1206         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1207                 unsigned int idx = i + 1;
1208
1209                 if (i >= bp->rx_cp_nr_rings)
1210                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1211                 else
1212                         cpr = bp->rx_queues[i]->cp_ring;
1213                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1214                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, idx);
1215                         if (rc)
1216                                 return rc;
1217                 }
1218         }
1219         return 0;
1220 }
1221
1222 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1223 {
1224         unsigned int i;
1225         int rc = 0;
1226
1227         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1228                 struct bnxt_tx_queue *txq;
1229                 struct bnxt_rx_queue *rxq;
1230                 struct bnxt_cp_ring_info *cpr;
1231                 unsigned int idx = i + 1;
1232
1233                 if (i >= bp->rx_cp_nr_rings) {
1234                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1235                         cpr = txq->cp_ring;
1236                 } else {
1237                         rxq = bp->rx_queues[i];
1238                         cpr = rxq->cp_ring;
1239                 }
1240
1241                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, idx);
1242
1243                 if (rc)
1244                         return rc;
1245         }
1246         return rc;
1247 }
1248
1249 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1250 {
1251         uint16_t i;
1252         uint32_t rc = 0;
1253
1254         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1255                 unsigned int idx = i + 1;
1256
1257                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID) {
1258                         RTE_LOG(ERR, PMD,
1259                                 "Attempt to free invalid ring group %d\n",
1260                                 idx);
1261                         continue;
1262                 }
1263
1264                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1265
1266                 if (rc)
1267                         return rc;
1268         }
1269         return rc;
1270 }
1271
1272 static void bnxt_free_cp_ring(struct bnxt *bp,
1273                               struct bnxt_cp_ring_info *cpr, unsigned int idx)
1274 {
1275         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1276
1277         bnxt_hwrm_ring_free(bp, cp_ring,
1278                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1279         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1280         bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1281         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1282                         sizeof(*cpr->cp_desc_ring));
1283         cpr->cp_raw_cons = 0;
1284 }
1285
1286 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1287 {
1288         unsigned int i;
1289         int rc = 0;
1290
1291         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1292                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1293                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1294                 struct bnxt_ring *ring = txr->tx_ring_struct;
1295                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1296                 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1297
1298                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1299                         bnxt_hwrm_ring_free(bp, ring,
1300                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1301                         ring->fw_ring_id = INVALID_HW_RING_ID;
1302                         memset(txr->tx_desc_ring, 0,
1303                                         txr->tx_ring_struct->ring_size *
1304                                         sizeof(*txr->tx_desc_ring));
1305                         memset(txr->tx_buf_ring, 0,
1306                                         txr->tx_ring_struct->ring_size *
1307                                         sizeof(*txr->tx_buf_ring));
1308                         txr->tx_prod = 0;
1309                         txr->tx_cons = 0;
1310                 }
1311                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1312                         bnxt_free_cp_ring(bp, cpr, idx);
1313         }
1314
1315         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1316                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1317                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1318                 struct bnxt_ring *ring = rxr->rx_ring_struct;
1319                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1320                 unsigned int idx = i + 1;
1321
1322                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1323                         bnxt_hwrm_ring_free(bp, ring,
1324                                         HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1325                         ring->fw_ring_id = INVALID_HW_RING_ID;
1326                         bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1327                         memset(rxr->rx_desc_ring, 0,
1328                                         rxr->rx_ring_struct->ring_size *
1329                                         sizeof(*rxr->rx_desc_ring));
1330                         memset(rxr->rx_buf_ring, 0,
1331                                         rxr->rx_ring_struct->ring_size *
1332                                         sizeof(*rxr->rx_buf_ring));
1333                         rxr->rx_prod = 0;
1334                 }
1335                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1336                         bnxt_free_cp_ring(bp, cpr, idx);
1337         }
1338
1339         /* Default completion ring */
1340         {
1341                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1342
1343                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1344                         bnxt_free_cp_ring(bp, cpr, 0);
1345         }
1346
1347         return rc;
1348 }
1349
1350 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1351 {
1352         uint16_t i;
1353         uint32_t rc = 0;
1354
1355         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1356                 unsigned int idx = i + 1;
1357
1358                 if (bp->grp_info[idx].cp_fw_ring_id == INVALID_HW_RING_ID ||
1359                     bp->grp_info[idx].rx_fw_ring_id == INVALID_HW_RING_ID)
1360                         continue;
1361
1362                 rc = bnxt_hwrm_ring_grp_alloc(bp, idx);
1363
1364                 if (rc)
1365                         return rc;
1366         }
1367         return rc;
1368 }
1369
1370 void bnxt_free_hwrm_resources(struct bnxt *bp)
1371 {
1372         /* Release memzone */
1373         rte_free(bp->hwrm_cmd_resp_addr);
1374         bp->hwrm_cmd_resp_addr = NULL;
1375         bp->hwrm_cmd_resp_dma_addr = 0;
1376 }
1377
1378 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1379 {
1380         struct rte_pci_device *pdev = bp->pdev;
1381         char type[RTE_MEMZONE_NAMESIZE];
1382
1383         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1384                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1385         bp->max_req_len = HWRM_MAX_REQ_LEN;
1386         bp->max_resp_len = HWRM_MAX_RESP_LEN;
1387         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1388         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1389         if (bp->hwrm_cmd_resp_addr == NULL)
1390                 return -ENOMEM;
1391         bp->hwrm_cmd_resp_dma_addr =
1392                 rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
1393         if (bp->hwrm_cmd_resp_dma_addr == 0) {
1394                 RTE_LOG(ERR, PMD,
1395                         "unable to map response address to physical memory\n");
1396                 return -ENOMEM;
1397         }
1398         rte_spinlock_init(&bp->hwrm_lock);
1399
1400         return 0;
1401 }
1402
1403 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1404 {
1405         struct bnxt_filter_info *filter;
1406         int rc = 0;
1407
1408         STAILQ_FOREACH(filter, &vnic->filter, next) {
1409                 rc = bnxt_hwrm_clear_filter(bp, filter);
1410                 if (rc)
1411                         break;
1412         }
1413         return rc;
1414 }
1415
1416 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1417 {
1418         struct bnxt_filter_info *filter;
1419         int rc = 0;
1420
1421         STAILQ_FOREACH(filter, &vnic->filter, next) {
1422                 rc = bnxt_hwrm_set_filter(bp, vnic, filter);
1423                 if (rc)
1424                         break;
1425         }
1426         return rc;
1427 }
1428
1429 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1430 {
1431         struct bnxt_vnic_info *vnic;
1432         unsigned int i;
1433
1434         if (bp->vnic_info == NULL)
1435                 return;
1436
1437         vnic = &bp->vnic_info[0];
1438         if (BNXT_PF(bp))
1439                 bnxt_hwrm_cfa_l2_clear_rx_mask(bp, vnic);
1440
1441         /* VNIC resources */
1442         for (i = 0; i < bp->nr_vnics; i++) {
1443                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1444
1445                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1446
1447                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1448                 bnxt_hwrm_vnic_free(bp, vnic);
1449         }
1450         /* Ring resources */
1451         bnxt_free_all_hwrm_rings(bp);
1452         bnxt_free_all_hwrm_ring_grps(bp);
1453         bnxt_free_all_hwrm_stat_ctxs(bp);
1454 }
1455
1456 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1457 {
1458         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1459
1460         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1461                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1462
1463         switch (conf_link_speed) {
1464         case ETH_LINK_SPEED_10M_HD:
1465         case ETH_LINK_SPEED_100M_HD:
1466                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1467         }
1468         return hw_link_duplex;
1469 }
1470
1471 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1472 {
1473         uint16_t eth_link_speed = 0;
1474
1475         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1476                 return ETH_LINK_SPEED_AUTONEG;
1477
1478         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1479         case ETH_LINK_SPEED_100M:
1480         case ETH_LINK_SPEED_100M_HD:
1481                 eth_link_speed =
1482                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1483                 break;
1484         case ETH_LINK_SPEED_1G:
1485                 eth_link_speed =
1486                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1487                 break;
1488         case ETH_LINK_SPEED_2_5G:
1489                 eth_link_speed =
1490                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1491                 break;
1492         case ETH_LINK_SPEED_10G:
1493                 eth_link_speed =
1494                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1495                 break;
1496         case ETH_LINK_SPEED_20G:
1497                 eth_link_speed =
1498                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1499                 break;
1500         case ETH_LINK_SPEED_25G:
1501                 eth_link_speed =
1502                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1503                 break;
1504         case ETH_LINK_SPEED_40G:
1505                 eth_link_speed =
1506                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1507                 break;
1508         case ETH_LINK_SPEED_50G:
1509                 eth_link_speed =
1510                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1511                 break;
1512         default:
1513                 RTE_LOG(ERR, PMD,
1514                         "Unsupported link speed %d; default to AUTO\n",
1515                         conf_link_speed);
1516                 break;
1517         }
1518         return eth_link_speed;
1519 }
1520
1521 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1522                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1523                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1524                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1525
1526 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
1527 {
1528         uint32_t one_speed;
1529
1530         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1531                 return 0;
1532
1533         if (link_speed & ETH_LINK_SPEED_FIXED) {
1534                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1535
1536                 if (one_speed & (one_speed - 1)) {
1537                         RTE_LOG(ERR, PMD,
1538                                 "Invalid advertised speeds (%u) for port %u\n",
1539                                 link_speed, port_id);
1540                         return -EINVAL;
1541                 }
1542                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1543                         RTE_LOG(ERR, PMD,
1544                                 "Unsupported advertised speed (%u) for port %u\n",
1545                                 link_speed, port_id);
1546                         return -EINVAL;
1547                 }
1548         } else {
1549                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1550                         RTE_LOG(ERR, PMD,
1551                                 "Unsupported advertised speeds (%u) for port %u\n",
1552                                 link_speed, port_id);
1553                         return -EINVAL;
1554                 }
1555         }
1556         return 0;
1557 }
1558
1559 static uint16_t bnxt_parse_eth_link_speed_mask(uint32_t link_speed)
1560 {
1561         uint16_t ret = 0;
1562
1563         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1564                 link_speed = BNXT_SUPPORTED_SPEEDS;
1565
1566         if (link_speed & ETH_LINK_SPEED_100M)
1567                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1568         if (link_speed & ETH_LINK_SPEED_100M_HD)
1569                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1570         if (link_speed & ETH_LINK_SPEED_1G)
1571                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1572         if (link_speed & ETH_LINK_SPEED_2_5G)
1573                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1574         if (link_speed & ETH_LINK_SPEED_10G)
1575                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1576         if (link_speed & ETH_LINK_SPEED_20G)
1577                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1578         if (link_speed & ETH_LINK_SPEED_25G)
1579                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1580         if (link_speed & ETH_LINK_SPEED_40G)
1581                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1582         if (link_speed & ETH_LINK_SPEED_50G)
1583                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1584         return ret;
1585 }
1586
1587 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
1588 {
1589         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
1590
1591         switch (hw_link_speed) {
1592         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
1593                 eth_link_speed = ETH_SPEED_NUM_100M;
1594                 break;
1595         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
1596                 eth_link_speed = ETH_SPEED_NUM_1G;
1597                 break;
1598         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
1599                 eth_link_speed = ETH_SPEED_NUM_2_5G;
1600                 break;
1601         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
1602                 eth_link_speed = ETH_SPEED_NUM_10G;
1603                 break;
1604         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
1605                 eth_link_speed = ETH_SPEED_NUM_20G;
1606                 break;
1607         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
1608                 eth_link_speed = ETH_SPEED_NUM_25G;
1609                 break;
1610         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
1611                 eth_link_speed = ETH_SPEED_NUM_40G;
1612                 break;
1613         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
1614                 eth_link_speed = ETH_SPEED_NUM_50G;
1615                 break;
1616         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
1617         default:
1618                 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
1619                         hw_link_speed);
1620                 break;
1621         }
1622         return eth_link_speed;
1623 }
1624
1625 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
1626 {
1627         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1628
1629         switch (hw_link_duplex) {
1630         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
1631         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
1632                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1633                 break;
1634         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
1635                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
1636                 break;
1637         default:
1638                 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
1639                         hw_link_duplex);
1640                 break;
1641         }
1642         return eth_link_duplex;
1643 }
1644
1645 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
1646 {
1647         int rc = 0;
1648         struct bnxt_link_info *link_info = &bp->link_info;
1649
1650         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
1651         if (rc) {
1652                 RTE_LOG(ERR, PMD,
1653                         "Get link config failed with rc %d\n", rc);
1654                 goto exit;
1655         }
1656         if (link_info->link_up)
1657                 link->link_speed =
1658                         bnxt_parse_hw_link_speed(link_info->link_speed);
1659         else
1660                 link->link_speed = ETH_LINK_SPEED_10M;
1661         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
1662         link->link_status = link_info->link_up;
1663         link->link_autoneg = link_info->auto_mode ==
1664                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
1665                 ETH_LINK_SPEED_FIXED : ETH_LINK_SPEED_AUTONEG;
1666 exit:
1667         return rc;
1668 }
1669
1670 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
1671 {
1672         int rc = 0;
1673         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1674         struct bnxt_link_info link_req;
1675         uint16_t speed;
1676
1677         if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
1678                 return 0;
1679
1680         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
1681                         bp->eth_dev->data->port_id);
1682         if (rc)
1683                 goto error;
1684
1685         memset(&link_req, 0, sizeof(link_req));
1686         link_req.link_up = link_up;
1687         if (!link_up)
1688                 goto port_phy_cfg;
1689
1690         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
1691         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
1692         if (speed == 0) {
1693                 link_req.phy_flags |=
1694                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
1695                 link_req.auto_mode =
1696                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1697                 link_req.auto_link_speed_mask =
1698                         bnxt_parse_eth_link_speed_mask(dev_conf->link_speeds);
1699         } else {
1700                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
1701                 link_req.link_speed = speed;
1702                 RTE_LOG(INFO, PMD, "Set Link Speed %x\n", speed);
1703         }
1704         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
1705         link_req.auto_pause = bp->link_info.auto_pause;
1706         link_req.force_pause = bp->link_info.force_pause;
1707
1708 port_phy_cfg:
1709         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
1710         if (rc) {
1711                 RTE_LOG(ERR, PMD,
1712                         "Set link config failed with rc %d\n", rc);
1713         }
1714
1715         rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1716 error:
1717         return rc;
1718 }
1719
1720 /* JIRA 22088 */
1721 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
1722 {
1723         struct hwrm_func_qcfg_input req = {0};
1724         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1725         int rc = 0;
1726
1727         HWRM_PREP(req, FUNC_QCFG, -1, resp);
1728         req.fid = rte_cpu_to_le_16(0xffff);
1729
1730         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1731
1732         HWRM_CHECK_RESULT;
1733
1734         /* Hard Coded.. 0xfff VLAN ID mask */
1735         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
1736
1737         switch (resp->port_partition_type) {
1738         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
1739         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
1740         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
1741                 bp->port_partition_type = resp->port_partition_type;
1742                 break;
1743         default:
1744                 bp->port_partition_type = 0;
1745                 break;
1746         }
1747
1748         return rc;
1749 }
1750
1751 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
1752                                    struct hwrm_func_qcaps_output *qcaps)
1753 {
1754         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
1755         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
1756                sizeof(qcaps->mac_address));
1757         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
1758         qcaps->max_rx_rings = fcfg->num_rx_rings;
1759         qcaps->max_tx_rings = fcfg->num_tx_rings;
1760         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
1761         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
1762         qcaps->max_vfs = 0;
1763         qcaps->first_vf_id = 0;
1764         qcaps->max_vnics = fcfg->num_vnics;
1765         qcaps->max_decap_records = 0;
1766         qcaps->max_encap_records = 0;
1767         qcaps->max_tx_wm_flows = 0;
1768         qcaps->max_tx_em_flows = 0;
1769         qcaps->max_rx_wm_flows = 0;
1770         qcaps->max_rx_em_flows = 0;
1771         qcaps->max_flow_id = 0;
1772         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
1773         qcaps->max_sp_tx_rings = 0;
1774         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
1775 }
1776
1777 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
1778 {
1779         struct hwrm_func_cfg_input req = {0};
1780         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1781         int rc;
1782
1783         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
1784                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
1785                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
1786                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
1787                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1788                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
1789                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
1790                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1791                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
1792                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
1793         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
1794         req.mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1795                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
1796         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1797                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
1798         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1799         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
1800         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
1801         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
1802         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
1803         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
1804         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
1805         req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
1806         req.fid = rte_cpu_to_le_16(0xffff);
1807
1808         HWRM_PREP(req, FUNC_CFG, -1, resp);
1809
1810         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1811         HWRM_CHECK_RESULT;
1812
1813         return rc;
1814 }
1815
1816 static void populate_vf_func_cfg_req(struct bnxt *bp,
1817                                      struct hwrm_func_cfg_input *req,
1818                                      int num_vfs)
1819 {
1820         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
1821                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
1822                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
1823                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
1824                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1825                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
1826                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
1827                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1828                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
1829                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
1830
1831         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1832                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
1833         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1834                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
1835         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
1836                                                 (num_vfs + 1));
1837         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
1838         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
1839                                                (num_vfs + 1));
1840         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
1841         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
1842         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
1843         /* TODO: For now, do not support VMDq/RFS on VFs. */
1844         req->num_vnics = rte_cpu_to_le_16(1);
1845         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
1846                                                  (num_vfs + 1));
1847 }
1848
1849 static void add_random_mac_if_needed(struct bnxt *bp,
1850                                      struct hwrm_func_cfg_input *cfg_req,
1851                                      int vf)
1852 {
1853         struct ether_addr mac;
1854
1855         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
1856                 return;
1857
1858         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
1859                 cfg_req->enables |=
1860                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1861                 eth_random_addr(cfg_req->dflt_mac_addr);
1862                 bp->pf.vf_info[vf].random_mac = true;
1863         } else {
1864                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
1865         }
1866 }
1867
1868 static void reserve_resources_from_vf(struct bnxt *bp,
1869                                       struct hwrm_func_cfg_input *cfg_req,
1870                                       int vf)
1871 {
1872         struct hwrm_func_qcaps_input req = {0};
1873         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1874         int rc;
1875
1876         /* Get the actual allocated values now */
1877         HWRM_PREP(req, FUNC_QCAPS, -1, resp);
1878         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1879         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1880
1881         if (rc) {
1882                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
1883                 copy_func_cfg_to_qcaps(cfg_req, resp);
1884         } else if (resp->error_code) {
1885                 rc = rte_le_to_cpu_16(resp->error_code);
1886                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
1887                 copy_func_cfg_to_qcaps(cfg_req, resp);
1888         }
1889
1890         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
1891         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
1892         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
1893         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
1894         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
1895         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
1896         /*
1897          * TODO: While not supporting VMDq with VFs, max_vnics is always
1898          * forced to 1 in this case
1899          */
1900         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
1901         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
1902 }
1903
1904 static int update_pf_resource_max(struct bnxt *bp)
1905 {
1906         struct hwrm_func_qcfg_input req = {0};
1907         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1908         int rc;
1909
1910         /* And copy the allocated numbers into the pf struct */
1911         HWRM_PREP(req, FUNC_QCFG, -1, resp);
1912         req.fid = rte_cpu_to_le_16(0xffff);
1913         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1914         HWRM_CHECK_RESULT;
1915
1916         /* Only TX ring value reflects actual allocation? TODO */
1917         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
1918         bp->pf.evb_mode = resp->evb_mode;
1919
1920         return rc;
1921 }
1922
1923 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
1924 {
1925         int rc;
1926
1927         if (!BNXT_PF(bp)) {
1928                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
1929                 return -1;
1930         }
1931
1932         rc = bnxt_hwrm_func_qcaps(bp);
1933         if (rc)
1934                 return rc;
1935
1936         bp->pf.func_cfg_flags &=
1937                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
1938                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
1939         bp->pf.func_cfg_flags |=
1940                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
1941         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
1942         return rc;
1943 }
1944
1945 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
1946 {
1947         struct hwrm_func_cfg_input req = {0};
1948         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1949         int i;
1950         size_t sz;
1951         int rc = 0;
1952         size_t req_buf_sz;
1953
1954         if (!BNXT_PF(bp)) {
1955                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
1956                 return -1;
1957         }
1958
1959         rc = bnxt_hwrm_func_qcaps(bp);
1960
1961         if (rc)
1962                 return rc;
1963
1964         bp->pf.active_vfs = num_vfs;
1965
1966         /*
1967          * First, configure the PF to only use one TX ring.  This ensures that
1968          * there are enough rings for all VFs.
1969          *
1970          * If we don't do this, when we call func_alloc() later, we will lock
1971          * extra rings to the PF that won't be available during func_cfg() of
1972          * the VFs.
1973          *
1974          * This has been fixed with firmware versions above 20.6.54
1975          */
1976         bp->pf.func_cfg_flags &=
1977                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
1978                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
1979         bp->pf.func_cfg_flags |=
1980                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
1981         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
1982         if (rc)
1983                 return rc;
1984
1985         /*
1986          * Now, create and register a buffer to hold forwarded VF requests
1987          */
1988         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
1989         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
1990                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
1991         if (bp->pf.vf_req_buf == NULL) {
1992                 rc = -ENOMEM;
1993                 goto error_free;
1994         }
1995         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
1996                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
1997         for (i = 0; i < num_vfs; i++)
1998                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
1999                                         (i * HWRM_MAX_REQ_LEN);
2000
2001         rc = bnxt_hwrm_func_buf_rgtr(bp);
2002         if (rc)
2003                 goto error_free;
2004
2005         populate_vf_func_cfg_req(bp, &req, num_vfs);
2006
2007         bp->pf.active_vfs = 0;
2008         for (i = 0; i < num_vfs; i++) {
2009                 add_random_mac_if_needed(bp, &req, i);
2010
2011                 HWRM_PREP(req, FUNC_CFG, -1, resp);
2012                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2013                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2014                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2015
2016                 /* Clear enable flag for next pass */
2017                 req.enables &= ~rte_cpu_to_le_32(
2018                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2019
2020                 if (rc || resp->error_code) {
2021                         RTE_LOG(ERR, PMD,
2022                                 "Failed to initizlie VF %d\n", i);
2023                         RTE_LOG(ERR, PMD,
2024                                 "Not all VFs available. (%d, %d)\n",
2025                                 rc, resp->error_code);
2026                         break;
2027                 }
2028
2029                 reserve_resources_from_vf(bp, &req, i);
2030                 bp->pf.active_vfs++;
2031         }
2032
2033         /*
2034          * Now configure the PF to use "the rest" of the resources
2035          * We're using STD_TX_RING_MODE here though which will limit the TX
2036          * rings.  This will allow QoS to function properly.  Not setting this
2037          * will cause PF rings to break bandwidth settings.
2038          */
2039         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2040         if (rc)
2041                 goto error_free;
2042
2043         rc = update_pf_resource_max(bp);
2044         if (rc)
2045                 goto error_free;
2046
2047         return rc;
2048
2049 error_free:
2050         bnxt_hwrm_func_buf_unrgtr(bp);
2051         return rc;
2052 }
2053
2054
2055 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2056 {
2057         int rc = 0;
2058         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2059         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2060
2061         HWRM_PREP(req, FUNC_BUF_RGTR, -1, resp);
2062
2063         req.req_buf_num_pages = rte_cpu_to_le_16(1);
2064         req.req_buf_page_size = rte_cpu_to_le_16(
2065                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2066         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2067         req.req_buf_page_addr[0] =
2068                 rte_cpu_to_le_64(rte_mem_virt2phy(bp->pf.vf_req_buf));
2069         if (req.req_buf_page_addr[0] == 0) {
2070                 RTE_LOG(ERR, PMD,
2071                         "unable to map buffer address to physical memory\n");
2072                 return -ENOMEM;
2073         }
2074
2075         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2076
2077         HWRM_CHECK_RESULT;
2078
2079         return rc;
2080 }
2081
2082 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2083 {
2084         int rc = 0;
2085         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2086         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2087
2088         HWRM_PREP(req, FUNC_BUF_UNRGTR, -1, resp);
2089
2090         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2091
2092         HWRM_CHECK_RESULT;
2093
2094         return rc;
2095 }
2096
2097 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2098 {
2099         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2100         struct hwrm_func_cfg_input req = {0};
2101         int rc;
2102
2103         HWRM_PREP(req, FUNC_CFG, -1, resp);
2104         req.fid = rte_cpu_to_le_16(0xffff);
2105         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2106         req.enables = rte_cpu_to_le_32(
2107                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2108         req.async_event_cr = rte_cpu_to_le_16(
2109                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2110         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2111         HWRM_CHECK_RESULT;
2112
2113         return rc;
2114 }
2115
2116 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2117 {
2118         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2119         struct hwrm_func_vf_cfg_input req = {0};
2120         int rc;
2121
2122         HWRM_PREP(req, FUNC_VF_CFG, -1, resp);
2123         req.enables = rte_cpu_to_le_32(
2124                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2125         req.async_event_cr = rte_cpu_to_le_16(
2126                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2127         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2128         HWRM_CHECK_RESULT;
2129
2130         return rc;
2131 }
2132
2133 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2134                               void *encaped, size_t ec_size)
2135 {
2136         int rc = 0;
2137         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2138         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2139
2140         if (ec_size > sizeof(req.encap_request))
2141                 return -1;
2142
2143         HWRM_PREP(req, REJECT_FWD_RESP, -1, resp);
2144
2145         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2146         memcpy(req.encap_request, encaped, ec_size);
2147
2148         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2149
2150         HWRM_CHECK_RESULT;
2151
2152         return rc;
2153 }
2154
2155 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2156                                        struct ether_addr *mac)
2157 {
2158         struct hwrm_func_qcfg_input req = {0};
2159         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2160         int rc;
2161
2162         HWRM_PREP(req, FUNC_QCFG, -1, resp);
2163         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2164         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2165
2166         HWRM_CHECK_RESULT;
2167
2168         memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2169         return rc;
2170 }
2171
2172 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2173                             void *encaped, size_t ec_size)
2174 {
2175         int rc = 0;
2176         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2177         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2178
2179         if (ec_size > sizeof(req.encap_request))
2180                 return -1;
2181
2182         HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
2183
2184         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2185         memcpy(req.encap_request, encaped, ec_size);
2186
2187         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2188
2189         HWRM_CHECK_RESULT;
2190
2191         return rc;
2192 }