drivers/net/bnxt/bnxt_hwrm.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <unistd.h>
  35
  36 #include <rte_byteorder.h>
  37 #include <rte_common.h>
  38 #include <rte_cycles.h>
  39 #include <rte_malloc.h>
  40 #include <rte_memzone.h>
  41 #include <rte_version.h>
  42
  43 #include "bnxt.h"
  44 #include "bnxt_cpr.h"
  45 #include "bnxt_filter.h"
  46 #include "bnxt_hwrm.h"
  47 #include "bnxt_rxq.h"
  48 #include "bnxt_rxr.h"
  49 #include "bnxt_ring.h"
  50 #include "bnxt_txq.h"
  51 #include "bnxt_txr.h"
  52 #include "bnxt_vnic.h"
  53 #include "hsi_struct_def_dpdk.h"
  54
  55 #include <rte_io.h>
  56
  57 #define HWRM_CMD_TIMEOUT                10000
  58
  59 struct bnxt_plcmodes_cfg {
  60         uint32_t        flags;
  61         uint16_t        jumbo_thresh;
  62         uint16_t        hds_offset;
  63         uint16_t        hds_threshold;
  64 };
  65
  66 static int page_getenum(size_t size)
  67 {
  68         if (size <= 1 << 4)
  69                 return 4;
  70         if (size <= 1 << 12)
  71                 return 12;
  72         if (size <= 1 << 13)
  73                 return 13;
  74         if (size <= 1 << 16)
  75                 return 16;
  76         if (size <= 1 << 21)
  77                 return 21;
  78         if (size <= 1 << 22)
  79                 return 22;
  80         if (size <= 1 << 30)
  81                 return 30;
  82         RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
  83         return sizeof(void *) * 8 - 1;
  84 }
  85
  86 static int page_roundup(size_t size)
  87 {
  88         return 1 << page_getenum(size);
  89 }
  90
  91 /*
  92  * HWRM Functions (sent to HWRM)
  93  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  94  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  95  * command was failed by the ChiMP.
  96  */
  97
  98 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  99                                         uint32_t msg_len)
 100 {
 101         unsigned int i;
 102         struct input *req = msg;
 103         struct output *resp = bp->hwrm_cmd_resp_addr;
 104         uint32_t *data = msg;
 105         uint8_t *bar;
 106         uint8_t *valid;
 107         uint16_t max_req_len = bp->max_req_len;
 108         struct hwrm_short_input short_input = { 0 };
 109
 110         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->max_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 /* Sync memory write before updating doorbell */
 127                 rte_wmb();
 128
 129                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 130         }
 131
 132         /* Write request msg to hwrm channel */
 133         for (i = 0; i < msg_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + i;
 135                 rte_write32(*data, bar);
 136                 data++;
 137         }
 138
 139         /* Zero the rest of the request space */
 140         for (; i < max_req_len; i += 4) {
 141                 bar = (uint8_t *)bp->bar0 + i;
 142                 rte_write32(0, bar);
 143         }
 144
 145         /* Ring channel doorbell */
 146         bar = (uint8_t *)bp->bar0 + 0x100;
 147         rte_write32(1, bar);
 148
 149         /* Poll for the valid bit */
 150         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 151                 /* Sanity check on the resp->resp_len */
 152                 rte_rmb();
 153                 if (resp->resp_len && resp->resp_len <=
 154                                 bp->max_resp_len) {
 155                         /* Last byte of resp contains the valid key */
 156                         valid = (uint8_t *)resp + resp->resp_len - 1;
 157                         if (*valid == HWRM_RESP_VALID_KEY)
 158                                 break;
 159                 }
 160                 rte_delay_us(600);
 161         }
 162
 163         if (i >= HWRM_CMD_TIMEOUT) {
 164                 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
 165                         req->req_type);
 166                 goto err_ret;
 167         }
 168         return 0;
 169
 170 err_ret:
 171         return -1;
 172 }
 173
 174 /*
 175  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 176  * spinlock, and does initial processing.
 177  *
 178  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 179  * releases the spinlock only if it returns.  If the regular int return codes
 180  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 181  * directly, rather it should be copied and modified to suit the function.
 182  *
 183  * HWRM_UNLOCK() must be called after all response processing is completed.
 184  */
 185 #define HWRM_PREP(req, type) do { \
 186         rte_spinlock_lock(&bp->hwrm_lock); \
 187         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 188         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 189         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 190         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 191         req.target_id = rte_cpu_to_le_16(0xffff); \
 192         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 193 } while (0)
 194
 195 #define HWRM_CHECK_RESULT() do {\
 196         if (rc) { \
 197                 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
 198                         __func__, rc); \
 199                 rte_spinlock_unlock(&bp->hwrm_lock); \
 200                 return rc; \
 201         } \
 202         if (resp->error_code) { \
 203                 rc = rte_le_to_cpu_16(resp->error_code); \
 204                 if (resp->resp_len >= 16) { \
 205                         struct hwrm_err_output *tmp_hwrm_err_op = \
 206                                                 (void *)resp; \
 207                         RTE_LOG(ERR, PMD, \
 208                                 "%s error %d:%d:%08x:%04x\n", \
 209                                 __func__, \
 210                                 rc, tmp_hwrm_err_op->cmd_err, \
 211                                 rte_le_to_cpu_32(\
 212                                         tmp_hwrm_err_op->opaque_0), \
 213                                 rte_le_to_cpu_16(\
 214                                         tmp_hwrm_err_op->opaque_1)); \
 215                 } \
 216                 else { \
 217                         RTE_LOG(ERR, PMD, \
 218                                 "%s error %d\n", __func__, rc); \
 219                 } \
 220                 rte_spinlock_unlock(&bp->hwrm_lock); \
 221                 return rc; \
 222         } \
 223 } while (0)
 224
 225 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 226
 227 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 228 {
 229         int rc = 0;
 230         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 231         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 232
 233         HWRM_PREP(req, CFA_L2_SET_RX_MASK);
 234         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 235         req.mask = 0;
 236
 237         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 238
 239         HWRM_CHECK_RESULT();
 240         HWRM_UNLOCK();
 241
 242         return rc;
 243 }
 244
 245 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 246                                  struct bnxt_vnic_info *vnic,
 247                                  uint16_t vlan_count,
 248                                  struct bnxt_vlan_table_entry *vlan_table)
 249 {
 250         int rc = 0;
 251         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 252         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 253         uint32_t mask = 0;
 254
 255         HWRM_PREP(req, CFA_L2_SET_RX_MASK);
 256         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 257
 258         /* FIXME add multicast flag, when multicast adding options is supported
 259          * by ethtool.
 260          */
 261         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 262                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 263         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 264                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 265         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 266                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 267         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 268                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 269         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 270                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 271         if (vnic->mc_addr_cnt) {
 272                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 273                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 274                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 275         }
 276         if (vlan_table) {
 277                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 278                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 279                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 280                          rte_mem_virt2phy(vlan_table));
 281                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 282         }
 283         req.mask = rte_cpu_to_le_32(mask);
 284
 285         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 286
 287         HWRM_CHECK_RESULT();
 288         HWRM_UNLOCK();
 289
 290         return rc;
 291 }
 292
 293 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 294                         uint16_t vlan_count,
 295                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 296 {
 297         int rc = 0;
 298         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 299         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 300                                                 bp->hwrm_cmd_resp_addr;
 301
 302         /*
 303          * Older HWRM versions did not support this command, and the set_rx_mask
 304          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 305          * removed from set_rx_mask call, and this command was added.
 306          *
 307          * This command is also present from 1.7.8.11 and higher,
 308          * as well as 1.7.8.0
 309          */
 310         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 311                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 312                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 313                                         (11)))
 314                                 return 0;
 315                 }
 316         }
 317         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG);
 318         req.fid = rte_cpu_to_le_16(fid);
 319
 320         req.vlan_tag_mask_tbl_addr =
 321                 rte_cpu_to_le_64(rte_mem_virt2phy(vlan_table));
 322         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 323
 324         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 325
 326         HWRM_CHECK_RESULT();
 327         HWRM_UNLOCK();
 328
 329         return rc;
 330 }
 331
 332 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 333                            struct bnxt_filter_info *filter)
 334 {
 335         int rc = 0;
 336         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 337         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 338
 339         if (filter->fw_l2_filter_id == UINT64_MAX)
 340                 return 0;
 341
 342         HWRM_PREP(req, CFA_L2_FILTER_FREE);
 343
 344         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 345
 346         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 347
 348         HWRM_CHECK_RESULT();
 349         HWRM_UNLOCK();
 350
 351         filter->fw_l2_filter_id = -1;
 352
 353         return 0;
 354 }
 355
 356 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 357                          uint16_t dst_id,
 358                          struct bnxt_filter_info *filter)
 359 {
 360         int rc = 0;
 361         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 362         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 363         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 364         const struct rte_eth_vmdq_rx_conf *conf =
 365                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 366         uint32_t enables = 0;
 367         uint16_t j = dst_id - 1;
 368
 369         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 370         if (conf->pool_map[j].pools & (1UL << j)) {
 371                 RTE_LOG(DEBUG, PMD,
 372                         "Add vlan %u to vmdq pool %u\n",
 373                         conf->pool_map[j].vlan_id, j);
 374
 375                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 376                 filter->enables |=
 377                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 378                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 379         }
 380
 381         if (filter->fw_l2_filter_id != UINT64_MAX)
 382                 bnxt_hwrm_clear_l2_filter(bp, filter);
 383
 384         HWRM_PREP(req, CFA_L2_FILTER_ALLOC);
 385
 386         req.flags = rte_cpu_to_le_32(filter->flags);
 387
 388         enables = filter->enables |
 389               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 390         req.dst_id = rte_cpu_to_le_16(dst_id);
 391
 392         if (enables &
 393             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 394                 memcpy(req.l2_addr, filter->l2_addr,
 395                        ETHER_ADDR_LEN);
 396         if (enables &
 397             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 398                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 399                        ETHER_ADDR_LEN);
 400         if (enables &
 401             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 402                 req.l2_ovlan = filter->l2_ovlan;
 403         if (enables &
 404             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 405                 req.l2_ovlan = filter->l2_ivlan;
 406         if (enables &
 407             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 408                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 409         if (enables &
 410             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 411                 req.l2_ovlan_mask = filter->l2_ivlan_mask;
 412         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 413                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 414         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 415                 req.src_type = filter->src_type;
 416
 417         req.enables = rte_cpu_to_le_32(enables);
 418
 419         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 420
 421         HWRM_CHECK_RESULT();
 422
 423         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 424         HWRM_UNLOCK();
 425
 426         return rc;
 427 }
 428
 429 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 430 {
 431         int rc = 0;
 432         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 433         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 434         uint16_t new_max_vfs;
 435         int i;
 436
 437         HWRM_PREP(req, FUNC_QCAPS);
 438
 439         req.fid = rte_cpu_to_le_16(0xffff);
 440
 441         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 442
 443         HWRM_CHECK_RESULT();
 444
 445         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 446         if (BNXT_PF(bp)) {
 447                 bp->pf.port_id = resp->port_id;
 448                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 449                 new_max_vfs = bp->pdev->max_vfs;
 450                 if (new_max_vfs != bp->pf.max_vfs) {
 451                         if (bp->pf.vf_info)
 452                                 rte_free(bp->pf.vf_info);
 453                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 454                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 455                         bp->pf.max_vfs = new_max_vfs;
 456                         for (i = 0; i < new_max_vfs; i++) {
 457                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 458                                 bp->pf.vf_info[i].vlan_table =
 459                                         rte_zmalloc("VF VLAN table",
 460                                                     getpagesize(),
 461                                                     getpagesize());
 462                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 463                                         RTE_LOG(ERR, PMD,
 464                                         "Fail to alloc VLAN table for VF %d\n",
 465                                         i);
 466                                 else
 467                                         rte_mem_lock_page(
 468                                                 bp->pf.vf_info[i].vlan_table);
 469                                 bp->pf.vf_info[i].vlan_as_table =
 470                                         rte_zmalloc("VF VLAN AS table",
 471                                                     getpagesize(),
 472                                                     getpagesize());
 473                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 474                                         RTE_LOG(ERR, PMD,
 475                                         "Alloc VLAN AS table for VF %d fail\n",
 476                                         i);
 477                                 else
 478                                         rte_mem_lock_page(
 479                                                bp->pf.vf_info[i].vlan_as_table);
 480                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 481                         }
 482                 }
 483         }
 484
 485         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 486         memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
 487         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 488         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 489         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 490         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 491         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 492         /* TODO: For now, do not support VMDq/RFS on VFs. */
 493         if (BNXT_PF(bp)) {
 494                 if (bp->pf.max_vfs)
 495                         bp->max_vnics = 1;
 496                 else
 497                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 498         } else {
 499                 bp->max_vnics = 1;
 500         }
 501         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 502         if (BNXT_PF(bp))
 503                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 504         HWRM_UNLOCK();
 505
 506         return rc;
 507 }
 508
 509 int bnxt_hwrm_func_reset(struct bnxt *bp)
 510 {
 511         int rc = 0;
 512         struct hwrm_func_reset_input req = {.req_type = 0 };
 513         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 514
 515         HWRM_PREP(req, FUNC_RESET);
 516
 517         req.enables = rte_cpu_to_le_32(0);
 518
 519         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 520
 521         HWRM_CHECK_RESULT();
 522         HWRM_UNLOCK();
 523
 524         return rc;
 525 }
 526
 527 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 528 {
 529         int rc;
 530         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 531         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 532
 533         if (bp->flags & BNXT_FLAG_REGISTERED)
 534                 return 0;
 535
 536         HWRM_PREP(req, FUNC_DRV_RGTR);
 537         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 538                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 539         req.ver_maj = RTE_VER_YEAR;
 540         req.ver_min = RTE_VER_MONTH;
 541         req.ver_upd = RTE_VER_MINOR;
 542
 543         if (BNXT_PF(bp)) {
 544                 req.enables |= rte_cpu_to_le_32(
 545                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
 546                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 547                        RTE_MIN(sizeof(req.vf_req_fwd),
 548                                sizeof(bp->pf.vf_req_fwd)));
 549         }
 550
 551         req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1);   /* TODO: Use MACRO */
 552         memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
 553
 554         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 555
 556         HWRM_CHECK_RESULT();
 557         HWRM_UNLOCK();
 558
 559         bp->flags |= BNXT_FLAG_REGISTERED;
 560
 561         return rc;
 562 }
 563
 564 int bnxt_hwrm_ver_get(struct bnxt *bp)
 565 {
 566         int rc = 0;
 567         struct hwrm_ver_get_input req = {.req_type = 0 };
 568         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 569         uint32_t my_version;
 570         uint32_t fw_version;
 571         uint16_t max_resp_len;
 572         char type[RTE_MEMZONE_NAMESIZE];
 573         uint32_t dev_caps_cfg;
 574
 575         bp->max_req_len = HWRM_MAX_REQ_LEN;
 576         HWRM_PREP(req, VER_GET);
 577
 578         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 579         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 580         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 581
 582         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 583
 584         HWRM_CHECK_RESULT();
 585
 586         RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
 587                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
 588                 resp->hwrm_intf_upd,
 589                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
 590         bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
 591                         (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
 592         RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
 593                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 594
 595         my_version = HWRM_VERSION_MAJOR << 16;
 596         my_version |= HWRM_VERSION_MINOR << 8;
 597         my_version |= HWRM_VERSION_UPDATE;
 598
 599         fw_version = resp->hwrm_intf_maj << 16;
 600         fw_version |= resp->hwrm_intf_min << 8;
 601         fw_version |= resp->hwrm_intf_upd;
 602
 603         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
 604                 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
 605                 rc = -EINVAL;
 606                 goto error;
 607         }
 608
 609         if (my_version != fw_version) {
 610                 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
 611                 if (my_version < fw_version) {
 612                         RTE_LOG(INFO, PMD,
 613                                 "Firmware API version is newer than driver.\n");
 614                         RTE_LOG(INFO, PMD,
 615                                 "The driver may be missing features.\n");
 616                 } else {
 617                         RTE_LOG(INFO, PMD,
 618                                 "Firmware API version is older than driver.\n");
 619                         RTE_LOG(INFO, PMD,
 620                                 "Not all driver features may be functional.\n");
 621                 }
 622         }
 623
 624         if (bp->max_req_len > resp->max_req_win_len) {
 625                 RTE_LOG(ERR, PMD, "Unsupported request length\n");
 626                 rc = -EINVAL;
 627         }
 628         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 629         max_resp_len = resp->max_resp_len;
 630         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 631
 632         if (bp->max_resp_len != max_resp_len) {
 633                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 634                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 635                         bp->pdev->addr.devid, bp->pdev->addr.function);
 636
 637                 rte_free(bp->hwrm_cmd_resp_addr);
 638
 639                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 640                 if (bp->hwrm_cmd_resp_addr == NULL) {
 641                         rc = -ENOMEM;
 642                         goto error;
 643                 }
 644                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 645                 bp->hwrm_cmd_resp_dma_addr =
 646                         rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
 647                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 648                         RTE_LOG(ERR, PMD,
 649                         "Unable to map response buffer to physical memory.\n");
 650                         rc = -ENOMEM;
 651                         goto error;
 652                 }
 653                 bp->max_resp_len = max_resp_len;
 654         }
 655
 656         if ((dev_caps_cfg &
 657                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 658             (dev_caps_cfg &
 659              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
 660                 RTE_LOG(DEBUG, PMD, "Short command supported\n");
 661
 662                 rte_free(bp->hwrm_short_cmd_req_addr);
 663
 664                 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
 665                                                         bp->max_req_len, 0);
 666                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 667                         rc = -ENOMEM;
 668                         goto error;
 669                 }
 670                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 671                 bp->hwrm_short_cmd_req_dma_addr =
 672                         rte_mem_virt2phy(bp->hwrm_short_cmd_req_addr);
 673                 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
 674                         rte_free(bp->hwrm_short_cmd_req_addr);
 675                         RTE_LOG(ERR, PMD,
 676                                 "Unable to map buffer to physical memory.\n");
 677                         rc = -ENOMEM;
 678                         goto error;
 679                 }
 680
 681                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 682         }
 683
 684 error:
 685         HWRM_UNLOCK();
 686         return rc;
 687 }
 688
 689 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 690 {
 691         int rc;
 692         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 693         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 694
 695         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 696                 return 0;
 697
 698         HWRM_PREP(req, FUNC_DRV_UNRGTR);
 699         req.flags = flags;
 700
 701         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 702
 703         HWRM_CHECK_RESULT();
 704         HWRM_UNLOCK();
 705
 706         bp->flags &= ~BNXT_FLAG_REGISTERED;
 707
 708         return rc;
 709 }
 710
 711 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 712 {
 713         int rc = 0;
 714         struct hwrm_port_phy_cfg_input req = {0};
 715         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 716         uint32_t enables = 0;
 717         uint32_t link_speed_mask =
 718                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 719
 720         HWRM_PREP(req, PORT_PHY_CFG);
 721
 722         if (conf->link_up) {
 723                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 724                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 725                 /*
 726                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 727                  * any auto mode, even "none".
 728                  */
 729                 if (!conf->link_speed) {
 730                         req.auto_mode = conf->auto_mode;
 731                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 732                         if (conf->auto_mode ==
 733                             HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK) {
 734                                 req.auto_link_speed_mask =
 735                                         conf->auto_link_speed_mask;
 736                                 enables |= link_speed_mask;
 737                         }
 738                         if (bp->link_info.auto_link_speed) {
 739                                 req.auto_link_speed =
 740                                         bp->link_info.auto_link_speed;
 741                                 enables |=
 742                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
 743                         }
 744                 }
 745                 req.auto_duplex = conf->duplex;
 746                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 747                 req.auto_pause = conf->auto_pause;
 748                 req.force_pause = conf->force_pause;
 749                 /* Set force_pause if there is no auto or if there is a force */
 750                 if (req.auto_pause && !req.force_pause)
 751                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 752                 else
 753                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 754
 755                 req.enables = rte_cpu_to_le_32(enables);
 756         } else {
 757                 req.flags =
 758                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
 759                 RTE_LOG(INFO, PMD, "Force Link Down\n");
 760         }
 761
 762         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 763
 764         HWRM_CHECK_RESULT();
 765         HWRM_UNLOCK();
 766
 767         return rc;
 768 }
 769
 770 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
 771                                    struct bnxt_link_info *link_info)
 772 {
 773         int rc = 0;
 774         struct hwrm_port_phy_qcfg_input req = {0};
 775         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 776
 777         HWRM_PREP(req, PORT_PHY_QCFG);
 778
 779         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 780
 781         HWRM_CHECK_RESULT();
 782
 783         link_info->phy_link_status = resp->link;
 784         link_info->link_up =
 785                 (link_info->phy_link_status ==
 786                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
 787         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
 788         link_info->duplex = resp->duplex_cfg;
 789         link_info->pause = resp->pause;
 790         link_info->auto_pause = resp->auto_pause;
 791         link_info->force_pause = resp->force_pause;
 792         link_info->auto_mode = resp->auto_mode;
 793
 794         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
 795         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
 796         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
 797         link_info->phy_ver[0] = resp->phy_maj;
 798         link_info->phy_ver[1] = resp->phy_min;
 799         link_info->phy_ver[2] = resp->phy_bld;
 800
 801         HWRM_UNLOCK();
 802
 803         return rc;
 804 }
 805
 806 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 807 {
 808         int rc = 0;
 809         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 810         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 811
 812         HWRM_PREP(req, QUEUE_QPORTCFG);
 813
 814         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 815
 816         HWRM_CHECK_RESULT();
 817
 818 #define GET_QUEUE_INFO(x) \
 819         bp->cos_queue[x].id = resp->queue_id##x; \
 820         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 821
 822         GET_QUEUE_INFO(0);
 823         GET_QUEUE_INFO(1);
 824         GET_QUEUE_INFO(2);
 825         GET_QUEUE_INFO(3);
 826         GET_QUEUE_INFO(4);
 827         GET_QUEUE_INFO(5);
 828         GET_QUEUE_INFO(6);
 829         GET_QUEUE_INFO(7);
 830
 831         HWRM_UNLOCK();
 832
 833         return rc;
 834 }
 835
 836 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
 837                          struct bnxt_ring *ring,
 838                          uint32_t ring_type, uint32_t map_index,
 839                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
 840 {
 841         int rc = 0;
 842         uint32_t enables = 0;
 843         struct hwrm_ring_alloc_input req = {.req_type = 0 };
 844         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 845
 846         HWRM_PREP(req, RING_ALLOC);
 847
 848         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
 849         req.fbo = rte_cpu_to_le_32(0);
 850         /* Association of ring index with doorbell index */
 851         req.logical_id = rte_cpu_to_le_16(map_index);
 852         req.length = rte_cpu_to_le_32(ring->ring_size);
 853
 854         switch (ring_type) {
 855         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
 856                 req.queue_id = bp->cos_queue[0].id;
 857                 /* FALLTHROUGH */
 858         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
 859                 req.ring_type = ring_type;
 860                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
 861                 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
 862                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
 863                         enables |=
 864                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
 865                 break;
 866         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
 867                 req.ring_type = ring_type;
 868                 /*
 869                  * TODO: Some HWRM versions crash with
 870                  * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
 871                  */
 872                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
 873                 break;
 874         default:
 875                 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
 876                         ring_type);
 877                 HWRM_UNLOCK();
 878                 return -1;
 879         }
 880         req.enables = rte_cpu_to_le_32(enables);
 881
 882         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 883
 884         if (rc || resp->error_code) {
 885                 if (rc == 0 && resp->error_code)
 886                         rc = rte_le_to_cpu_16(resp->error_code);
 887                 switch (ring_type) {
 888                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 889                         RTE_LOG(ERR, PMD,
 890                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
 891                         HWRM_UNLOCK();
 892                         return rc;
 893                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 894                         RTE_LOG(ERR, PMD,
 895                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
 896                         HWRM_UNLOCK();
 897                         return rc;
 898                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 899                         RTE_LOG(ERR, PMD,
 900                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
 901                         HWRM_UNLOCK();
 902                         return rc;
 903                 default:
 904                         RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
 905                         HWRM_UNLOCK();
 906                         return rc;
 907                 }
 908         }
 909
 910         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
 911         HWRM_UNLOCK();
 912         return rc;
 913 }
 914
 915 int bnxt_hwrm_ring_free(struct bnxt *bp,
 916                         struct bnxt_ring *ring, uint32_t ring_type)
 917 {
 918         int rc;
 919         struct hwrm_ring_free_input req = {.req_type = 0 };
 920         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
 921
 922         HWRM_PREP(req, RING_FREE);
 923
 924         req.ring_type = ring_type;
 925         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
 926
 927         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 928
 929         if (rc || resp->error_code) {
 930                 if (rc == 0 && resp->error_code)
 931                         rc = rte_le_to_cpu_16(resp->error_code);
 932                 HWRM_UNLOCK();
 933
 934                 switch (ring_type) {
 935                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 936                         RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
 937                                 rc);
 938                         return rc;
 939                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 940                         RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
 941                                 rc);
 942                         return rc;
 943                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 944                         RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
 945                                 rc);
 946                         return rc;
 947                 default:
 948                         RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
 949                         return rc;
 950                 }
 951         }
 952         HWRM_UNLOCK();
 953         return 0;
 954 }
 955
 956 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
 957 {
 958         int rc = 0;
 959         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
 960         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 961
 962         HWRM_PREP(req, RING_GRP_ALLOC);
 963
 964         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
 965         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
 966         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
 967         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
 968
 969         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 970
 971         HWRM_CHECK_RESULT();
 972
 973         bp->grp_info[idx].fw_grp_id =
 974             rte_le_to_cpu_16(resp->ring_group_id);
 975
 976         HWRM_UNLOCK();
 977
 978         return rc;
 979 }
 980
 981 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
 982 {
 983         int rc;
 984         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
 985         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
 986
 987         HWRM_PREP(req, RING_GRP_FREE);
 988
 989         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
 990
 991         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 992
 993         HWRM_CHECK_RESULT();
 994         HWRM_UNLOCK();
 995
 996         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
 997         return rc;
 998 }
 999
1000 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1001 {
1002         int rc = 0;
1003         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1004         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1005
1006         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1007                 return rc;
1008
1009         HWRM_PREP(req, STAT_CTX_CLR_STATS);
1010
1011         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1012
1013         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1014
1015         HWRM_CHECK_RESULT();
1016         HWRM_UNLOCK();
1017
1018         return rc;
1019 }
1020
1021 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1022                                 unsigned int idx __rte_unused)
1023 {
1024         int rc;
1025         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1026         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1027
1028         HWRM_PREP(req, STAT_CTX_ALLOC);
1029
1030         req.update_period_ms = rte_cpu_to_le_32(0);
1031
1032         req.stats_dma_addr =
1033             rte_cpu_to_le_64(cpr->hw_stats_map);
1034
1035         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1036
1037         HWRM_CHECK_RESULT();
1038
1039         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1040
1041         HWRM_UNLOCK();
1042         bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
1043
1044         return rc;
1045 }
1046
1047 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1048                                 unsigned int idx __rte_unused)
1049 {
1050         int rc;
1051         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1052         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1053
1054         HWRM_PREP(req, STAT_CTX_FREE);
1055
1056         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1057
1058         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1059
1060         HWRM_CHECK_RESULT();
1061         HWRM_UNLOCK();
1062
1063         return rc;
1064 }
1065
1066 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1067 {
1068         int rc = 0, i, j;
1069         struct hwrm_vnic_alloc_input req = { 0 };
1070         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1071
1072         /* map ring groups to this vnic */
1073         RTE_LOG(DEBUG, PMD, "Alloc VNIC. Start %x, End %x\n",
1074                 vnic->start_grp_id, vnic->end_grp_id);
1075         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
1076                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1077         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1078         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1079         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1080         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1081         vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1082                                 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1083         HWRM_PREP(req, VNIC_ALLOC);
1084
1085         if (vnic->func_default)
1086                 req.flags = HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT;
1087         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1088
1089         HWRM_CHECK_RESULT();
1090
1091         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1092         HWRM_UNLOCK();
1093         RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1094         return rc;
1095 }
1096
1097 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1098                                         struct bnxt_vnic_info *vnic,
1099                                         struct bnxt_plcmodes_cfg *pmode)
1100 {
1101         int rc = 0;
1102         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1103         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1104
1105         HWRM_PREP(req, VNIC_PLCMODES_QCFG);
1106
1107         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1108
1109         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1110
1111         HWRM_CHECK_RESULT();
1112
1113         pmode->flags = rte_le_to_cpu_32(resp->flags);
1114         /* dflt_vnic bit doesn't exist in the _cfg command */
1115         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1116         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1117         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1118         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1119
1120         HWRM_UNLOCK();
1121
1122         return rc;
1123 }
1124
1125 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1126                                        struct bnxt_vnic_info *vnic,
1127                                        struct bnxt_plcmodes_cfg *pmode)
1128 {
1129         int rc = 0;
1130         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1131         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1132
1133         HWRM_PREP(req, VNIC_PLCMODES_CFG);
1134
1135         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1136         req.flags = rte_cpu_to_le_32(pmode->flags);
1137         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1138         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1139         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1140         req.enables = rte_cpu_to_le_32(
1141             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1142             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1143             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1144         );
1145
1146         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1147
1148         HWRM_CHECK_RESULT();
1149         HWRM_UNLOCK();
1150
1151         return rc;
1152 }
1153
1154 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1155 {
1156         int rc = 0;
1157         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1158         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1159         uint32_t ctx_enable_flag = 0;
1160         struct bnxt_plcmodes_cfg pmodes;
1161
1162         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1163                 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1164                 return rc;
1165         }
1166
1167         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1168         if (rc)
1169                 return rc;
1170
1171         HWRM_PREP(req, VNIC_CFG);
1172
1173         /* Only RSS support for now TBD: COS & LB */
1174         req.enables =
1175             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1176         if (vnic->lb_rule != 0xffff)
1177                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1178         if (vnic->cos_rule != 0xffff)
1179                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1180         if (vnic->rss_rule != 0xffff) {
1181                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1182                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1183         }
1184         req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1185         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1186         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1187         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1188         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1189         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1190         req.mru = rte_cpu_to_le_16(vnic->mru);
1191         if (vnic->func_default)
1192                 req.flags |=
1193                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1194         if (vnic->vlan_strip)
1195                 req.flags |=
1196                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1197         if (vnic->bd_stall)
1198                 req.flags |=
1199                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1200         if (vnic->roce_dual)
1201                 req.flags |= rte_cpu_to_le_32(
1202                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1203         if (vnic->roce_only)
1204                 req.flags |= rte_cpu_to_le_32(
1205                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1206         if (vnic->rss_dflt_cr)
1207                 req.flags |= rte_cpu_to_le_32(
1208                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1209
1210         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1211
1212         HWRM_CHECK_RESULT();
1213         HWRM_UNLOCK();
1214
1215         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1216
1217         return rc;
1218 }
1219
1220 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1221                 int16_t fw_vf_id)
1222 {
1223         int rc = 0;
1224         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1225         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1226
1227         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1228                 RTE_LOG(DEBUG, PMD, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1229                 return rc;
1230         }
1231         HWRM_PREP(req, VNIC_QCFG);
1232
1233         req.enables =
1234                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1235         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1236         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1237
1238         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1239
1240         HWRM_CHECK_RESULT();
1241
1242         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1243         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1244         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1245         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1246         vnic->mru = rte_le_to_cpu_16(resp->mru);
1247         vnic->func_default = rte_le_to_cpu_32(
1248                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1249         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1250                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1251         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1252                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1253         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1254                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1255         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1256                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1257         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1258                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1259
1260         HWRM_UNLOCK();
1261
1262         return rc;
1263 }
1264
1265 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1266 {
1267         int rc = 0;
1268         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1269         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1270                                                 bp->hwrm_cmd_resp_addr;
1271
1272         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC);
1273
1274         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1275
1276         HWRM_CHECK_RESULT();
1277
1278         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1279         HWRM_UNLOCK();
1280         RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1281
1282         return rc;
1283 }
1284
1285 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1286 {
1287         int rc = 0;
1288         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1289         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1290                                                 bp->hwrm_cmd_resp_addr;
1291
1292         if (vnic->rss_rule == 0xffff) {
1293                 RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1294                 return rc;
1295         }
1296         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE);
1297
1298         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1299
1300         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1301
1302         HWRM_CHECK_RESULT();
1303         HWRM_UNLOCK();
1304
1305         vnic->rss_rule = INVALID_HW_RING_ID;
1306
1307         return rc;
1308 }
1309
1310 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1311 {
1312         int rc = 0;
1313         struct hwrm_vnic_free_input req = {.req_type = 0 };
1314         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1315
1316         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1317                 RTE_LOG(DEBUG, PMD, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1318                 return rc;
1319         }
1320
1321         HWRM_PREP(req, VNIC_FREE);
1322
1323         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1324
1325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1326
1327         HWRM_CHECK_RESULT();
1328         HWRM_UNLOCK();
1329
1330         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1331         return rc;
1332 }
1333
1334 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1335                            struct bnxt_vnic_info *vnic)
1336 {
1337         int rc = 0;
1338         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1339         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1340
1341         HWRM_PREP(req, VNIC_RSS_CFG);
1342
1343         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1344
1345         req.ring_grp_tbl_addr =
1346             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1347         req.hash_key_tbl_addr =
1348             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1349         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1350
1351         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1352
1353         HWRM_CHECK_RESULT();
1354         HWRM_UNLOCK();
1355
1356         return rc;
1357 }
1358
1359 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1360                         struct bnxt_vnic_info *vnic)
1361 {
1362         int rc = 0;
1363         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1364         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1365         uint16_t size;
1366
1367         HWRM_PREP(req, VNIC_PLCMODES_CFG);
1368
1369         req.flags = rte_cpu_to_le_32(
1370                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1371
1372         req.enables = rte_cpu_to_le_32(
1373                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1374
1375         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1376         size -= RTE_PKTMBUF_HEADROOM;
1377
1378         req.jumbo_thresh = rte_cpu_to_le_16(size);
1379         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1380
1381         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1382
1383         HWRM_CHECK_RESULT();
1384         HWRM_UNLOCK();
1385
1386         return rc;
1387 }
1388
1389 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1390                         struct bnxt_vnic_info *vnic, bool enable)
1391 {
1392         int rc = 0;
1393         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1394         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1395
1396         HWRM_PREP(req, VNIC_TPA_CFG);
1397
1398         if (enable) {
1399                 req.enables = rte_cpu_to_le_32(
1400                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1401                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1402                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1403                 req.flags = rte_cpu_to_le_32(
1404                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1405                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1406                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1407                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1408                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1409                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1410                 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1411                 req.max_agg_segs = rte_cpu_to_le_16(5);
1412                 req.max_aggs =
1413                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1414                 req.min_agg_len = rte_cpu_to_le_32(512);
1415         }
1416
1417         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1418
1419         HWRM_CHECK_RESULT();
1420         HWRM_UNLOCK();
1421
1422         return rc;
1423 }
1424
1425 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1426 {
1427         struct hwrm_func_cfg_input req = {0};
1428         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1429         int rc;
1430
1431         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1432         req.enables = rte_cpu_to_le_32(
1433                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1434         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1435         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1436
1437         HWRM_PREP(req, FUNC_CFG);
1438
1439         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1440         HWRM_CHECK_RESULT();
1441         HWRM_UNLOCK();
1442
1443         bp->pf.vf_info[vf].random_mac = false;
1444
1445         return rc;
1446 }
1447
1448 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1449                                   uint64_t *dropped)
1450 {
1451         int rc = 0;
1452         struct hwrm_func_qstats_input req = {.req_type = 0};
1453         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1454
1455         HWRM_PREP(req, FUNC_QSTATS);
1456
1457         req.fid = rte_cpu_to_le_16(fid);
1458
1459         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1460
1461         HWRM_CHECK_RESULT();
1462
1463         if (dropped)
1464                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1465
1466         HWRM_UNLOCK();
1467
1468         return rc;
1469 }
1470
1471 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1472                           struct rte_eth_stats *stats)
1473 {
1474         int rc = 0;
1475         struct hwrm_func_qstats_input req = {.req_type = 0};
1476         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1477
1478         HWRM_PREP(req, FUNC_QSTATS);
1479
1480         req.fid = rte_cpu_to_le_16(fid);
1481
1482         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1483
1484         HWRM_CHECK_RESULT();
1485
1486         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1487         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1488         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1489         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1490         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1491         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1492
1493         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1494         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1495         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1496         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1497         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1498         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1499
1500         stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1501         stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1502
1503         stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1504
1505         HWRM_UNLOCK();
1506
1507         return rc;
1508 }
1509
1510 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1511 {
1512         int rc = 0;
1513         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1514         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1515
1516         HWRM_PREP(req, FUNC_CLR_STATS);
1517
1518         req.fid = rte_cpu_to_le_16(fid);
1519
1520         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1521
1522         HWRM_CHECK_RESULT();
1523         HWRM_UNLOCK();
1524
1525         return rc;
1526 }
1527
1528 /*
1529  * HWRM utility functions
1530  */
1531
1532 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1533 {
1534         unsigned int i;
1535         int rc = 0;
1536
1537         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1538                 struct bnxt_tx_queue *txq;
1539                 struct bnxt_rx_queue *rxq;
1540                 struct bnxt_cp_ring_info *cpr;
1541
1542                 if (i >= bp->rx_cp_nr_rings) {
1543                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1544                         cpr = txq->cp_ring;
1545                 } else {
1546                         rxq = bp->rx_queues[i];
1547                         cpr = rxq->cp_ring;
1548                 }
1549
1550                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1551                 if (rc)
1552                         return rc;
1553         }
1554         return 0;
1555 }
1556
1557 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1558 {
1559         int rc;
1560         unsigned int i;
1561         struct bnxt_cp_ring_info *cpr;
1562
1563         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1564
1565                 if (i >= bp->rx_cp_nr_rings)
1566                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1567                 else
1568                         cpr = bp->rx_queues[i]->cp_ring;
1569                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1570                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1571                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1572                         /*
1573                          * TODO. Need a better way to reset grp_info.stats_ctx
1574                          * for Rx rings only. stats_ctx is not saved for Tx
1575                          * in grp_info.
1576                          */
1577                         bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
1578                         if (rc)
1579                                 return rc;
1580                 }
1581         }
1582         return 0;
1583 }
1584
1585 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1586 {
1587         unsigned int i;
1588         int rc = 0;
1589
1590         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1591                 struct bnxt_tx_queue *txq;
1592                 struct bnxt_rx_queue *rxq;
1593                 struct bnxt_cp_ring_info *cpr;
1594
1595                 if (i >= bp->rx_cp_nr_rings) {
1596                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1597                         cpr = txq->cp_ring;
1598                 } else {
1599                         rxq = bp->rx_queues[i];
1600                         cpr = rxq->cp_ring;
1601                 }
1602
1603                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1604
1605                 if (rc)
1606                         return rc;
1607         }
1608         return rc;
1609 }
1610
1611 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1612 {
1613         uint16_t idx;
1614         uint32_t rc = 0;
1615
1616         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1617
1618                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1619                         continue;
1620
1621                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1622
1623                 if (rc)
1624                         return rc;
1625         }
1626         return rc;
1627 }
1628
1629 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1630                                 unsigned int idx __rte_unused)
1631 {
1632         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1633
1634         bnxt_hwrm_ring_free(bp, cp_ring,
1635                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1636         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1637         bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1638         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1639                         sizeof(*cpr->cp_desc_ring));
1640         cpr->cp_raw_cons = 0;
1641 }
1642
1643 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1644 {
1645         unsigned int i;
1646         int rc = 0;
1647
1648         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1649                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1650                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1651                 struct bnxt_ring *ring = txr->tx_ring_struct;
1652                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1653                 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1654
1655                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1656                         bnxt_hwrm_ring_free(bp, ring,
1657                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1658                         ring->fw_ring_id = INVALID_HW_RING_ID;
1659                         memset(txr->tx_desc_ring, 0,
1660                                         txr->tx_ring_struct->ring_size *
1661                                         sizeof(*txr->tx_desc_ring));
1662                         memset(txr->tx_buf_ring, 0,
1663                                         txr->tx_ring_struct->ring_size *
1664                                         sizeof(*txr->tx_buf_ring));
1665                         txr->tx_prod = 0;
1666                         txr->tx_cons = 0;
1667                 }
1668                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1669                         bnxt_free_cp_ring(bp, cpr, idx);
1670                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1671                 }
1672         }
1673
1674         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1675                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1676                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1677                 struct bnxt_ring *ring = rxr->rx_ring_struct;
1678                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1679                 unsigned int idx = i + 1;
1680
1681                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1682                         bnxt_hwrm_ring_free(bp, ring,
1683                                         HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1684                         ring->fw_ring_id = INVALID_HW_RING_ID;
1685                         bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1686                         memset(rxr->rx_desc_ring, 0,
1687                                         rxr->rx_ring_struct->ring_size *
1688                                         sizeof(*rxr->rx_desc_ring));
1689                         memset(rxr->rx_buf_ring, 0,
1690                                         rxr->rx_ring_struct->ring_size *
1691                                         sizeof(*rxr->rx_buf_ring));
1692                         rxr->rx_prod = 0;
1693                         memset(rxr->ag_buf_ring, 0,
1694                                         rxr->ag_ring_struct->ring_size *
1695                                         sizeof(*rxr->ag_buf_ring));
1696                         rxr->ag_prod = 0;
1697                 }
1698                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1699                         bnxt_free_cp_ring(bp, cpr, idx);
1700                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1701                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1702                 }
1703         }
1704
1705         /* Default completion ring */
1706         {
1707                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1708
1709                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1710                         bnxt_free_cp_ring(bp, cpr, 0);
1711                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1712                 }
1713         }
1714
1715         return rc;
1716 }
1717
1718 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1719 {
1720         uint16_t i;
1721         uint32_t rc = 0;
1722
1723         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1724                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1725                 if (rc)
1726                         return rc;
1727         }
1728         return rc;
1729 }
1730
1731 void bnxt_free_hwrm_resources(struct bnxt *bp)
1732 {
1733         /* Release memzone */
1734         rte_free(bp->hwrm_cmd_resp_addr);
1735         rte_free(bp->hwrm_short_cmd_req_addr);
1736         bp->hwrm_cmd_resp_addr = NULL;
1737         bp->hwrm_short_cmd_req_addr = NULL;
1738         bp->hwrm_cmd_resp_dma_addr = 0;
1739         bp->hwrm_short_cmd_req_dma_addr = 0;
1740 }
1741
1742 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1743 {
1744         struct rte_pci_device *pdev = bp->pdev;
1745         char type[RTE_MEMZONE_NAMESIZE];
1746
1747         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1748                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1749         bp->max_resp_len = HWRM_MAX_RESP_LEN;
1750         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1751         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1752         if (bp->hwrm_cmd_resp_addr == NULL)
1753                 return -ENOMEM;
1754         bp->hwrm_cmd_resp_dma_addr =
1755                 rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
1756         if (bp->hwrm_cmd_resp_dma_addr == 0) {
1757                 RTE_LOG(ERR, PMD,
1758                         "unable to map response address to physical memory\n");
1759                 return -ENOMEM;
1760         }
1761         rte_spinlock_init(&bp->hwrm_lock);
1762
1763         return 0;
1764 }
1765
1766 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1767 {
1768         struct bnxt_filter_info *filter;
1769         int rc = 0;
1770
1771         STAILQ_FOREACH(filter, &vnic->filter, next) {
1772                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1773                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
1774                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1775                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1776                 else
1777                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1778                 //if (rc)
1779                         //break;
1780         }
1781         return rc;
1782 }
1783
1784 static int
1785 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1786 {
1787         struct bnxt_filter_info *filter;
1788         struct rte_flow *flow;
1789         int rc = 0;
1790
1791         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
1792                 filter = flow->filter;
1793                 RTE_LOG(ERR, PMD, "filter type %d\n", filter->filter_type);
1794                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1795                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
1796                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1797                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1798                 else
1799                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1800
1801                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
1802                 rte_free(flow);
1803                 //if (rc)
1804                         //break;
1805         }
1806         return rc;
1807 }
1808
1809 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1810 {
1811         struct bnxt_filter_info *filter;
1812         int rc = 0;
1813
1814         STAILQ_FOREACH(filter, &vnic->filter, next) {
1815                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1816                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
1817                                                      filter);
1818                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1819                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
1820                                                          filter);
1821                 else
1822                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
1823                                                      filter);
1824                 if (rc)
1825                         break;
1826         }
1827         return rc;
1828 }
1829
1830 void bnxt_free_tunnel_ports(struct bnxt *bp)
1831 {
1832         if (bp->vxlan_port_cnt)
1833                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1834                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1835         bp->vxlan_port = 0;
1836         if (bp->geneve_port_cnt)
1837                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1838                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1839         bp->geneve_port = 0;
1840 }
1841
1842 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1843 {
1844         int i;
1845
1846         if (bp->vnic_info == NULL)
1847                 return;
1848
1849         /*
1850          * Cleanup VNICs in reverse order, to make sure the L2 filter
1851          * from vnic0 is last to be cleaned up.
1852          */
1853         for (i = bp->nr_vnics - 1; i >= 0; i--) {
1854                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1855
1856                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
1857
1858                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1859
1860                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1861
1862                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1863
1864                 bnxt_hwrm_vnic_free(bp, vnic);
1865         }
1866         /* Ring resources */
1867         bnxt_free_all_hwrm_rings(bp);
1868         bnxt_free_all_hwrm_ring_grps(bp);
1869         bnxt_free_all_hwrm_stat_ctxs(bp);
1870         bnxt_free_tunnel_ports(bp);
1871 }
1872
1873 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1874 {
1875         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1876
1877         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1878                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1879
1880         switch (conf_link_speed) {
1881         case ETH_LINK_SPEED_10M_HD:
1882         case ETH_LINK_SPEED_100M_HD:
1883                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1884         }
1885         return hw_link_duplex;
1886 }
1887
1888 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1889 {
1890         uint16_t eth_link_speed = 0;
1891
1892         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1893                 return ETH_LINK_SPEED_AUTONEG;
1894
1895         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1896         case ETH_LINK_SPEED_100M:
1897         case ETH_LINK_SPEED_100M_HD:
1898                 eth_link_speed =
1899                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1900                 break;
1901         case ETH_LINK_SPEED_1G:
1902                 eth_link_speed =
1903                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1904                 break;
1905         case ETH_LINK_SPEED_2_5G:
1906                 eth_link_speed =
1907                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1908                 break;
1909         case ETH_LINK_SPEED_10G:
1910                 eth_link_speed =
1911                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1912                 break;
1913         case ETH_LINK_SPEED_20G:
1914                 eth_link_speed =
1915                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1916                 break;
1917         case ETH_LINK_SPEED_25G:
1918                 eth_link_speed =
1919                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1920                 break;
1921         case ETH_LINK_SPEED_40G:
1922                 eth_link_speed =
1923                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1924                 break;
1925         case ETH_LINK_SPEED_50G:
1926                 eth_link_speed =
1927                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1928                 break;
1929         default:
1930                 RTE_LOG(ERR, PMD,
1931                         "Unsupported link speed %d; default to AUTO\n",
1932                         conf_link_speed);
1933                 break;
1934         }
1935         return eth_link_speed;
1936 }
1937
1938 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1939                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1940                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1941                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1942
1943 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
1944 {
1945         uint32_t one_speed;
1946
1947         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1948                 return 0;
1949
1950         if (link_speed & ETH_LINK_SPEED_FIXED) {
1951                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1952
1953                 if (one_speed & (one_speed - 1)) {
1954                         RTE_LOG(ERR, PMD,
1955                                 "Invalid advertised speeds (%u) for port %u\n",
1956                                 link_speed, port_id);
1957                         return -EINVAL;
1958                 }
1959                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1960                         RTE_LOG(ERR, PMD,
1961                                 "Unsupported advertised speed (%u) for port %u\n",
1962                                 link_speed, port_id);
1963                         return -EINVAL;
1964                 }
1965         } else {
1966                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1967                         RTE_LOG(ERR, PMD,
1968                                 "Unsupported advertised speeds (%u) for port %u\n",
1969                                 link_speed, port_id);
1970                         return -EINVAL;
1971                 }
1972         }
1973         return 0;
1974 }
1975
1976 static uint16_t
1977 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
1978 {
1979         uint16_t ret = 0;
1980
1981         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
1982                 if (bp->link_info.support_speeds)
1983                         return bp->link_info.support_speeds;
1984                 link_speed = BNXT_SUPPORTED_SPEEDS;
1985         }
1986
1987         if (link_speed & ETH_LINK_SPEED_100M)
1988                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1989         if (link_speed & ETH_LINK_SPEED_100M_HD)
1990                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1991         if (link_speed & ETH_LINK_SPEED_1G)
1992                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1993         if (link_speed & ETH_LINK_SPEED_2_5G)
1994                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1995         if (link_speed & ETH_LINK_SPEED_10G)
1996                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1997         if (link_speed & ETH_LINK_SPEED_20G)
1998                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1999         if (link_speed & ETH_LINK_SPEED_25G)
2000                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2001         if (link_speed & ETH_LINK_SPEED_40G)
2002                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2003         if (link_speed & ETH_LINK_SPEED_50G)
2004                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2005         return ret;
2006 }
2007
2008 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2009 {
2010         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2011
2012         switch (hw_link_speed) {
2013         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2014                 eth_link_speed = ETH_SPEED_NUM_100M;
2015                 break;
2016         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2017                 eth_link_speed = ETH_SPEED_NUM_1G;
2018                 break;
2019         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2020                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2021                 break;
2022         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2023                 eth_link_speed = ETH_SPEED_NUM_10G;
2024                 break;
2025         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2026                 eth_link_speed = ETH_SPEED_NUM_20G;
2027                 break;
2028         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2029                 eth_link_speed = ETH_SPEED_NUM_25G;
2030                 break;
2031         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2032                 eth_link_speed = ETH_SPEED_NUM_40G;
2033                 break;
2034         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2035                 eth_link_speed = ETH_SPEED_NUM_50G;
2036                 break;
2037         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2038         default:
2039                 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
2040                         hw_link_speed);
2041                 break;
2042         }
2043         return eth_link_speed;
2044 }
2045
2046 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2047 {
2048         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2049
2050         switch (hw_link_duplex) {
2051         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2052         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2053                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2054                 break;
2055         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2056                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2057                 break;
2058         default:
2059                 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
2060                         hw_link_duplex);
2061                 break;
2062         }
2063         return eth_link_duplex;
2064 }
2065
2066 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2067 {
2068         int rc = 0;
2069         struct bnxt_link_info *link_info = &bp->link_info;
2070
2071         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2072         if (rc) {
2073                 RTE_LOG(ERR, PMD,
2074                         "Get link config failed with rc %d\n", rc);
2075                 goto exit;
2076         }
2077         if (link_info->link_speed)
2078                 link->link_speed =
2079                         bnxt_parse_hw_link_speed(link_info->link_speed);
2080         else
2081                 link->link_speed = ETH_SPEED_NUM_NONE;
2082         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2083         link->link_status = link_info->link_up;
2084         link->link_autoneg = link_info->auto_mode ==
2085                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2086                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2087 exit:
2088         return rc;
2089 }
2090
2091 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2092 {
2093         int rc = 0;
2094         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2095         struct bnxt_link_info link_req;
2096         uint16_t speed;
2097
2098         if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
2099                 return 0;
2100
2101         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2102                         bp->eth_dev->data->port_id);
2103         if (rc)
2104                 goto error;
2105
2106         memset(&link_req, 0, sizeof(link_req));
2107         link_req.link_up = link_up;
2108         if (!link_up)
2109                 goto port_phy_cfg;
2110
2111         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2112         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2113         if (speed == 0) {
2114                 link_req.phy_flags |=
2115                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2116                 link_req.auto_mode =
2117                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
2118                 link_req.auto_link_speed_mask =
2119                         bnxt_parse_eth_link_speed_mask(bp,
2120                                                        dev_conf->link_speeds);
2121         } else {
2122                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2123                 link_req.link_speed = speed;
2124                 RTE_LOG(INFO, PMD, "Set Link Speed %x\n", speed);
2125         }
2126         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2127         link_req.auto_pause = bp->link_info.auto_pause;
2128         link_req.force_pause = bp->link_info.force_pause;
2129
2130 port_phy_cfg:
2131         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2132         if (rc) {
2133                 RTE_LOG(ERR, PMD,
2134                         "Set link config failed with rc %d\n", rc);
2135         }
2136
2137 error:
2138         return rc;
2139 }
2140
2141 /* JIRA 22088 */
2142 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2143 {
2144         struct hwrm_func_qcfg_input req = {0};
2145         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2146         int rc = 0;
2147
2148         HWRM_PREP(req, FUNC_QCFG);
2149         req.fid = rte_cpu_to_le_16(0xffff);
2150
2151         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2152
2153         HWRM_CHECK_RESULT();
2154
2155         /* Hard Coded.. 0xfff VLAN ID mask */
2156         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2157
2158         switch (resp->port_partition_type) {
2159         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2160         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2161         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2162                 bp->port_partition_type = resp->port_partition_type;
2163                 break;
2164         default:
2165                 bp->port_partition_type = 0;
2166                 break;
2167         }
2168
2169         HWRM_UNLOCK();
2170
2171         return rc;
2172 }
2173
2174 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2175                                    struct hwrm_func_qcaps_output *qcaps)
2176 {
2177         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2178         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2179                sizeof(qcaps->mac_address));
2180         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2181         qcaps->max_rx_rings = fcfg->num_rx_rings;
2182         qcaps->max_tx_rings = fcfg->num_tx_rings;
2183         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2184         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2185         qcaps->max_vfs = 0;
2186         qcaps->first_vf_id = 0;
2187         qcaps->max_vnics = fcfg->num_vnics;
2188         qcaps->max_decap_records = 0;
2189         qcaps->max_encap_records = 0;
2190         qcaps->max_tx_wm_flows = 0;
2191         qcaps->max_tx_em_flows = 0;
2192         qcaps->max_rx_wm_flows = 0;
2193         qcaps->max_rx_em_flows = 0;
2194         qcaps->max_flow_id = 0;
2195         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2196         qcaps->max_sp_tx_rings = 0;
2197         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2198 }
2199
2200 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2201 {
2202         struct hwrm_func_cfg_input req = {0};
2203         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2204         int rc;
2205
2206         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2207                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2208                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2209                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2210                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2211                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2212                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2213                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2214                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2215                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2216         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2217         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2218         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2219                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
2220         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2221         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2222         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2223         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2224         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2225         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2226         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2227         req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2228         req.fid = rte_cpu_to_le_16(0xffff);
2229
2230         HWRM_PREP(req, FUNC_CFG);
2231
2232         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2233
2234         HWRM_CHECK_RESULT();
2235         HWRM_UNLOCK();
2236
2237         return rc;
2238 }
2239
2240 static void populate_vf_func_cfg_req(struct bnxt *bp,
2241                                      struct hwrm_func_cfg_input *req,
2242                                      int num_vfs)
2243 {
2244         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2245                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2246                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2247                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2248                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2249                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2250                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2251                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2252                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2253                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2254
2255         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2256                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2257         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2258                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2259         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2260                                                 (num_vfs + 1));
2261         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2262         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2263                                                (num_vfs + 1));
2264         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2265         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2266         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2267         /* TODO: For now, do not support VMDq/RFS on VFs. */
2268         req->num_vnics = rte_cpu_to_le_16(1);
2269         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2270                                                  (num_vfs + 1));
2271 }
2272
2273 static void add_random_mac_if_needed(struct bnxt *bp,
2274                                      struct hwrm_func_cfg_input *cfg_req,
2275                                      int vf)
2276 {
2277         struct ether_addr mac;
2278
2279         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2280                 return;
2281
2282         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2283                 cfg_req->enables |=
2284                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2285                 eth_random_addr(cfg_req->dflt_mac_addr);
2286                 bp->pf.vf_info[vf].random_mac = true;
2287         } else {
2288                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2289         }
2290 }
2291
2292 static void reserve_resources_from_vf(struct bnxt *bp,
2293                                       struct hwrm_func_cfg_input *cfg_req,
2294                                       int vf)
2295 {
2296         struct hwrm_func_qcaps_input req = {0};
2297         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2298         int rc;
2299
2300         /* Get the actual allocated values now */
2301         HWRM_PREP(req, FUNC_QCAPS);
2302         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2303         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2304
2305         if (rc) {
2306                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
2307                 copy_func_cfg_to_qcaps(cfg_req, resp);
2308         } else if (resp->error_code) {
2309                 rc = rte_le_to_cpu_16(resp->error_code);
2310                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
2311                 copy_func_cfg_to_qcaps(cfg_req, resp);
2312         }
2313
2314         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2315         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2316         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2317         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2318         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2319         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2320         /*
2321          * TODO: While not supporting VMDq with VFs, max_vnics is always
2322          * forced to 1 in this case
2323          */
2324         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2325         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2326
2327         HWRM_UNLOCK();
2328 }
2329
2330 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2331 {
2332         struct hwrm_func_qcfg_input req = {0};
2333         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2334         int rc;
2335
2336         /* Check for zero MAC address */
2337         HWRM_PREP(req, FUNC_QCFG);
2338         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2339         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2340         if (rc) {
2341                 RTE_LOG(ERR, PMD, "hwrm_func_qcfg failed rc:%d\n", rc);
2342                 return -1;
2343         } else if (resp->error_code) {
2344                 rc = rte_le_to_cpu_16(resp->error_code);
2345                 RTE_LOG(ERR, PMD, "hwrm_func_qcfg error %d\n", rc);
2346                 return -1;
2347         }
2348         rc = rte_le_to_cpu_16(resp->vlan);
2349
2350         HWRM_UNLOCK();
2351
2352         return rc;
2353 }
2354
2355 static int update_pf_resource_max(struct bnxt *bp)
2356 {
2357         struct hwrm_func_qcfg_input req = {0};
2358         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2359         int rc;
2360
2361         /* And copy the allocated numbers into the pf struct */
2362         HWRM_PREP(req, FUNC_QCFG);
2363         req.fid = rte_cpu_to_le_16(0xffff);
2364         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2365         HWRM_CHECK_RESULT();
2366
2367         /* Only TX ring value reflects actual allocation? TODO */
2368         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2369         bp->pf.evb_mode = resp->evb_mode;
2370
2371         HWRM_UNLOCK();
2372
2373         return rc;
2374 }
2375
2376 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2377 {
2378         int rc;
2379
2380         if (!BNXT_PF(bp)) {
2381                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2382                 return -1;
2383         }
2384
2385         rc = bnxt_hwrm_func_qcaps(bp);
2386         if (rc)
2387                 return rc;
2388
2389         bp->pf.func_cfg_flags &=
2390                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2391                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2392         bp->pf.func_cfg_flags |=
2393                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2394         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2395         return rc;
2396 }
2397
2398 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2399 {
2400         struct hwrm_func_cfg_input req = {0};
2401         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2402         int i;
2403         size_t sz;
2404         int rc = 0;
2405         size_t req_buf_sz;
2406
2407         if (!BNXT_PF(bp)) {
2408                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2409                 return -1;
2410         }
2411
2412         rc = bnxt_hwrm_func_qcaps(bp);
2413
2414         if (rc)
2415                 return rc;
2416
2417         bp->pf.active_vfs = num_vfs;
2418
2419         /*
2420          * First, configure the PF to only use one TX ring.  This ensures that
2421          * there are enough rings for all VFs.
2422          *
2423          * If we don't do this, when we call func_alloc() later, we will lock
2424          * extra rings to the PF that won't be available during func_cfg() of
2425          * the VFs.
2426          *
2427          * This has been fixed with firmware versions above 20.6.54
2428          */
2429         bp->pf.func_cfg_flags &=
2430                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2431                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2432         bp->pf.func_cfg_flags |=
2433                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2434         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2435         if (rc)
2436                 return rc;
2437
2438         /*
2439          * Now, create and register a buffer to hold forwarded VF requests
2440          */
2441         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2442         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2443                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2444         if (bp->pf.vf_req_buf == NULL) {
2445                 rc = -ENOMEM;
2446                 goto error_free;
2447         }
2448         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2449                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2450         for (i = 0; i < num_vfs; i++)
2451                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2452                                         (i * HWRM_MAX_REQ_LEN);
2453
2454         rc = bnxt_hwrm_func_buf_rgtr(bp);
2455         if (rc)
2456                 goto error_free;
2457
2458         populate_vf_func_cfg_req(bp, &req, num_vfs);
2459
2460         bp->pf.active_vfs = 0;
2461         for (i = 0; i < num_vfs; i++) {
2462                 add_random_mac_if_needed(bp, &req, i);
2463
2464                 HWRM_PREP(req, FUNC_CFG);
2465                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2466                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2467                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2468
2469                 /* Clear enable flag for next pass */
2470                 req.enables &= ~rte_cpu_to_le_32(
2471                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2472
2473                 if (rc || resp->error_code) {
2474                         RTE_LOG(ERR, PMD,
2475                                 "Failed to initizlie VF %d\n", i);
2476                         RTE_LOG(ERR, PMD,
2477                                 "Not all VFs available. (%d, %d)\n",
2478                                 rc, resp->error_code);
2479                         HWRM_UNLOCK();
2480                         break;
2481                 }
2482
2483                 HWRM_UNLOCK();
2484
2485                 reserve_resources_from_vf(bp, &req, i);
2486                 bp->pf.active_vfs++;
2487                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2488         }
2489
2490         /*
2491          * Now configure the PF to use "the rest" of the resources
2492          * We're using STD_TX_RING_MODE here though which will limit the TX
2493          * rings.  This will allow QoS to function properly.  Not setting this
2494          * will cause PF rings to break bandwidth settings.
2495          */
2496         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2497         if (rc)
2498                 goto error_free;
2499
2500         rc = update_pf_resource_max(bp);
2501         if (rc)
2502                 goto error_free;
2503
2504         return rc;
2505
2506 error_free:
2507         bnxt_hwrm_func_buf_unrgtr(bp);
2508         return rc;
2509 }
2510
2511 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2512 {
2513         struct hwrm_func_cfg_input req = {0};
2514         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2515         int rc;
2516
2517         HWRM_PREP(req, FUNC_CFG);
2518
2519         req.fid = rte_cpu_to_le_16(0xffff);
2520         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2521         req.evb_mode = bp->pf.evb_mode;
2522
2523         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2524         HWRM_CHECK_RESULT();
2525         HWRM_UNLOCK();
2526
2527         return rc;
2528 }
2529
2530 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2531                                 uint8_t tunnel_type)
2532 {
2533         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2534         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2535         int rc = 0;
2536
2537         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC);
2538         req.tunnel_type = tunnel_type;
2539         req.tunnel_dst_port_val = port;
2540         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2541         HWRM_CHECK_RESULT();
2542
2543         switch (tunnel_type) {
2544         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2545                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2546                 bp->vxlan_port = port;
2547                 break;
2548         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2549                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2550                 bp->geneve_port = port;
2551                 break;
2552         default:
2553                 break;
2554         }
2555
2556         HWRM_UNLOCK();
2557
2558         return rc;
2559 }
2560
2561 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2562                                 uint8_t tunnel_type)
2563 {
2564         struct hwrm_tunnel_dst_port_free_input req = {0};
2565         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2566         int rc = 0;
2567
2568         HWRM_PREP(req, TUNNEL_DST_PORT_FREE);
2569
2570         req.tunnel_type = tunnel_type;
2571         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2572         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2573
2574         HWRM_CHECK_RESULT();
2575         HWRM_UNLOCK();
2576
2577         return rc;
2578 }
2579
2580 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2581                                         uint32_t flags)
2582 {
2583         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2584         struct hwrm_func_cfg_input req = {0};
2585         int rc;
2586
2587         HWRM_PREP(req, FUNC_CFG);
2588
2589         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2590         req.flags = rte_cpu_to_le_32(flags);
2591         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2592
2593         HWRM_CHECK_RESULT();
2594         HWRM_UNLOCK();
2595
2596         return rc;
2597 }
2598
2599 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2600 {
2601         uint32_t *flag = flagp;
2602
2603         vnic->flags = *flag;
2604 }
2605
2606 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2607 {
2608         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2609 }
2610
2611 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2612 {
2613         int rc = 0;
2614         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2615         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2616
2617         HWRM_PREP(req, FUNC_BUF_RGTR);
2618
2619         req.req_buf_num_pages = rte_cpu_to_le_16(1);
2620         req.req_buf_page_size = rte_cpu_to_le_16(
2621                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2622         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2623         req.req_buf_page_addr[0] =
2624                 rte_cpu_to_le_64(rte_mem_virt2phy(bp->pf.vf_req_buf));
2625         if (req.req_buf_page_addr[0] == 0) {
2626                 RTE_LOG(ERR, PMD,
2627                         "unable to map buffer address to physical memory\n");
2628                 return -ENOMEM;
2629         }
2630
2631         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2632
2633         HWRM_CHECK_RESULT();
2634         HWRM_UNLOCK();
2635
2636         return rc;
2637 }
2638
2639 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2640 {
2641         int rc = 0;
2642         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2643         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2644
2645         HWRM_PREP(req, FUNC_BUF_UNRGTR);
2646
2647         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2648
2649         HWRM_CHECK_RESULT();
2650         HWRM_UNLOCK();
2651
2652         return rc;
2653 }
2654
2655 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2656 {
2657         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2658         struct hwrm_func_cfg_input req = {0};
2659         int rc;
2660
2661         HWRM_PREP(req, FUNC_CFG);
2662
2663         req.fid = rte_cpu_to_le_16(0xffff);
2664         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2665         req.enables = rte_cpu_to_le_32(
2666                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2667         req.async_event_cr = rte_cpu_to_le_16(
2668                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2669         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2670
2671         HWRM_CHECK_RESULT();
2672         HWRM_UNLOCK();
2673
2674         return rc;
2675 }
2676
2677 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2678 {
2679         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2680         struct hwrm_func_vf_cfg_input req = {0};
2681         int rc;
2682
2683         HWRM_PREP(req, FUNC_VF_CFG);
2684
2685         req.enables = rte_cpu_to_le_32(
2686                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2687         req.async_event_cr = rte_cpu_to_le_16(
2688                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2690
2691         HWRM_CHECK_RESULT();
2692         HWRM_UNLOCK();
2693
2694         return rc;
2695 }
2696
2697 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2698 {
2699         struct hwrm_func_cfg_input req = {0};
2700         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2701         uint16_t dflt_vlan, fid;
2702         uint32_t func_cfg_flags;
2703         int rc = 0;
2704
2705         HWRM_PREP(req, FUNC_CFG);
2706
2707         if (is_vf) {
2708                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2709                 fid = bp->pf.vf_info[vf].fid;
2710                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2711         } else {
2712                 fid = rte_cpu_to_le_16(0xffff);
2713                 func_cfg_flags = bp->pf.func_cfg_flags;
2714                 dflt_vlan = bp->vlan;
2715         }
2716
2717         req.flags = rte_cpu_to_le_32(func_cfg_flags);
2718         req.fid = rte_cpu_to_le_16(fid);
2719         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2720         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2721
2722         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2723
2724         HWRM_CHECK_RESULT();
2725         HWRM_UNLOCK();
2726
2727         return rc;
2728 }
2729
2730 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2731                         uint16_t max_bw, uint16_t enables)
2732 {
2733         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2734         struct hwrm_func_cfg_input req = {0};
2735         int rc;
2736
2737         HWRM_PREP(req, FUNC_CFG);
2738
2739         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2740         req.enables |= rte_cpu_to_le_32(enables);
2741         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2742         req.max_bw = rte_cpu_to_le_32(max_bw);
2743         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2744
2745         HWRM_CHECK_RESULT();
2746         HWRM_UNLOCK();
2747
2748         return rc;
2749 }
2750
2751 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2752 {
2753         struct hwrm_func_cfg_input req = {0};
2754         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2755         int rc = 0;
2756
2757         HWRM_PREP(req, FUNC_CFG);
2758
2759         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2760         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2761         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2762         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2763
2764         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2765
2766         HWRM_CHECK_RESULT();
2767         HWRM_UNLOCK();
2768
2769         return rc;
2770 }
2771
2772 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2773                               void *encaped, size_t ec_size)
2774 {
2775         int rc = 0;
2776         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2777         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2778
2779         if (ec_size > sizeof(req.encap_request))
2780                 return -1;
2781
2782         HWRM_PREP(req, REJECT_FWD_RESP);
2783
2784         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2785         memcpy(req.encap_request, encaped, ec_size);
2786
2787         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2788
2789         HWRM_CHECK_RESULT();
2790         HWRM_UNLOCK();
2791
2792         return rc;
2793 }
2794
2795 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2796                                        struct ether_addr *mac)
2797 {
2798         struct hwrm_func_qcfg_input req = {0};
2799         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2800         int rc;
2801
2802         HWRM_PREP(req, FUNC_QCFG);
2803
2804         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2805         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2806
2807         HWRM_CHECK_RESULT();
2808
2809         memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2810
2811         HWRM_UNLOCK();
2812
2813         return rc;
2814 }
2815
2816 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2817                             void *encaped, size_t ec_size)
2818 {
2819         int rc = 0;
2820         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2821         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2822
2823         if (ec_size > sizeof(req.encap_request))
2824                 return -1;
2825
2826         HWRM_PREP(req, EXEC_FWD_RESP);
2827
2828         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2829         memcpy(req.encap_request, encaped, ec_size);
2830
2831         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2832
2833         HWRM_CHECK_RESULT();
2834         HWRM_UNLOCK();
2835
2836         return rc;
2837 }
2838
2839 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2840                          struct rte_eth_stats *stats, uint8_t rx)
2841 {
2842         int rc = 0;
2843         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2844         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2845
2846         HWRM_PREP(req, STAT_CTX_QUERY);
2847
2848         req.stat_ctx_id = rte_cpu_to_le_32(cid);
2849
2850         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2851
2852         HWRM_CHECK_RESULT();
2853
2854         if (rx) {
2855                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2856                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2857                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2858                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2859                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2860                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2861                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2862                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2863         } else {
2864                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2865                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2866                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2867                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2868                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2869                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2870                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2871         }
2872
2873
2874         HWRM_UNLOCK();
2875
2876         return rc;
2877 }
2878
2879 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2880 {
2881         struct hwrm_port_qstats_input req = {0};
2882         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2883         struct bnxt_pf_info *pf = &bp->pf;
2884         int rc;
2885
2886         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2887                 return 0;
2888
2889         HWRM_PREP(req, PORT_QSTATS);
2890
2891         req.port_id = rte_cpu_to_le_16(pf->port_id);
2892         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
2893         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
2894         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2895
2896         HWRM_CHECK_RESULT();
2897         HWRM_UNLOCK();
2898
2899         return rc;
2900 }
2901
2902 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
2903 {
2904         struct hwrm_port_clr_stats_input req = {0};
2905         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2906         struct bnxt_pf_info *pf = &bp->pf;
2907         int rc;
2908
2909         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2910                 return 0;
2911
2912         HWRM_PREP(req, PORT_CLR_STATS);
2913
2914         req.port_id = rte_cpu_to_le_16(pf->port_id);
2915         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2916
2917         HWRM_CHECK_RESULT();
2918         HWRM_UNLOCK();
2919
2920         return rc;
2921 }
2922
2923 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
2924 {
2925         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2926         struct hwrm_port_led_qcaps_input req = {0};
2927         int rc;
2928
2929         if (BNXT_VF(bp))
2930                 return 0;
2931
2932         HWRM_PREP(req, PORT_LED_QCAPS);
2933         req.port_id = bp->pf.port_id;
2934         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2935
2936         HWRM_CHECK_RESULT();
2937
2938         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
2939                 unsigned int i;
2940
2941                 bp->num_leds = resp->num_leds;
2942                 memcpy(bp->leds, &resp->led0_id,
2943                         sizeof(bp->leds[0]) * bp->num_leds);
2944                 for (i = 0; i < bp->num_leds; i++) {
2945                         struct bnxt_led_info *led = &bp->leds[i];
2946
2947                         uint16_t caps = led->led_state_caps;
2948
2949                         if (!led->led_group_id ||
2950                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
2951                                 bp->num_leds = 0;
2952                                 break;
2953                         }
2954                 }
2955         }
2956
2957         HWRM_UNLOCK();
2958
2959         return rc;
2960 }
2961
2962 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
2963 {
2964         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2965         struct hwrm_port_led_cfg_input req = {0};
2966         struct bnxt_led_cfg *led_cfg;
2967         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
2968         uint16_t duration = 0;
2969         int rc, i;
2970
2971         if (!bp->num_leds || BNXT_VF(bp))
2972                 return -EOPNOTSUPP;
2973
2974         HWRM_PREP(req, PORT_LED_CFG);
2975
2976         if (led_on) {
2977                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
2978                 duration = rte_cpu_to_le_16(500);
2979         }
2980         req.port_id = bp->pf.port_id;
2981         req.num_leds = bp->num_leds;
2982         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
2983         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
2984                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
2985                 led_cfg->led_id = bp->leds[i].led_id;
2986                 led_cfg->led_state = led_state;
2987                 led_cfg->led_blink_on = duration;
2988                 led_cfg->led_blink_off = duration;
2989                 led_cfg->led_group_id = bp->leds[i].led_group_id;
2990         }
2991
2992         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2993
2994         HWRM_CHECK_RESULT();
2995         HWRM_UNLOCK();
2996
2997         return rc;
2998 }
2999
3000 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3001                                uint32_t *length)
3002 {
3003         int rc;
3004         struct hwrm_nvm_get_dir_info_input req = {0};
3005         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3006
3007         HWRM_PREP(req, NVM_GET_DIR_INFO);
3008
3009         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3010
3011         HWRM_CHECK_RESULT();
3012         HWRM_UNLOCK();
3013
3014         if (!rc) {
3015                 *entries = rte_le_to_cpu_32(resp->entries);
3016                 *length = rte_le_to_cpu_32(resp->entry_length);
3017         }
3018         return rc;
3019 }
3020
3021 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3022 {
3023         int rc;
3024         uint32_t dir_entries;
3025         uint32_t entry_length;
3026         uint8_t *buf;
3027         size_t buflen;
3028         phys_addr_t dma_handle;
3029         struct hwrm_nvm_get_dir_entries_input req = {0};
3030         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3031
3032         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3033         if (rc != 0)
3034                 return rc;
3035
3036         *data++ = dir_entries;
3037         *data++ = entry_length;
3038         len -= 2;
3039         memset(data, 0xff, len);
3040
3041         buflen = dir_entries * entry_length;
3042         buf = rte_malloc("nvm_dir", buflen, 0);
3043         rte_mem_lock_page(buf);
3044         if (buf == NULL)
3045                 return -ENOMEM;
3046         dma_handle = rte_mem_virt2phy(buf);
3047         if (dma_handle == 0) {
3048                 RTE_LOG(ERR, PMD,
3049                         "unable to map response address to physical memory\n");
3050                 return -ENOMEM;
3051         }
3052         HWRM_PREP(req, NVM_GET_DIR_ENTRIES);
3053         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3054         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3055
3056         HWRM_CHECK_RESULT();
3057         HWRM_UNLOCK();
3058
3059         if (rc == 0)
3060                 memcpy(data, buf, len > buflen ? buflen : len);
3061
3062         rte_free(buf);
3063
3064         return rc;
3065 }
3066
3067 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3068                              uint32_t offset, uint32_t length,
3069                              uint8_t *data)
3070 {
3071         int rc;
3072         uint8_t *buf;
3073         phys_addr_t dma_handle;
3074         struct hwrm_nvm_read_input req = {0};
3075         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3076
3077         buf = rte_malloc("nvm_item", length, 0);
3078         rte_mem_lock_page(buf);
3079         if (!buf)
3080                 return -ENOMEM;
3081
3082         dma_handle = rte_mem_virt2phy(buf);
3083         if (dma_handle == 0) {
3084                 RTE_LOG(ERR, PMD,
3085                         "unable to map response address to physical memory\n");
3086                 return -ENOMEM;
3087         }
3088         HWRM_PREP(req, NVM_READ);
3089         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3090         req.dir_idx = rte_cpu_to_le_16(index);
3091         req.offset = rte_cpu_to_le_32(offset);
3092         req.len = rte_cpu_to_le_32(length);
3093         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3094         HWRM_CHECK_RESULT();
3095         HWRM_UNLOCK();
3096         if (rc == 0)
3097                 memcpy(data, buf, length);
3098
3099         rte_free(buf);
3100         return rc;
3101 }
3102
3103 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3104 {
3105         int rc;
3106         struct hwrm_nvm_erase_dir_entry_input req = {0};
3107         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3108
3109         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY);
3110         req.dir_idx = rte_cpu_to_le_16(index);
3111         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3112         HWRM_CHECK_RESULT();
3113         HWRM_UNLOCK();
3114
3115         return rc;
3116 }
3117
3118
3119 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3120                           uint16_t dir_ordinal, uint16_t dir_ext,
3121                           uint16_t dir_attr, const uint8_t *data,
3122                           size_t data_len)
3123 {
3124         int rc;
3125         struct hwrm_nvm_write_input req = {0};
3126         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3127         phys_addr_t dma_handle;
3128         uint8_t *buf;
3129
3130         HWRM_PREP(req, NVM_WRITE);
3131
3132         req.dir_type = rte_cpu_to_le_16(dir_type);
3133         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3134         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3135         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3136         req.dir_data_length = rte_cpu_to_le_32(data_len);
3137
3138         buf = rte_malloc("nvm_write", data_len, 0);
3139         rte_mem_lock_page(buf);
3140         if (!buf)
3141                 return -ENOMEM;
3142
3143         dma_handle = rte_mem_virt2phy(buf);
3144         if (dma_handle == 0) {
3145                 RTE_LOG(ERR, PMD,
3146                         "unable to map response address to physical memory\n");
3147                 return -ENOMEM;
3148         }
3149         memcpy(buf, data, data_len);
3150         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3151
3152         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3153
3154         HWRM_CHECK_RESULT();
3155         HWRM_UNLOCK();
3156
3157         rte_free(buf);
3158         return rc;
3159 }
3160
3161 static void
3162 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3163 {
3164         uint32_t *count = cbdata;
3165
3166         *count = *count + 1;
3167 }
3168
3169 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3170                                      struct bnxt_vnic_info *vnic __rte_unused)
3171 {
3172         return 0;
3173 }
3174
3175 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3176 {
3177         uint32_t count = 0;
3178
3179         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3180             &count, bnxt_vnic_count_hwrm_stub);
3181
3182         return count;
3183 }
3184
3185 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3186                                         uint16_t *vnic_ids)
3187 {
3188         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3189         struct hwrm_func_vf_vnic_ids_query_output *resp =
3190                                                 bp->hwrm_cmd_resp_addr;
3191         int rc;
3192
3193         /* First query all VNIC ids */
3194         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY);
3195
3196         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3197         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3198         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2phy(vnic_ids));
3199
3200         if (req.vnic_id_tbl_addr == 0) {
3201                 HWRM_UNLOCK();
3202                 RTE_LOG(ERR, PMD,
3203                 "unable to map VNIC ID table address to physical memory\n");
3204                 return -ENOMEM;
3205         }
3206         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3207         if (rc) {
3208                 HWRM_UNLOCK();
3209                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3210                 return -1;
3211         } else if (resp->error_code) {
3212                 rc = rte_le_to_cpu_16(resp->error_code);
3213                 HWRM_UNLOCK();
3214                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query error %d\n", rc);
3215                 return -1;
3216         }
3217         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3218
3219         HWRM_UNLOCK();
3220
3221         return rc;
3222 }
3223
3224 /*
3225  * This function queries the VNIC IDs  for a specified VF. It then calls
3226  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3227  * Then it calls the hwrm_cb function to program this new vnic configuration.
3228  */
3229 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3230         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3231         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3232 {
3233         struct bnxt_vnic_info vnic;
3234         int rc = 0;
3235         int i, num_vnic_ids;
3236         uint16_t *vnic_ids;
3237         size_t vnic_id_sz;
3238         size_t sz;
3239
3240         /* First query all VNIC ids */
3241         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3242         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3243                         RTE_CACHE_LINE_SIZE);
3244         if (vnic_ids == NULL) {
3245                 rc = -ENOMEM;
3246                 return rc;
3247         }
3248         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3249                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3250
3251         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3252
3253         if (num_vnic_ids < 0)
3254                 return num_vnic_ids;
3255
3256         /* Retrieve VNIC, update bd_stall then update */
3257
3258         for (i = 0; i < num_vnic_ids; i++) {
3259                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3260                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3261                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3262                 if (rc)
3263                         break;
3264                 if (vnic.mru <= 4)      /* Indicates unallocated */
3265                         continue;
3266
3267                 vnic_cb(&vnic, cbdata);
3268
3269                 rc = hwrm_cb(bp, &vnic);
3270                 if (rc)
3271                         break;
3272         }
3273
3274         rte_free(vnic_ids);
3275
3276         return rc;
3277 }
3278
3279 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3280                                               bool on)
3281 {
3282         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3283         struct hwrm_func_cfg_input req = {0};
3284         int rc;
3285
3286         HWRM_PREP(req, FUNC_CFG);
3287
3288         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3289         req.enables |= rte_cpu_to_le_32(
3290                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3291         req.vlan_antispoof_mode = on ?
3292                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3293                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3294         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3295
3296         HWRM_CHECK_RESULT();
3297         HWRM_UNLOCK();
3298
3299         return rc;
3300 }
3301
3302 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3303 {
3304         struct bnxt_vnic_info vnic;
3305         uint16_t *vnic_ids;
3306         size_t vnic_id_sz;
3307         int num_vnic_ids, i;
3308         size_t sz;
3309         int rc;
3310
3311         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3312         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3313                         RTE_CACHE_LINE_SIZE);
3314         if (vnic_ids == NULL) {
3315                 rc = -ENOMEM;
3316                 return rc;
3317         }
3318
3319         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3320                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3321
3322         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3323         if (rc <= 0)
3324                 goto exit;
3325         num_vnic_ids = rc;
3326
3327         /*
3328          * Loop through to find the default VNIC ID.
3329          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3330          * by sending the hwrm_func_qcfg command to the firmware.
3331          */
3332         for (i = 0; i < num_vnic_ids; i++) {
3333                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3334                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3335                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3336                                         bp->pf.first_vf_id + vf);
3337                 if (rc)
3338                         goto exit;
3339                 if (vnic.func_default) {
3340                         rte_free(vnic_ids);
3341                         return vnic.fw_vnic_id;
3342                 }
3343         }
3344         /* Could not find a default VNIC. */
3345         RTE_LOG(ERR, PMD, "No default VNIC\n");
3346 exit:
3347         rte_free(vnic_ids);
3348         return -1;
3349 }
3350
3351 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3352                          uint16_t dst_id,
3353                          struct bnxt_filter_info *filter)
3354 {
3355         int rc = 0;
3356         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3357         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3358         uint32_t enables = 0;
3359
3360         if (filter->fw_em_filter_id != UINT64_MAX)
3361                 bnxt_hwrm_clear_em_filter(bp, filter);
3362
3363         HWRM_PREP(req, CFA_EM_FLOW_ALLOC);
3364
3365         req.flags = rte_cpu_to_le_32(filter->flags);
3366
3367         enables = filter->enables |
3368               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3369         req.dst_id = rte_cpu_to_le_16(dst_id);
3370
3371         if (filter->ip_addr_type) {
3372                 req.ip_addr_type = filter->ip_addr_type;
3373                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3374         }
3375         if (enables &
3376             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3377                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3378         if (enables &
3379             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3380                 memcpy(req.src_macaddr, filter->src_macaddr,
3381                        ETHER_ADDR_LEN);
3382         if (enables &
3383             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3384                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3385                        ETHER_ADDR_LEN);
3386         if (enables &
3387             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3388                 req.ovlan_vid = filter->l2_ovlan;
3389         if (enables &
3390             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3391                 req.ivlan_vid = filter->l2_ivlan;
3392         if (enables &
3393             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3394                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3395         if (enables &
3396             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3397                 req.ip_protocol = filter->ip_protocol;
3398         if (enables &
3399             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3400                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3401         if (enables &
3402             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3403                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3404         if (enables &
3405             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3406                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3407         if (enables &
3408             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3409                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3410         if (enables &
3411             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3412                 req.mirror_vnic_id = filter->mirror_vnic_id;
3413
3414         req.enables = rte_cpu_to_le_32(enables);
3415
3416         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3417
3418         HWRM_CHECK_RESULT();
3419
3420         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3421         HWRM_UNLOCK();
3422
3423         return rc;
3424 }
3425
3426 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3427 {
3428         int rc = 0;
3429         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3430         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3431
3432         if (filter->fw_em_filter_id == UINT64_MAX)
3433                 return 0;
3434
3435         RTE_LOG(ERR, PMD, "Clear EM filter\n");
3436         HWRM_PREP(req, CFA_EM_FLOW_FREE);
3437
3438         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3439
3440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3441
3442         HWRM_CHECK_RESULT();
3443         HWRM_UNLOCK();
3444
3445         filter->fw_em_filter_id = -1;
3446         filter->fw_l2_filter_id = -1;
3447
3448         return 0;
3449 }
3450
3451 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3452                          uint16_t dst_id,
3453                          struct bnxt_filter_info *filter)
3454 {
3455         int rc = 0;
3456         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3457         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3458                                                 bp->hwrm_cmd_resp_addr;
3459         uint32_t enables = 0;
3460
3461         if (filter->fw_ntuple_filter_id != UINT64_MAX)
3462                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3463
3464         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC);
3465
3466         req.flags = rte_cpu_to_le_32(filter->flags);
3467
3468         enables = filter->enables |
3469               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3470         req.dst_id = rte_cpu_to_le_16(dst_id);
3471
3472
3473         if (filter->ip_addr_type) {
3474                 req.ip_addr_type = filter->ip_addr_type;
3475                 enables |=
3476                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3477         }
3478         if (enables &
3479             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3480                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3481         if (enables &
3482             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3483                 memcpy(req.src_macaddr, filter->src_macaddr,
3484                        ETHER_ADDR_LEN);
3485         //if (enables &
3486             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3487                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3488                        //ETHER_ADDR_LEN);
3489         if (enables &
3490             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3491                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3492         if (enables &
3493             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3494                 req.ip_protocol = filter->ip_protocol;
3495         if (enables &
3496             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3497                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3498         if (enables &
3499             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3500                 req.src_ipaddr_mask[0] =
3501                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3502         if (enables &
3503             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3504                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3505         if (enables &
3506             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3507                 req.dst_ipaddr_mask[0] =
3508                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3509         if (enables &
3510             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3511                 req.src_port = rte_cpu_to_le_16(filter->src_port);
3512         if (enables &
3513             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3514                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3515         if (enables &
3516             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3517                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3518         if (enables &
3519             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3520                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3521         if (enables &
3522             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3523                 req.mirror_vnic_id = filter->mirror_vnic_id;
3524
3525         req.enables = rte_cpu_to_le_32(enables);
3526
3527         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3528
3529         HWRM_CHECK_RESULT();
3530
3531         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3532         HWRM_UNLOCK();
3533
3534         return rc;
3535 }
3536
3537 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3538                                 struct bnxt_filter_info *filter)
3539 {
3540         int rc = 0;
3541         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3542         struct hwrm_cfa_ntuple_filter_free_output *resp =
3543                                                 bp->hwrm_cmd_resp_addr;
3544
3545         if (filter->fw_ntuple_filter_id == UINT64_MAX)
3546                 return 0;
3547
3548         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE);
3549
3550         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3551
3552         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3553
3554         HWRM_CHECK_RESULT();
3555         HWRM_UNLOCK();
3556
3557         filter->fw_ntuple_filter_id = -1;
3558         filter->fw_l2_filter_id = -1;
3559
3560         return 0;
3561 }