drivers/net/e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 #define EM_EIAC                 0x000DC
  60
  61 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  62
  63
  64 static int eth_em_configure(struct rte_eth_dev *dev);
  65 static int eth_em_start(struct rte_eth_dev *dev);
  66 static void eth_em_stop(struct rte_eth_dev *dev);
  67 static void eth_em_close(struct rte_eth_dev *dev);
  68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  72 static int eth_em_link_update(struct rte_eth_dev *dev,
  73                                 int wait_to_complete);
  74 static void eth_em_stats_get(struct rte_eth_dev *dev,
  75                                 struct rte_eth_stats *rte_stats);
  76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  77 static void eth_em_infos_get(struct rte_eth_dev *dev,
  78                                 struct rte_eth_dev_info *dev_info);
  79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  80                                 struct rte_eth_fc_conf *fc_conf);
  81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  82                                 struct rte_eth_fc_conf *fc_conf);
  83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  84 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  86 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
  87                                    struct rte_intr_handle *handle);
  88 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
  89                                                         void *param);
  90
  91 static int em_hw_init(struct e1000_hw *hw);
  92 static int em_hardware_init(struct e1000_hw *hw);
  93 static void em_hw_control_acquire(struct e1000_hw *hw);
  94 static void em_hw_control_release(struct e1000_hw *hw);
  95 static void em_init_manageability(struct e1000_hw *hw);
  96 static void em_release_manageability(struct e1000_hw *hw);
  97
  98 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  99
 100 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 101                 uint16_t vlan_id, int on);
 102 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 103 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 104 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 105 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 106 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 107
 108 /*
 109 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 110                                         uint16_t vlan_id, int on);
 111 */
 112
 113 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 114 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 115 static void em_lsc_intr_disable(struct e1000_hw *hw);
 116 static void em_rxq_intr_enable(struct e1000_hw *hw);
 117 static void em_rxq_intr_disable(struct e1000_hw *hw);
 118
 119 static int eth_em_led_on(struct rte_eth_dev *dev);
 120 static int eth_em_led_off(struct rte_eth_dev *dev);
 121
 122 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 123 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 124                 uint32_t index, uint32_t pool);
 125 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 126
 127 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
 128                                    struct ether_addr *mc_addr_set,
 129                                    uint32_t nb_mc_addr);
 130
 131 #define EM_FC_PAUSE_TIME 0x0680
 132 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 133 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 134
 135 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 136
 137 /*
 138  * The set of PCI devices this driver supports
 139  */
 140 static const struct rte_pci_id pci_id_em_map[] = {
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 158         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 159         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 160         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 161         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 162         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 163         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 164         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 165         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 166         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 167         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 168         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 169         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 170         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 171         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 172         { .vendor_id = 0, /* sentinel */ },
 173 };
 174
 175 static const struct eth_dev_ops eth_em_ops = {
 176         .dev_configure        = eth_em_configure,
 177         .dev_start            = eth_em_start,
 178         .dev_stop             = eth_em_stop,
 179         .dev_close            = eth_em_close,
 180         .promiscuous_enable   = eth_em_promiscuous_enable,
 181         .promiscuous_disable  = eth_em_promiscuous_disable,
 182         .allmulticast_enable  = eth_em_allmulticast_enable,
 183         .allmulticast_disable = eth_em_allmulticast_disable,
 184         .link_update          = eth_em_link_update,
 185         .stats_get            = eth_em_stats_get,
 186         .stats_reset          = eth_em_stats_reset,
 187         .dev_infos_get        = eth_em_infos_get,
 188         .mtu_set              = eth_em_mtu_set,
 189         .vlan_filter_set      = eth_em_vlan_filter_set,
 190         .vlan_offload_set     = eth_em_vlan_offload_set,
 191         .rx_queue_setup       = eth_em_rx_queue_setup,
 192         .rx_queue_release     = eth_em_rx_queue_release,
 193         .rx_queue_count       = eth_em_rx_queue_count,
 194         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 195         .tx_queue_setup       = eth_em_tx_queue_setup,
 196         .tx_queue_release     = eth_em_tx_queue_release,
 197         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 198         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 199         .dev_led_on           = eth_em_led_on,
 200         .dev_led_off          = eth_em_led_off,
 201         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 202         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 203         .mac_addr_add         = eth_em_rar_set,
 204         .mac_addr_remove      = eth_em_rar_clear,
 205         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 206         .rxq_info_get         = em_rxq_info_get,
 207         .txq_info_get         = em_txq_info_get,
 208 };
 209
 210 /**
 211  * Atomically reads the link status information from global
 212  * structure rte_eth_dev.
 213  *
 214  * @param dev
 215  *   - Pointer to the structure rte_eth_dev to read from.
 216  *   - Pointer to the buffer to be saved with the link status.
 217  *
 218  * @return
 219  *   - On success, zero.
 220  *   - On failure, negative value.
 221  */
 222 static inline int
 223 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 224                                 struct rte_eth_link *link)
 225 {
 226         struct rte_eth_link *dst = link;
 227         struct rte_eth_link *src = &(dev->data->dev_link);
 228
 229         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 230                                         *(uint64_t *)src) == 0)
 231                 return -1;
 232
 233         return 0;
 234 }
 235
 236 /**
 237  * Atomically writes the link status information into global
 238  * structure rte_eth_dev.
 239  *
 240  * @param dev
 241  *   - Pointer to the structure rte_eth_dev to read from.
 242  *   - Pointer to the buffer to be saved with the link status.
 243  *
 244  * @return
 245  *   - On success, zero.
 246  *   - On failure, negative value.
 247  */
 248 static inline int
 249 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 250                                 struct rte_eth_link *link)
 251 {
 252         struct rte_eth_link *dst = &(dev->data->dev_link);
 253         struct rte_eth_link *src = link;
 254
 255         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 256                                         *(uint64_t *)src) == 0)
 257                 return -1;
 258
 259         return 0;
 260 }
 261
 262 /**
 263  *  eth_em_dev_is_ich8 - Check for ICH8 device
 264  *  @hw: pointer to the HW structure
 265  *
 266  *  return TRUE for ICH8, otherwise FALSE
 267  **/
 268 static bool
 269 eth_em_dev_is_ich8(struct e1000_hw *hw)
 270 {
 271         DEBUGFUNC("eth_em_dev_is_ich8");
 272
 273         switch (hw->device_id) {
 274         case E1000_DEV_ID_PCH_LPT_I217_LM:
 275         case E1000_DEV_ID_PCH_LPT_I217_V:
 276         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 277         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 278         case E1000_DEV_ID_PCH_I218_V2:
 279         case E1000_DEV_ID_PCH_I218_LM2:
 280         case E1000_DEV_ID_PCH_I218_V3:
 281         case E1000_DEV_ID_PCH_I218_LM3:
 282                 return 1;
 283         default:
 284                 return 0;
 285         }
 286 }
 287
 288 static int
 289 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 290 {
 291         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
 292         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 293         struct e1000_adapter *adapter =
 294                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 295         struct e1000_hw *hw =
 296                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 297         struct e1000_vfta * shadow_vfta =
 298                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 299
 300         eth_dev->dev_ops = &eth_em_ops;
 301         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 302         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 303
 304         /* for secondary processes, we don't initialise any further as primary
 305          * has already done this work. Only check we don't need a different
 306          * RX function */
 307         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 308                 if (eth_dev->data->scattered_rx)
 309                         eth_dev->rx_pkt_burst =
 310                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 311                 return 0;
 312         }
 313
 314         rte_eth_copy_pci_info(eth_dev, pci_dev);
 315
 316         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 317         hw->device_id = pci_dev->id.device_id;
 318         adapter->stopped = 0;
 319
 320         /* For ICH8 support we'll need to map the flash memory BAR */
 321         if (eth_em_dev_is_ich8(hw))
 322                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 323
 324         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 325                         em_hw_init(hw) != 0) {
 326                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 327                         "failed to init HW",
 328                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 329                         pci_dev->id.device_id);
 330                 return -ENODEV;
 331         }
 332
 333         /* Allocate memory for storing MAC addresses */
 334         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 335                         hw->mac.rar_entry_count, 0);
 336         if (eth_dev->data->mac_addrs == NULL) {
 337                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 338                         "store MAC addresses",
 339                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 340                 return -ENOMEM;
 341         }
 342
 343         /* Copy the permanent MAC address */
 344         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 345                 eth_dev->data->mac_addrs);
 346
 347         /* initialize the vfta */
 348         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 349
 350         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 351                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 352                      pci_dev->id.device_id);
 353
 354         rte_intr_callback_register(intr_handle,
 355                                    eth_em_interrupt_handler, eth_dev);
 356
 357         return 0;
 358 }
 359
 360 static int
 361 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 362 {
 363         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
 364         struct e1000_adapter *adapter =
 365                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 366         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 367
 368         PMD_INIT_FUNC_TRACE();
 369
 370         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 371                 return -EPERM;
 372
 373         if (adapter->stopped == 0)
 374                 eth_em_close(eth_dev);
 375
 376         eth_dev->dev_ops = NULL;
 377         eth_dev->rx_pkt_burst = NULL;
 378         eth_dev->tx_pkt_burst = NULL;
 379
 380         rte_free(eth_dev->data->mac_addrs);
 381         eth_dev->data->mac_addrs = NULL;
 382
 383         /* disable uio intr before callback unregister */
 384         rte_intr_disable(intr_handle);
 385         rte_intr_callback_unregister(intr_handle,
 386                                      eth_em_interrupt_handler, eth_dev);
 387
 388         return 0;
 389 }
 390
 391 static struct eth_driver rte_em_pmd = {
 392         .pci_drv = {
 393                 .id_table = pci_id_em_map,
 394                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 395                         RTE_PCI_DRV_DETACHABLE,
 396                 .probe = rte_eth_dev_pci_probe,
 397                 .remove = rte_eth_dev_pci_remove,
 398         },
 399         .eth_dev_init = eth_em_dev_init,
 400         .eth_dev_uninit = eth_em_dev_uninit,
 401         .dev_private_size = sizeof(struct e1000_adapter),
 402 };
 403
 404 static int
 405 em_hw_init(struct e1000_hw *hw)
 406 {
 407         int diag;
 408
 409         diag = hw->mac.ops.init_params(hw);
 410         if (diag != 0) {
 411                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 412                 return diag;
 413         }
 414         diag = hw->nvm.ops.init_params(hw);
 415         if (diag != 0) {
 416                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 417                 return diag;
 418         }
 419         diag = hw->phy.ops.init_params(hw);
 420         if (diag != 0) {
 421                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 422                 return diag;
 423         }
 424         (void) e1000_get_bus_info(hw);
 425
 426         hw->mac.autoneg = 1;
 427         hw->phy.autoneg_wait_to_complete = 0;
 428         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 429
 430         e1000_init_script_state_82541(hw, TRUE);
 431         e1000_set_tbi_compatibility_82543(hw, TRUE);
 432
 433         /* Copper options */
 434         if (hw->phy.media_type == e1000_media_type_copper) {
 435                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 436                 hw->phy.disable_polarity_correction = 0;
 437                 hw->phy.ms_type = e1000_ms_hw_default;
 438         }
 439
 440         /*
 441          * Start from a known state, this is important in reading the nvm
 442          * and mac from that.
 443          */
 444         e1000_reset_hw(hw);
 445
 446         /* Make sure we have a good EEPROM before we read from it */
 447         if (e1000_validate_nvm_checksum(hw) < 0) {
 448                 /*
 449                  * Some PCI-E parts fail the first check due to
 450                  * the link being in sleep state, call it again,
 451                  * if it fails a second time its a real issue.
 452                  */
 453                 diag = e1000_validate_nvm_checksum(hw);
 454                 if (diag < 0) {
 455                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 456                         goto error;
 457                 }
 458         }
 459
 460         /* Read the permanent MAC address out of the EEPROM */
 461         diag = e1000_read_mac_addr(hw);
 462         if (diag != 0) {
 463                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 464                 goto error;
 465         }
 466
 467         /* Now initialize the hardware */
 468         diag = em_hardware_init(hw);
 469         if (diag != 0) {
 470                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 471                 goto error;
 472         }
 473
 474         hw->mac.get_link_status = 1;
 475
 476         /* Indicate SOL/IDER usage */
 477         diag = e1000_check_reset_block(hw);
 478         if (diag < 0) {
 479                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 480                         "SOL/IDER session");
 481         }
 482         return 0;
 483
 484 error:
 485         em_hw_control_release(hw);
 486         return diag;
 487 }
 488
 489 static int
 490 eth_em_configure(struct rte_eth_dev *dev)
 491 {
 492         struct e1000_interrupt *intr =
 493                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 494
 495         PMD_INIT_FUNC_TRACE();
 496         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 497         PMD_INIT_FUNC_TRACE();
 498
 499         return 0;
 500 }
 501
 502 static void
 503 em_set_pba(struct e1000_hw *hw)
 504 {
 505         uint32_t pba;
 506
 507         /*
 508          * Packet Buffer Allocation (PBA)
 509          * Writing PBA sets the receive portion of the buffer
 510          * the remainder is used for the transmit buffer.
 511          * Devices before the 82547 had a Packet Buffer of 64K.
 512          * After the 82547 the buffer was reduced to 40K.
 513          */
 514         switch (hw->mac.type) {
 515                 case e1000_82547:
 516                 case e1000_82547_rev_2:
 517                 /* 82547: Total Packet Buffer is 40K */
 518                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 519                         break;
 520                 case e1000_82571:
 521                 case e1000_82572:
 522                 case e1000_80003es2lan:
 523                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 524                         break;
 525                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 526                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 527                         break;
 528                 case e1000_82574:
 529                 case e1000_82583:
 530                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 531                         break;
 532                 case e1000_ich8lan:
 533                         pba = E1000_PBA_8K;
 534                         break;
 535                 case e1000_ich9lan:
 536                 case e1000_ich10lan:
 537                         pba = E1000_PBA_10K;
 538                         break;
 539                 case e1000_pchlan:
 540                 case e1000_pch2lan:
 541                 case e1000_pch_lpt:
 542                         pba = E1000_PBA_26K;
 543                         break;
 544                 default:
 545                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 546         }
 547
 548         E1000_WRITE_REG(hw, E1000_PBA, pba);
 549 }
 550
 551 static int
 552 eth_em_start(struct rte_eth_dev *dev)
 553 {
 554         struct e1000_adapter *adapter =
 555                 E1000_DEV_PRIVATE(dev->data->dev_private);
 556         struct e1000_hw *hw =
 557                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 558         struct rte_pci_device *pci_dev =
 559                 E1000_DEV_TO_PCI(dev);
 560         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 561         int ret, mask;
 562         uint32_t intr_vector = 0;
 563         uint32_t *speeds;
 564         int num_speeds;
 565         bool autoneg;
 566
 567         PMD_INIT_FUNC_TRACE();
 568
 569         eth_em_stop(dev);
 570
 571         e1000_power_up_phy(hw);
 572
 573         /* Set default PBA value */
 574         em_set_pba(hw);
 575
 576         /* Put the address into the Receive Address Array */
 577         e1000_rar_set(hw, hw->mac.addr, 0);
 578
 579         /*
 580          * With the 82571 adapter, RAR[0] may be overwritten
 581          * when the other port is reset, we make a duplicate
 582          * in RAR[14] for that eventuality, this assures
 583          * the interface continues to function.
 584          */
 585         if (hw->mac.type == e1000_82571) {
 586                 e1000_set_laa_state_82571(hw, TRUE);
 587                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 588         }
 589
 590         /* Initialize the hardware */
 591         if (em_hardware_init(hw)) {
 592                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 593                 return -EIO;
 594         }
 595
 596         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 597
 598         /* Configure for OS presence */
 599         em_init_manageability(hw);
 600
 601         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 602                 intr_vector = dev->data->nb_rx_queues;
 603                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 604                         return -1;
 605         }
 606
 607         if (rte_intr_dp_is_en(intr_handle)) {
 608                 intr_handle->intr_vec =
 609                         rte_zmalloc("intr_vec",
 610                                         dev->data->nb_rx_queues * sizeof(int), 0);
 611                 if (intr_handle->intr_vec == NULL) {
 612                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 613                                                 " intr_vec\n", dev->data->nb_rx_queues);
 614                         return -ENOMEM;
 615                 }
 616
 617                 /* enable rx interrupt */
 618                 em_rxq_intr_enable(hw);
 619         }
 620
 621         eth_em_tx_init(dev);
 622
 623         ret = eth_em_rx_init(dev);
 624         if (ret) {
 625                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 626                 em_dev_clear_queues(dev);
 627                 return ret;
 628         }
 629
 630         e1000_clear_hw_cntrs_base_generic(hw);
 631
 632         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 633                         ETH_VLAN_EXTEND_MASK;
 634         eth_em_vlan_offload_set(dev, mask);
 635
 636         /* Set Interrupt Throttling Rate to maximum allowed value. */
 637         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 638
 639         /* Setup link speed and duplex */
 640         speeds = &dev->data->dev_conf.link_speeds;
 641         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 642                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 643                 hw->mac.autoneg = 1;
 644         } else {
 645                 num_speeds = 0;
 646                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 647
 648                 /* Reset */
 649                 hw->phy.autoneg_advertised = 0;
 650
 651                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 652                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 653                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 654                         num_speeds = -1;
 655                         goto error_invalid_config;
 656                 }
 657                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 658                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 659                         num_speeds++;
 660                 }
 661                 if (*speeds & ETH_LINK_SPEED_10M) {
 662                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 663                         num_speeds++;
 664                 }
 665                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 666                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 667                         num_speeds++;
 668                 }
 669                 if (*speeds & ETH_LINK_SPEED_100M) {
 670                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 671                         num_speeds++;
 672                 }
 673                 if (*speeds & ETH_LINK_SPEED_1G) {
 674                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 675                         num_speeds++;
 676                 }
 677                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 678                         goto error_invalid_config;
 679
 680                 /* Set/reset the mac.autoneg based on the link speed,
 681                  * fixed or not
 682                  */
 683                 if (!autoneg) {
 684                         hw->mac.autoneg = 0;
 685                         hw->mac.forced_speed_duplex =
 686                                         hw->phy.autoneg_advertised;
 687                 } else {
 688                         hw->mac.autoneg = 1;
 689                 }
 690         }
 691
 692         e1000_setup_link(hw);
 693
 694         if (rte_intr_allow_others(intr_handle)) {
 695                 /* check if lsc interrupt is enabled */
 696                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 697                         ret = eth_em_interrupt_setup(dev);
 698                         if (ret) {
 699                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 700                                 em_dev_clear_queues(dev);
 701                                 return ret;
 702                         }
 703                 }
 704         } else {
 705                 rte_intr_callback_unregister(intr_handle,
 706                                                 eth_em_interrupt_handler,
 707                                                 (void *)dev);
 708                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 709                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 710                                      " no intr multiplex\n");
 711         }
 712         /* check if rxq interrupt is enabled */
 713         if (dev->data->dev_conf.intr_conf.rxq != 0)
 714                 eth_em_rxq_interrupt_setup(dev);
 715
 716         rte_intr_enable(intr_handle);
 717
 718         adapter->stopped = 0;
 719
 720         PMD_INIT_LOG(DEBUG, "<<");
 721
 722         return 0;
 723
 724 error_invalid_config:
 725         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 726                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 727         em_dev_clear_queues(dev);
 728         return -EINVAL;
 729 }
 730
 731 /*********************************************************************
 732  *
 733  *  This routine disables all traffic on the adapter by issuing a
 734  *  global reset on the MAC.
 735  *
 736  **********************************************************************/
 737 static void
 738 eth_em_stop(struct rte_eth_dev *dev)
 739 {
 740         struct rte_eth_link link;
 741         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 742         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
 743         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 744
 745         em_rxq_intr_disable(hw);
 746         em_lsc_intr_disable(hw);
 747
 748         e1000_reset_hw(hw);
 749         if (hw->mac.type >= e1000_82544)
 750                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 751
 752         /* Power down the phy. Needed to make the link go down */
 753         e1000_power_down_phy(hw);
 754
 755         em_dev_clear_queues(dev);
 756
 757         /* clear the recorded link status */
 758         memset(&link, 0, sizeof(link));
 759         rte_em_dev_atomic_write_link_status(dev, &link);
 760
 761         if (!rte_intr_allow_others(intr_handle))
 762                 /* resume to the default handler */
 763                 rte_intr_callback_register(intr_handle,
 764                                            eth_em_interrupt_handler,
 765                                            (void *)dev);
 766
 767         /* Clean datapath event and queue/vec mapping */
 768         rte_intr_efd_disable(intr_handle);
 769         if (intr_handle->intr_vec != NULL) {
 770                 rte_free(intr_handle->intr_vec);
 771                 intr_handle->intr_vec = NULL;
 772         }
 773 }
 774
 775 static void
 776 eth_em_close(struct rte_eth_dev *dev)
 777 {
 778         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 779         struct e1000_adapter *adapter =
 780                 E1000_DEV_PRIVATE(dev->data->dev_private);
 781
 782         eth_em_stop(dev);
 783         adapter->stopped = 1;
 784         em_dev_free_queues(dev);
 785         e1000_phy_hw_reset(hw);
 786         em_release_manageability(hw);
 787         em_hw_control_release(hw);
 788 }
 789
 790 static int
 791 em_get_rx_buffer_size(struct e1000_hw *hw)
 792 {
 793         uint32_t rx_buf_size;
 794
 795         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 796         return rx_buf_size;
 797 }
 798
 799 /*********************************************************************
 800  *
 801  *  Initialize the hardware
 802  *
 803  **********************************************************************/
 804 static int
 805 em_hardware_init(struct e1000_hw *hw)
 806 {
 807         uint32_t rx_buf_size;
 808         int diag;
 809
 810         /* Issue a global reset */
 811         e1000_reset_hw(hw);
 812
 813         /* Let the firmware know the OS is in control */
 814         em_hw_control_acquire(hw);
 815
 816         /*
 817          * These parameters control the automatic generation (Tx) and
 818          * response (Rx) to Ethernet PAUSE frames.
 819          * - High water mark should allow for at least two standard size (1518)
 820          *   frames to be received after sending an XOFF.
 821          * - Low water mark works best when it is very near the high water mark.
 822          *   This allows the receiver to restart by sending XON when it has
 823          *   drained a bit. Here we use an arbitrary value of 1500 which will
 824          *   restart after one full frame is pulled from the buffer. There
 825          *   could be several smaller frames in the buffer and if so they will
 826          *   not trigger the XON until their total number reduces the buffer
 827          *   by 1500.
 828          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 829          */
 830         rx_buf_size = em_get_rx_buffer_size(hw);
 831
 832         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 833         hw->fc.low_water = hw->fc.high_water - 1500;
 834
 835         if (hw->mac.type == e1000_80003es2lan)
 836                 hw->fc.pause_time = UINT16_MAX;
 837         else
 838                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 839
 840         hw->fc.send_xon = 1;
 841
 842         /* Set Flow control, use the tunable location if sane */
 843         if (em_fc_setting <= e1000_fc_full)
 844                 hw->fc.requested_mode = em_fc_setting;
 845         else
 846                 hw->fc.requested_mode = e1000_fc_none;
 847
 848         /* Workaround: no TX flow ctrl for PCH */
 849         if (hw->mac.type == e1000_pchlan)
 850                 hw->fc.requested_mode = e1000_fc_rx_pause;
 851
 852         /* Override - settings for PCH2LAN, ya its magic :) */
 853         if (hw->mac.type == e1000_pch2lan) {
 854                 hw->fc.high_water = 0x5C20;
 855                 hw->fc.low_water = 0x5048;
 856                 hw->fc.pause_time = 0x0650;
 857                 hw->fc.refresh_time = 0x0400;
 858         } else if (hw->mac.type == e1000_pch_lpt) {
 859                 hw->fc.requested_mode = e1000_fc_full;
 860         }
 861
 862         diag = e1000_init_hw(hw);
 863         if (diag < 0)
 864                 return diag;
 865         e1000_check_for_link(hw);
 866         return 0;
 867 }
 868
 869 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 870 static void
 871 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 872 {
 873         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 874         struct e1000_hw_stats *stats =
 875                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 876         int pause_frames;
 877
 878         if(hw->phy.media_type == e1000_media_type_copper ||
 879                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 880                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 881                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 882         }
 883
 884         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 885         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 886         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 887         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 888
 889         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 890         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 891         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 892         stats->dc += E1000_READ_REG(hw, E1000_DC);
 893         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 894         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 895         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 896
 897         /*
 898          * For watchdog management we need to know if we have been
 899          * paused during the last interval, so capture that here.
 900          */
 901         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 902         stats->xoffrxc += pause_frames;
 903         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 904         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 905         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 906         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 907         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 908         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 909         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 910         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 911         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 912         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 913         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 914         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 915
 916         /*
 917          * For the 64-bit byte counters the low dword must be read first.
 918          * Both registers clear on the read of the high dword.
 919          */
 920
 921         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 922         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 923         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 924         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 925
 926         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 927         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 928         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 929         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 930         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 931
 932         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 933         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 934
 935         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 936         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 937         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 938         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 939         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 940         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 941         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 942         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 943         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 944         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 945
 946         /* Interrupt Counts */
 947
 948         if (hw->mac.type >= e1000_82571) {
 949                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 950                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 951                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 952                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 953                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 954                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 955                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 956                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 957                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 958         }
 959
 960         if (hw->mac.type >= e1000_82543) {
 961                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 962                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 963                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 964                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 965                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 966                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 967         }
 968
 969         if (rte_stats == NULL)
 970                 return;
 971
 972         /* Rx Errors */
 973         rte_stats->imissed = stats->mpc;
 974         rte_stats->ierrors = stats->crcerrs +
 975                              stats->rlec + stats->ruc + stats->roc +
 976                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 977
 978         /* Tx Errors */
 979         rte_stats->oerrors = stats->ecol + stats->latecol;
 980
 981         rte_stats->ipackets = stats->gprc;
 982         rte_stats->opackets = stats->gptc;
 983         rte_stats->ibytes   = stats->gorc;
 984         rte_stats->obytes   = stats->gotc;
 985 }
 986
 987 static void
 988 eth_em_stats_reset(struct rte_eth_dev *dev)
 989 {
 990         struct e1000_hw_stats *hw_stats =
 991                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 992
 993         /* HW registers are cleared on read */
 994         eth_em_stats_get(dev, NULL);
 995
 996         /* Reset software totals */
 997         memset(hw_stats, 0, sizeof(*hw_stats));
 998 }
 999
1000 static int
1001 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1002 {
1003         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1004         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1005         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1006
1007         em_rxq_intr_enable(hw);
1008         rte_intr_enable(intr_handle);
1009
1010         return 0;
1011 }
1012
1013 static int
1014 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1015 {
1016         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1017
1018         em_rxq_intr_disable(hw);
1019
1020         return 0;
1021 }
1022
1023 static uint32_t
1024 em_get_max_pktlen(const struct e1000_hw *hw)
1025 {
1026         switch (hw->mac.type) {
1027         case e1000_82571:
1028         case e1000_82572:
1029         case e1000_ich9lan:
1030         case e1000_ich10lan:
1031         case e1000_pch2lan:
1032         case e1000_pch_lpt:
1033         case e1000_82574:
1034         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1035         case e1000_82583:
1036                 return 0x2412;
1037         case e1000_pchlan:
1038                 return 0x1000;
1039         /* Adapters that do not support jumbo frames */
1040         case e1000_ich8lan:
1041                 return ETHER_MAX_LEN;
1042         default:
1043                 return MAX_JUMBO_FRAME_SIZE;
1044         }
1045 }
1046
1047 static void
1048 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1049 {
1050         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1051
1052         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1053         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1054         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1055         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1056
1057         /*
1058          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1059          * Unfortunatelly, all these nics have just one TX context.
1060          * So we have few choises for TX:
1061          * - Use just one TX queue.
1062          * - Allow cksum offload only for one TX queue.
1063          * - Don't allow TX cksum offload at all.
1064          * For now, option #1 was chosen.
1065          * To use second RX queue we have to use extended RX descriptor
1066          * (Multiple Receive Queues are mutually exclusive with UDP
1067          * fragmentation and are not supported when a legacy receive
1068          * descriptor format is used).
1069          * Which means separate RX routinies - as legacy nics (82540, 82545)
1070          * don't support extended RXD.
1071          * To avoid it we support just one RX queue for now (no RSS).
1072          */
1073
1074         dev_info->max_rx_queues = 1;
1075         dev_info->max_tx_queues = 1;
1076
1077         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1078                 .nb_max = E1000_MAX_RING_DESC,
1079                 .nb_min = E1000_MIN_RING_DESC,
1080                 .nb_align = EM_RXD_ALIGN,
1081         };
1082
1083         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1084                 .nb_max = E1000_MAX_RING_DESC,
1085                 .nb_min = E1000_MIN_RING_DESC,
1086                 .nb_align = EM_TXD_ALIGN,
1087         };
1088
1089         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1090                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1091                         ETH_LINK_SPEED_1G;
1092 }
1093
1094 /* return 0 means link status changed, -1 means not changed */
1095 static int
1096 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1097 {
1098         struct e1000_hw *hw =
1099                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1100         struct rte_eth_link link, old;
1101         int link_check, count;
1102
1103         link_check = 0;
1104         hw->mac.get_link_status = 1;
1105
1106         /* possible wait-to-complete in up to 9 seconds */
1107         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1108                 /* Read the real link status */
1109                 switch (hw->phy.media_type) {
1110                 case e1000_media_type_copper:
1111                         /* Do the work to read phy */
1112                         e1000_check_for_link(hw);
1113                         link_check = !hw->mac.get_link_status;
1114                         break;
1115
1116                 case e1000_media_type_fiber:
1117                         e1000_check_for_link(hw);
1118                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1119                                         E1000_STATUS_LU);
1120                         break;
1121
1122                 case e1000_media_type_internal_serdes:
1123                         e1000_check_for_link(hw);
1124                         link_check = hw->mac.serdes_has_link;
1125                         break;
1126
1127                 default:
1128                         break;
1129                 }
1130                 if (link_check || wait_to_complete == 0)
1131                         break;
1132                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1133         }
1134         memset(&link, 0, sizeof(link));
1135         rte_em_dev_atomic_read_link_status(dev, &link);
1136         old = link;
1137
1138         /* Now we check if a transition has happened */
1139         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1140                 uint16_t duplex, speed;
1141                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1142                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1143                                 ETH_LINK_FULL_DUPLEX :
1144                                 ETH_LINK_HALF_DUPLEX;
1145                 link.link_speed = speed;
1146                 link.link_status = ETH_LINK_UP;
1147                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1148                                 ETH_LINK_SPEED_FIXED);
1149         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1150                 link.link_speed = 0;
1151                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1152                 link.link_status = ETH_LINK_DOWN;
1153                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1154         }
1155         rte_em_dev_atomic_write_link_status(dev, &link);
1156
1157         /* not changed */
1158         if (old.link_status == link.link_status)
1159                 return -1;
1160
1161         /* changed */
1162         return 0;
1163 }
1164
1165 /*
1166  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1167  * For ASF and Pass Through versions of f/w this means
1168  * that the driver is loaded. For AMT version type f/w
1169  * this means that the network i/f is open.
1170  */
1171 static void
1172 em_hw_control_acquire(struct e1000_hw *hw)
1173 {
1174         uint32_t ctrl_ext, swsm;
1175
1176         /* Let firmware know the driver has taken over */
1177         if (hw->mac.type == e1000_82573) {
1178                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1179                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1180
1181         } else {
1182                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1183                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1184                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1185         }
1186 }
1187
1188 /*
1189  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1190  * For ASF and Pass Through versions of f/w this means that the
1191  * driver is no longer loaded. For AMT versions of the
1192  * f/w this means that the network i/f is closed.
1193  */
1194 static void
1195 em_hw_control_release(struct e1000_hw *hw)
1196 {
1197         uint32_t ctrl_ext, swsm;
1198
1199         /* Let firmware taken over control of h/w */
1200         if (hw->mac.type == e1000_82573) {
1201                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1202                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1203         } else {
1204                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1205                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1206                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1207         }
1208 }
1209
1210 /*
1211  * Bit of a misnomer, what this really means is
1212  * to enable OS management of the system... aka
1213  * to disable special hardware management features.
1214  */
1215 static void
1216 em_init_manageability(struct e1000_hw *hw)
1217 {
1218         if (e1000_enable_mng_pass_thru(hw)) {
1219                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1220                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1221
1222                 /* disable hardware interception of ARP */
1223                 manc &= ~(E1000_MANC_ARP_EN);
1224
1225                 /* enable receiving management packets to the host */
1226                 manc |= E1000_MANC_EN_MNG2HOST;
1227                 manc2h |= 1 << 5;  /* Mng Port 623 */
1228                 manc2h |= 1 << 6;  /* Mng Port 664 */
1229                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1230                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1231         }
1232 }
1233
1234 /*
1235  * Give control back to hardware management
1236  * controller if there is one.
1237  */
1238 static void
1239 em_release_manageability(struct e1000_hw *hw)
1240 {
1241         uint32_t manc;
1242
1243         if (e1000_enable_mng_pass_thru(hw)) {
1244                 manc = E1000_READ_REG(hw, E1000_MANC);
1245
1246                 /* re-enable hardware interception of ARP */
1247                 manc |= E1000_MANC_ARP_EN;
1248                 manc &= ~E1000_MANC_EN_MNG2HOST;
1249
1250                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1251         }
1252 }
1253
1254 static void
1255 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1256 {
1257         struct e1000_hw *hw =
1258                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1259         uint32_t rctl;
1260
1261         rctl = E1000_READ_REG(hw, E1000_RCTL);
1262         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1263         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1264 }
1265
1266 static void
1267 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1268 {
1269         struct e1000_hw *hw =
1270                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1271         uint32_t rctl;
1272
1273         rctl = E1000_READ_REG(hw, E1000_RCTL);
1274         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1275         if (dev->data->all_multicast == 1)
1276                 rctl |= E1000_RCTL_MPE;
1277         else
1278                 rctl &= (~E1000_RCTL_MPE);
1279         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1280 }
1281
1282 static void
1283 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1284 {
1285         struct e1000_hw *hw =
1286                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1287         uint32_t rctl;
1288
1289         rctl = E1000_READ_REG(hw, E1000_RCTL);
1290         rctl |= E1000_RCTL_MPE;
1291         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1292 }
1293
1294 static void
1295 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1296 {
1297         struct e1000_hw *hw =
1298                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1299         uint32_t rctl;
1300
1301         if (dev->data->promiscuous == 1)
1302                 return; /* must remain in all_multicast mode */
1303         rctl = E1000_READ_REG(hw, E1000_RCTL);
1304         rctl &= (~E1000_RCTL_MPE);
1305         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1306 }
1307
1308 static int
1309 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1310 {
1311         struct e1000_hw *hw =
1312                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1313         struct e1000_vfta * shadow_vfta =
1314                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1315         uint32_t vfta;
1316         uint32_t vid_idx;
1317         uint32_t vid_bit;
1318
1319         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1320                               E1000_VFTA_ENTRY_MASK);
1321         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1322         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1323         if (on)
1324                 vfta |= vid_bit;
1325         else
1326                 vfta &= ~vid_bit;
1327         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1328
1329         /* update local VFTA copy */
1330         shadow_vfta->vfta[vid_idx] = vfta;
1331
1332         return 0;
1333 }
1334
1335 static void
1336 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1337 {
1338         struct e1000_hw *hw =
1339                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1340         uint32_t reg;
1341
1342         /* Filter Table Disable */
1343         reg = E1000_READ_REG(hw, E1000_RCTL);
1344         reg &= ~E1000_RCTL_CFIEN;
1345         reg &= ~E1000_RCTL_VFE;
1346         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1347 }
1348
1349 static void
1350 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1351 {
1352         struct e1000_hw *hw =
1353                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1354         struct e1000_vfta * shadow_vfta =
1355                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1356         uint32_t reg;
1357         int i;
1358
1359         /* Filter Table Enable, CFI not used for packet acceptance */
1360         reg = E1000_READ_REG(hw, E1000_RCTL);
1361         reg &= ~E1000_RCTL_CFIEN;
1362         reg |= E1000_RCTL_VFE;
1363         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1364
1365         /* restore vfta from local copy */
1366         for (i = 0; i < IGB_VFTA_SIZE; i++)
1367                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1368 }
1369
1370 static void
1371 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1372 {
1373         struct e1000_hw *hw =
1374                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1375         uint32_t reg;
1376
1377         /* VLAN Mode Disable */
1378         reg = E1000_READ_REG(hw, E1000_CTRL);
1379         reg &= ~E1000_CTRL_VME;
1380         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1381
1382 }
1383
1384 static void
1385 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1386 {
1387         struct e1000_hw *hw =
1388                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1389         uint32_t reg;
1390
1391         /* VLAN Mode Enable */
1392         reg = E1000_READ_REG(hw, E1000_CTRL);
1393         reg |= E1000_CTRL_VME;
1394         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1395 }
1396
1397 static void
1398 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1399 {
1400         if(mask & ETH_VLAN_STRIP_MASK){
1401                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1402                         em_vlan_hw_strip_enable(dev);
1403                 else
1404                         em_vlan_hw_strip_disable(dev);
1405         }
1406
1407         if(mask & ETH_VLAN_FILTER_MASK){
1408                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1409                         em_vlan_hw_filter_enable(dev);
1410                 else
1411                         em_vlan_hw_filter_disable(dev);
1412         }
1413 }
1414
1415 /*
1416  * It enables the interrupt mask and then enable the interrupt.
1417  *
1418  * @param dev
1419  *  Pointer to struct rte_eth_dev.
1420  *
1421  * @return
1422  *  - On success, zero.
1423  *  - On failure, a negative value.
1424  */
1425 static int
1426 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1427 {
1428         uint32_t regval;
1429         struct e1000_hw *hw =
1430                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1431
1432         /* clear interrupt */
1433         E1000_READ_REG(hw, E1000_ICR);
1434         regval = E1000_READ_REG(hw, E1000_IMS);
1435         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1436         return 0;
1437 }
1438
1439 /*
1440  * It clears the interrupt causes and enables the interrupt.
1441  * It will be called once only during nic initialized.
1442  *
1443  * @param dev
1444  *  Pointer to struct rte_eth_dev.
1445  *
1446  * @return
1447  *  - On success, zero.
1448  *  - On failure, a negative value.
1449  */
1450 static int
1451 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1452 {
1453         struct e1000_hw *hw =
1454         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1455
1456         E1000_READ_REG(hw, E1000_ICR);
1457         em_rxq_intr_enable(hw);
1458         return 0;
1459 }
1460
1461 /*
1462  * It enable receive packet interrupt.
1463  * @param hw
1464  * Pointer to struct e1000_hw
1465  *
1466  * @return
1467  */
1468 static void
1469 em_rxq_intr_enable(struct e1000_hw *hw)
1470 {
1471         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1472         E1000_WRITE_FLUSH(hw);
1473 }
1474
1475 /*
1476  * It disabled lsc interrupt.
1477  * @param hw
1478  * Pointer to struct e1000_hw
1479  *
1480  * @return
1481  */
1482 static void
1483 em_lsc_intr_disable(struct e1000_hw *hw)
1484 {
1485         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1486         E1000_WRITE_FLUSH(hw);
1487 }
1488
1489 /*
1490  * It disabled receive packet interrupt.
1491  * @param hw
1492  * Pointer to struct e1000_hw
1493  *
1494  * @return
1495  */
1496 static void
1497 em_rxq_intr_disable(struct e1000_hw *hw)
1498 {
1499         E1000_READ_REG(hw, E1000_ICR);
1500         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1501         E1000_WRITE_FLUSH(hw);
1502 }
1503
1504 /*
1505  * It reads ICR and gets interrupt causes, check it and set a bit flag
1506  * to update link status.
1507  *
1508  * @param dev
1509  *  Pointer to struct rte_eth_dev.
1510  *
1511  * @return
1512  *  - On success, zero.
1513  *  - On failure, a negative value.
1514  */
1515 static int
1516 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1517 {
1518         uint32_t icr;
1519         struct e1000_hw *hw =
1520                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1521         struct e1000_interrupt *intr =
1522                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1523
1524         /* read-on-clear nic registers here */
1525         icr = E1000_READ_REG(hw, E1000_ICR);
1526         if (icr & E1000_ICR_LSC) {
1527                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1528         }
1529
1530         return 0;
1531 }
1532
1533 /*
1534  * It executes link_update after knowing an interrupt is prsent.
1535  *
1536  * @param dev
1537  *  Pointer to struct rte_eth_dev.
1538  *
1539  * @return
1540  *  - On success, zero.
1541  *  - On failure, a negative value.
1542  */
1543 static int
1544 eth_em_interrupt_action(struct rte_eth_dev *dev,
1545                         struct rte_intr_handle *intr_handle)
1546 {
1547         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1548         struct e1000_hw *hw =
1549                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1550         struct e1000_interrupt *intr =
1551                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1552         uint32_t tctl, rctl;
1553         struct rte_eth_link link;
1554         int ret;
1555
1556         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1557                 return -1;
1558
1559         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1560         rte_intr_enable(intr_handle);
1561
1562         /* set get_link_status to check register later */
1563         hw->mac.get_link_status = 1;
1564         ret = eth_em_link_update(dev, 0);
1565
1566         /* check if link has changed */
1567         if (ret < 0)
1568                 return 0;
1569
1570         memset(&link, 0, sizeof(link));
1571         rte_em_dev_atomic_read_link_status(dev, &link);
1572         if (link.link_status) {
1573                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1574                              dev->data->port_id, (unsigned)link.link_speed,
1575                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1576                              "full-duplex" : "half-duplex");
1577         } else {
1578                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1579         }
1580         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1581                      pci_dev->addr.domain, pci_dev->addr.bus,
1582                      pci_dev->addr.devid, pci_dev->addr.function);
1583
1584         tctl = E1000_READ_REG(hw, E1000_TCTL);
1585         rctl = E1000_READ_REG(hw, E1000_RCTL);
1586         if (link.link_status) {
1587                 /* enable Tx/Rx */
1588                 tctl |= E1000_TCTL_EN;
1589                 rctl |= E1000_RCTL_EN;
1590         } else {
1591                 /* disable Tx/Rx */
1592                 tctl &= ~E1000_TCTL_EN;
1593                 rctl &= ~E1000_RCTL_EN;
1594         }
1595         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1596         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1597         E1000_WRITE_FLUSH(hw);
1598
1599         return 0;
1600 }
1601
1602 /**
1603  * Interrupt handler which shall be registered at first.
1604  *
1605  * @param handle
1606  *  Pointer to interrupt handle.
1607  * @param param
1608  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1609  *
1610  * @return
1611  *  void
1612  */
1613 static void
1614 eth_em_interrupt_handler(struct rte_intr_handle *handle,
1615                          void *param)
1616 {
1617         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1618
1619         eth_em_interrupt_get_status(dev);
1620         eth_em_interrupt_action(dev, handle);
1621         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1622 }
1623
1624 static int
1625 eth_em_led_on(struct rte_eth_dev *dev)
1626 {
1627         struct e1000_hw *hw;
1628
1629         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1630         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1631 }
1632
1633 static int
1634 eth_em_led_off(struct rte_eth_dev *dev)
1635 {
1636         struct e1000_hw *hw;
1637
1638         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1639         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1640 }
1641
1642 static int
1643 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1644 {
1645         struct e1000_hw *hw;
1646         uint32_t ctrl;
1647         int tx_pause;
1648         int rx_pause;
1649
1650         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1651         fc_conf->pause_time = hw->fc.pause_time;
1652         fc_conf->high_water = hw->fc.high_water;
1653         fc_conf->low_water = hw->fc.low_water;
1654         fc_conf->send_xon = hw->fc.send_xon;
1655         fc_conf->autoneg = hw->mac.autoneg;
1656
1657         /*
1658          * Return rx_pause and tx_pause status according to actual setting of
1659          * the TFCE and RFCE bits in the CTRL register.
1660          */
1661         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1662         if (ctrl & E1000_CTRL_TFCE)
1663                 tx_pause = 1;
1664         else
1665                 tx_pause = 0;
1666
1667         if (ctrl & E1000_CTRL_RFCE)
1668                 rx_pause = 1;
1669         else
1670                 rx_pause = 0;
1671
1672         if (rx_pause && tx_pause)
1673                 fc_conf->mode = RTE_FC_FULL;
1674         else if (rx_pause)
1675                 fc_conf->mode = RTE_FC_RX_PAUSE;
1676         else if (tx_pause)
1677                 fc_conf->mode = RTE_FC_TX_PAUSE;
1678         else
1679                 fc_conf->mode = RTE_FC_NONE;
1680
1681         return 0;
1682 }
1683
1684 static int
1685 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1686 {
1687         struct e1000_hw *hw;
1688         int err;
1689         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1690                 e1000_fc_none,
1691                 e1000_fc_rx_pause,
1692                 e1000_fc_tx_pause,
1693                 e1000_fc_full
1694         };
1695         uint32_t rx_buf_size;
1696         uint32_t max_high_water;
1697         uint32_t rctl;
1698
1699         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1700         if (fc_conf->autoneg != hw->mac.autoneg)
1701                 return -ENOTSUP;
1702         rx_buf_size = em_get_rx_buffer_size(hw);
1703         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1704
1705         /* At least reserve one Ethernet frame for watermark */
1706         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1707         if ((fc_conf->high_water > max_high_water) ||
1708             (fc_conf->high_water < fc_conf->low_water)) {
1709                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1710                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1711                 return -EINVAL;
1712         }
1713
1714         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1715         hw->fc.pause_time     = fc_conf->pause_time;
1716         hw->fc.high_water     = fc_conf->high_water;
1717         hw->fc.low_water      = fc_conf->low_water;
1718         hw->fc.send_xon       = fc_conf->send_xon;
1719
1720         err = e1000_setup_link_generic(hw);
1721         if (err == E1000_SUCCESS) {
1722
1723                 /* check if we want to forward MAC frames - driver doesn't have native
1724                  * capability to do that, so we'll write the registers ourselves */
1725
1726                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1727
1728                 /* set or clear MFLCN.PMCF bit depending on configuration */
1729                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1730                         rctl |= E1000_RCTL_PMCF;
1731                 else
1732                         rctl &= ~E1000_RCTL_PMCF;
1733
1734                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1735                 E1000_WRITE_FLUSH(hw);
1736
1737                 return 0;
1738         }
1739
1740         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1741         return -EIO;
1742 }
1743
1744 static void
1745 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1746                 uint32_t index, __rte_unused uint32_t pool)
1747 {
1748         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1749
1750         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1751 }
1752
1753 static void
1754 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1755 {
1756         uint8_t addr[ETHER_ADDR_LEN];
1757         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1758
1759         memset(addr, 0, sizeof(addr));
1760
1761         e1000_rar_set(hw, addr, index);
1762 }
1763
1764 static int
1765 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1766 {
1767         struct rte_eth_dev_info dev_info;
1768         struct e1000_hw *hw;
1769         uint32_t frame_size;
1770         uint32_t rctl;
1771
1772         eth_em_infos_get(dev, &dev_info);
1773         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1774
1775         /* check that mtu is within the allowed range */
1776         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1777                 return -EINVAL;
1778
1779         /* refuse mtu that requires the support of scattered packets when this
1780          * feature has not been enabled before. */
1781         if (!dev->data->scattered_rx &&
1782             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1783                 return -EINVAL;
1784
1785         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1786         rctl = E1000_READ_REG(hw, E1000_RCTL);
1787
1788         /* switch to jumbo mode if needed */
1789         if (frame_size > ETHER_MAX_LEN) {
1790                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1791                 rctl |= E1000_RCTL_LPE;
1792         } else {
1793                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1794                 rctl &= ~E1000_RCTL_LPE;
1795         }
1796         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1797
1798         /* update max frame size */
1799         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1800         return 0;
1801 }
1802
1803 static int
1804 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1805                         struct ether_addr *mc_addr_set,
1806                         uint32_t nb_mc_addr)
1807 {
1808         struct e1000_hw *hw;
1809
1810         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1811         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1812         return 0;
1813 }
1814
1815 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd.pci_drv);
1816 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1817 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio");