5f6e66dd4abd5a86cea0d50f75bef7d9859f024e
[dpdk.git] / drivers / net / e1000 / em_ethdev.c
1 /*-
2  *   BSD LICENSE
3  *
4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
5  *   All rights reserved.
6  *
7  *   Redistribution and use in source and binary forms, with or without
8  *   modification, are permitted provided that the following conditions
9  *   are met:
10  *
11  *     * Redistributions of source code must retain the above copyright
12  *       notice, this list of conditions and the following disclaimer.
13  *     * Redistributions in binary form must reproduce the above copyright
14  *       notice, this list of conditions and the following disclaimer in
15  *       the documentation and/or other materials provided with the
16  *       distribution.
17  *     * Neither the name of Intel Corporation nor the names of its
18  *       contributors may be used to endorse or promote products derived
19  *       from this software without specific prior written permission.
20  *
21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33
34 #include <sys/queue.h>
35 #include <stdio.h>
36 #include <errno.h>
37 #include <stdint.h>
38 #include <stdarg.h>
39
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
43 #include <rte_log.h>
44 #include <rte_debug.h>
45 #include <rte_pci.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
50 #include <rte_eal.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
53 #include <rte_dev.h>
54
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
58
59 #define EM_EIAC                 0x000DC
60
61 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
62
63
64 static int eth_em_configure(struct rte_eth_dev *dev);
65 static int eth_em_start(struct rte_eth_dev *dev);
66 static void eth_em_stop(struct rte_eth_dev *dev);
67 static void eth_em_close(struct rte_eth_dev *dev);
68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
72 static int eth_em_link_update(struct rte_eth_dev *dev,
73                                 int wait_to_complete);
74 static void eth_em_stats_get(struct rte_eth_dev *dev,
75                                 struct rte_eth_stats *rte_stats);
76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
77 static void eth_em_infos_get(struct rte_eth_dev *dev,
78                                 struct rte_eth_dev_info *dev_info);
79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
80                                 struct rte_eth_fc_conf *fc_conf);
81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
82                                 struct rte_eth_fc_conf *fc_conf);
83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
84 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
86 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
87                                    struct rte_intr_handle *handle);
88 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
89                                                         void *param);
90
91 static int em_hw_init(struct e1000_hw *hw);
92 static int em_hardware_init(struct e1000_hw *hw);
93 static void em_hw_control_acquire(struct e1000_hw *hw);
94 static void em_hw_control_release(struct e1000_hw *hw);
95 static void em_init_manageability(struct e1000_hw *hw);
96 static void em_release_manageability(struct e1000_hw *hw);
97
98 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
99
100 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
101                 uint16_t vlan_id, int on);
102 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
103 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
104 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
105 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
106 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
107
108 /*
109 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
110                                         uint16_t vlan_id, int on);
111 */
112
113 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
114 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
115 static void em_lsc_intr_disable(struct e1000_hw *hw);
116 static void em_rxq_intr_enable(struct e1000_hw *hw);
117 static void em_rxq_intr_disable(struct e1000_hw *hw);
118
119 static int eth_em_led_on(struct rte_eth_dev *dev);
120 static int eth_em_led_off(struct rte_eth_dev *dev);
121
122 static int em_get_rx_buffer_size(struct e1000_hw *hw);
123 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
124                 uint32_t index, uint32_t pool);
125 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
126
127 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
128                                    struct ether_addr *mc_addr_set,
129                                    uint32_t nb_mc_addr);
130
131 #define EM_FC_PAUSE_TIME 0x0680
132 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
133 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
134
135 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
136
137 /*
138  * The set of PCI devices this driver supports
139  */
140 static const struct rte_pci_id pci_id_em_map[] = {
141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
158         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
159         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
160         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
161         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
162         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
163         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
164         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
165         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
166         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
167         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
168         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
169         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
170         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
171         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
172         { .vendor_id = 0, /* sentinel */ },
173 };
174
175 static const struct eth_dev_ops eth_em_ops = {
176         .dev_configure        = eth_em_configure,
177         .dev_start            = eth_em_start,
178         .dev_stop             = eth_em_stop,
179         .dev_close            = eth_em_close,
180         .promiscuous_enable   = eth_em_promiscuous_enable,
181         .promiscuous_disable  = eth_em_promiscuous_disable,
182         .allmulticast_enable  = eth_em_allmulticast_enable,
183         .allmulticast_disable = eth_em_allmulticast_disable,
184         .link_update          = eth_em_link_update,
185         .stats_get            = eth_em_stats_get,
186         .stats_reset          = eth_em_stats_reset,
187         .dev_infos_get        = eth_em_infos_get,
188         .mtu_set              = eth_em_mtu_set,
189         .vlan_filter_set      = eth_em_vlan_filter_set,
190         .vlan_offload_set     = eth_em_vlan_offload_set,
191         .rx_queue_setup       = eth_em_rx_queue_setup,
192         .rx_queue_release     = eth_em_rx_queue_release,
193         .rx_queue_count       = eth_em_rx_queue_count,
194         .rx_descriptor_done   = eth_em_rx_descriptor_done,
195         .tx_queue_setup       = eth_em_tx_queue_setup,
196         .tx_queue_release     = eth_em_tx_queue_release,
197         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
198         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
199         .dev_led_on           = eth_em_led_on,
200         .dev_led_off          = eth_em_led_off,
201         .flow_ctrl_get        = eth_em_flow_ctrl_get,
202         .flow_ctrl_set        = eth_em_flow_ctrl_set,
203         .mac_addr_add         = eth_em_rar_set,
204         .mac_addr_remove      = eth_em_rar_clear,
205         .set_mc_addr_list     = eth_em_set_mc_addr_list,
206         .rxq_info_get         = em_rxq_info_get,
207         .txq_info_get         = em_txq_info_get,
208 };
209
210 /**
211  * Atomically reads the link status information from global
212  * structure rte_eth_dev.
213  *
214  * @param dev
215  *   - Pointer to the structure rte_eth_dev to read from.
216  *   - Pointer to the buffer to be saved with the link status.
217  *
218  * @return
219  *   - On success, zero.
220  *   - On failure, negative value.
221  */
222 static inline int
223 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
224                                 struct rte_eth_link *link)
225 {
226         struct rte_eth_link *dst = link;
227         struct rte_eth_link *src = &(dev->data->dev_link);
228
229         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
230                                         *(uint64_t *)src) == 0)
231                 return -1;
232
233         return 0;
234 }
235
236 /**
237  * Atomically writes the link status information into global
238  * structure rte_eth_dev.
239  *
240  * @param dev
241  *   - Pointer to the structure rte_eth_dev to read from.
242  *   - Pointer to the buffer to be saved with the link status.
243  *
244  * @return
245  *   - On success, zero.
246  *   - On failure, negative value.
247  */
248 static inline int
249 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
250                                 struct rte_eth_link *link)
251 {
252         struct rte_eth_link *dst = &(dev->data->dev_link);
253         struct rte_eth_link *src = link;
254
255         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
256                                         *(uint64_t *)src) == 0)
257                 return -1;
258
259         return 0;
260 }
261
262 /**
263  *  eth_em_dev_is_ich8 - Check for ICH8 device
264  *  @hw: pointer to the HW structure
265  *
266  *  return TRUE for ICH8, otherwise FALSE
267  **/
268 static bool
269 eth_em_dev_is_ich8(struct e1000_hw *hw)
270 {
271         DEBUGFUNC("eth_em_dev_is_ich8");
272
273         switch (hw->device_id) {
274         case E1000_DEV_ID_PCH_LPT_I217_LM:
275         case E1000_DEV_ID_PCH_LPT_I217_V:
276         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
277         case E1000_DEV_ID_PCH_LPTLP_I218_V:
278         case E1000_DEV_ID_PCH_I218_V2:
279         case E1000_DEV_ID_PCH_I218_LM2:
280         case E1000_DEV_ID_PCH_I218_V3:
281         case E1000_DEV_ID_PCH_I218_LM3:
282                 return 1;
283         default:
284                 return 0;
285         }
286 }
287
288 static int
289 eth_em_dev_init(struct rte_eth_dev *eth_dev)
290 {
291         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
292         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
293         struct e1000_adapter *adapter =
294                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
295         struct e1000_hw *hw =
296                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
297         struct e1000_vfta * shadow_vfta =
298                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
299
300         eth_dev->dev_ops = &eth_em_ops;
301         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
302         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
303         eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
304
305         /* for secondary processes, we don't initialise any further as primary
306          * has already done this work. Only check we don't need a different
307          * RX function */
308         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
309                 if (eth_dev->data->scattered_rx)
310                         eth_dev->rx_pkt_burst =
311                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
312                 return 0;
313         }
314
315         rte_eth_copy_pci_info(eth_dev, pci_dev);
316
317         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
318         hw->device_id = pci_dev->id.device_id;
319         adapter->stopped = 0;
320
321         /* For ICH8 support we'll need to map the flash memory BAR */
322         if (eth_em_dev_is_ich8(hw))
323                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
324
325         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
326                         em_hw_init(hw) != 0) {
327                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
328                         "failed to init HW",
329                         eth_dev->data->port_id, pci_dev->id.vendor_id,
330                         pci_dev->id.device_id);
331                 return -ENODEV;
332         }
333
334         /* Allocate memory for storing MAC addresses */
335         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
336                         hw->mac.rar_entry_count, 0);
337         if (eth_dev->data->mac_addrs == NULL) {
338                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
339                         "store MAC addresses",
340                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
341                 return -ENOMEM;
342         }
343
344         /* Copy the permanent MAC address */
345         ether_addr_copy((struct ether_addr *) hw->mac.addr,
346                 eth_dev->data->mac_addrs);
347
348         /* initialize the vfta */
349         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
350
351         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
352                      eth_dev->data->port_id, pci_dev->id.vendor_id,
353                      pci_dev->id.device_id);
354
355         rte_intr_callback_register(intr_handle,
356                                    eth_em_interrupt_handler, eth_dev);
357
358         return 0;
359 }
360
361 static int
362 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
363 {
364         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
365         struct e1000_adapter *adapter =
366                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
367         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
368
369         PMD_INIT_FUNC_TRACE();
370
371         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
372                 return -EPERM;
373
374         if (adapter->stopped == 0)
375                 eth_em_close(eth_dev);
376
377         eth_dev->dev_ops = NULL;
378         eth_dev->rx_pkt_burst = NULL;
379         eth_dev->tx_pkt_burst = NULL;
380
381         rte_free(eth_dev->data->mac_addrs);
382         eth_dev->data->mac_addrs = NULL;
383
384         /* disable uio intr before callback unregister */
385         rte_intr_disable(intr_handle);
386         rte_intr_callback_unregister(intr_handle,
387                                      eth_em_interrupt_handler, eth_dev);
388
389         return 0;
390 }
391
392 static struct eth_driver rte_em_pmd = {
393         .pci_drv = {
394                 .id_table = pci_id_em_map,
395                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
396                         RTE_PCI_DRV_DETACHABLE,
397                 .probe = rte_eth_dev_pci_probe,
398                 .remove = rte_eth_dev_pci_remove,
399         },
400         .eth_dev_init = eth_em_dev_init,
401         .eth_dev_uninit = eth_em_dev_uninit,
402         .dev_private_size = sizeof(struct e1000_adapter),
403 };
404
405 static int
406 em_hw_init(struct e1000_hw *hw)
407 {
408         int diag;
409
410         diag = hw->mac.ops.init_params(hw);
411         if (diag != 0) {
412                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
413                 return diag;
414         }
415         diag = hw->nvm.ops.init_params(hw);
416         if (diag != 0) {
417                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
418                 return diag;
419         }
420         diag = hw->phy.ops.init_params(hw);
421         if (diag != 0) {
422                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
423                 return diag;
424         }
425         (void) e1000_get_bus_info(hw);
426
427         hw->mac.autoneg = 1;
428         hw->phy.autoneg_wait_to_complete = 0;
429         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
430
431         e1000_init_script_state_82541(hw, TRUE);
432         e1000_set_tbi_compatibility_82543(hw, TRUE);
433
434         /* Copper options */
435         if (hw->phy.media_type == e1000_media_type_copper) {
436                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
437                 hw->phy.disable_polarity_correction = 0;
438                 hw->phy.ms_type = e1000_ms_hw_default;
439         }
440
441         /*
442          * Start from a known state, this is important in reading the nvm
443          * and mac from that.
444          */
445         e1000_reset_hw(hw);
446
447         /* Make sure we have a good EEPROM before we read from it */
448         if (e1000_validate_nvm_checksum(hw) < 0) {
449                 /*
450                  * Some PCI-E parts fail the first check due to
451                  * the link being in sleep state, call it again,
452                  * if it fails a second time its a real issue.
453                  */
454                 diag = e1000_validate_nvm_checksum(hw);
455                 if (diag < 0) {
456                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
457                         goto error;
458                 }
459         }
460
461         /* Read the permanent MAC address out of the EEPROM */
462         diag = e1000_read_mac_addr(hw);
463         if (diag != 0) {
464                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
465                 goto error;
466         }
467
468         /* Now initialize the hardware */
469         diag = em_hardware_init(hw);
470         if (diag != 0) {
471                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
472                 goto error;
473         }
474
475         hw->mac.get_link_status = 1;
476
477         /* Indicate SOL/IDER usage */
478         diag = e1000_check_reset_block(hw);
479         if (diag < 0) {
480                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
481                         "SOL/IDER session");
482         }
483         return 0;
484
485 error:
486         em_hw_control_release(hw);
487         return diag;
488 }
489
490 static int
491 eth_em_configure(struct rte_eth_dev *dev)
492 {
493         struct e1000_interrupt *intr =
494                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
495
496         PMD_INIT_FUNC_TRACE();
497         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
498         PMD_INIT_FUNC_TRACE();
499
500         return 0;
501 }
502
503 static void
504 em_set_pba(struct e1000_hw *hw)
505 {
506         uint32_t pba;
507
508         /*
509          * Packet Buffer Allocation (PBA)
510          * Writing PBA sets the receive portion of the buffer
511          * the remainder is used for the transmit buffer.
512          * Devices before the 82547 had a Packet Buffer of 64K.
513          * After the 82547 the buffer was reduced to 40K.
514          */
515         switch (hw->mac.type) {
516                 case e1000_82547:
517                 case e1000_82547_rev_2:
518                 /* 82547: Total Packet Buffer is 40K */
519                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
520                         break;
521                 case e1000_82571:
522                 case e1000_82572:
523                 case e1000_80003es2lan:
524                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
525                         break;
526                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
527                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
528                         break;
529                 case e1000_82574:
530                 case e1000_82583:
531                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
532                         break;
533                 case e1000_ich8lan:
534                         pba = E1000_PBA_8K;
535                         break;
536                 case e1000_ich9lan:
537                 case e1000_ich10lan:
538                         pba = E1000_PBA_10K;
539                         break;
540                 case e1000_pchlan:
541                 case e1000_pch2lan:
542                 case e1000_pch_lpt:
543                         pba = E1000_PBA_26K;
544                         break;
545                 default:
546                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
547         }
548
549         E1000_WRITE_REG(hw, E1000_PBA, pba);
550 }
551
552 static int
553 eth_em_start(struct rte_eth_dev *dev)
554 {
555         struct e1000_adapter *adapter =
556                 E1000_DEV_PRIVATE(dev->data->dev_private);
557         struct e1000_hw *hw =
558                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
559         struct rte_pci_device *pci_dev =
560                 E1000_DEV_TO_PCI(dev);
561         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
562         int ret, mask;
563         uint32_t intr_vector = 0;
564         uint32_t *speeds;
565         int num_speeds;
566         bool autoneg;
567
568         PMD_INIT_FUNC_TRACE();
569
570         eth_em_stop(dev);
571
572         e1000_power_up_phy(hw);
573
574         /* Set default PBA value */
575         em_set_pba(hw);
576
577         /* Put the address into the Receive Address Array */
578         e1000_rar_set(hw, hw->mac.addr, 0);
579
580         /*
581          * With the 82571 adapter, RAR[0] may be overwritten
582          * when the other port is reset, we make a duplicate
583          * in RAR[14] for that eventuality, this assures
584          * the interface continues to function.
585          */
586         if (hw->mac.type == e1000_82571) {
587                 e1000_set_laa_state_82571(hw, TRUE);
588                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
589         }
590
591         /* Initialize the hardware */
592         if (em_hardware_init(hw)) {
593                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
594                 return -EIO;
595         }
596
597         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
598
599         /* Configure for OS presence */
600         em_init_manageability(hw);
601
602         if (dev->data->dev_conf.intr_conf.rxq != 0) {
603                 intr_vector = dev->data->nb_rx_queues;
604                 if (rte_intr_efd_enable(intr_handle, intr_vector))
605                         return -1;
606         }
607
608         if (rte_intr_dp_is_en(intr_handle)) {
609                 intr_handle->intr_vec =
610                         rte_zmalloc("intr_vec",
611                                         dev->data->nb_rx_queues * sizeof(int), 0);
612                 if (intr_handle->intr_vec == NULL) {
613                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
614                                                 " intr_vec\n", dev->data->nb_rx_queues);
615                         return -ENOMEM;
616                 }
617
618                 /* enable rx interrupt */
619                 em_rxq_intr_enable(hw);
620         }
621
622         eth_em_tx_init(dev);
623
624         ret = eth_em_rx_init(dev);
625         if (ret) {
626                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
627                 em_dev_clear_queues(dev);
628                 return ret;
629         }
630
631         e1000_clear_hw_cntrs_base_generic(hw);
632
633         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
634                         ETH_VLAN_EXTEND_MASK;
635         eth_em_vlan_offload_set(dev, mask);
636
637         /* Set Interrupt Throttling Rate to maximum allowed value. */
638         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
639
640         /* Setup link speed and duplex */
641         speeds = &dev->data->dev_conf.link_speeds;
642         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
643                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
644                 hw->mac.autoneg = 1;
645         } else {
646                 num_speeds = 0;
647                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
648
649                 /* Reset */
650                 hw->phy.autoneg_advertised = 0;
651
652                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
653                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
654                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
655                         num_speeds = -1;
656                         goto error_invalid_config;
657                 }
658                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
659                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
660                         num_speeds++;
661                 }
662                 if (*speeds & ETH_LINK_SPEED_10M) {
663                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
664                         num_speeds++;
665                 }
666                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
667                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
668                         num_speeds++;
669                 }
670                 if (*speeds & ETH_LINK_SPEED_100M) {
671                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
672                         num_speeds++;
673                 }
674                 if (*speeds & ETH_LINK_SPEED_1G) {
675                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
676                         num_speeds++;
677                 }
678                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
679                         goto error_invalid_config;
680
681                 /* Set/reset the mac.autoneg based on the link speed,
682                  * fixed or not
683                  */
684                 if (!autoneg) {
685                         hw->mac.autoneg = 0;
686                         hw->mac.forced_speed_duplex =
687                                         hw->phy.autoneg_advertised;
688                 } else {
689                         hw->mac.autoneg = 1;
690                 }
691         }
692
693         e1000_setup_link(hw);
694
695         if (rte_intr_allow_others(intr_handle)) {
696                 /* check if lsc interrupt is enabled */
697                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
698                         ret = eth_em_interrupt_setup(dev);
699                         if (ret) {
700                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
701                                 em_dev_clear_queues(dev);
702                                 return ret;
703                         }
704                 }
705         } else {
706                 rte_intr_callback_unregister(intr_handle,
707                                                 eth_em_interrupt_handler,
708                                                 (void *)dev);
709                 if (dev->data->dev_conf.intr_conf.lsc != 0)
710                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
711                                      " no intr multiplex\n");
712         }
713         /* check if rxq interrupt is enabled */
714         if (dev->data->dev_conf.intr_conf.rxq != 0)
715                 eth_em_rxq_interrupt_setup(dev);
716
717         rte_intr_enable(intr_handle);
718
719         adapter->stopped = 0;
720
721         PMD_INIT_LOG(DEBUG, "<<");
722
723         return 0;
724
725 error_invalid_config:
726         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
727                      dev->data->dev_conf.link_speeds, dev->data->port_id);
728         em_dev_clear_queues(dev);
729         return -EINVAL;
730 }
731
732 /*********************************************************************
733  *
734  *  This routine disables all traffic on the adapter by issuing a
735  *  global reset on the MAC.
736  *
737  **********************************************************************/
738 static void
739 eth_em_stop(struct rte_eth_dev *dev)
740 {
741         struct rte_eth_link link;
742         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
743         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
744         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
745
746         em_rxq_intr_disable(hw);
747         em_lsc_intr_disable(hw);
748
749         e1000_reset_hw(hw);
750         if (hw->mac.type >= e1000_82544)
751                 E1000_WRITE_REG(hw, E1000_WUC, 0);
752
753         /* Power down the phy. Needed to make the link go down */
754         e1000_power_down_phy(hw);
755
756         em_dev_clear_queues(dev);
757
758         /* clear the recorded link status */
759         memset(&link, 0, sizeof(link));
760         rte_em_dev_atomic_write_link_status(dev, &link);
761
762         if (!rte_intr_allow_others(intr_handle))
763                 /* resume to the default handler */
764                 rte_intr_callback_register(intr_handle,
765                                            eth_em_interrupt_handler,
766                                            (void *)dev);
767
768         /* Clean datapath event and queue/vec mapping */
769         rte_intr_efd_disable(intr_handle);
770         if (intr_handle->intr_vec != NULL) {
771                 rte_free(intr_handle->intr_vec);
772                 intr_handle->intr_vec = NULL;
773         }
774 }
775
776 static void
777 eth_em_close(struct rte_eth_dev *dev)
778 {
779         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
780         struct e1000_adapter *adapter =
781                 E1000_DEV_PRIVATE(dev->data->dev_private);
782
783         eth_em_stop(dev);
784         adapter->stopped = 1;
785         em_dev_free_queues(dev);
786         e1000_phy_hw_reset(hw);
787         em_release_manageability(hw);
788         em_hw_control_release(hw);
789 }
790
791 static int
792 em_get_rx_buffer_size(struct e1000_hw *hw)
793 {
794         uint32_t rx_buf_size;
795
796         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
797         return rx_buf_size;
798 }
799
800 /*********************************************************************
801  *
802  *  Initialize the hardware
803  *
804  **********************************************************************/
805 static int
806 em_hardware_init(struct e1000_hw *hw)
807 {
808         uint32_t rx_buf_size;
809         int diag;
810
811         /* Issue a global reset */
812         e1000_reset_hw(hw);
813
814         /* Let the firmware know the OS is in control */
815         em_hw_control_acquire(hw);
816
817         /*
818          * These parameters control the automatic generation (Tx) and
819          * response (Rx) to Ethernet PAUSE frames.
820          * - High water mark should allow for at least two standard size (1518)
821          *   frames to be received after sending an XOFF.
822          * - Low water mark works best when it is very near the high water mark.
823          *   This allows the receiver to restart by sending XON when it has
824          *   drained a bit. Here we use an arbitrary value of 1500 which will
825          *   restart after one full frame is pulled from the buffer. There
826          *   could be several smaller frames in the buffer and if so they will
827          *   not trigger the XON until their total number reduces the buffer
828          *   by 1500.
829          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
830          */
831         rx_buf_size = em_get_rx_buffer_size(hw);
832
833         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
834         hw->fc.low_water = hw->fc.high_water - 1500;
835
836         if (hw->mac.type == e1000_80003es2lan)
837                 hw->fc.pause_time = UINT16_MAX;
838         else
839                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
840
841         hw->fc.send_xon = 1;
842
843         /* Set Flow control, use the tunable location if sane */
844         if (em_fc_setting <= e1000_fc_full)
845                 hw->fc.requested_mode = em_fc_setting;
846         else
847                 hw->fc.requested_mode = e1000_fc_none;
848
849         /* Workaround: no TX flow ctrl for PCH */
850         if (hw->mac.type == e1000_pchlan)
851                 hw->fc.requested_mode = e1000_fc_rx_pause;
852
853         /* Override - settings for PCH2LAN, ya its magic :) */
854         if (hw->mac.type == e1000_pch2lan) {
855                 hw->fc.high_water = 0x5C20;
856                 hw->fc.low_water = 0x5048;
857                 hw->fc.pause_time = 0x0650;
858                 hw->fc.refresh_time = 0x0400;
859         } else if (hw->mac.type == e1000_pch_lpt) {
860                 hw->fc.requested_mode = e1000_fc_full;
861         }
862
863         diag = e1000_init_hw(hw);
864         if (diag < 0)
865                 return diag;
866         e1000_check_for_link(hw);
867         return 0;
868 }
869
870 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
871 static void
872 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
873 {
874         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
875         struct e1000_hw_stats *stats =
876                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
877         int pause_frames;
878
879         if(hw->phy.media_type == e1000_media_type_copper ||
880                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
881                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
882                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
883         }
884
885         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
886         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
887         stats->scc += E1000_READ_REG(hw, E1000_SCC);
888         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
889
890         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
891         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
892         stats->colc += E1000_READ_REG(hw, E1000_COLC);
893         stats->dc += E1000_READ_REG(hw, E1000_DC);
894         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
895         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
896         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
897
898         /*
899          * For watchdog management we need to know if we have been
900          * paused during the last interval, so capture that here.
901          */
902         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
903         stats->xoffrxc += pause_frames;
904         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
905         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
906         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
907         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
908         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
909         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
910         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
911         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
912         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
913         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
914         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
915         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
916
917         /*
918          * For the 64-bit byte counters the low dword must be read first.
919          * Both registers clear on the read of the high dword.
920          */
921
922         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
923         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
924         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
925         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
926
927         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
928         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
929         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
930         stats->roc += E1000_READ_REG(hw, E1000_ROC);
931         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
932
933         stats->tor += E1000_READ_REG(hw, E1000_TORH);
934         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
935
936         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
937         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
938         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
939         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
940         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
941         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
942         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
943         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
944         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
945         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
946
947         /* Interrupt Counts */
948
949         if (hw->mac.type >= e1000_82571) {
950                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
951                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
952                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
953                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
954                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
955                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
956                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
957                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
958                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
959         }
960
961         if (hw->mac.type >= e1000_82543) {
962                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
963                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
964                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
965                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
966                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
967                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
968         }
969
970         if (rte_stats == NULL)
971                 return;
972
973         /* Rx Errors */
974         rte_stats->imissed = stats->mpc;
975         rte_stats->ierrors = stats->crcerrs +
976                              stats->rlec + stats->ruc + stats->roc +
977                              stats->rxerrc + stats->algnerrc + stats->cexterr;
978
979         /* Tx Errors */
980         rte_stats->oerrors = stats->ecol + stats->latecol;
981
982         rte_stats->ipackets = stats->gprc;
983         rte_stats->opackets = stats->gptc;
984         rte_stats->ibytes   = stats->gorc;
985         rte_stats->obytes   = stats->gotc;
986 }
987
988 static void
989 eth_em_stats_reset(struct rte_eth_dev *dev)
990 {
991         struct e1000_hw_stats *hw_stats =
992                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
993
994         /* HW registers are cleared on read */
995         eth_em_stats_get(dev, NULL);
996
997         /* Reset software totals */
998         memset(hw_stats, 0, sizeof(*hw_stats));
999 }
1000
1001 static int
1002 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1003 {
1004         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1005         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1006         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1007
1008         em_rxq_intr_enable(hw);
1009         rte_intr_enable(intr_handle);
1010
1011         return 0;
1012 }
1013
1014 static int
1015 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1016 {
1017         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1018
1019         em_rxq_intr_disable(hw);
1020
1021         return 0;
1022 }
1023
1024 static uint32_t
1025 em_get_max_pktlen(const struct e1000_hw *hw)
1026 {
1027         switch (hw->mac.type) {
1028         case e1000_82571:
1029         case e1000_82572:
1030         case e1000_ich9lan:
1031         case e1000_ich10lan:
1032         case e1000_pch2lan:
1033         case e1000_pch_lpt:
1034         case e1000_82574:
1035         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1036         case e1000_82583:
1037                 return 0x2412;
1038         case e1000_pchlan:
1039                 return 0x1000;
1040         /* Adapters that do not support jumbo frames */
1041         case e1000_ich8lan:
1042                 return ETHER_MAX_LEN;
1043         default:
1044                 return MAX_JUMBO_FRAME_SIZE;
1045         }
1046 }
1047
1048 static void
1049 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1050 {
1051         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1052
1053         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1054         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1055         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1056         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1057
1058         /*
1059          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1060          * Unfortunatelly, all these nics have just one TX context.
1061          * So we have few choises for TX:
1062          * - Use just one TX queue.
1063          * - Allow cksum offload only for one TX queue.
1064          * - Don't allow TX cksum offload at all.
1065          * For now, option #1 was chosen.
1066          * To use second RX queue we have to use extended RX descriptor
1067          * (Multiple Receive Queues are mutually exclusive with UDP
1068          * fragmentation and are not supported when a legacy receive
1069          * descriptor format is used).
1070          * Which means separate RX routinies - as legacy nics (82540, 82545)
1071          * don't support extended RXD.
1072          * To avoid it we support just one RX queue for now (no RSS).
1073          */
1074
1075         dev_info->max_rx_queues = 1;
1076         dev_info->max_tx_queues = 1;
1077
1078         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1079                 .nb_max = E1000_MAX_RING_DESC,
1080                 .nb_min = E1000_MIN_RING_DESC,
1081                 .nb_align = EM_RXD_ALIGN,
1082         };
1083
1084         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1085                 .nb_max = E1000_MAX_RING_DESC,
1086                 .nb_min = E1000_MIN_RING_DESC,
1087                 .nb_align = EM_TXD_ALIGN,
1088                 .nb_seg_max = EM_TX_MAX_SEG,
1089                 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1090         };
1091
1092         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1093                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1094                         ETH_LINK_SPEED_1G;
1095 }
1096
1097 /* return 0 means link status changed, -1 means not changed */
1098 static int
1099 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1100 {
1101         struct e1000_hw *hw =
1102                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1103         struct rte_eth_link link, old;
1104         int link_check, count;
1105
1106         link_check = 0;
1107         hw->mac.get_link_status = 1;
1108
1109         /* possible wait-to-complete in up to 9 seconds */
1110         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1111                 /* Read the real link status */
1112                 switch (hw->phy.media_type) {
1113                 case e1000_media_type_copper:
1114                         /* Do the work to read phy */
1115                         e1000_check_for_link(hw);
1116                         link_check = !hw->mac.get_link_status;
1117                         break;
1118
1119                 case e1000_media_type_fiber:
1120                         e1000_check_for_link(hw);
1121                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1122                                         E1000_STATUS_LU);
1123                         break;
1124
1125                 case e1000_media_type_internal_serdes:
1126                         e1000_check_for_link(hw);
1127                         link_check = hw->mac.serdes_has_link;
1128                         break;
1129
1130                 default:
1131                         break;
1132                 }
1133                 if (link_check || wait_to_complete == 0)
1134                         break;
1135                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1136         }
1137         memset(&link, 0, sizeof(link));
1138         rte_em_dev_atomic_read_link_status(dev, &link);
1139         old = link;
1140
1141         /* Now we check if a transition has happened */
1142         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1143                 uint16_t duplex, speed;
1144                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1145                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1146                                 ETH_LINK_FULL_DUPLEX :
1147                                 ETH_LINK_HALF_DUPLEX;
1148                 link.link_speed = speed;
1149                 link.link_status = ETH_LINK_UP;
1150                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1151                                 ETH_LINK_SPEED_FIXED);
1152         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1153                 link.link_speed = 0;
1154                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1155                 link.link_status = ETH_LINK_DOWN;
1156                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1157         }
1158         rte_em_dev_atomic_write_link_status(dev, &link);
1159
1160         /* not changed */
1161         if (old.link_status == link.link_status)
1162                 return -1;
1163
1164         /* changed */
1165         return 0;
1166 }
1167
1168 /*
1169  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1170  * For ASF and Pass Through versions of f/w this means
1171  * that the driver is loaded. For AMT version type f/w
1172  * this means that the network i/f is open.
1173  */
1174 static void
1175 em_hw_control_acquire(struct e1000_hw *hw)
1176 {
1177         uint32_t ctrl_ext, swsm;
1178
1179         /* Let firmware know the driver has taken over */
1180         if (hw->mac.type == e1000_82573) {
1181                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1182                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1183
1184         } else {
1185                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1186                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1187                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1188         }
1189 }
1190
1191 /*
1192  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1193  * For ASF and Pass Through versions of f/w this means that the
1194  * driver is no longer loaded. For AMT versions of the
1195  * f/w this means that the network i/f is closed.
1196  */
1197 static void
1198 em_hw_control_release(struct e1000_hw *hw)
1199 {
1200         uint32_t ctrl_ext, swsm;
1201
1202         /* Let firmware taken over control of h/w */
1203         if (hw->mac.type == e1000_82573) {
1204                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1205                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1206         } else {
1207                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1208                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1209                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1210         }
1211 }
1212
1213 /*
1214  * Bit of a misnomer, what this really means is
1215  * to enable OS management of the system... aka
1216  * to disable special hardware management features.
1217  */
1218 static void
1219 em_init_manageability(struct e1000_hw *hw)
1220 {
1221         if (e1000_enable_mng_pass_thru(hw)) {
1222                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1223                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1224
1225                 /* disable hardware interception of ARP */
1226                 manc &= ~(E1000_MANC_ARP_EN);
1227
1228                 /* enable receiving management packets to the host */
1229                 manc |= E1000_MANC_EN_MNG2HOST;
1230                 manc2h |= 1 << 5;  /* Mng Port 623 */
1231                 manc2h |= 1 << 6;  /* Mng Port 664 */
1232                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1233                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1234         }
1235 }
1236
1237 /*
1238  * Give control back to hardware management
1239  * controller if there is one.
1240  */
1241 static void
1242 em_release_manageability(struct e1000_hw *hw)
1243 {
1244         uint32_t manc;
1245
1246         if (e1000_enable_mng_pass_thru(hw)) {
1247                 manc = E1000_READ_REG(hw, E1000_MANC);
1248
1249                 /* re-enable hardware interception of ARP */
1250                 manc |= E1000_MANC_ARP_EN;
1251                 manc &= ~E1000_MANC_EN_MNG2HOST;
1252
1253                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1254         }
1255 }
1256
1257 static void
1258 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1259 {
1260         struct e1000_hw *hw =
1261                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1262         uint32_t rctl;
1263
1264         rctl = E1000_READ_REG(hw, E1000_RCTL);
1265         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1266         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1267 }
1268
1269 static void
1270 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1271 {
1272         struct e1000_hw *hw =
1273                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274         uint32_t rctl;
1275
1276         rctl = E1000_READ_REG(hw, E1000_RCTL);
1277         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1278         if (dev->data->all_multicast == 1)
1279                 rctl |= E1000_RCTL_MPE;
1280         else
1281                 rctl &= (~E1000_RCTL_MPE);
1282         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1283 }
1284
1285 static void
1286 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1287 {
1288         struct e1000_hw *hw =
1289                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1290         uint32_t rctl;
1291
1292         rctl = E1000_READ_REG(hw, E1000_RCTL);
1293         rctl |= E1000_RCTL_MPE;
1294         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1295 }
1296
1297 static void
1298 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1299 {
1300         struct e1000_hw *hw =
1301                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1302         uint32_t rctl;
1303
1304         if (dev->data->promiscuous == 1)
1305                 return; /* must remain in all_multicast mode */
1306         rctl = E1000_READ_REG(hw, E1000_RCTL);
1307         rctl &= (~E1000_RCTL_MPE);
1308         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1309 }
1310
1311 static int
1312 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1313 {
1314         struct e1000_hw *hw =
1315                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1316         struct e1000_vfta * shadow_vfta =
1317                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1318         uint32_t vfta;
1319         uint32_t vid_idx;
1320         uint32_t vid_bit;
1321
1322         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1323                               E1000_VFTA_ENTRY_MASK);
1324         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1325         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1326         if (on)
1327                 vfta |= vid_bit;
1328         else
1329                 vfta &= ~vid_bit;
1330         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1331
1332         /* update local VFTA copy */
1333         shadow_vfta->vfta[vid_idx] = vfta;
1334
1335         return 0;
1336 }
1337
1338 static void
1339 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1340 {
1341         struct e1000_hw *hw =
1342                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1343         uint32_t reg;
1344
1345         /* Filter Table Disable */
1346         reg = E1000_READ_REG(hw, E1000_RCTL);
1347         reg &= ~E1000_RCTL_CFIEN;
1348         reg &= ~E1000_RCTL_VFE;
1349         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1350 }
1351
1352 static void
1353 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1354 {
1355         struct e1000_hw *hw =
1356                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1357         struct e1000_vfta * shadow_vfta =
1358                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1359         uint32_t reg;
1360         int i;
1361
1362         /* Filter Table Enable, CFI not used for packet acceptance */
1363         reg = E1000_READ_REG(hw, E1000_RCTL);
1364         reg &= ~E1000_RCTL_CFIEN;
1365         reg |= E1000_RCTL_VFE;
1366         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1367
1368         /* restore vfta from local copy */
1369         for (i = 0; i < IGB_VFTA_SIZE; i++)
1370                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1371 }
1372
1373 static void
1374 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1375 {
1376         struct e1000_hw *hw =
1377                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1378         uint32_t reg;
1379
1380         /* VLAN Mode Disable */
1381         reg = E1000_READ_REG(hw, E1000_CTRL);
1382         reg &= ~E1000_CTRL_VME;
1383         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1384
1385 }
1386
1387 static void
1388 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1389 {
1390         struct e1000_hw *hw =
1391                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1392         uint32_t reg;
1393
1394         /* VLAN Mode Enable */
1395         reg = E1000_READ_REG(hw, E1000_CTRL);
1396         reg |= E1000_CTRL_VME;
1397         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1398 }
1399
1400 static void
1401 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1402 {
1403         if(mask & ETH_VLAN_STRIP_MASK){
1404                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1405                         em_vlan_hw_strip_enable(dev);
1406                 else
1407                         em_vlan_hw_strip_disable(dev);
1408         }
1409
1410         if(mask & ETH_VLAN_FILTER_MASK){
1411                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1412                         em_vlan_hw_filter_enable(dev);
1413                 else
1414                         em_vlan_hw_filter_disable(dev);
1415         }
1416 }
1417
1418 /*
1419  * It enables the interrupt mask and then enable the interrupt.
1420  *
1421  * @param dev
1422  *  Pointer to struct rte_eth_dev.
1423  *
1424  * @return
1425  *  - On success, zero.
1426  *  - On failure, a negative value.
1427  */
1428 static int
1429 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1430 {
1431         uint32_t regval;
1432         struct e1000_hw *hw =
1433                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1434
1435         /* clear interrupt */
1436         E1000_READ_REG(hw, E1000_ICR);
1437         regval = E1000_READ_REG(hw, E1000_IMS);
1438         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1439         return 0;
1440 }
1441
1442 /*
1443  * It clears the interrupt causes and enables the interrupt.
1444  * It will be called once only during nic initialized.
1445  *
1446  * @param dev
1447  *  Pointer to struct rte_eth_dev.
1448  *
1449  * @return
1450  *  - On success, zero.
1451  *  - On failure, a negative value.
1452  */
1453 static int
1454 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1455 {
1456         struct e1000_hw *hw =
1457         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1458
1459         E1000_READ_REG(hw, E1000_ICR);
1460         em_rxq_intr_enable(hw);
1461         return 0;
1462 }
1463
1464 /*
1465  * It enable receive packet interrupt.
1466  * @param hw
1467  * Pointer to struct e1000_hw
1468  *
1469  * @return
1470  */
1471 static void
1472 em_rxq_intr_enable(struct e1000_hw *hw)
1473 {
1474         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1475         E1000_WRITE_FLUSH(hw);
1476 }
1477
1478 /*
1479  * It disabled lsc interrupt.
1480  * @param hw
1481  * Pointer to struct e1000_hw
1482  *
1483  * @return
1484  */
1485 static void
1486 em_lsc_intr_disable(struct e1000_hw *hw)
1487 {
1488         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1489         E1000_WRITE_FLUSH(hw);
1490 }
1491
1492 /*
1493  * It disabled receive packet interrupt.
1494  * @param hw
1495  * Pointer to struct e1000_hw
1496  *
1497  * @return
1498  */
1499 static void
1500 em_rxq_intr_disable(struct e1000_hw *hw)
1501 {
1502         E1000_READ_REG(hw, E1000_ICR);
1503         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1504         E1000_WRITE_FLUSH(hw);
1505 }
1506
1507 /*
1508  * It reads ICR and gets interrupt causes, check it and set a bit flag
1509  * to update link status.
1510  *
1511  * @param dev
1512  *  Pointer to struct rte_eth_dev.
1513  *
1514  * @return
1515  *  - On success, zero.
1516  *  - On failure, a negative value.
1517  */
1518 static int
1519 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1520 {
1521         uint32_t icr;
1522         struct e1000_hw *hw =
1523                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524         struct e1000_interrupt *intr =
1525                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1526
1527         /* read-on-clear nic registers here */
1528         icr = E1000_READ_REG(hw, E1000_ICR);
1529         if (icr & E1000_ICR_LSC) {
1530                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1531         }
1532
1533         return 0;
1534 }
1535
1536 /*
1537  * It executes link_update after knowing an interrupt is prsent.
1538  *
1539  * @param dev
1540  *  Pointer to struct rte_eth_dev.
1541  *
1542  * @return
1543  *  - On success, zero.
1544  *  - On failure, a negative value.
1545  */
1546 static int
1547 eth_em_interrupt_action(struct rte_eth_dev *dev,
1548                         struct rte_intr_handle *intr_handle)
1549 {
1550         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1551         struct e1000_hw *hw =
1552                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1553         struct e1000_interrupt *intr =
1554                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1555         uint32_t tctl, rctl;
1556         struct rte_eth_link link;
1557         int ret;
1558
1559         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1560                 return -1;
1561
1562         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1563         rte_intr_enable(intr_handle);
1564
1565         /* set get_link_status to check register later */
1566         hw->mac.get_link_status = 1;
1567         ret = eth_em_link_update(dev, 0);
1568
1569         /* check if link has changed */
1570         if (ret < 0)
1571                 return 0;
1572
1573         memset(&link, 0, sizeof(link));
1574         rte_em_dev_atomic_read_link_status(dev, &link);
1575         if (link.link_status) {
1576                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1577                              dev->data->port_id, (unsigned)link.link_speed,
1578                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1579                              "full-duplex" : "half-duplex");
1580         } else {
1581                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1582         }
1583         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1584                      pci_dev->addr.domain, pci_dev->addr.bus,
1585                      pci_dev->addr.devid, pci_dev->addr.function);
1586
1587         tctl = E1000_READ_REG(hw, E1000_TCTL);
1588         rctl = E1000_READ_REG(hw, E1000_RCTL);
1589         if (link.link_status) {
1590                 /* enable Tx/Rx */
1591                 tctl |= E1000_TCTL_EN;
1592                 rctl |= E1000_RCTL_EN;
1593         } else {
1594                 /* disable Tx/Rx */
1595                 tctl &= ~E1000_TCTL_EN;
1596                 rctl &= ~E1000_RCTL_EN;
1597         }
1598         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1599         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1600         E1000_WRITE_FLUSH(hw);
1601
1602         return 0;
1603 }
1604
1605 /**
1606  * Interrupt handler which shall be registered at first.
1607  *
1608  * @param handle
1609  *  Pointer to interrupt handle.
1610  * @param param
1611  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1612  *
1613  * @return
1614  *  void
1615  */
1616 static void
1617 eth_em_interrupt_handler(struct rte_intr_handle *handle,
1618                          void *param)
1619 {
1620         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1621
1622         eth_em_interrupt_get_status(dev);
1623         eth_em_interrupt_action(dev, handle);
1624         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1625 }
1626
1627 static int
1628 eth_em_led_on(struct rte_eth_dev *dev)
1629 {
1630         struct e1000_hw *hw;
1631
1632         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1633         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1634 }
1635
1636 static int
1637 eth_em_led_off(struct rte_eth_dev *dev)
1638 {
1639         struct e1000_hw *hw;
1640
1641         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1642         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1643 }
1644
1645 static int
1646 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1647 {
1648         struct e1000_hw *hw;
1649         uint32_t ctrl;
1650         int tx_pause;
1651         int rx_pause;
1652
1653         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654         fc_conf->pause_time = hw->fc.pause_time;
1655         fc_conf->high_water = hw->fc.high_water;
1656         fc_conf->low_water = hw->fc.low_water;
1657         fc_conf->send_xon = hw->fc.send_xon;
1658         fc_conf->autoneg = hw->mac.autoneg;
1659
1660         /*
1661          * Return rx_pause and tx_pause status according to actual setting of
1662          * the TFCE and RFCE bits in the CTRL register.
1663          */
1664         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1665         if (ctrl & E1000_CTRL_TFCE)
1666                 tx_pause = 1;
1667         else
1668                 tx_pause = 0;
1669
1670         if (ctrl & E1000_CTRL_RFCE)
1671                 rx_pause = 1;
1672         else
1673                 rx_pause = 0;
1674
1675         if (rx_pause && tx_pause)
1676                 fc_conf->mode = RTE_FC_FULL;
1677         else if (rx_pause)
1678                 fc_conf->mode = RTE_FC_RX_PAUSE;
1679         else if (tx_pause)
1680                 fc_conf->mode = RTE_FC_TX_PAUSE;
1681         else
1682                 fc_conf->mode = RTE_FC_NONE;
1683
1684         return 0;
1685 }
1686
1687 static int
1688 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1689 {
1690         struct e1000_hw *hw;
1691         int err;
1692         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1693                 e1000_fc_none,
1694                 e1000_fc_rx_pause,
1695                 e1000_fc_tx_pause,
1696                 e1000_fc_full
1697         };
1698         uint32_t rx_buf_size;
1699         uint32_t max_high_water;
1700         uint32_t rctl;
1701
1702         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1703         if (fc_conf->autoneg != hw->mac.autoneg)
1704                 return -ENOTSUP;
1705         rx_buf_size = em_get_rx_buffer_size(hw);
1706         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1707
1708         /* At least reserve one Ethernet frame for watermark */
1709         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1710         if ((fc_conf->high_water > max_high_water) ||
1711             (fc_conf->high_water < fc_conf->low_water)) {
1712                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1713                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1714                 return -EINVAL;
1715         }
1716
1717         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1718         hw->fc.pause_time     = fc_conf->pause_time;
1719         hw->fc.high_water     = fc_conf->high_water;
1720         hw->fc.low_water      = fc_conf->low_water;
1721         hw->fc.send_xon       = fc_conf->send_xon;
1722
1723         err = e1000_setup_link_generic(hw);
1724         if (err == E1000_SUCCESS) {
1725
1726                 /* check if we want to forward MAC frames - driver doesn't have native
1727                  * capability to do that, so we'll write the registers ourselves */
1728
1729                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1730
1731                 /* set or clear MFLCN.PMCF bit depending on configuration */
1732                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1733                         rctl |= E1000_RCTL_PMCF;
1734                 else
1735                         rctl &= ~E1000_RCTL_PMCF;
1736
1737                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1738                 E1000_WRITE_FLUSH(hw);
1739
1740                 return 0;
1741         }
1742
1743         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1744         return -EIO;
1745 }
1746
1747 static void
1748 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1749                 uint32_t index, __rte_unused uint32_t pool)
1750 {
1751         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1752
1753         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1754 }
1755
1756 static void
1757 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1758 {
1759         uint8_t addr[ETHER_ADDR_LEN];
1760         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1761
1762         memset(addr, 0, sizeof(addr));
1763
1764         e1000_rar_set(hw, addr, index);
1765 }
1766
1767 static int
1768 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1769 {
1770         struct rte_eth_dev_info dev_info;
1771         struct e1000_hw *hw;
1772         uint32_t frame_size;
1773         uint32_t rctl;
1774
1775         eth_em_infos_get(dev, &dev_info);
1776         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1777
1778         /* check that mtu is within the allowed range */
1779         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1780                 return -EINVAL;
1781
1782         /* refuse mtu that requires the support of scattered packets when this
1783          * feature has not been enabled before. */
1784         if (!dev->data->scattered_rx &&
1785             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1786                 return -EINVAL;
1787
1788         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1789         rctl = E1000_READ_REG(hw, E1000_RCTL);
1790
1791         /* switch to jumbo mode if needed */
1792         if (frame_size > ETHER_MAX_LEN) {
1793                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1794                 rctl |= E1000_RCTL_LPE;
1795         } else {
1796                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1797                 rctl &= ~E1000_RCTL_LPE;
1798         }
1799         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1800
1801         /* update max frame size */
1802         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1803         return 0;
1804 }
1805
1806 static int
1807 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1808                         struct ether_addr *mc_addr_set,
1809                         uint32_t nb_mc_addr)
1810 {
1811         struct e1000_hw *hw;
1812
1813         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1814         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1815         return 0;
1816 }
1817
1818 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd.pci_drv);
1819 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1820 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio");