4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memory.h>
50 #include <rte_memzone.h>
52 #include <rte_atomic.h>
53 #include <rte_malloc.h>
56 #include "e1000_logs.h"
57 #include "base/e1000_api.h"
58 #include "e1000_ethdev.h"
60 #define EM_EIAC 0x000DC
62 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
65 static int eth_em_configure(struct rte_eth_dev *dev);
66 static int eth_em_start(struct rte_eth_dev *dev);
67 static void eth_em_stop(struct rte_eth_dev *dev);
68 static void eth_em_close(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
70 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
72 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
73 static int eth_em_link_update(struct rte_eth_dev *dev,
74 int wait_to_complete);
75 static int eth_em_stats_get(struct rte_eth_dev *dev,
76 struct rte_eth_stats *rte_stats);
77 static void eth_em_stats_reset(struct rte_eth_dev *dev);
78 static void eth_em_infos_get(struct rte_eth_dev *dev,
79 struct rte_eth_dev_info *dev_info);
80 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
81 struct rte_eth_fc_conf *fc_conf);
82 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
83 struct rte_eth_fc_conf *fc_conf);
84 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
85 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
86 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
87 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
88 struct rte_intr_handle *handle);
89 static void eth_em_interrupt_handler(void *param);
91 static int em_hw_init(struct e1000_hw *hw);
92 static int em_hardware_init(struct e1000_hw *hw);
93 static void em_hw_control_acquire(struct e1000_hw *hw);
94 static void em_hw_control_release(struct e1000_hw *hw);
95 static void em_init_manageability(struct e1000_hw *hw);
96 static void em_release_manageability(struct e1000_hw *hw);
98 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
100 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
101 uint16_t vlan_id, int on);
102 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
103 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
104 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
105 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
106 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
109 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
110 uint16_t vlan_id, int on);
113 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
114 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
115 static void em_lsc_intr_disable(struct e1000_hw *hw);
116 static void em_rxq_intr_enable(struct e1000_hw *hw);
117 static void em_rxq_intr_disable(struct e1000_hw *hw);
119 static int eth_em_led_on(struct rte_eth_dev *dev);
120 static int eth_em_led_off(struct rte_eth_dev *dev);
122 static int em_get_rx_buffer_size(struct e1000_hw *hw);
123 static int eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
124 uint32_t index, uint32_t pool);
125 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
127 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
128 struct ether_addr *mc_addr_set,
129 uint32_t nb_mc_addr);
131 #define EM_FC_PAUSE_TIME 0x0680
132 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
133 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
135 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
138 * The set of PCI devices this driver supports
140 static const struct rte_pci_id pci_id_em_map[] = {
141 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
142 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
143 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
144 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
145 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
146 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
147 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
148 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
149 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
150 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
151 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
152 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
153 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
154 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
155 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
156 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
157 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
158 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
159 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
160 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
161 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
162 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
163 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
164 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
165 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
166 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
167 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
168 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
169 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
170 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
171 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
172 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
173 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
174 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
175 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
176 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
177 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
178 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
179 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
180 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
181 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
182 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
183 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
184 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
185 { .vendor_id = 0, /* sentinel */ },
188 static const struct eth_dev_ops eth_em_ops = {
189 .dev_configure = eth_em_configure,
190 .dev_start = eth_em_start,
191 .dev_stop = eth_em_stop,
192 .dev_close = eth_em_close,
193 .promiscuous_enable = eth_em_promiscuous_enable,
194 .promiscuous_disable = eth_em_promiscuous_disable,
195 .allmulticast_enable = eth_em_allmulticast_enable,
196 .allmulticast_disable = eth_em_allmulticast_disable,
197 .link_update = eth_em_link_update,
198 .stats_get = eth_em_stats_get,
199 .stats_reset = eth_em_stats_reset,
200 .dev_infos_get = eth_em_infos_get,
201 .mtu_set = eth_em_mtu_set,
202 .vlan_filter_set = eth_em_vlan_filter_set,
203 .vlan_offload_set = eth_em_vlan_offload_set,
204 .rx_queue_setup = eth_em_rx_queue_setup,
205 .rx_queue_release = eth_em_rx_queue_release,
206 .rx_queue_count = eth_em_rx_queue_count,
207 .rx_descriptor_done = eth_em_rx_descriptor_done,
208 .rx_descriptor_status = eth_em_rx_descriptor_status,
209 .tx_descriptor_status = eth_em_tx_descriptor_status,
210 .tx_queue_setup = eth_em_tx_queue_setup,
211 .tx_queue_release = eth_em_tx_queue_release,
212 .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
213 .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
214 .dev_led_on = eth_em_led_on,
215 .dev_led_off = eth_em_led_off,
216 .flow_ctrl_get = eth_em_flow_ctrl_get,
217 .flow_ctrl_set = eth_em_flow_ctrl_set,
218 .mac_addr_add = eth_em_rar_set,
219 .mac_addr_remove = eth_em_rar_clear,
220 .set_mc_addr_list = eth_em_set_mc_addr_list,
221 .rxq_info_get = em_rxq_info_get,
222 .txq_info_get = em_txq_info_get,
226 * Atomically reads the link status information from global
227 * structure rte_eth_dev.
230 * - Pointer to the structure rte_eth_dev to read from.
231 * - Pointer to the buffer to be saved with the link status.
234 * - On success, zero.
235 * - On failure, negative value.
238 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
239 struct rte_eth_link *link)
241 struct rte_eth_link *dst = link;
242 struct rte_eth_link *src = &(dev->data->dev_link);
244 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
245 *(uint64_t *)src) == 0)
252 * Atomically writes the link status information into global
253 * structure rte_eth_dev.
256 * - Pointer to the structure rte_eth_dev to read from.
257 * - Pointer to the buffer to be saved with the link status.
260 * - On success, zero.
261 * - On failure, negative value.
264 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
265 struct rte_eth_link *link)
267 struct rte_eth_link *dst = &(dev->data->dev_link);
268 struct rte_eth_link *src = link;
270 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
271 *(uint64_t *)src) == 0)
278 * eth_em_dev_is_ich8 - Check for ICH8 device
279 * @hw: pointer to the HW structure
281 * return TRUE for ICH8, otherwise FALSE
284 eth_em_dev_is_ich8(struct e1000_hw *hw)
286 DEBUGFUNC("eth_em_dev_is_ich8");
288 switch (hw->device_id) {
289 case E1000_DEV_ID_PCH_LPT_I217_LM:
290 case E1000_DEV_ID_PCH_LPT_I217_V:
291 case E1000_DEV_ID_PCH_LPTLP_I218_LM:
292 case E1000_DEV_ID_PCH_LPTLP_I218_V:
293 case E1000_DEV_ID_PCH_I218_V2:
294 case E1000_DEV_ID_PCH_I218_LM2:
295 case E1000_DEV_ID_PCH_I218_V3:
296 case E1000_DEV_ID_PCH_I218_LM3:
297 case E1000_DEV_ID_PCH_SPT_I219_LM:
298 case E1000_DEV_ID_PCH_SPT_I219_V:
299 case E1000_DEV_ID_PCH_SPT_I219_LM2:
300 case E1000_DEV_ID_PCH_SPT_I219_V2:
301 case E1000_DEV_ID_PCH_LBG_I219_LM3:
302 case E1000_DEV_ID_PCH_SPT_I219_LM4:
303 case E1000_DEV_ID_PCH_SPT_I219_V4:
304 case E1000_DEV_ID_PCH_SPT_I219_LM5:
305 case E1000_DEV_ID_PCH_SPT_I219_V5:
306 case E1000_DEV_ID_PCH_CNP_I219_LM6:
307 case E1000_DEV_ID_PCH_CNP_I219_V6:
308 case E1000_DEV_ID_PCH_CNP_I219_LM7:
309 case E1000_DEV_ID_PCH_CNP_I219_V7:
317 eth_em_dev_init(struct rte_eth_dev *eth_dev)
319 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
320 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
321 struct e1000_adapter *adapter =
322 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
323 struct e1000_hw *hw =
324 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
325 struct e1000_vfta * shadow_vfta =
326 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
328 eth_dev->dev_ops = ð_em_ops;
329 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
330 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
331 eth_dev->tx_pkt_prepare = (eth_tx_prep_t)ð_em_prep_pkts;
333 /* for secondary processes, we don't initialise any further as primary
334 * has already done this work. Only check we don't need a different
336 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
337 if (eth_dev->data->scattered_rx)
338 eth_dev->rx_pkt_burst =
339 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
343 rte_eth_copy_pci_info(eth_dev, pci_dev);
344 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
346 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
347 hw->device_id = pci_dev->id.device_id;
348 adapter->stopped = 0;
350 /* For ICH8 support we'll need to map the flash memory BAR */
351 if (eth_em_dev_is_ich8(hw))
352 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
354 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
355 em_hw_init(hw) != 0) {
356 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
358 eth_dev->data->port_id, pci_dev->id.vendor_id,
359 pci_dev->id.device_id);
363 /* Allocate memory for storing MAC addresses */
364 eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
365 hw->mac.rar_entry_count, 0);
366 if (eth_dev->data->mac_addrs == NULL) {
367 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
368 "store MAC addresses",
369 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
373 /* Copy the permanent MAC address */
374 ether_addr_copy((struct ether_addr *) hw->mac.addr,
375 eth_dev->data->mac_addrs);
377 /* initialize the vfta */
378 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
380 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
381 eth_dev->data->port_id, pci_dev->id.vendor_id,
382 pci_dev->id.device_id);
384 rte_intr_callback_register(intr_handle,
385 eth_em_interrupt_handler, eth_dev);
391 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
393 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
394 struct e1000_adapter *adapter =
395 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
396 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
398 PMD_INIT_FUNC_TRACE();
400 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
403 if (adapter->stopped == 0)
404 eth_em_close(eth_dev);
406 eth_dev->dev_ops = NULL;
407 eth_dev->rx_pkt_burst = NULL;
408 eth_dev->tx_pkt_burst = NULL;
410 rte_free(eth_dev->data->mac_addrs);
411 eth_dev->data->mac_addrs = NULL;
413 /* disable uio intr before callback unregister */
414 rte_intr_disable(intr_handle);
415 rte_intr_callback_unregister(intr_handle,
416 eth_em_interrupt_handler, eth_dev);
421 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
422 struct rte_pci_device *pci_dev)
424 return rte_eth_dev_pci_generic_probe(pci_dev,
425 sizeof(struct e1000_adapter), eth_em_dev_init);
428 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
430 return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
433 static struct rte_pci_driver rte_em_pmd = {
434 .id_table = pci_id_em_map,
435 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
436 RTE_PCI_DRV_IOVA_AS_VA,
437 .probe = eth_em_pci_probe,
438 .remove = eth_em_pci_remove,
442 em_hw_init(struct e1000_hw *hw)
446 diag = hw->mac.ops.init_params(hw);
448 PMD_INIT_LOG(ERR, "MAC Initialization Error");
451 diag = hw->nvm.ops.init_params(hw);
453 PMD_INIT_LOG(ERR, "NVM Initialization Error");
456 diag = hw->phy.ops.init_params(hw);
458 PMD_INIT_LOG(ERR, "PHY Initialization Error");
461 (void) e1000_get_bus_info(hw);
464 hw->phy.autoneg_wait_to_complete = 0;
465 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
467 e1000_init_script_state_82541(hw, TRUE);
468 e1000_set_tbi_compatibility_82543(hw, TRUE);
471 if (hw->phy.media_type == e1000_media_type_copper) {
472 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
473 hw->phy.disable_polarity_correction = 0;
474 hw->phy.ms_type = e1000_ms_hw_default;
478 * Start from a known state, this is important in reading the nvm
483 /* Make sure we have a good EEPROM before we read from it */
484 if (e1000_validate_nvm_checksum(hw) < 0) {
486 * Some PCI-E parts fail the first check due to
487 * the link being in sleep state, call it again,
488 * if it fails a second time its a real issue.
490 diag = e1000_validate_nvm_checksum(hw);
492 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
497 /* Read the permanent MAC address out of the EEPROM */
498 diag = e1000_read_mac_addr(hw);
500 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
504 /* Now initialize the hardware */
505 diag = em_hardware_init(hw);
507 PMD_INIT_LOG(ERR, "Hardware initialization failed");
511 hw->mac.get_link_status = 1;
513 /* Indicate SOL/IDER usage */
514 diag = e1000_check_reset_block(hw);
516 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
522 em_hw_control_release(hw);
527 eth_em_configure(struct rte_eth_dev *dev)
529 struct e1000_interrupt *intr =
530 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
532 PMD_INIT_FUNC_TRACE();
533 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
534 PMD_INIT_FUNC_TRACE();
540 em_set_pba(struct e1000_hw *hw)
545 * Packet Buffer Allocation (PBA)
546 * Writing PBA sets the receive portion of the buffer
547 * the remainder is used for the transmit buffer.
548 * Devices before the 82547 had a Packet Buffer of 64K.
549 * After the 82547 the buffer was reduced to 40K.
551 switch (hw->mac.type) {
553 case e1000_82547_rev_2:
554 /* 82547: Total Packet Buffer is 40K */
555 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
559 case e1000_80003es2lan:
560 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
562 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
563 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
567 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
584 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
587 E1000_WRITE_REG(hw, E1000_PBA, pba);
591 eth_em_start(struct rte_eth_dev *dev)
593 struct e1000_adapter *adapter =
594 E1000_DEV_PRIVATE(dev->data->dev_private);
595 struct e1000_hw *hw =
596 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
597 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
598 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
600 uint32_t intr_vector = 0;
605 PMD_INIT_FUNC_TRACE();
609 e1000_power_up_phy(hw);
611 /* Set default PBA value */
614 /* Put the address into the Receive Address Array */
615 e1000_rar_set(hw, hw->mac.addr, 0);
618 * With the 82571 adapter, RAR[0] may be overwritten
619 * when the other port is reset, we make a duplicate
620 * in RAR[14] for that eventuality, this assures
621 * the interface continues to function.
623 if (hw->mac.type == e1000_82571) {
624 e1000_set_laa_state_82571(hw, TRUE);
625 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
628 /* Initialize the hardware */
629 if (em_hardware_init(hw)) {
630 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
634 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
636 /* Configure for OS presence */
637 em_init_manageability(hw);
639 if (dev->data->dev_conf.intr_conf.rxq != 0) {
640 intr_vector = dev->data->nb_rx_queues;
641 if (rte_intr_efd_enable(intr_handle, intr_vector))
645 if (rte_intr_dp_is_en(intr_handle)) {
646 intr_handle->intr_vec =
647 rte_zmalloc("intr_vec",
648 dev->data->nb_rx_queues * sizeof(int), 0);
649 if (intr_handle->intr_vec == NULL) {
650 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
651 " intr_vec", dev->data->nb_rx_queues);
655 /* enable rx interrupt */
656 em_rxq_intr_enable(hw);
661 ret = eth_em_rx_init(dev);
663 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
664 em_dev_clear_queues(dev);
668 e1000_clear_hw_cntrs_base_generic(hw);
670 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
671 ETH_VLAN_EXTEND_MASK;
672 eth_em_vlan_offload_set(dev, mask);
674 /* Set Interrupt Throttling Rate to maximum allowed value. */
675 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
677 /* Setup link speed and duplex */
678 speeds = &dev->data->dev_conf.link_speeds;
679 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
680 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
684 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
687 hw->phy.autoneg_advertised = 0;
689 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
690 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
691 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
693 goto error_invalid_config;
695 if (*speeds & ETH_LINK_SPEED_10M_HD) {
696 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
699 if (*speeds & ETH_LINK_SPEED_10M) {
700 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
703 if (*speeds & ETH_LINK_SPEED_100M_HD) {
704 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
707 if (*speeds & ETH_LINK_SPEED_100M) {
708 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
711 if (*speeds & ETH_LINK_SPEED_1G) {
712 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
715 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
716 goto error_invalid_config;
718 /* Set/reset the mac.autoneg based on the link speed,
723 hw->mac.forced_speed_duplex =
724 hw->phy.autoneg_advertised;
730 e1000_setup_link(hw);
732 if (rte_intr_allow_others(intr_handle)) {
733 /* check if lsc interrupt is enabled */
734 if (dev->data->dev_conf.intr_conf.lsc != 0) {
735 ret = eth_em_interrupt_setup(dev);
737 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
738 em_dev_clear_queues(dev);
743 rte_intr_callback_unregister(intr_handle,
744 eth_em_interrupt_handler,
746 if (dev->data->dev_conf.intr_conf.lsc != 0)
747 PMD_INIT_LOG(INFO, "lsc won't enable because of"
748 " no intr multiplexn");
750 /* check if rxq interrupt is enabled */
751 if (dev->data->dev_conf.intr_conf.rxq != 0)
752 eth_em_rxq_interrupt_setup(dev);
754 rte_intr_enable(intr_handle);
756 adapter->stopped = 0;
758 PMD_INIT_LOG(DEBUG, "<<");
762 error_invalid_config:
763 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
764 dev->data->dev_conf.link_speeds, dev->data->port_id);
765 em_dev_clear_queues(dev);
769 /*********************************************************************
771 * This routine disables all traffic on the adapter by issuing a
772 * global reset on the MAC.
774 **********************************************************************/
776 eth_em_stop(struct rte_eth_dev *dev)
778 struct rte_eth_link link;
779 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
780 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
781 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
783 em_rxq_intr_disable(hw);
784 em_lsc_intr_disable(hw);
787 if (hw->mac.type >= e1000_82544)
788 E1000_WRITE_REG(hw, E1000_WUC, 0);
790 /* Power down the phy. Needed to make the link go down */
791 e1000_power_down_phy(hw);
793 em_dev_clear_queues(dev);
795 /* clear the recorded link status */
796 memset(&link, 0, sizeof(link));
797 rte_em_dev_atomic_write_link_status(dev, &link);
799 if (!rte_intr_allow_others(intr_handle))
800 /* resume to the default handler */
801 rte_intr_callback_register(intr_handle,
802 eth_em_interrupt_handler,
805 /* Clean datapath event and queue/vec mapping */
806 rte_intr_efd_disable(intr_handle);
807 if (intr_handle->intr_vec != NULL) {
808 rte_free(intr_handle->intr_vec);
809 intr_handle->intr_vec = NULL;
814 eth_em_close(struct rte_eth_dev *dev)
816 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
817 struct e1000_adapter *adapter =
818 E1000_DEV_PRIVATE(dev->data->dev_private);
821 adapter->stopped = 1;
822 em_dev_free_queues(dev);
823 e1000_phy_hw_reset(hw);
824 em_release_manageability(hw);
825 em_hw_control_release(hw);
829 em_get_rx_buffer_size(struct e1000_hw *hw)
831 uint32_t rx_buf_size;
833 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
837 /*********************************************************************
839 * Initialize the hardware
841 **********************************************************************/
843 em_hardware_init(struct e1000_hw *hw)
845 uint32_t rx_buf_size;
848 /* Issue a global reset */
851 /* Let the firmware know the OS is in control */
852 em_hw_control_acquire(hw);
855 * These parameters control the automatic generation (Tx) and
856 * response (Rx) to Ethernet PAUSE frames.
857 * - High water mark should allow for at least two standard size (1518)
858 * frames to be received after sending an XOFF.
859 * - Low water mark works best when it is very near the high water mark.
860 * This allows the receiver to restart by sending XON when it has
861 * drained a bit. Here we use an arbitrary value of 1500 which will
862 * restart after one full frame is pulled from the buffer. There
863 * could be several smaller frames in the buffer and if so they will
864 * not trigger the XON until their total number reduces the buffer
866 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
868 rx_buf_size = em_get_rx_buffer_size(hw);
870 hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
871 hw->fc.low_water = hw->fc.high_water - 1500;
873 if (hw->mac.type == e1000_80003es2lan)
874 hw->fc.pause_time = UINT16_MAX;
876 hw->fc.pause_time = EM_FC_PAUSE_TIME;
880 /* Set Flow control, use the tunable location if sane */
881 if (em_fc_setting <= e1000_fc_full)
882 hw->fc.requested_mode = em_fc_setting;
884 hw->fc.requested_mode = e1000_fc_none;
886 /* Workaround: no TX flow ctrl for PCH */
887 if (hw->mac.type == e1000_pchlan)
888 hw->fc.requested_mode = e1000_fc_rx_pause;
890 /* Override - settings for PCH2LAN, ya its magic :) */
891 if (hw->mac.type == e1000_pch2lan) {
892 hw->fc.high_water = 0x5C20;
893 hw->fc.low_water = 0x5048;
894 hw->fc.pause_time = 0x0650;
895 hw->fc.refresh_time = 0x0400;
896 } else if (hw->mac.type == e1000_pch_lpt ||
897 hw->mac.type == e1000_pch_spt ||
898 hw->mac.type == e1000_pch_cnp) {
899 hw->fc.requested_mode = e1000_fc_full;
902 diag = e1000_init_hw(hw);
905 e1000_check_for_link(hw);
909 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
911 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
913 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
914 struct e1000_hw_stats *stats =
915 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
918 if(hw->phy.media_type == e1000_media_type_copper ||
919 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
920 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
921 stats->sec += E1000_READ_REG(hw, E1000_SEC);
924 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
925 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
926 stats->scc += E1000_READ_REG(hw, E1000_SCC);
927 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
929 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
930 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
931 stats->colc += E1000_READ_REG(hw, E1000_COLC);
932 stats->dc += E1000_READ_REG(hw, E1000_DC);
933 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
934 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
935 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
938 * For watchdog management we need to know if we have been
939 * paused during the last interval, so capture that here.
941 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
942 stats->xoffrxc += pause_frames;
943 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
944 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
945 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
946 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
947 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
948 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
949 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
950 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
951 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
952 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
953 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
954 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
957 * For the 64-bit byte counters the low dword must be read first.
958 * Both registers clear on the read of the high dword.
961 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
962 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
963 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
964 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
966 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
967 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
968 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
969 stats->roc += E1000_READ_REG(hw, E1000_ROC);
970 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
972 stats->tor += E1000_READ_REG(hw, E1000_TORH);
973 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
975 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
976 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
977 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
978 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
979 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
980 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
981 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
982 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
983 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
984 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
986 /* Interrupt Counts */
988 if (hw->mac.type >= e1000_82571) {
989 stats->iac += E1000_READ_REG(hw, E1000_IAC);
990 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
991 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
992 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
993 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
994 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
995 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
996 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
997 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1000 if (hw->mac.type >= e1000_82543) {
1001 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1002 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1003 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1004 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1005 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1006 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1009 if (rte_stats == NULL)
1013 rte_stats->imissed = stats->mpc;
1014 rte_stats->ierrors = stats->crcerrs +
1015 stats->rlec + stats->ruc + stats->roc +
1016 stats->rxerrc + stats->algnerrc + stats->cexterr;
1019 rte_stats->oerrors = stats->ecol + stats->latecol;
1021 rte_stats->ipackets = stats->gprc;
1022 rte_stats->opackets = stats->gptc;
1023 rte_stats->ibytes = stats->gorc;
1024 rte_stats->obytes = stats->gotc;
1029 eth_em_stats_reset(struct rte_eth_dev *dev)
1031 struct e1000_hw_stats *hw_stats =
1032 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1034 /* HW registers are cleared on read */
1035 eth_em_stats_get(dev, NULL);
1037 /* Reset software totals */
1038 memset(hw_stats, 0, sizeof(*hw_stats));
1042 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1044 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1045 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1046 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1048 em_rxq_intr_enable(hw);
1049 rte_intr_enable(intr_handle);
1055 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1057 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1059 em_rxq_intr_disable(hw);
1065 em_get_max_pktlen(const struct e1000_hw *hw)
1067 switch (hw->mac.type) {
1071 case e1000_ich10lan:
1077 case e1000_80003es2lan: /* 9K Jumbo Frame size */
1082 /* Adapters that do not support jumbo frames */
1084 return ETHER_MAX_LEN;
1086 return MAX_JUMBO_FRAME_SIZE;
1091 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1093 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1095 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1096 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1097 dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1098 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1099 dev_info->rx_offload_capa =
1100 DEV_RX_OFFLOAD_VLAN_STRIP |
1101 DEV_RX_OFFLOAD_IPV4_CKSUM |
1102 DEV_RX_OFFLOAD_UDP_CKSUM |
1103 DEV_RX_OFFLOAD_TCP_CKSUM;
1104 dev_info->tx_offload_capa =
1105 DEV_TX_OFFLOAD_VLAN_INSERT |
1106 DEV_TX_OFFLOAD_IPV4_CKSUM |
1107 DEV_TX_OFFLOAD_UDP_CKSUM |
1108 DEV_TX_OFFLOAD_TCP_CKSUM;
1111 * Starting with 631xESB hw supports 2 TX/RX queues per port.
1112 * Unfortunatelly, all these nics have just one TX context.
1113 * So we have few choises for TX:
1114 * - Use just one TX queue.
1115 * - Allow cksum offload only for one TX queue.
1116 * - Don't allow TX cksum offload at all.
1117 * For now, option #1 was chosen.
1118 * To use second RX queue we have to use extended RX descriptor
1119 * (Multiple Receive Queues are mutually exclusive with UDP
1120 * fragmentation and are not supported when a legacy receive
1121 * descriptor format is used).
1122 * Which means separate RX routinies - as legacy nics (82540, 82545)
1123 * don't support extended RXD.
1124 * To avoid it we support just one RX queue for now (no RSS).
1127 dev_info->max_rx_queues = 1;
1128 dev_info->max_tx_queues = 1;
1130 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1131 .nb_max = E1000_MAX_RING_DESC,
1132 .nb_min = E1000_MIN_RING_DESC,
1133 .nb_align = EM_RXD_ALIGN,
1136 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1137 .nb_max = E1000_MAX_RING_DESC,
1138 .nb_min = E1000_MIN_RING_DESC,
1139 .nb_align = EM_TXD_ALIGN,
1140 .nb_seg_max = EM_TX_MAX_SEG,
1141 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1144 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1145 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1149 /* return 0 means link status changed, -1 means not changed */
1151 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1153 struct e1000_hw *hw =
1154 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1155 struct rte_eth_link link, old;
1156 int link_check, count;
1159 hw->mac.get_link_status = 1;
1161 /* possible wait-to-complete in up to 9 seconds */
1162 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1163 /* Read the real link status */
1164 switch (hw->phy.media_type) {
1165 case e1000_media_type_copper:
1166 /* Do the work to read phy */
1167 e1000_check_for_link(hw);
1168 link_check = !hw->mac.get_link_status;
1171 case e1000_media_type_fiber:
1172 e1000_check_for_link(hw);
1173 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1177 case e1000_media_type_internal_serdes:
1178 e1000_check_for_link(hw);
1179 link_check = hw->mac.serdes_has_link;
1185 if (link_check || wait_to_complete == 0)
1187 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1189 memset(&link, 0, sizeof(link));
1190 rte_em_dev_atomic_read_link_status(dev, &link);
1193 /* Now we check if a transition has happened */
1194 if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1195 uint16_t duplex, speed;
1196 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1197 link.link_duplex = (duplex == FULL_DUPLEX) ?
1198 ETH_LINK_FULL_DUPLEX :
1199 ETH_LINK_HALF_DUPLEX;
1200 link.link_speed = speed;
1201 link.link_status = ETH_LINK_UP;
1202 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1203 ETH_LINK_SPEED_FIXED);
1204 } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1205 link.link_speed = 0;
1206 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1207 link.link_status = ETH_LINK_DOWN;
1208 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1210 rte_em_dev_atomic_write_link_status(dev, &link);
1213 if (old.link_status == link.link_status)
1221 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1222 * For ASF and Pass Through versions of f/w this means
1223 * that the driver is loaded. For AMT version type f/w
1224 * this means that the network i/f is open.
1227 em_hw_control_acquire(struct e1000_hw *hw)
1229 uint32_t ctrl_ext, swsm;
1231 /* Let firmware know the driver has taken over */
1232 if (hw->mac.type == e1000_82573) {
1233 swsm = E1000_READ_REG(hw, E1000_SWSM);
1234 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1237 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1238 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1239 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1244 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1245 * For ASF and Pass Through versions of f/w this means that the
1246 * driver is no longer loaded. For AMT versions of the
1247 * f/w this means that the network i/f is closed.
1250 em_hw_control_release(struct e1000_hw *hw)
1252 uint32_t ctrl_ext, swsm;
1254 /* Let firmware taken over control of h/w */
1255 if (hw->mac.type == e1000_82573) {
1256 swsm = E1000_READ_REG(hw, E1000_SWSM);
1257 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1259 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1260 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1261 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1266 * Bit of a misnomer, what this really means is
1267 * to enable OS management of the system... aka
1268 * to disable special hardware management features.
1271 em_init_manageability(struct e1000_hw *hw)
1273 if (e1000_enable_mng_pass_thru(hw)) {
1274 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1275 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1277 /* disable hardware interception of ARP */
1278 manc &= ~(E1000_MANC_ARP_EN);
1280 /* enable receiving management packets to the host */
1281 manc |= E1000_MANC_EN_MNG2HOST;
1282 manc2h |= 1 << 5; /* Mng Port 623 */
1283 manc2h |= 1 << 6; /* Mng Port 664 */
1284 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1285 E1000_WRITE_REG(hw, E1000_MANC, manc);
1290 * Give control back to hardware management
1291 * controller if there is one.
1294 em_release_manageability(struct e1000_hw *hw)
1298 if (e1000_enable_mng_pass_thru(hw)) {
1299 manc = E1000_READ_REG(hw, E1000_MANC);
1301 /* re-enable hardware interception of ARP */
1302 manc |= E1000_MANC_ARP_EN;
1303 manc &= ~E1000_MANC_EN_MNG2HOST;
1305 E1000_WRITE_REG(hw, E1000_MANC, manc);
1310 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1312 struct e1000_hw *hw =
1313 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1316 rctl = E1000_READ_REG(hw, E1000_RCTL);
1317 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1318 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1322 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1324 struct e1000_hw *hw =
1325 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1328 rctl = E1000_READ_REG(hw, E1000_RCTL);
1329 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1330 if (dev->data->all_multicast == 1)
1331 rctl |= E1000_RCTL_MPE;
1333 rctl &= (~E1000_RCTL_MPE);
1334 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1338 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1340 struct e1000_hw *hw =
1341 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1344 rctl = E1000_READ_REG(hw, E1000_RCTL);
1345 rctl |= E1000_RCTL_MPE;
1346 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1350 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1352 struct e1000_hw *hw =
1353 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1356 if (dev->data->promiscuous == 1)
1357 return; /* must remain in all_multicast mode */
1358 rctl = E1000_READ_REG(hw, E1000_RCTL);
1359 rctl &= (~E1000_RCTL_MPE);
1360 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1364 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1366 struct e1000_hw *hw =
1367 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1368 struct e1000_vfta * shadow_vfta =
1369 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1374 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1375 E1000_VFTA_ENTRY_MASK);
1376 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1377 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1382 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1384 /* update local VFTA copy */
1385 shadow_vfta->vfta[vid_idx] = vfta;
1391 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1393 struct e1000_hw *hw =
1394 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397 /* Filter Table Disable */
1398 reg = E1000_READ_REG(hw, E1000_RCTL);
1399 reg &= ~E1000_RCTL_CFIEN;
1400 reg &= ~E1000_RCTL_VFE;
1401 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1405 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1407 struct e1000_hw *hw =
1408 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1409 struct e1000_vfta * shadow_vfta =
1410 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1414 /* Filter Table Enable, CFI not used for packet acceptance */
1415 reg = E1000_READ_REG(hw, E1000_RCTL);
1416 reg &= ~E1000_RCTL_CFIEN;
1417 reg |= E1000_RCTL_VFE;
1418 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1420 /* restore vfta from local copy */
1421 for (i = 0; i < IGB_VFTA_SIZE; i++)
1422 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1426 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1428 struct e1000_hw *hw =
1429 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1432 /* VLAN Mode Disable */
1433 reg = E1000_READ_REG(hw, E1000_CTRL);
1434 reg &= ~E1000_CTRL_VME;
1435 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1440 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1442 struct e1000_hw *hw =
1443 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1446 /* VLAN Mode Enable */
1447 reg = E1000_READ_REG(hw, E1000_CTRL);
1448 reg |= E1000_CTRL_VME;
1449 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1453 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1455 if(mask & ETH_VLAN_STRIP_MASK){
1456 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1457 em_vlan_hw_strip_enable(dev);
1459 em_vlan_hw_strip_disable(dev);
1462 if(mask & ETH_VLAN_FILTER_MASK){
1463 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1464 em_vlan_hw_filter_enable(dev);
1466 em_vlan_hw_filter_disable(dev);
1471 * It enables the interrupt mask and then enable the interrupt.
1474 * Pointer to struct rte_eth_dev.
1477 * - On success, zero.
1478 * - On failure, a negative value.
1481 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1484 struct e1000_hw *hw =
1485 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1487 /* clear interrupt */
1488 E1000_READ_REG(hw, E1000_ICR);
1489 regval = E1000_READ_REG(hw, E1000_IMS);
1490 E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1495 * It clears the interrupt causes and enables the interrupt.
1496 * It will be called once only during nic initialized.
1499 * Pointer to struct rte_eth_dev.
1502 * - On success, zero.
1503 * - On failure, a negative value.
1506 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1508 struct e1000_hw *hw =
1509 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1511 E1000_READ_REG(hw, E1000_ICR);
1512 em_rxq_intr_enable(hw);
1517 * It enable receive packet interrupt.
1519 * Pointer to struct e1000_hw
1524 em_rxq_intr_enable(struct e1000_hw *hw)
1526 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1527 E1000_WRITE_FLUSH(hw);
1531 * It disabled lsc interrupt.
1533 * Pointer to struct e1000_hw
1538 em_lsc_intr_disable(struct e1000_hw *hw)
1540 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1541 E1000_WRITE_FLUSH(hw);
1545 * It disabled receive packet interrupt.
1547 * Pointer to struct e1000_hw
1552 em_rxq_intr_disable(struct e1000_hw *hw)
1554 E1000_READ_REG(hw, E1000_ICR);
1555 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1556 E1000_WRITE_FLUSH(hw);
1560 * It reads ICR and gets interrupt causes, check it and set a bit flag
1561 * to update link status.
1564 * Pointer to struct rte_eth_dev.
1567 * - On success, zero.
1568 * - On failure, a negative value.
1571 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1574 struct e1000_hw *hw =
1575 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1576 struct e1000_interrupt *intr =
1577 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1579 /* read-on-clear nic registers here */
1580 icr = E1000_READ_REG(hw, E1000_ICR);
1581 if (icr & E1000_ICR_LSC) {
1582 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1589 * It executes link_update after knowing an interrupt is prsent.
1592 * Pointer to struct rte_eth_dev.
1595 * - On success, zero.
1596 * - On failure, a negative value.
1599 eth_em_interrupt_action(struct rte_eth_dev *dev,
1600 struct rte_intr_handle *intr_handle)
1602 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1603 struct e1000_hw *hw =
1604 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1605 struct e1000_interrupt *intr =
1606 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1607 uint32_t tctl, rctl;
1608 struct rte_eth_link link;
1611 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1614 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1615 rte_intr_enable(intr_handle);
1617 /* set get_link_status to check register later */
1618 hw->mac.get_link_status = 1;
1619 ret = eth_em_link_update(dev, 0);
1621 /* check if link has changed */
1625 memset(&link, 0, sizeof(link));
1626 rte_em_dev_atomic_read_link_status(dev, &link);
1627 if (link.link_status) {
1628 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1629 dev->data->port_id, link.link_speed,
1630 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1631 "full-duplex" : "half-duplex");
1633 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1635 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1636 pci_dev->addr.domain, pci_dev->addr.bus,
1637 pci_dev->addr.devid, pci_dev->addr.function);
1639 tctl = E1000_READ_REG(hw, E1000_TCTL);
1640 rctl = E1000_READ_REG(hw, E1000_RCTL);
1641 if (link.link_status) {
1643 tctl |= E1000_TCTL_EN;
1644 rctl |= E1000_RCTL_EN;
1647 tctl &= ~E1000_TCTL_EN;
1648 rctl &= ~E1000_RCTL_EN;
1650 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1651 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1652 E1000_WRITE_FLUSH(hw);
1658 * Interrupt handler which shall be registered at first.
1661 * Pointer to interrupt handle.
1663 * The address of parameter (struct rte_eth_dev *) regsitered before.
1669 eth_em_interrupt_handler(void *param)
1671 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1673 eth_em_interrupt_get_status(dev);
1674 eth_em_interrupt_action(dev, dev->intr_handle);
1675 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1679 eth_em_led_on(struct rte_eth_dev *dev)
1681 struct e1000_hw *hw;
1683 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1684 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1688 eth_em_led_off(struct rte_eth_dev *dev)
1690 struct e1000_hw *hw;
1692 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1693 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1697 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1699 struct e1000_hw *hw;
1704 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1705 fc_conf->pause_time = hw->fc.pause_time;
1706 fc_conf->high_water = hw->fc.high_water;
1707 fc_conf->low_water = hw->fc.low_water;
1708 fc_conf->send_xon = hw->fc.send_xon;
1709 fc_conf->autoneg = hw->mac.autoneg;
1712 * Return rx_pause and tx_pause status according to actual setting of
1713 * the TFCE and RFCE bits in the CTRL register.
1715 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1716 if (ctrl & E1000_CTRL_TFCE)
1721 if (ctrl & E1000_CTRL_RFCE)
1726 if (rx_pause && tx_pause)
1727 fc_conf->mode = RTE_FC_FULL;
1729 fc_conf->mode = RTE_FC_RX_PAUSE;
1731 fc_conf->mode = RTE_FC_TX_PAUSE;
1733 fc_conf->mode = RTE_FC_NONE;
1739 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1741 struct e1000_hw *hw;
1743 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1749 uint32_t rx_buf_size;
1750 uint32_t max_high_water;
1753 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1754 if (fc_conf->autoneg != hw->mac.autoneg)
1756 rx_buf_size = em_get_rx_buffer_size(hw);
1757 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1759 /* At least reserve one Ethernet frame for watermark */
1760 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1761 if ((fc_conf->high_water > max_high_water) ||
1762 (fc_conf->high_water < fc_conf->low_water)) {
1763 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1764 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1768 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1769 hw->fc.pause_time = fc_conf->pause_time;
1770 hw->fc.high_water = fc_conf->high_water;
1771 hw->fc.low_water = fc_conf->low_water;
1772 hw->fc.send_xon = fc_conf->send_xon;
1774 err = e1000_setup_link_generic(hw);
1775 if (err == E1000_SUCCESS) {
1777 /* check if we want to forward MAC frames - driver doesn't have native
1778 * capability to do that, so we'll write the registers ourselves */
1780 rctl = E1000_READ_REG(hw, E1000_RCTL);
1782 /* set or clear MFLCN.PMCF bit depending on configuration */
1783 if (fc_conf->mac_ctrl_frame_fwd != 0)
1784 rctl |= E1000_RCTL_PMCF;
1786 rctl &= ~E1000_RCTL_PMCF;
1788 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1789 E1000_WRITE_FLUSH(hw);
1794 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1799 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1800 uint32_t index, __rte_unused uint32_t pool)
1802 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1804 return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1808 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1810 uint8_t addr[ETHER_ADDR_LEN];
1811 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1813 memset(addr, 0, sizeof(addr));
1815 e1000_rar_set(hw, addr, index);
1819 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1821 struct rte_eth_dev_info dev_info;
1822 struct e1000_hw *hw;
1823 uint32_t frame_size;
1826 eth_em_infos_get(dev, &dev_info);
1827 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1829 /* check that mtu is within the allowed range */
1830 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1833 /* refuse mtu that requires the support of scattered packets when this
1834 * feature has not been enabled before. */
1835 if (!dev->data->scattered_rx &&
1836 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1839 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1840 rctl = E1000_READ_REG(hw, E1000_RCTL);
1842 /* switch to jumbo mode if needed */
1843 if (frame_size > ETHER_MAX_LEN) {
1844 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1845 rctl |= E1000_RCTL_LPE;
1847 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1848 rctl &= ~E1000_RCTL_LPE;
1850 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1852 /* update max frame size */
1853 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1858 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1859 struct ether_addr *mc_addr_set,
1860 uint32_t nb_mc_addr)
1862 struct e1000_hw *hw;
1864 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1865 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1869 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1870 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1871 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");