a8c26edca7f551305860c809ddc12dbe17fba864
[dpdk.git] / drivers / net / e1000 / em_ethdev.c
1 /*-
2  *   BSD LICENSE
3  *
4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5  *   All rights reserved.
6  *
7  *   Redistribution and use in source and binary forms, with or without
8  *   modification, are permitted provided that the following conditions
9  *   are met:
10  *
11  *     * Redistributions of source code must retain the above copyright
12  *       notice, this list of conditions and the following disclaimer.
13  *     * Redistributions in binary form must reproduce the above copyright
14  *       notice, this list of conditions and the following disclaimer in
15  *       the documentation and/or other materials provided with the
16  *       distribution.
17  *     * Neither the name of Intel Corporation nor the names of its
18  *       contributors may be used to endorse or promote products derived
19  *       from this software without specific prior written permission.
20  *
21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33
34 #include <sys/queue.h>
35 #include <stdio.h>
36 #include <errno.h>
37 #include <stdint.h>
38 #include <stdarg.h>
39
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
43 #include <rte_log.h>
44 #include <rte_debug.h>
45 #include <rte_pci.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
50 #include <rte_eal.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
53 #include <rte_dev.h>
54
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
58
59 #define EM_EIAC                 0x000DC
60
61 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
62
63
64 static int eth_em_configure(struct rte_eth_dev *dev);
65 static int eth_em_start(struct rte_eth_dev *dev);
66 static void eth_em_stop(struct rte_eth_dev *dev);
67 static void eth_em_close(struct rte_eth_dev *dev);
68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
72 static int eth_em_link_update(struct rte_eth_dev *dev,
73                                 int wait_to_complete);
74 static void eth_em_stats_get(struct rte_eth_dev *dev,
75                                 struct rte_eth_stats *rte_stats);
76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
77 static void eth_em_infos_get(struct rte_eth_dev *dev,
78                                 struct rte_eth_dev_info *dev_info);
79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
80                                 struct rte_eth_fc_conf *fc_conf);
81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
82                                 struct rte_eth_fc_conf *fc_conf);
83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
84 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
86 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
87 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
88                                                         void *param);
89
90 static int em_hw_init(struct e1000_hw *hw);
91 static int em_hardware_init(struct e1000_hw *hw);
92 static void em_hw_control_acquire(struct e1000_hw *hw);
93 static void em_hw_control_release(struct e1000_hw *hw);
94 static void em_init_manageability(struct e1000_hw *hw);
95 static void em_release_manageability(struct e1000_hw *hw);
96
97 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
98
99 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
100                 uint16_t vlan_id, int on);
101 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
102 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
103 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
104 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
105 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
106
107 /*
108 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
109                                         uint16_t vlan_id, int on);
110 */
111
112 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
113 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
114 static void em_lsc_intr_disable(struct e1000_hw *hw);
115 static void em_rxq_intr_enable(struct e1000_hw *hw);
116 static void em_rxq_intr_disable(struct e1000_hw *hw);
117
118 static int eth_em_led_on(struct rte_eth_dev *dev);
119 static int eth_em_led_off(struct rte_eth_dev *dev);
120
121 static int em_get_rx_buffer_size(struct e1000_hw *hw);
122 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
123                 uint32_t index, uint32_t pool);
124 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
125
126 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
127                                    struct ether_addr *mc_addr_set,
128                                    uint32_t nb_mc_addr);
129
130 #define EM_FC_PAUSE_TIME 0x0680
131 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
132 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
133
134 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
135
136 /*
137  * The set of PCI devices this driver supports
138  */
139 static const struct rte_pci_id pci_id_em_map[] = {
140
141 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
142 #include "rte_pci_dev_ids.h"
143
144 {0},
145 };
146
147 static const struct eth_dev_ops eth_em_ops = {
148         .dev_configure        = eth_em_configure,
149         .dev_start            = eth_em_start,
150         .dev_stop             = eth_em_stop,
151         .dev_close            = eth_em_close,
152         .promiscuous_enable   = eth_em_promiscuous_enable,
153         .promiscuous_disable  = eth_em_promiscuous_disable,
154         .allmulticast_enable  = eth_em_allmulticast_enable,
155         .allmulticast_disable = eth_em_allmulticast_disable,
156         .link_update          = eth_em_link_update,
157         .stats_get            = eth_em_stats_get,
158         .stats_reset          = eth_em_stats_reset,
159         .dev_infos_get        = eth_em_infos_get,
160         .mtu_set              = eth_em_mtu_set,
161         .vlan_filter_set      = eth_em_vlan_filter_set,
162         .vlan_offload_set     = eth_em_vlan_offload_set,
163         .rx_queue_setup       = eth_em_rx_queue_setup,
164         .rx_queue_release     = eth_em_rx_queue_release,
165         .rx_queue_count       = eth_em_rx_queue_count,
166         .rx_descriptor_done   = eth_em_rx_descriptor_done,
167         .tx_queue_setup       = eth_em_tx_queue_setup,
168         .tx_queue_release     = eth_em_tx_queue_release,
169         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
170         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
171         .dev_led_on           = eth_em_led_on,
172         .dev_led_off          = eth_em_led_off,
173         .flow_ctrl_get        = eth_em_flow_ctrl_get,
174         .flow_ctrl_set        = eth_em_flow_ctrl_set,
175         .mac_addr_add         = eth_em_rar_set,
176         .mac_addr_remove      = eth_em_rar_clear,
177         .set_mc_addr_list     = eth_em_set_mc_addr_list,
178         .rxq_info_get         = em_rxq_info_get,
179         .txq_info_get         = em_txq_info_get,
180 };
181
182 /**
183  * Atomically reads the link status information from global
184  * structure rte_eth_dev.
185  *
186  * @param dev
187  *   - Pointer to the structure rte_eth_dev to read from.
188  *   - Pointer to the buffer to be saved with the link status.
189  *
190  * @return
191  *   - On success, zero.
192  *   - On failure, negative value.
193  */
194 static inline int
195 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
196                                 struct rte_eth_link *link)
197 {
198         struct rte_eth_link *dst = link;
199         struct rte_eth_link *src = &(dev->data->dev_link);
200
201         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
202                                         *(uint64_t *)src) == 0)
203                 return -1;
204
205         return 0;
206 }
207
208 /**
209  * Atomically writes the link status information into global
210  * structure rte_eth_dev.
211  *
212  * @param dev
213  *   - Pointer to the structure rte_eth_dev to read from.
214  *   - Pointer to the buffer to be saved with the link status.
215  *
216  * @return
217  *   - On success, zero.
218  *   - On failure, negative value.
219  */
220 static inline int
221 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
222                                 struct rte_eth_link *link)
223 {
224         struct rte_eth_link *dst = &(dev->data->dev_link);
225         struct rte_eth_link *src = link;
226
227         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
228                                         *(uint64_t *)src) == 0)
229                 return -1;
230
231         return 0;
232 }
233
234 /**
235  *  eth_em_dev_is_ich8 - Check for ICH8 device
236  *  @hw: pointer to the HW structure
237  *
238  *  return TRUE for ICH8, otherwise FALSE
239  **/
240 static bool
241 eth_em_dev_is_ich8(struct e1000_hw *hw)
242 {
243         DEBUGFUNC("eth_em_dev_is_ich8");
244
245         switch (hw->device_id) {
246         case E1000_DEV_ID_PCH_LPT_I217_LM:
247         case E1000_DEV_ID_PCH_LPT_I217_V:
248         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
249         case E1000_DEV_ID_PCH_LPTLP_I218_V:
250         case E1000_DEV_ID_PCH_I218_V2:
251         case E1000_DEV_ID_PCH_I218_LM2:
252         case E1000_DEV_ID_PCH_I218_V3:
253         case E1000_DEV_ID_PCH_I218_LM3:
254                 return 1;
255         default:
256                 return 0;
257         }
258 }
259
260 static int
261 eth_em_dev_init(struct rte_eth_dev *eth_dev)
262 {
263         struct rte_pci_device *pci_dev;
264         struct e1000_adapter *adapter =
265                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
266         struct e1000_hw *hw =
267                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
268         struct e1000_vfta * shadow_vfta =
269                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
270
271         pci_dev = eth_dev->pci_dev;
272
273         eth_dev->dev_ops = &eth_em_ops;
274         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
275         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
276
277         /* for secondary processes, we don't initialise any further as primary
278          * has already done this work. Only check we don't need a different
279          * RX function */
280         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
281                 if (eth_dev->data->scattered_rx)
282                         eth_dev->rx_pkt_burst =
283                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
284                 return 0;
285         }
286
287         rte_eth_copy_pci_info(eth_dev, pci_dev);
288
289         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
290         hw->device_id = pci_dev->id.device_id;
291         adapter->stopped = 0;
292
293         /* For ICH8 support we'll need to map the flash memory BAR */
294         if (eth_em_dev_is_ich8(hw))
295                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
296
297         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
298                         em_hw_init(hw) != 0) {
299                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
300                         "failed to init HW",
301                         eth_dev->data->port_id, pci_dev->id.vendor_id,
302                         pci_dev->id.device_id);
303                 return -ENODEV;
304         }
305
306         /* Allocate memory for storing MAC addresses */
307         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
308                         hw->mac.rar_entry_count, 0);
309         if (eth_dev->data->mac_addrs == NULL) {
310                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
311                         "store MAC addresses",
312                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
313                 return -ENOMEM;
314         }
315
316         /* Copy the permanent MAC address */
317         ether_addr_copy((struct ether_addr *) hw->mac.addr,
318                 eth_dev->data->mac_addrs);
319
320         /* initialize the vfta */
321         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
322
323         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
324                      eth_dev->data->port_id, pci_dev->id.vendor_id,
325                      pci_dev->id.device_id);
326
327         rte_intr_callback_register(&(pci_dev->intr_handle),
328                 eth_em_interrupt_handler, (void *)eth_dev);
329
330         return 0;
331 }
332
333 static int
334 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
335 {
336         struct rte_pci_device *pci_dev;
337         struct e1000_adapter *adapter =
338                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
339
340         PMD_INIT_FUNC_TRACE();
341
342         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
343                 return -EPERM;
344
345         pci_dev = eth_dev->pci_dev;
346
347         if (adapter->stopped == 0)
348                 eth_em_close(eth_dev);
349
350         eth_dev->dev_ops = NULL;
351         eth_dev->rx_pkt_burst = NULL;
352         eth_dev->tx_pkt_burst = NULL;
353
354         rte_free(eth_dev->data->mac_addrs);
355         eth_dev->data->mac_addrs = NULL;
356
357         /* disable uio intr before callback unregister */
358         rte_intr_disable(&(pci_dev->intr_handle));
359         rte_intr_callback_unregister(&(pci_dev->intr_handle),
360                 eth_em_interrupt_handler, (void *)eth_dev);
361
362         return 0;
363 }
364
365 static struct eth_driver rte_em_pmd = {
366         .pci_drv = {
367                 .name = "rte_em_pmd",
368                 .id_table = pci_id_em_map,
369                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
370                         RTE_PCI_DRV_DETACHABLE,
371         },
372         .eth_dev_init = eth_em_dev_init,
373         .eth_dev_uninit = eth_em_dev_uninit,
374         .dev_private_size = sizeof(struct e1000_adapter),
375 };
376
377 static int
378 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
379 {
380         rte_eth_driver_register(&rte_em_pmd);
381         return 0;
382 }
383
384 static int
385 em_hw_init(struct e1000_hw *hw)
386 {
387         int diag;
388
389         diag = hw->mac.ops.init_params(hw);
390         if (diag != 0) {
391                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
392                 return diag;
393         }
394         diag = hw->nvm.ops.init_params(hw);
395         if (diag != 0) {
396                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
397                 return diag;
398         }
399         diag = hw->phy.ops.init_params(hw);
400         if (diag != 0) {
401                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
402                 return diag;
403         }
404         (void) e1000_get_bus_info(hw);
405
406         hw->mac.autoneg = 1;
407         hw->phy.autoneg_wait_to_complete = 0;
408         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
409
410         e1000_init_script_state_82541(hw, TRUE);
411         e1000_set_tbi_compatibility_82543(hw, TRUE);
412
413         /* Copper options */
414         if (hw->phy.media_type == e1000_media_type_copper) {
415                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
416                 hw->phy.disable_polarity_correction = 0;
417                 hw->phy.ms_type = e1000_ms_hw_default;
418         }
419
420         /*
421          * Start from a known state, this is important in reading the nvm
422          * and mac from that.
423          */
424         e1000_reset_hw(hw);
425
426         /* Make sure we have a good EEPROM before we read from it */
427         if (e1000_validate_nvm_checksum(hw) < 0) {
428                 /*
429                  * Some PCI-E parts fail the first check due to
430                  * the link being in sleep state, call it again,
431                  * if it fails a second time its a real issue.
432                  */
433                 diag = e1000_validate_nvm_checksum(hw);
434                 if (diag < 0) {
435                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
436                         goto error;
437                 }
438         }
439
440         /* Read the permanent MAC address out of the EEPROM */
441         diag = e1000_read_mac_addr(hw);
442         if (diag != 0) {
443                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
444                 goto error;
445         }
446
447         /* Now initialize the hardware */
448         diag = em_hardware_init(hw);
449         if (diag != 0) {
450                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
451                 goto error;
452         }
453
454         hw->mac.get_link_status = 1;
455
456         /* Indicate SOL/IDER usage */
457         diag = e1000_check_reset_block(hw);
458         if (diag < 0) {
459                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
460                         "SOL/IDER session");
461         }
462         return 0;
463
464 error:
465         em_hw_control_release(hw);
466         return diag;
467 }
468
469 static int
470 eth_em_configure(struct rte_eth_dev *dev)
471 {
472         struct e1000_interrupt *intr =
473                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
474
475         PMD_INIT_FUNC_TRACE();
476         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
477         PMD_INIT_FUNC_TRACE();
478
479         return 0;
480 }
481
482 static void
483 em_set_pba(struct e1000_hw *hw)
484 {
485         uint32_t pba;
486
487         /*
488          * Packet Buffer Allocation (PBA)
489          * Writing PBA sets the receive portion of the buffer
490          * the remainder is used for the transmit buffer.
491          * Devices before the 82547 had a Packet Buffer of 64K.
492          * After the 82547 the buffer was reduced to 40K.
493          */
494         switch (hw->mac.type) {
495                 case e1000_82547:
496                 case e1000_82547_rev_2:
497                 /* 82547: Total Packet Buffer is 40K */
498                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
499                         break;
500                 case e1000_82571:
501                 case e1000_82572:
502                 case e1000_80003es2lan:
503                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
504                         break;
505                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
506                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
507                         break;
508                 case e1000_82574:
509                 case e1000_82583:
510                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
511                         break;
512                 case e1000_ich8lan:
513                         pba = E1000_PBA_8K;
514                         break;
515                 case e1000_ich9lan:
516                 case e1000_ich10lan:
517                         pba = E1000_PBA_10K;
518                         break;
519                 case e1000_pchlan:
520                 case e1000_pch2lan:
521                 case e1000_pch_lpt:
522                         pba = E1000_PBA_26K;
523                         break;
524                 default:
525                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
526         }
527
528         E1000_WRITE_REG(hw, E1000_PBA, pba);
529 }
530
531 static int
532 eth_em_start(struct rte_eth_dev *dev)
533 {
534         struct e1000_adapter *adapter =
535                 E1000_DEV_PRIVATE(dev->data->dev_private);
536         struct e1000_hw *hw =
537                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
538         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
539         int ret, mask;
540         uint32_t intr_vector = 0;
541
542         PMD_INIT_FUNC_TRACE();
543
544         eth_em_stop(dev);
545
546         e1000_power_up_phy(hw);
547
548         /* Set default PBA value */
549         em_set_pba(hw);
550
551         /* Put the address into the Receive Address Array */
552         e1000_rar_set(hw, hw->mac.addr, 0);
553
554         /*
555          * With the 82571 adapter, RAR[0] may be overwritten
556          * when the other port is reset, we make a duplicate
557          * in RAR[14] for that eventuality, this assures
558          * the interface continues to function.
559          */
560         if (hw->mac.type == e1000_82571) {
561                 e1000_set_laa_state_82571(hw, TRUE);
562                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
563         }
564
565         /* Initialize the hardware */
566         if (em_hardware_init(hw)) {
567                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
568                 return -EIO;
569         }
570
571         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
572
573         /* Configure for OS presence */
574         em_init_manageability(hw);
575
576         if (dev->data->dev_conf.intr_conf.rxq != 0) {
577                 intr_vector = dev->data->nb_rx_queues;
578                 if (rte_intr_efd_enable(intr_handle, intr_vector))
579                         return -1;
580         }
581
582         if (rte_intr_dp_is_en(intr_handle)) {
583                 intr_handle->intr_vec =
584                         rte_zmalloc("intr_vec",
585                                         dev->data->nb_rx_queues * sizeof(int), 0);
586                 if (intr_handle->intr_vec == NULL) {
587                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
588                                                 " intr_vec\n", dev->data->nb_rx_queues);
589                         return -ENOMEM;
590                 }
591
592                 /* enable rx interrupt */
593                 em_rxq_intr_enable(hw);
594         }
595
596         eth_em_tx_init(dev);
597
598         ret = eth_em_rx_init(dev);
599         if (ret) {
600                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
601                 em_dev_clear_queues(dev);
602                 return ret;
603         }
604
605         e1000_clear_hw_cntrs_base_generic(hw);
606
607         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
608                         ETH_VLAN_EXTEND_MASK;
609         eth_em_vlan_offload_set(dev, mask);
610
611         /* Set Interrupt Throttling Rate to maximum allowed value. */
612         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
613
614         /* Setup link speed and duplex */
615         switch (dev->data->dev_conf.link_speed) {
616         case ETH_LINK_SPEED_AUTONEG:
617                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
618                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
619                 else if (dev->data->dev_conf.link_duplex ==
620                                         ETH_LINK_HALF_DUPLEX)
621                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
622                 else if (dev->data->dev_conf.link_duplex ==
623                                         ETH_LINK_FULL_DUPLEX)
624                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
625                 else
626                         goto error_invalid_config;
627                 break;
628         case ETH_LINK_SPEED_10:
629                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
630                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
631                 else if (dev->data->dev_conf.link_duplex ==
632                                         ETH_LINK_HALF_DUPLEX)
633                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
634                 else if (dev->data->dev_conf.link_duplex ==
635                                         ETH_LINK_FULL_DUPLEX)
636                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
637                 else
638                         goto error_invalid_config;
639                 break;
640         case ETH_LINK_SPEED_100:
641                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
642                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
643                 else if (dev->data->dev_conf.link_duplex ==
644                                         ETH_LINK_HALF_DUPLEX)
645                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
646                 else if (dev->data->dev_conf.link_duplex ==
647                                         ETH_LINK_FULL_DUPLEX)
648                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
649                 else
650                         goto error_invalid_config;
651                 break;
652         case ETH_LINK_SPEED_1000:
653                 if ((dev->data->dev_conf.link_duplex ==
654                                 ETH_LINK_AUTONEG_DUPLEX) ||
655                         (dev->data->dev_conf.link_duplex ==
656                                         ETH_LINK_FULL_DUPLEX))
657                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
658                 else
659                         goto error_invalid_config;
660                 break;
661         case ETH_LINK_SPEED_10000:
662         default:
663                 goto error_invalid_config;
664         }
665         e1000_setup_link(hw);
666
667         if (rte_intr_allow_others(intr_handle)) {
668                 /* check if lsc interrupt is enabled */
669                 if (dev->data->dev_conf.intr_conf.lsc != 0)
670                         ret = eth_em_interrupt_setup(dev);
671                         if (ret) {
672                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
673                                 em_dev_clear_queues(dev);
674                                 return ret;
675                         }
676         } else {
677                 rte_intr_callback_unregister(intr_handle,
678                                                 eth_em_interrupt_handler,
679                                                 (void *)dev);
680                 if (dev->data->dev_conf.intr_conf.lsc != 0)
681                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
682                                      " no intr multiplex\n");
683         }
684         /* check if rxq interrupt is enabled */
685         if (dev->data->dev_conf.intr_conf.rxq != 0)
686                 eth_em_rxq_interrupt_setup(dev);
687
688         rte_intr_enable(intr_handle);
689
690         adapter->stopped = 0;
691
692         PMD_INIT_LOG(DEBUG, "<<");
693
694         return 0;
695
696 error_invalid_config:
697         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
698                      dev->data->dev_conf.link_speed,
699                      dev->data->dev_conf.link_duplex, dev->data->port_id);
700         em_dev_clear_queues(dev);
701         return -EINVAL;
702 }
703
704 /*********************************************************************
705  *
706  *  This routine disables all traffic on the adapter by issuing a
707  *  global reset on the MAC.
708  *
709  **********************************************************************/
710 static void
711 eth_em_stop(struct rte_eth_dev *dev)
712 {
713         struct rte_eth_link link;
714         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
715         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
716
717         em_rxq_intr_disable(hw);
718         em_lsc_intr_disable(hw);
719
720         e1000_reset_hw(hw);
721         if (hw->mac.type >= e1000_82544)
722                 E1000_WRITE_REG(hw, E1000_WUC, 0);
723
724         /* Power down the phy. Needed to make the link go down */
725         e1000_power_down_phy(hw);
726
727         em_dev_clear_queues(dev);
728
729         /* clear the recorded link status */
730         memset(&link, 0, sizeof(link));
731         rte_em_dev_atomic_write_link_status(dev, &link);
732
733         if (!rte_intr_allow_others(intr_handle))
734                 /* resume to the default handler */
735                 rte_intr_callback_register(intr_handle,
736                                            eth_em_interrupt_handler,
737                                            (void *)dev);
738
739         /* Clean datapath event and queue/vec mapping */
740         rte_intr_efd_disable(intr_handle);
741         if (intr_handle->intr_vec != NULL) {
742                 rte_free(intr_handle->intr_vec);
743                 intr_handle->intr_vec = NULL;
744         }
745 }
746
747 static void
748 eth_em_close(struct rte_eth_dev *dev)
749 {
750         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
751         struct e1000_adapter *adapter =
752                 E1000_DEV_PRIVATE(dev->data->dev_private);
753
754         eth_em_stop(dev);
755         adapter->stopped = 1;
756         em_dev_free_queues(dev);
757         e1000_phy_hw_reset(hw);
758         em_release_manageability(hw);
759         em_hw_control_release(hw);
760 }
761
762 static int
763 em_get_rx_buffer_size(struct e1000_hw *hw)
764 {
765         uint32_t rx_buf_size;
766
767         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
768         return rx_buf_size;
769 }
770
771 /*********************************************************************
772  *
773  *  Initialize the hardware
774  *
775  **********************************************************************/
776 static int
777 em_hardware_init(struct e1000_hw *hw)
778 {
779         uint32_t rx_buf_size;
780         int diag;
781
782         /* Issue a global reset */
783         e1000_reset_hw(hw);
784
785         /* Let the firmware know the OS is in control */
786         em_hw_control_acquire(hw);
787
788         /*
789          * These parameters control the automatic generation (Tx) and
790          * response (Rx) to Ethernet PAUSE frames.
791          * - High water mark should allow for at least two standard size (1518)
792          *   frames to be received after sending an XOFF.
793          * - Low water mark works best when it is very near the high water mark.
794          *   This allows the receiver to restart by sending XON when it has
795          *   drained a bit. Here we use an arbitrary value of 1500 which will
796          *   restart after one full frame is pulled from the buffer. There
797          *   could be several smaller frames in the buffer and if so they will
798          *   not trigger the XON until their total number reduces the buffer
799          *   by 1500.
800          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
801          */
802         rx_buf_size = em_get_rx_buffer_size(hw);
803
804         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
805         hw->fc.low_water = hw->fc.high_water - 1500;
806
807         if (hw->mac.type == e1000_80003es2lan)
808                 hw->fc.pause_time = UINT16_MAX;
809         else
810                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
811
812         hw->fc.send_xon = 1;
813
814         /* Set Flow control, use the tunable location if sane */
815         if (em_fc_setting <= e1000_fc_full)
816                 hw->fc.requested_mode = em_fc_setting;
817         else
818                 hw->fc.requested_mode = e1000_fc_none;
819
820         /* Workaround: no TX flow ctrl for PCH */
821         if (hw->mac.type == e1000_pchlan)
822                 hw->fc.requested_mode = e1000_fc_rx_pause;
823
824         /* Override - settings for PCH2LAN, ya its magic :) */
825         if (hw->mac.type == e1000_pch2lan) {
826                 hw->fc.high_water = 0x5C20;
827                 hw->fc.low_water = 0x5048;
828                 hw->fc.pause_time = 0x0650;
829                 hw->fc.refresh_time = 0x0400;
830         } else if (hw->mac.type == e1000_pch_lpt) {
831                 hw->fc.requested_mode = e1000_fc_full;
832         }
833
834         diag = e1000_init_hw(hw);
835         if (diag < 0)
836                 return diag;
837         e1000_check_for_link(hw);
838         return 0;
839 }
840
841 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
842 static void
843 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
844 {
845         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
846         struct e1000_hw_stats *stats =
847                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
848         int pause_frames;
849
850         if(hw->phy.media_type == e1000_media_type_copper ||
851                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
852                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
853                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
854         }
855
856         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
857         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
858         stats->scc += E1000_READ_REG(hw, E1000_SCC);
859         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
860
861         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
862         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
863         stats->colc += E1000_READ_REG(hw, E1000_COLC);
864         stats->dc += E1000_READ_REG(hw, E1000_DC);
865         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
866         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
867         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
868
869         /*
870          * For watchdog management we need to know if we have been
871          * paused during the last interval, so capture that here.
872          */
873         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
874         stats->xoffrxc += pause_frames;
875         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
876         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
877         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
878         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
879         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
880         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
881         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
882         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
883         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
884         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
885         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
886         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
887
888         /*
889          * For the 64-bit byte counters the low dword must be read first.
890          * Both registers clear on the read of the high dword.
891          */
892
893         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
894         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
895         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
896         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
897
898         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
899         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
900         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
901         stats->roc += E1000_READ_REG(hw, E1000_ROC);
902         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
903
904         stats->tor += E1000_READ_REG(hw, E1000_TORH);
905         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
906
907         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
908         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
909         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
910         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
911         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
912         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
913         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
914         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
915         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
916         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
917
918         /* Interrupt Counts */
919
920         if (hw->mac.type >= e1000_82571) {
921                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
922                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
923                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
924                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
925                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
926                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
927                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
928                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
929                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
930         }
931
932         if (hw->mac.type >= e1000_82543) {
933                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
934                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
935                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
936                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
937                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
938                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
939         }
940
941         if (rte_stats == NULL)
942                 return;
943
944         /* Rx Errors */
945         rte_stats->imissed = stats->mpc;
946         rte_stats->ierrors = stats->crcerrs +
947                              stats->rlec + stats->ruc + stats->roc +
948                              rte_stats->imissed +
949                              stats->rxerrc + stats->algnerrc + stats->cexterr;
950
951         /* Tx Errors */
952         rte_stats->oerrors = stats->ecol + stats->latecol;
953
954         rte_stats->ipackets = stats->gprc;
955         rte_stats->opackets = stats->gptc;
956         rte_stats->ibytes   = stats->gorc;
957         rte_stats->obytes   = stats->gotc;
958 }
959
960 static void
961 eth_em_stats_reset(struct rte_eth_dev *dev)
962 {
963         struct e1000_hw_stats *hw_stats =
964                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
965
966         /* HW registers are cleared on read */
967         eth_em_stats_get(dev, NULL);
968
969         /* Reset software totals */
970         memset(hw_stats, 0, sizeof(*hw_stats));
971 }
972
973 static int
974 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
975 {
976         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
977
978         em_rxq_intr_enable(hw);
979         rte_intr_enable(&dev->pci_dev->intr_handle);
980
981         return 0;
982 }
983
984 static int
985 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
986 {
987         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
988
989         em_rxq_intr_disable(hw);
990
991         return 0;
992 }
993
994 static uint32_t
995 em_get_max_pktlen(const struct e1000_hw *hw)
996 {
997         switch (hw->mac.type) {
998         case e1000_82571:
999         case e1000_82572:
1000         case e1000_ich9lan:
1001         case e1000_ich10lan:
1002         case e1000_pch2lan:
1003         case e1000_pch_lpt:
1004         case e1000_82574:
1005         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1006         case e1000_82583:
1007                 return 0x2412;
1008         case e1000_pchlan:
1009                 return 0x1000;
1010         /* Adapters that do not support jumbo frames */
1011         case e1000_ich8lan:
1012                 return ETHER_MAX_LEN;
1013         default:
1014                 return MAX_JUMBO_FRAME_SIZE;
1015         }
1016 }
1017
1018 static void
1019 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1020 {
1021         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1022
1023         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1024         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1025         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1026
1027         /*
1028          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1029          * Unfortunatelly, all these nics have just one TX context.
1030          * So we have few choises for TX:
1031          * - Use just one TX queue.
1032          * - Allow cksum offload only for one TX queue.
1033          * - Don't allow TX cksum offload at all.
1034          * For now, option #1 was chosen.
1035          * To use second RX queue we have to use extended RX descriptor
1036          * (Multiple Receive Queues are mutually exclusive with UDP
1037          * fragmentation and are not supported when a legacy receive
1038          * descriptor format is used).
1039          * Which means separate RX routinies - as legacy nics (82540, 82545)
1040          * don't support extended RXD.
1041          * To avoid it we support just one RX queue for now (no RSS).
1042          */
1043
1044         dev_info->max_rx_queues = 1;
1045         dev_info->max_tx_queues = 1;
1046
1047         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1048                 .nb_max = E1000_MAX_RING_DESC,
1049                 .nb_min = E1000_MIN_RING_DESC,
1050                 .nb_align = EM_RXD_ALIGN,
1051         };
1052
1053         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1054                 .nb_max = E1000_MAX_RING_DESC,
1055                 .nb_min = E1000_MIN_RING_DESC,
1056                 .nb_align = EM_TXD_ALIGN,
1057         };
1058 }
1059
1060 /* return 0 means link status changed, -1 means not changed */
1061 static int
1062 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1063 {
1064         struct e1000_hw *hw =
1065                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1066         struct rte_eth_link link, old;
1067         int link_check, count;
1068
1069         link_check = 0;
1070         hw->mac.get_link_status = 1;
1071
1072         /* possible wait-to-complete in up to 9 seconds */
1073         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1074                 /* Read the real link status */
1075                 switch (hw->phy.media_type) {
1076                 case e1000_media_type_copper:
1077                         /* Do the work to read phy */
1078                         e1000_check_for_link(hw);
1079                         link_check = !hw->mac.get_link_status;
1080                         break;
1081
1082                 case e1000_media_type_fiber:
1083                         e1000_check_for_link(hw);
1084                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1085                                         E1000_STATUS_LU);
1086                         break;
1087
1088                 case e1000_media_type_internal_serdes:
1089                         e1000_check_for_link(hw);
1090                         link_check = hw->mac.serdes_has_link;
1091                         break;
1092
1093                 default:
1094                         break;
1095                 }
1096                 if (link_check || wait_to_complete == 0)
1097                         break;
1098                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1099         }
1100         memset(&link, 0, sizeof(link));
1101         rte_em_dev_atomic_read_link_status(dev, &link);
1102         old = link;
1103
1104         /* Now we check if a transition has happened */
1105         if (link_check && (link.link_status == 0)) {
1106                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1107                         &link.link_duplex);
1108                 link.link_status = 1;
1109         } else if (!link_check && (link.link_status == 1)) {
1110                 link.link_speed = 0;
1111                 link.link_duplex = 0;
1112                 link.link_status = 0;
1113         }
1114         rte_em_dev_atomic_write_link_status(dev, &link);
1115
1116         /* not changed */
1117         if (old.link_status == link.link_status)
1118                 return -1;
1119
1120         /* changed */
1121         return 0;
1122 }
1123
1124 /*
1125  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1126  * For ASF and Pass Through versions of f/w this means
1127  * that the driver is loaded. For AMT version type f/w
1128  * this means that the network i/f is open.
1129  */
1130 static void
1131 em_hw_control_acquire(struct e1000_hw *hw)
1132 {
1133         uint32_t ctrl_ext, swsm;
1134
1135         /* Let firmware know the driver has taken over */
1136         if (hw->mac.type == e1000_82573) {
1137                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1138                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1139
1140         } else {
1141                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1142                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1143                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1144         }
1145 }
1146
1147 /*
1148  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1149  * For ASF and Pass Through versions of f/w this means that the
1150  * driver is no longer loaded. For AMT versions of the
1151  * f/w this means that the network i/f is closed.
1152  */
1153 static void
1154 em_hw_control_release(struct e1000_hw *hw)
1155 {
1156         uint32_t ctrl_ext, swsm;
1157
1158         /* Let firmware taken over control of h/w */
1159         if (hw->mac.type == e1000_82573) {
1160                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1161                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1162         } else {
1163                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1164                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1165                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1166         }
1167 }
1168
1169 /*
1170  * Bit of a misnomer, what this really means is
1171  * to enable OS management of the system... aka
1172  * to disable special hardware management features.
1173  */
1174 static void
1175 em_init_manageability(struct e1000_hw *hw)
1176 {
1177         if (e1000_enable_mng_pass_thru(hw)) {
1178                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1179                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1180
1181                 /* disable hardware interception of ARP */
1182                 manc &= ~(E1000_MANC_ARP_EN);
1183
1184                 /* enable receiving management packets to the host */
1185                 manc |= E1000_MANC_EN_MNG2HOST;
1186                 manc2h |= 1 << 5;  /* Mng Port 623 */
1187                 manc2h |= 1 << 6;  /* Mng Port 664 */
1188                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1189                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1190         }
1191 }
1192
1193 /*
1194  * Give control back to hardware management
1195  * controller if there is one.
1196  */
1197 static void
1198 em_release_manageability(struct e1000_hw *hw)
1199 {
1200         uint32_t manc;
1201
1202         if (e1000_enable_mng_pass_thru(hw)) {
1203                 manc = E1000_READ_REG(hw, E1000_MANC);
1204
1205                 /* re-enable hardware interception of ARP */
1206                 manc |= E1000_MANC_ARP_EN;
1207                 manc &= ~E1000_MANC_EN_MNG2HOST;
1208
1209                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1210         }
1211 }
1212
1213 static void
1214 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1215 {
1216         struct e1000_hw *hw =
1217                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1218         uint32_t rctl;
1219
1220         rctl = E1000_READ_REG(hw, E1000_RCTL);
1221         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1222         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1223 }
1224
1225 static void
1226 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1227 {
1228         struct e1000_hw *hw =
1229                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1230         uint32_t rctl;
1231
1232         rctl = E1000_READ_REG(hw, E1000_RCTL);
1233         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1234         if (dev->data->all_multicast == 1)
1235                 rctl |= E1000_RCTL_MPE;
1236         else
1237                 rctl &= (~E1000_RCTL_MPE);
1238         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1239 }
1240
1241 static void
1242 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1243 {
1244         struct e1000_hw *hw =
1245                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1246         uint32_t rctl;
1247
1248         rctl = E1000_READ_REG(hw, E1000_RCTL);
1249         rctl |= E1000_RCTL_MPE;
1250         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1251 }
1252
1253 static void
1254 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1255 {
1256         struct e1000_hw *hw =
1257                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1258         uint32_t rctl;
1259
1260         if (dev->data->promiscuous == 1)
1261                 return; /* must remain in all_multicast mode */
1262         rctl = E1000_READ_REG(hw, E1000_RCTL);
1263         rctl &= (~E1000_RCTL_MPE);
1264         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1265 }
1266
1267 static int
1268 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1269 {
1270         struct e1000_hw *hw =
1271                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1272         struct e1000_vfta * shadow_vfta =
1273                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1274         uint32_t vfta;
1275         uint32_t vid_idx;
1276         uint32_t vid_bit;
1277
1278         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1279                               E1000_VFTA_ENTRY_MASK);
1280         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1281         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1282         if (on)
1283                 vfta |= vid_bit;
1284         else
1285                 vfta &= ~vid_bit;
1286         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1287
1288         /* update local VFTA copy */
1289         shadow_vfta->vfta[vid_idx] = vfta;
1290
1291         return 0;
1292 }
1293
1294 static void
1295 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1296 {
1297         struct e1000_hw *hw =
1298                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1299         uint32_t reg;
1300
1301         /* Filter Table Disable */
1302         reg = E1000_READ_REG(hw, E1000_RCTL);
1303         reg &= ~E1000_RCTL_CFIEN;
1304         reg &= ~E1000_RCTL_VFE;
1305         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1306 }
1307
1308 static void
1309 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1310 {
1311         struct e1000_hw *hw =
1312                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1313         struct e1000_vfta * shadow_vfta =
1314                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1315         uint32_t reg;
1316         int i;
1317
1318         /* Filter Table Enable, CFI not used for packet acceptance */
1319         reg = E1000_READ_REG(hw, E1000_RCTL);
1320         reg &= ~E1000_RCTL_CFIEN;
1321         reg |= E1000_RCTL_VFE;
1322         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1323
1324         /* restore vfta from local copy */
1325         for (i = 0; i < IGB_VFTA_SIZE; i++)
1326                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1327 }
1328
1329 static void
1330 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1331 {
1332         struct e1000_hw *hw =
1333                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1334         uint32_t reg;
1335
1336         /* VLAN Mode Disable */
1337         reg = E1000_READ_REG(hw, E1000_CTRL);
1338         reg &= ~E1000_CTRL_VME;
1339         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1340
1341 }
1342
1343 static void
1344 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1345 {
1346         struct e1000_hw *hw =
1347                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348         uint32_t reg;
1349
1350         /* VLAN Mode Enable */
1351         reg = E1000_READ_REG(hw, E1000_CTRL);
1352         reg |= E1000_CTRL_VME;
1353         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1354 }
1355
1356 static void
1357 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1358 {
1359         if(mask & ETH_VLAN_STRIP_MASK){
1360                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1361                         em_vlan_hw_strip_enable(dev);
1362                 else
1363                         em_vlan_hw_strip_disable(dev);
1364         }
1365
1366         if(mask & ETH_VLAN_FILTER_MASK){
1367                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1368                         em_vlan_hw_filter_enable(dev);
1369                 else
1370                         em_vlan_hw_filter_disable(dev);
1371         }
1372 }
1373
1374 /*
1375  * It enables the interrupt mask and then enable the interrupt.
1376  *
1377  * @param dev
1378  *  Pointer to struct rte_eth_dev.
1379  *
1380  * @return
1381  *  - On success, zero.
1382  *  - On failure, a negative value.
1383  */
1384 static int
1385 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1386 {
1387         uint32_t regval;
1388         struct e1000_hw *hw =
1389                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1390
1391         /* clear interrupt */
1392         E1000_READ_REG(hw, E1000_ICR);
1393         regval = E1000_READ_REG(hw, E1000_IMS);
1394         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1395         return 0;
1396 }
1397
1398 /*
1399  * It clears the interrupt causes and enables the interrupt.
1400  * It will be called once only during nic initialized.
1401  *
1402  * @param dev
1403  *  Pointer to struct rte_eth_dev.
1404  *
1405  * @return
1406  *  - On success, zero.
1407  *  - On failure, a negative value.
1408  */
1409 static int
1410 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1411 {
1412         struct e1000_hw *hw =
1413         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1414
1415         E1000_READ_REG(hw, E1000_ICR);
1416         em_rxq_intr_enable(hw);
1417         return 0;
1418 }
1419
1420 /*
1421  * It enable receive packet interrupt.
1422  * @param hw
1423  * Pointer to struct e1000_hw
1424  *
1425  * @return
1426  */
1427 static void
1428 em_rxq_intr_enable(struct e1000_hw *hw)
1429 {
1430         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1431         E1000_WRITE_FLUSH(hw);
1432 }
1433
1434 /*
1435  * It disabled lsc interrupt.
1436  * @param hw
1437  * Pointer to struct e1000_hw
1438  *
1439  * @return
1440  */
1441 static void
1442 em_lsc_intr_disable(struct e1000_hw *hw)
1443 {
1444         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1445         E1000_WRITE_FLUSH(hw);
1446 }
1447
1448 /*
1449  * It disabled receive packet interrupt.
1450  * @param hw
1451  * Pointer to struct e1000_hw
1452  *
1453  * @return
1454  */
1455 static void
1456 em_rxq_intr_disable(struct e1000_hw *hw)
1457 {
1458         E1000_READ_REG(hw, E1000_ICR);
1459         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1460         E1000_WRITE_FLUSH(hw);
1461 }
1462
1463 /*
1464  * It reads ICR and gets interrupt causes, check it and set a bit flag
1465  * to update link status.
1466  *
1467  * @param dev
1468  *  Pointer to struct rte_eth_dev.
1469  *
1470  * @return
1471  *  - On success, zero.
1472  *  - On failure, a negative value.
1473  */
1474 static int
1475 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1476 {
1477         uint32_t icr;
1478         struct e1000_hw *hw =
1479                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1480         struct e1000_interrupt *intr =
1481                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1482
1483         /* read-on-clear nic registers here */
1484         icr = E1000_READ_REG(hw, E1000_ICR);
1485         if (icr & E1000_ICR_LSC) {
1486                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1487         }
1488
1489         return 0;
1490 }
1491
1492 /*
1493  * It executes link_update after knowing an interrupt is prsent.
1494  *
1495  * @param dev
1496  *  Pointer to struct rte_eth_dev.
1497  *
1498  * @return
1499  *  - On success, zero.
1500  *  - On failure, a negative value.
1501  */
1502 static int
1503 eth_em_interrupt_action(struct rte_eth_dev *dev)
1504 {
1505         struct e1000_hw *hw =
1506                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1507         struct e1000_interrupt *intr =
1508                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1509         uint32_t tctl, rctl;
1510         struct rte_eth_link link;
1511         int ret;
1512
1513         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1514                 return -1;
1515
1516         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1517         rte_intr_enable(&(dev->pci_dev->intr_handle));
1518
1519         /* set get_link_status to check register later */
1520         hw->mac.get_link_status = 1;
1521         ret = eth_em_link_update(dev, 0);
1522
1523         /* check if link has changed */
1524         if (ret < 0)
1525                 return 0;
1526
1527         memset(&link, 0, sizeof(link));
1528         rte_em_dev_atomic_read_link_status(dev, &link);
1529         if (link.link_status) {
1530                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1531                              dev->data->port_id, (unsigned)link.link_speed,
1532                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1533                              "full-duplex" : "half-duplex");
1534         } else {
1535                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1536         }
1537         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1538                      dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1539                      dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1540
1541         tctl = E1000_READ_REG(hw, E1000_TCTL);
1542         rctl = E1000_READ_REG(hw, E1000_RCTL);
1543         if (link.link_status) {
1544                 /* enable Tx/Rx */
1545                 tctl |= E1000_TCTL_EN;
1546                 rctl |= E1000_RCTL_EN;
1547         } else {
1548                 /* disable Tx/Rx */
1549                 tctl &= ~E1000_TCTL_EN;
1550                 rctl &= ~E1000_RCTL_EN;
1551         }
1552         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1553         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1554         E1000_WRITE_FLUSH(hw);
1555
1556         return 0;
1557 }
1558
1559 /**
1560  * Interrupt handler which shall be registered at first.
1561  *
1562  * @param handle
1563  *  Pointer to interrupt handle.
1564  * @param param
1565  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1566  *
1567  * @return
1568  *  void
1569  */
1570 static void
1571 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1572                                                         void *param)
1573 {
1574         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1575
1576         eth_em_interrupt_get_status(dev);
1577         eth_em_interrupt_action(dev);
1578         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1579 }
1580
1581 static int
1582 eth_em_led_on(struct rte_eth_dev *dev)
1583 {
1584         struct e1000_hw *hw;
1585
1586         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1587         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1588 }
1589
1590 static int
1591 eth_em_led_off(struct rte_eth_dev *dev)
1592 {
1593         struct e1000_hw *hw;
1594
1595         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1596         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1597 }
1598
1599 static int
1600 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1601 {
1602         struct e1000_hw *hw;
1603         uint32_t ctrl;
1604         int tx_pause;
1605         int rx_pause;
1606
1607         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1608         fc_conf->pause_time = hw->fc.pause_time;
1609         fc_conf->high_water = hw->fc.high_water;
1610         fc_conf->low_water = hw->fc.low_water;
1611         fc_conf->send_xon = hw->fc.send_xon;
1612         fc_conf->autoneg = hw->mac.autoneg;
1613
1614         /*
1615          * Return rx_pause and tx_pause status according to actual setting of
1616          * the TFCE and RFCE bits in the CTRL register.
1617          */
1618         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1619         if (ctrl & E1000_CTRL_TFCE)
1620                 tx_pause = 1;
1621         else
1622                 tx_pause = 0;
1623
1624         if (ctrl & E1000_CTRL_RFCE)
1625                 rx_pause = 1;
1626         else
1627                 rx_pause = 0;
1628
1629         if (rx_pause && tx_pause)
1630                 fc_conf->mode = RTE_FC_FULL;
1631         else if (rx_pause)
1632                 fc_conf->mode = RTE_FC_RX_PAUSE;
1633         else if (tx_pause)
1634                 fc_conf->mode = RTE_FC_TX_PAUSE;
1635         else
1636                 fc_conf->mode = RTE_FC_NONE;
1637
1638         return 0;
1639 }
1640
1641 static int
1642 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1643 {
1644         struct e1000_hw *hw;
1645         int err;
1646         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1647                 e1000_fc_none,
1648                 e1000_fc_rx_pause,
1649                 e1000_fc_tx_pause,
1650                 e1000_fc_full
1651         };
1652         uint32_t rx_buf_size;
1653         uint32_t max_high_water;
1654         uint32_t rctl;
1655
1656         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1657         if (fc_conf->autoneg != hw->mac.autoneg)
1658                 return -ENOTSUP;
1659         rx_buf_size = em_get_rx_buffer_size(hw);
1660         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1661
1662         /* At least reserve one Ethernet frame for watermark */
1663         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1664         if ((fc_conf->high_water > max_high_water) ||
1665             (fc_conf->high_water < fc_conf->low_water)) {
1666                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1667                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1668                 return -EINVAL;
1669         }
1670
1671         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1672         hw->fc.pause_time     = fc_conf->pause_time;
1673         hw->fc.high_water     = fc_conf->high_water;
1674         hw->fc.low_water      = fc_conf->low_water;
1675         hw->fc.send_xon       = fc_conf->send_xon;
1676
1677         err = e1000_setup_link_generic(hw);
1678         if (err == E1000_SUCCESS) {
1679
1680                 /* check if we want to forward MAC frames - driver doesn't have native
1681                  * capability to do that, so we'll write the registers ourselves */
1682
1683                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1684
1685                 /* set or clear MFLCN.PMCF bit depending on configuration */
1686                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1687                         rctl |= E1000_RCTL_PMCF;
1688                 else
1689                         rctl &= ~E1000_RCTL_PMCF;
1690
1691                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1692                 E1000_WRITE_FLUSH(hw);
1693
1694                 return 0;
1695         }
1696
1697         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1698         return -EIO;
1699 }
1700
1701 static void
1702 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1703                 uint32_t index, __rte_unused uint32_t pool)
1704 {
1705         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1706
1707         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1708 }
1709
1710 static void
1711 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1712 {
1713         uint8_t addr[ETHER_ADDR_LEN];
1714         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1715
1716         memset(addr, 0, sizeof(addr));
1717
1718         e1000_rar_set(hw, addr, index);
1719 }
1720
1721 static int
1722 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1723 {
1724         struct rte_eth_dev_info dev_info;
1725         struct e1000_hw *hw;
1726         uint32_t frame_size;
1727         uint32_t rctl;
1728
1729         eth_em_infos_get(dev, &dev_info);
1730         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1731
1732         /* check that mtu is within the allowed range */
1733         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1734                 return -EINVAL;
1735
1736         /* refuse mtu that requires the support of scattered packets when this
1737          * feature has not been enabled before. */
1738         if (!dev->data->scattered_rx &&
1739             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1740                 return -EINVAL;
1741
1742         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1743         rctl = E1000_READ_REG(hw, E1000_RCTL);
1744
1745         /* switch to jumbo mode if needed */
1746         if (frame_size > ETHER_MAX_LEN) {
1747                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1748                 rctl |= E1000_RCTL_LPE;
1749         } else {
1750                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1751                 rctl &= ~E1000_RCTL_LPE;
1752         }
1753         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1754
1755         /* update max frame size */
1756         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1757         return 0;
1758 }
1759
1760 static int
1761 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1762                         struct ether_addr *mc_addr_set,
1763                         uint32_t nb_mc_addr)
1764 {
1765         struct e1000_hw *hw;
1766
1767         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1768         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1769         return 0;
1770 }
1771
1772 struct rte_driver em_pmd_drv = {
1773         .type = PMD_PDEV,
1774         .init = rte_em_pmd_init,
1775 };
1776
1777 PMD_REGISTER_DRIVER(em_pmd_drv);