drivers/net/e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 #define EM_EIAC                 0x000DC
  60
  61 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  62
  63
  64 static int eth_em_configure(struct rte_eth_dev *dev);
  65 static int eth_em_start(struct rte_eth_dev *dev);
  66 static void eth_em_stop(struct rte_eth_dev *dev);
  67 static void eth_em_close(struct rte_eth_dev *dev);
  68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  72 static int eth_em_link_update(struct rte_eth_dev *dev,
  73                                 int wait_to_complete);
  74 static void eth_em_stats_get(struct rte_eth_dev *dev,
  75                                 struct rte_eth_stats *rte_stats);
  76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  77 static void eth_em_infos_get(struct rte_eth_dev *dev,
  78                                 struct rte_eth_dev_info *dev_info);
  79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  80                                 struct rte_eth_fc_conf *fc_conf);
  81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  82                                 struct rte_eth_fc_conf *fc_conf);
  83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  84 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  86 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
  87                                    struct rte_intr_handle *handle);
  88 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
  89                                                         void *param);
  90
  91 static int em_hw_init(struct e1000_hw *hw);
  92 static int em_hardware_init(struct e1000_hw *hw);
  93 static void em_hw_control_acquire(struct e1000_hw *hw);
  94 static void em_hw_control_release(struct e1000_hw *hw);
  95 static void em_init_manageability(struct e1000_hw *hw);
  96 static void em_release_manageability(struct e1000_hw *hw);
  97
  98 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  99
 100 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 101                 uint16_t vlan_id, int on);
 102 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 103 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 104 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 105 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 106 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 107
 108 /*
 109 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 110                                         uint16_t vlan_id, int on);
 111 */
 112
 113 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 114 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 115 static void em_lsc_intr_disable(struct e1000_hw *hw);
 116 static void em_rxq_intr_enable(struct e1000_hw *hw);
 117 static void em_rxq_intr_disable(struct e1000_hw *hw);
 118
 119 static int eth_em_led_on(struct rte_eth_dev *dev);
 120 static int eth_em_led_off(struct rte_eth_dev *dev);
 121
 122 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 123 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 124                 uint32_t index, uint32_t pool);
 125 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 126
 127 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
 128                                    struct ether_addr *mc_addr_set,
 129                                    uint32_t nb_mc_addr);
 130
 131 #define EM_FC_PAUSE_TIME 0x0680
 132 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 133 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 134
 135 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 136
 137 /*
 138  * The set of PCI devices this driver supports
 139  */
 140 static const struct rte_pci_id pci_id_em_map[] = {
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 158         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 159         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 160         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 161         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 162         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 163         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 164         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 165         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 166         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 167         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 168         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 169         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 170         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 171         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 172         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
 173         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
 174         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
 175         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
 176         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
 177         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
 178         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
 179         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
 180         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
 181         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
 182         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
 183         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
 184         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
 185         { .vendor_id = 0, /* sentinel */ },
 186 };
 187
 188 static const struct eth_dev_ops eth_em_ops = {
 189         .dev_configure        = eth_em_configure,
 190         .dev_start            = eth_em_start,
 191         .dev_stop             = eth_em_stop,
 192         .dev_close            = eth_em_close,
 193         .promiscuous_enable   = eth_em_promiscuous_enable,
 194         .promiscuous_disable  = eth_em_promiscuous_disable,
 195         .allmulticast_enable  = eth_em_allmulticast_enable,
 196         .allmulticast_disable = eth_em_allmulticast_disable,
 197         .link_update          = eth_em_link_update,
 198         .stats_get            = eth_em_stats_get,
 199         .stats_reset          = eth_em_stats_reset,
 200         .dev_infos_get        = eth_em_infos_get,
 201         .mtu_set              = eth_em_mtu_set,
 202         .vlan_filter_set      = eth_em_vlan_filter_set,
 203         .vlan_offload_set     = eth_em_vlan_offload_set,
 204         .rx_queue_setup       = eth_em_rx_queue_setup,
 205         .rx_queue_release     = eth_em_rx_queue_release,
 206         .rx_queue_count       = eth_em_rx_queue_count,
 207         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 208         .tx_queue_setup       = eth_em_tx_queue_setup,
 209         .tx_queue_release     = eth_em_tx_queue_release,
 210         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 211         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 212         .dev_led_on           = eth_em_led_on,
 213         .dev_led_off          = eth_em_led_off,
 214         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 215         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 216         .mac_addr_add         = eth_em_rar_set,
 217         .mac_addr_remove      = eth_em_rar_clear,
 218         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 219         .rxq_info_get         = em_rxq_info_get,
 220         .txq_info_get         = em_txq_info_get,
 221 };
 222
 223 /**
 224  * Atomically reads the link status information from global
 225  * structure rte_eth_dev.
 226  *
 227  * @param dev
 228  *   - Pointer to the structure rte_eth_dev to read from.
 229  *   - Pointer to the buffer to be saved with the link status.
 230  *
 231  * @return
 232  *   - On success, zero.
 233  *   - On failure, negative value.
 234  */
 235 static inline int
 236 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 237                                 struct rte_eth_link *link)
 238 {
 239         struct rte_eth_link *dst = link;
 240         struct rte_eth_link *src = &(dev->data->dev_link);
 241
 242         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 243                                         *(uint64_t *)src) == 0)
 244                 return -1;
 245
 246         return 0;
 247 }
 248
 249 /**
 250  * Atomically writes the link status information into global
 251  * structure rte_eth_dev.
 252  *
 253  * @param dev
 254  *   - Pointer to the structure rte_eth_dev to read from.
 255  *   - Pointer to the buffer to be saved with the link status.
 256  *
 257  * @return
 258  *   - On success, zero.
 259  *   - On failure, negative value.
 260  */
 261 static inline int
 262 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 263                                 struct rte_eth_link *link)
 264 {
 265         struct rte_eth_link *dst = &(dev->data->dev_link);
 266         struct rte_eth_link *src = link;
 267
 268         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 269                                         *(uint64_t *)src) == 0)
 270                 return -1;
 271
 272         return 0;
 273 }
 274
 275 /**
 276  *  eth_em_dev_is_ich8 - Check for ICH8 device
 277  *  @hw: pointer to the HW structure
 278  *
 279  *  return TRUE for ICH8, otherwise FALSE
 280  **/
 281 static bool
 282 eth_em_dev_is_ich8(struct e1000_hw *hw)
 283 {
 284         DEBUGFUNC("eth_em_dev_is_ich8");
 285
 286         switch (hw->device_id) {
 287         case E1000_DEV_ID_PCH_LPT_I217_LM:
 288         case E1000_DEV_ID_PCH_LPT_I217_V:
 289         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 290         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 291         case E1000_DEV_ID_PCH_I218_V2:
 292         case E1000_DEV_ID_PCH_I218_LM2:
 293         case E1000_DEV_ID_PCH_I218_V3:
 294         case E1000_DEV_ID_PCH_I218_LM3:
 295         case E1000_DEV_ID_PCH_SPT_I219_LM:
 296         case E1000_DEV_ID_PCH_SPT_I219_V:
 297         case E1000_DEV_ID_PCH_SPT_I219_LM2:
 298         case E1000_DEV_ID_PCH_SPT_I219_V2:
 299         case E1000_DEV_ID_PCH_LBG_I219_LM3:
 300         case E1000_DEV_ID_PCH_SPT_I219_LM4:
 301         case E1000_DEV_ID_PCH_SPT_I219_V4:
 302         case E1000_DEV_ID_PCH_SPT_I219_LM5:
 303         case E1000_DEV_ID_PCH_SPT_I219_V5:
 304         case E1000_DEV_ID_PCH_CNP_I219_LM6:
 305         case E1000_DEV_ID_PCH_CNP_I219_V6:
 306         case E1000_DEV_ID_PCH_CNP_I219_LM7:
 307         case E1000_DEV_ID_PCH_CNP_I219_V7:
 308                 return 1;
 309         default:
 310                 return 0;
 311         }
 312 }
 313
 314 static int
 315 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 316 {
 317         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
 318         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 319         struct e1000_adapter *adapter =
 320                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 321         struct e1000_hw *hw =
 322                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 323         struct e1000_vfta * shadow_vfta =
 324                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 325
 326         eth_dev->dev_ops = &eth_em_ops;
 327         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 328         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 329         eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
 330
 331         /* for secondary processes, we don't initialise any further as primary
 332          * has already done this work. Only check we don't need a different
 333          * RX function */
 334         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 335                 if (eth_dev->data->scattered_rx)
 336                         eth_dev->rx_pkt_burst =
 337                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 338                 return 0;
 339         }
 340
 341         rte_eth_copy_pci_info(eth_dev, pci_dev);
 342         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
 343
 344         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 345         hw->device_id = pci_dev->id.device_id;
 346         adapter->stopped = 0;
 347
 348         /* For ICH8 support we'll need to map the flash memory BAR */
 349         if (eth_em_dev_is_ich8(hw))
 350                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 351
 352         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 353                         em_hw_init(hw) != 0) {
 354                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 355                         "failed to init HW",
 356                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 357                         pci_dev->id.device_id);
 358                 return -ENODEV;
 359         }
 360
 361         /* Allocate memory for storing MAC addresses */
 362         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 363                         hw->mac.rar_entry_count, 0);
 364         if (eth_dev->data->mac_addrs == NULL) {
 365                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 366                         "store MAC addresses",
 367                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 368                 return -ENOMEM;
 369         }
 370
 371         /* Copy the permanent MAC address */
 372         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 373                 eth_dev->data->mac_addrs);
 374
 375         /* initialize the vfta */
 376         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 377
 378         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 379                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 380                      pci_dev->id.device_id);
 381
 382         rte_intr_callback_register(intr_handle,
 383                                    eth_em_interrupt_handler, eth_dev);
 384
 385         return 0;
 386 }
 387
 388 static int
 389 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 390 {
 391         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
 392         struct e1000_adapter *adapter =
 393                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 394         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 395
 396         PMD_INIT_FUNC_TRACE();
 397
 398         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 399                 return -EPERM;
 400
 401         if (adapter->stopped == 0)
 402                 eth_em_close(eth_dev);
 403
 404         eth_dev->dev_ops = NULL;
 405         eth_dev->rx_pkt_burst = NULL;
 406         eth_dev->tx_pkt_burst = NULL;
 407
 408         rte_free(eth_dev->data->mac_addrs);
 409         eth_dev->data->mac_addrs = NULL;
 410
 411         /* disable uio intr before callback unregister */
 412         rte_intr_disable(intr_handle);
 413         rte_intr_callback_unregister(intr_handle,
 414                                      eth_em_interrupt_handler, eth_dev);
 415
 416         return 0;
 417 }
 418
 419 static struct eth_driver rte_em_pmd = {
 420         .pci_drv = {
 421                 .id_table = pci_id_em_map,
 422                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 423                 .probe = rte_eth_dev_pci_probe,
 424                 .remove = rte_eth_dev_pci_remove,
 425         },
 426         .eth_dev_init = eth_em_dev_init,
 427         .eth_dev_uninit = eth_em_dev_uninit,
 428         .dev_private_size = sizeof(struct e1000_adapter),
 429 };
 430
 431 static int
 432 em_hw_init(struct e1000_hw *hw)
 433 {
 434         int diag;
 435
 436         diag = hw->mac.ops.init_params(hw);
 437         if (diag != 0) {
 438                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 439                 return diag;
 440         }
 441         diag = hw->nvm.ops.init_params(hw);
 442         if (diag != 0) {
 443                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 444                 return diag;
 445         }
 446         diag = hw->phy.ops.init_params(hw);
 447         if (diag != 0) {
 448                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 449                 return diag;
 450         }
 451         (void) e1000_get_bus_info(hw);
 452
 453         hw->mac.autoneg = 1;
 454         hw->phy.autoneg_wait_to_complete = 0;
 455         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 456
 457         e1000_init_script_state_82541(hw, TRUE);
 458         e1000_set_tbi_compatibility_82543(hw, TRUE);
 459
 460         /* Copper options */
 461         if (hw->phy.media_type == e1000_media_type_copper) {
 462                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 463                 hw->phy.disable_polarity_correction = 0;
 464                 hw->phy.ms_type = e1000_ms_hw_default;
 465         }
 466
 467         /*
 468          * Start from a known state, this is important in reading the nvm
 469          * and mac from that.
 470          */
 471         e1000_reset_hw(hw);
 472
 473         /* Make sure we have a good EEPROM before we read from it */
 474         if (e1000_validate_nvm_checksum(hw) < 0) {
 475                 /*
 476                  * Some PCI-E parts fail the first check due to
 477                  * the link being in sleep state, call it again,
 478                  * if it fails a second time its a real issue.
 479                  */
 480                 diag = e1000_validate_nvm_checksum(hw);
 481                 if (diag < 0) {
 482                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 483                         goto error;
 484                 }
 485         }
 486
 487         /* Read the permanent MAC address out of the EEPROM */
 488         diag = e1000_read_mac_addr(hw);
 489         if (diag != 0) {
 490                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 491                 goto error;
 492         }
 493
 494         /* Now initialize the hardware */
 495         diag = em_hardware_init(hw);
 496         if (diag != 0) {
 497                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 498                 goto error;
 499         }
 500
 501         hw->mac.get_link_status = 1;
 502
 503         /* Indicate SOL/IDER usage */
 504         diag = e1000_check_reset_block(hw);
 505         if (diag < 0) {
 506                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 507                         "SOL/IDER session");
 508         }
 509         return 0;
 510
 511 error:
 512         em_hw_control_release(hw);
 513         return diag;
 514 }
 515
 516 static int
 517 eth_em_configure(struct rte_eth_dev *dev)
 518 {
 519         struct e1000_interrupt *intr =
 520                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 521
 522         PMD_INIT_FUNC_TRACE();
 523         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 524         PMD_INIT_FUNC_TRACE();
 525
 526         return 0;
 527 }
 528
 529 static void
 530 em_set_pba(struct e1000_hw *hw)
 531 {
 532         uint32_t pba;
 533
 534         /*
 535          * Packet Buffer Allocation (PBA)
 536          * Writing PBA sets the receive portion of the buffer
 537          * the remainder is used for the transmit buffer.
 538          * Devices before the 82547 had a Packet Buffer of 64K.
 539          * After the 82547 the buffer was reduced to 40K.
 540          */
 541         switch (hw->mac.type) {
 542                 case e1000_82547:
 543                 case e1000_82547_rev_2:
 544                 /* 82547: Total Packet Buffer is 40K */
 545                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 546                         break;
 547                 case e1000_82571:
 548                 case e1000_82572:
 549                 case e1000_80003es2lan:
 550                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 551                         break;
 552                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 553                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 554                         break;
 555                 case e1000_82574:
 556                 case e1000_82583:
 557                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 558                         break;
 559                 case e1000_ich8lan:
 560                         pba = E1000_PBA_8K;
 561                         break;
 562                 case e1000_ich9lan:
 563                 case e1000_ich10lan:
 564                         pba = E1000_PBA_10K;
 565                         break;
 566                 case e1000_pchlan:
 567                 case e1000_pch2lan:
 568                 case e1000_pch_lpt:
 569                 case e1000_pch_spt:
 570                 case e1000_pch_cnp:
 571                         pba = E1000_PBA_26K;
 572                         break;
 573                 default:
 574                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 575         }
 576
 577         E1000_WRITE_REG(hw, E1000_PBA, pba);
 578 }
 579
 580 static int
 581 eth_em_start(struct rte_eth_dev *dev)
 582 {
 583         struct e1000_adapter *adapter =
 584                 E1000_DEV_PRIVATE(dev->data->dev_private);
 585         struct e1000_hw *hw =
 586                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 587         struct rte_pci_device *pci_dev =
 588                 E1000_DEV_TO_PCI(dev);
 589         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 590         int ret, mask;
 591         uint32_t intr_vector = 0;
 592         uint32_t *speeds;
 593         int num_speeds;
 594         bool autoneg;
 595
 596         PMD_INIT_FUNC_TRACE();
 597
 598         eth_em_stop(dev);
 599
 600         e1000_power_up_phy(hw);
 601
 602         /* Set default PBA value */
 603         em_set_pba(hw);
 604
 605         /* Put the address into the Receive Address Array */
 606         e1000_rar_set(hw, hw->mac.addr, 0);
 607
 608         /*
 609          * With the 82571 adapter, RAR[0] may be overwritten
 610          * when the other port is reset, we make a duplicate
 611          * in RAR[14] for that eventuality, this assures
 612          * the interface continues to function.
 613          */
 614         if (hw->mac.type == e1000_82571) {
 615                 e1000_set_laa_state_82571(hw, TRUE);
 616                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 617         }
 618
 619         /* Initialize the hardware */
 620         if (em_hardware_init(hw)) {
 621                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 622                 return -EIO;
 623         }
 624
 625         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 626
 627         /* Configure for OS presence */
 628         em_init_manageability(hw);
 629
 630         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 631                 intr_vector = dev->data->nb_rx_queues;
 632                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 633                         return -1;
 634         }
 635
 636         if (rte_intr_dp_is_en(intr_handle)) {
 637                 intr_handle->intr_vec =
 638                         rte_zmalloc("intr_vec",
 639                                         dev->data->nb_rx_queues * sizeof(int), 0);
 640                 if (intr_handle->intr_vec == NULL) {
 641                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 642                                                 " intr_vec", dev->data->nb_rx_queues);
 643                         return -ENOMEM;
 644                 }
 645
 646                 /* enable rx interrupt */
 647                 em_rxq_intr_enable(hw);
 648         }
 649
 650         eth_em_tx_init(dev);
 651
 652         ret = eth_em_rx_init(dev);
 653         if (ret) {
 654                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 655                 em_dev_clear_queues(dev);
 656                 return ret;
 657         }
 658
 659         e1000_clear_hw_cntrs_base_generic(hw);
 660
 661         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 662                         ETH_VLAN_EXTEND_MASK;
 663         eth_em_vlan_offload_set(dev, mask);
 664
 665         /* Set Interrupt Throttling Rate to maximum allowed value. */
 666         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 667
 668         /* Setup link speed and duplex */
 669         speeds = &dev->data->dev_conf.link_speeds;
 670         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 671                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 672                 hw->mac.autoneg = 1;
 673         } else {
 674                 num_speeds = 0;
 675                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 676
 677                 /* Reset */
 678                 hw->phy.autoneg_advertised = 0;
 679
 680                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 681                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 682                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 683                         num_speeds = -1;
 684                         goto error_invalid_config;
 685                 }
 686                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 687                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 688                         num_speeds++;
 689                 }
 690                 if (*speeds & ETH_LINK_SPEED_10M) {
 691                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 692                         num_speeds++;
 693                 }
 694                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 695                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 696                         num_speeds++;
 697                 }
 698                 if (*speeds & ETH_LINK_SPEED_100M) {
 699                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 700                         num_speeds++;
 701                 }
 702                 if (*speeds & ETH_LINK_SPEED_1G) {
 703                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 704                         num_speeds++;
 705                 }
 706                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 707                         goto error_invalid_config;
 708
 709                 /* Set/reset the mac.autoneg based on the link speed,
 710                  * fixed or not
 711                  */
 712                 if (!autoneg) {
 713                         hw->mac.autoneg = 0;
 714                         hw->mac.forced_speed_duplex =
 715                                         hw->phy.autoneg_advertised;
 716                 } else {
 717                         hw->mac.autoneg = 1;
 718                 }
 719         }
 720
 721         e1000_setup_link(hw);
 722
 723         if (rte_intr_allow_others(intr_handle)) {
 724                 /* check if lsc interrupt is enabled */
 725                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 726                         ret = eth_em_interrupt_setup(dev);
 727                         if (ret) {
 728                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 729                                 em_dev_clear_queues(dev);
 730                                 return ret;
 731                         }
 732                 }
 733         } else {
 734                 rte_intr_callback_unregister(intr_handle,
 735                                                 eth_em_interrupt_handler,
 736                                                 (void *)dev);
 737                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 738                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 739                                      " no intr multiplexn");
 740         }
 741         /* check if rxq interrupt is enabled */
 742         if (dev->data->dev_conf.intr_conf.rxq != 0)
 743                 eth_em_rxq_interrupt_setup(dev);
 744
 745         rte_intr_enable(intr_handle);
 746
 747         adapter->stopped = 0;
 748
 749         PMD_INIT_LOG(DEBUG, "<<");
 750
 751         return 0;
 752
 753 error_invalid_config:
 754         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 755                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 756         em_dev_clear_queues(dev);
 757         return -EINVAL;
 758 }
 759
 760 /*********************************************************************
 761  *
 762  *  This routine disables all traffic on the adapter by issuing a
 763  *  global reset on the MAC.
 764  *
 765  **********************************************************************/
 766 static void
 767 eth_em_stop(struct rte_eth_dev *dev)
 768 {
 769         struct rte_eth_link link;
 770         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 771         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
 772         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 773
 774         em_rxq_intr_disable(hw);
 775         em_lsc_intr_disable(hw);
 776
 777         e1000_reset_hw(hw);
 778         if (hw->mac.type >= e1000_82544)
 779                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 780
 781         /* Power down the phy. Needed to make the link go down */
 782         e1000_power_down_phy(hw);
 783
 784         em_dev_clear_queues(dev);
 785
 786         /* clear the recorded link status */
 787         memset(&link, 0, sizeof(link));
 788         rte_em_dev_atomic_write_link_status(dev, &link);
 789
 790         if (!rte_intr_allow_others(intr_handle))
 791                 /* resume to the default handler */
 792                 rte_intr_callback_register(intr_handle,
 793                                            eth_em_interrupt_handler,
 794                                            (void *)dev);
 795
 796         /* Clean datapath event and queue/vec mapping */
 797         rte_intr_efd_disable(intr_handle);
 798         if (intr_handle->intr_vec != NULL) {
 799                 rte_free(intr_handle->intr_vec);
 800                 intr_handle->intr_vec = NULL;
 801         }
 802 }
 803
 804 static void
 805 eth_em_close(struct rte_eth_dev *dev)
 806 {
 807         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 808         struct e1000_adapter *adapter =
 809                 E1000_DEV_PRIVATE(dev->data->dev_private);
 810
 811         eth_em_stop(dev);
 812         adapter->stopped = 1;
 813         em_dev_free_queues(dev);
 814         e1000_phy_hw_reset(hw);
 815         em_release_manageability(hw);
 816         em_hw_control_release(hw);
 817 }
 818
 819 static int
 820 em_get_rx_buffer_size(struct e1000_hw *hw)
 821 {
 822         uint32_t rx_buf_size;
 823
 824         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 825         return rx_buf_size;
 826 }
 827
 828 /*********************************************************************
 829  *
 830  *  Initialize the hardware
 831  *
 832  **********************************************************************/
 833 static int
 834 em_hardware_init(struct e1000_hw *hw)
 835 {
 836         uint32_t rx_buf_size;
 837         int diag;
 838
 839         /* Issue a global reset */
 840         e1000_reset_hw(hw);
 841
 842         /* Let the firmware know the OS is in control */
 843         em_hw_control_acquire(hw);
 844
 845         /*
 846          * These parameters control the automatic generation (Tx) and
 847          * response (Rx) to Ethernet PAUSE frames.
 848          * - High water mark should allow for at least two standard size (1518)
 849          *   frames to be received after sending an XOFF.
 850          * - Low water mark works best when it is very near the high water mark.
 851          *   This allows the receiver to restart by sending XON when it has
 852          *   drained a bit. Here we use an arbitrary value of 1500 which will
 853          *   restart after one full frame is pulled from the buffer. There
 854          *   could be several smaller frames in the buffer and if so they will
 855          *   not trigger the XON until their total number reduces the buffer
 856          *   by 1500.
 857          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 858          */
 859         rx_buf_size = em_get_rx_buffer_size(hw);
 860
 861         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 862         hw->fc.low_water = hw->fc.high_water - 1500;
 863
 864         if (hw->mac.type == e1000_80003es2lan)
 865                 hw->fc.pause_time = UINT16_MAX;
 866         else
 867                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 868
 869         hw->fc.send_xon = 1;
 870
 871         /* Set Flow control, use the tunable location if sane */
 872         if (em_fc_setting <= e1000_fc_full)
 873                 hw->fc.requested_mode = em_fc_setting;
 874         else
 875                 hw->fc.requested_mode = e1000_fc_none;
 876
 877         /* Workaround: no TX flow ctrl for PCH */
 878         if (hw->mac.type == e1000_pchlan)
 879                 hw->fc.requested_mode = e1000_fc_rx_pause;
 880
 881         /* Override - settings for PCH2LAN, ya its magic :) */
 882         if (hw->mac.type == e1000_pch2lan) {
 883                 hw->fc.high_water = 0x5C20;
 884                 hw->fc.low_water = 0x5048;
 885                 hw->fc.pause_time = 0x0650;
 886                 hw->fc.refresh_time = 0x0400;
 887         } else if (hw->mac.type == e1000_pch_lpt ||
 888                    hw->mac.type == e1000_pch_spt ||
 889                    hw->mac.type == e1000_pch_cnp) {
 890                 hw->fc.requested_mode = e1000_fc_full;
 891         }
 892
 893         diag = e1000_init_hw(hw);
 894         if (diag < 0)
 895                 return diag;
 896         e1000_check_for_link(hw);
 897         return 0;
 898 }
 899
 900 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 901 static void
 902 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 903 {
 904         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 905         struct e1000_hw_stats *stats =
 906                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 907         int pause_frames;
 908
 909         if(hw->phy.media_type == e1000_media_type_copper ||
 910                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 911                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 912                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 913         }
 914
 915         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 916         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 917         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 918         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 919
 920         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 921         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 922         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 923         stats->dc += E1000_READ_REG(hw, E1000_DC);
 924         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 925         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 926         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 927
 928         /*
 929          * For watchdog management we need to know if we have been
 930          * paused during the last interval, so capture that here.
 931          */
 932         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 933         stats->xoffrxc += pause_frames;
 934         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 935         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 936         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 937         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 938         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 939         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 940         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 941         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 942         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 943         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 944         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 945         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 946
 947         /*
 948          * For the 64-bit byte counters the low dword must be read first.
 949          * Both registers clear on the read of the high dword.
 950          */
 951
 952         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 953         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 954         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 955         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 956
 957         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 958         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 959         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 960         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 961         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 962
 963         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 964         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 965
 966         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 967         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 968         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 969         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 970         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 971         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 972         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 973         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 974         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 975         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 976
 977         /* Interrupt Counts */
 978
 979         if (hw->mac.type >= e1000_82571) {
 980                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 981                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 982                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 983                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 984                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 985                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 986                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 987                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 988                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 989         }
 990
 991         if (hw->mac.type >= e1000_82543) {
 992                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 993                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 994                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 995                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 996                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 997                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 998         }
 999
1000         if (rte_stats == NULL)
1001                 return;
1002
1003         /* Rx Errors */
1004         rte_stats->imissed = stats->mpc;
1005         rte_stats->ierrors = stats->crcerrs +
1006                              stats->rlec + stats->ruc + stats->roc +
1007                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1008
1009         /* Tx Errors */
1010         rte_stats->oerrors = stats->ecol + stats->latecol;
1011
1012         rte_stats->ipackets = stats->gprc;
1013         rte_stats->opackets = stats->gptc;
1014         rte_stats->ibytes   = stats->gorc;
1015         rte_stats->obytes   = stats->gotc;
1016 }
1017
1018 static void
1019 eth_em_stats_reset(struct rte_eth_dev *dev)
1020 {
1021         struct e1000_hw_stats *hw_stats =
1022                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1023
1024         /* HW registers are cleared on read */
1025         eth_em_stats_get(dev, NULL);
1026
1027         /* Reset software totals */
1028         memset(hw_stats, 0, sizeof(*hw_stats));
1029 }
1030
1031 static int
1032 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1033 {
1034         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1035         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1036         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1037
1038         em_rxq_intr_enable(hw);
1039         rte_intr_enable(intr_handle);
1040
1041         return 0;
1042 }
1043
1044 static int
1045 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1046 {
1047         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1048
1049         em_rxq_intr_disable(hw);
1050
1051         return 0;
1052 }
1053
1054 static uint32_t
1055 em_get_max_pktlen(const struct e1000_hw *hw)
1056 {
1057         switch (hw->mac.type) {
1058         case e1000_82571:
1059         case e1000_82572:
1060         case e1000_ich9lan:
1061         case e1000_ich10lan:
1062         case e1000_pch2lan:
1063         case e1000_pch_lpt:
1064         case e1000_pch_spt:
1065         case e1000_pch_cnp:
1066         case e1000_82574:
1067         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1068         case e1000_82583:
1069                 return 0x2412;
1070         case e1000_pchlan:
1071                 return 0x1000;
1072         /* Adapters that do not support jumbo frames */
1073         case e1000_ich8lan:
1074                 return ETHER_MAX_LEN;
1075         default:
1076                 return MAX_JUMBO_FRAME_SIZE;
1077         }
1078 }
1079
1080 static void
1081 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1082 {
1083         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1084
1085         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1086         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1087         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1088         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1089
1090         /*
1091          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1092          * Unfortunatelly, all these nics have just one TX context.
1093          * So we have few choises for TX:
1094          * - Use just one TX queue.
1095          * - Allow cksum offload only for one TX queue.
1096          * - Don't allow TX cksum offload at all.
1097          * For now, option #1 was chosen.
1098          * To use second RX queue we have to use extended RX descriptor
1099          * (Multiple Receive Queues are mutually exclusive with UDP
1100          * fragmentation and are not supported when a legacy receive
1101          * descriptor format is used).
1102          * Which means separate RX routinies - as legacy nics (82540, 82545)
1103          * don't support extended RXD.
1104          * To avoid it we support just one RX queue for now (no RSS).
1105          */
1106
1107         dev_info->max_rx_queues = 1;
1108         dev_info->max_tx_queues = 1;
1109
1110         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1111                 .nb_max = E1000_MAX_RING_DESC,
1112                 .nb_min = E1000_MIN_RING_DESC,
1113                 .nb_align = EM_RXD_ALIGN,
1114         };
1115
1116         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1117                 .nb_max = E1000_MAX_RING_DESC,
1118                 .nb_min = E1000_MIN_RING_DESC,
1119                 .nb_align = EM_TXD_ALIGN,
1120                 .nb_seg_max = EM_TX_MAX_SEG,
1121                 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1122         };
1123
1124         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1125                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1126                         ETH_LINK_SPEED_1G;
1127 }
1128
1129 /* return 0 means link status changed, -1 means not changed */
1130 static int
1131 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1132 {
1133         struct e1000_hw *hw =
1134                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1135         struct rte_eth_link link, old;
1136         int link_check, count;
1137
1138         link_check = 0;
1139         hw->mac.get_link_status = 1;
1140
1141         /* possible wait-to-complete in up to 9 seconds */
1142         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1143                 /* Read the real link status */
1144                 switch (hw->phy.media_type) {
1145                 case e1000_media_type_copper:
1146                         /* Do the work to read phy */
1147                         e1000_check_for_link(hw);
1148                         link_check = !hw->mac.get_link_status;
1149                         break;
1150
1151                 case e1000_media_type_fiber:
1152                         e1000_check_for_link(hw);
1153                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1154                                         E1000_STATUS_LU);
1155                         break;
1156
1157                 case e1000_media_type_internal_serdes:
1158                         e1000_check_for_link(hw);
1159                         link_check = hw->mac.serdes_has_link;
1160                         break;
1161
1162                 default:
1163                         break;
1164                 }
1165                 if (link_check || wait_to_complete == 0)
1166                         break;
1167                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1168         }
1169         memset(&link, 0, sizeof(link));
1170         rte_em_dev_atomic_read_link_status(dev, &link);
1171         old = link;
1172
1173         /* Now we check if a transition has happened */
1174         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1175                 uint16_t duplex, speed;
1176                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1177                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1178                                 ETH_LINK_FULL_DUPLEX :
1179                                 ETH_LINK_HALF_DUPLEX;
1180                 link.link_speed = speed;
1181                 link.link_status = ETH_LINK_UP;
1182                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1183                                 ETH_LINK_SPEED_FIXED);
1184         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1185                 link.link_speed = 0;
1186                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1187                 link.link_status = ETH_LINK_DOWN;
1188                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1189         }
1190         rte_em_dev_atomic_write_link_status(dev, &link);
1191
1192         /* not changed */
1193         if (old.link_status == link.link_status)
1194                 return -1;
1195
1196         /* changed */
1197         return 0;
1198 }
1199
1200 /*
1201  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1202  * For ASF and Pass Through versions of f/w this means
1203  * that the driver is loaded. For AMT version type f/w
1204  * this means that the network i/f is open.
1205  */
1206 static void
1207 em_hw_control_acquire(struct e1000_hw *hw)
1208 {
1209         uint32_t ctrl_ext, swsm;
1210
1211         /* Let firmware know the driver has taken over */
1212         if (hw->mac.type == e1000_82573) {
1213                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1214                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1215
1216         } else {
1217                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1218                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1219                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1220         }
1221 }
1222
1223 /*
1224  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1225  * For ASF and Pass Through versions of f/w this means that the
1226  * driver is no longer loaded. For AMT versions of the
1227  * f/w this means that the network i/f is closed.
1228  */
1229 static void
1230 em_hw_control_release(struct e1000_hw *hw)
1231 {
1232         uint32_t ctrl_ext, swsm;
1233
1234         /* Let firmware taken over control of h/w */
1235         if (hw->mac.type == e1000_82573) {
1236                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1237                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1238         } else {
1239                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1240                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1241                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1242         }
1243 }
1244
1245 /*
1246  * Bit of a misnomer, what this really means is
1247  * to enable OS management of the system... aka
1248  * to disable special hardware management features.
1249  */
1250 static void
1251 em_init_manageability(struct e1000_hw *hw)
1252 {
1253         if (e1000_enable_mng_pass_thru(hw)) {
1254                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1255                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1256
1257                 /* disable hardware interception of ARP */
1258                 manc &= ~(E1000_MANC_ARP_EN);
1259
1260                 /* enable receiving management packets to the host */
1261                 manc |= E1000_MANC_EN_MNG2HOST;
1262                 manc2h |= 1 << 5;  /* Mng Port 623 */
1263                 manc2h |= 1 << 6;  /* Mng Port 664 */
1264                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1265                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1266         }
1267 }
1268
1269 /*
1270  * Give control back to hardware management
1271  * controller if there is one.
1272  */
1273 static void
1274 em_release_manageability(struct e1000_hw *hw)
1275 {
1276         uint32_t manc;
1277
1278         if (e1000_enable_mng_pass_thru(hw)) {
1279                 manc = E1000_READ_REG(hw, E1000_MANC);
1280
1281                 /* re-enable hardware interception of ARP */
1282                 manc |= E1000_MANC_ARP_EN;
1283                 manc &= ~E1000_MANC_EN_MNG2HOST;
1284
1285                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1286         }
1287 }
1288
1289 static void
1290 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1291 {
1292         struct e1000_hw *hw =
1293                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1294         uint32_t rctl;
1295
1296         rctl = E1000_READ_REG(hw, E1000_RCTL);
1297         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1298         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1299 }
1300
1301 static void
1302 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1303 {
1304         struct e1000_hw *hw =
1305                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1306         uint32_t rctl;
1307
1308         rctl = E1000_READ_REG(hw, E1000_RCTL);
1309         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1310         if (dev->data->all_multicast == 1)
1311                 rctl |= E1000_RCTL_MPE;
1312         else
1313                 rctl &= (~E1000_RCTL_MPE);
1314         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1315 }
1316
1317 static void
1318 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1319 {
1320         struct e1000_hw *hw =
1321                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1322         uint32_t rctl;
1323
1324         rctl = E1000_READ_REG(hw, E1000_RCTL);
1325         rctl |= E1000_RCTL_MPE;
1326         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1327 }
1328
1329 static void
1330 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1331 {
1332         struct e1000_hw *hw =
1333                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1334         uint32_t rctl;
1335
1336         if (dev->data->promiscuous == 1)
1337                 return; /* must remain in all_multicast mode */
1338         rctl = E1000_READ_REG(hw, E1000_RCTL);
1339         rctl &= (~E1000_RCTL_MPE);
1340         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1341 }
1342
1343 static int
1344 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1345 {
1346         struct e1000_hw *hw =
1347                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348         struct e1000_vfta * shadow_vfta =
1349                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1350         uint32_t vfta;
1351         uint32_t vid_idx;
1352         uint32_t vid_bit;
1353
1354         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1355                               E1000_VFTA_ENTRY_MASK);
1356         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1357         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1358         if (on)
1359                 vfta |= vid_bit;
1360         else
1361                 vfta &= ~vid_bit;
1362         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1363
1364         /* update local VFTA copy */
1365         shadow_vfta->vfta[vid_idx] = vfta;
1366
1367         return 0;
1368 }
1369
1370 static void
1371 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1372 {
1373         struct e1000_hw *hw =
1374                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1375         uint32_t reg;
1376
1377         /* Filter Table Disable */
1378         reg = E1000_READ_REG(hw, E1000_RCTL);
1379         reg &= ~E1000_RCTL_CFIEN;
1380         reg &= ~E1000_RCTL_VFE;
1381         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1382 }
1383
1384 static void
1385 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1386 {
1387         struct e1000_hw *hw =
1388                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1389         struct e1000_vfta * shadow_vfta =
1390                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1391         uint32_t reg;
1392         int i;
1393
1394         /* Filter Table Enable, CFI not used for packet acceptance */
1395         reg = E1000_READ_REG(hw, E1000_RCTL);
1396         reg &= ~E1000_RCTL_CFIEN;
1397         reg |= E1000_RCTL_VFE;
1398         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1399
1400         /* restore vfta from local copy */
1401         for (i = 0; i < IGB_VFTA_SIZE; i++)
1402                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1403 }
1404
1405 static void
1406 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1407 {
1408         struct e1000_hw *hw =
1409                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1410         uint32_t reg;
1411
1412         /* VLAN Mode Disable */
1413         reg = E1000_READ_REG(hw, E1000_CTRL);
1414         reg &= ~E1000_CTRL_VME;
1415         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1416
1417 }
1418
1419 static void
1420 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1421 {
1422         struct e1000_hw *hw =
1423                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1424         uint32_t reg;
1425
1426         /* VLAN Mode Enable */
1427         reg = E1000_READ_REG(hw, E1000_CTRL);
1428         reg |= E1000_CTRL_VME;
1429         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1430 }
1431
1432 static void
1433 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1434 {
1435         if(mask & ETH_VLAN_STRIP_MASK){
1436                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1437                         em_vlan_hw_strip_enable(dev);
1438                 else
1439                         em_vlan_hw_strip_disable(dev);
1440         }
1441
1442         if(mask & ETH_VLAN_FILTER_MASK){
1443                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1444                         em_vlan_hw_filter_enable(dev);
1445                 else
1446                         em_vlan_hw_filter_disable(dev);
1447         }
1448 }
1449
1450 /*
1451  * It enables the interrupt mask and then enable the interrupt.
1452  *
1453  * @param dev
1454  *  Pointer to struct rte_eth_dev.
1455  *
1456  * @return
1457  *  - On success, zero.
1458  *  - On failure, a negative value.
1459  */
1460 static int
1461 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1462 {
1463         uint32_t regval;
1464         struct e1000_hw *hw =
1465                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1466
1467         /* clear interrupt */
1468         E1000_READ_REG(hw, E1000_ICR);
1469         regval = E1000_READ_REG(hw, E1000_IMS);
1470         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1471         return 0;
1472 }
1473
1474 /*
1475  * It clears the interrupt causes and enables the interrupt.
1476  * It will be called once only during nic initialized.
1477  *
1478  * @param dev
1479  *  Pointer to struct rte_eth_dev.
1480  *
1481  * @return
1482  *  - On success, zero.
1483  *  - On failure, a negative value.
1484  */
1485 static int
1486 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1487 {
1488         struct e1000_hw *hw =
1489         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1490
1491         E1000_READ_REG(hw, E1000_ICR);
1492         em_rxq_intr_enable(hw);
1493         return 0;
1494 }
1495
1496 /*
1497  * It enable receive packet interrupt.
1498  * @param hw
1499  * Pointer to struct e1000_hw
1500  *
1501  * @return
1502  */
1503 static void
1504 em_rxq_intr_enable(struct e1000_hw *hw)
1505 {
1506         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1507         E1000_WRITE_FLUSH(hw);
1508 }
1509
1510 /*
1511  * It disabled lsc interrupt.
1512  * @param hw
1513  * Pointer to struct e1000_hw
1514  *
1515  * @return
1516  */
1517 static void
1518 em_lsc_intr_disable(struct e1000_hw *hw)
1519 {
1520         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1521         E1000_WRITE_FLUSH(hw);
1522 }
1523
1524 /*
1525  * It disabled receive packet interrupt.
1526  * @param hw
1527  * Pointer to struct e1000_hw
1528  *
1529  * @return
1530  */
1531 static void
1532 em_rxq_intr_disable(struct e1000_hw *hw)
1533 {
1534         E1000_READ_REG(hw, E1000_ICR);
1535         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1536         E1000_WRITE_FLUSH(hw);
1537 }
1538
1539 /*
1540  * It reads ICR and gets interrupt causes, check it and set a bit flag
1541  * to update link status.
1542  *
1543  * @param dev
1544  *  Pointer to struct rte_eth_dev.
1545  *
1546  * @return
1547  *  - On success, zero.
1548  *  - On failure, a negative value.
1549  */
1550 static int
1551 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1552 {
1553         uint32_t icr;
1554         struct e1000_hw *hw =
1555                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1556         struct e1000_interrupt *intr =
1557                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1558
1559         /* read-on-clear nic registers here */
1560         icr = E1000_READ_REG(hw, E1000_ICR);
1561         if (icr & E1000_ICR_LSC) {
1562                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1563         }
1564
1565         return 0;
1566 }
1567
1568 /*
1569  * It executes link_update after knowing an interrupt is prsent.
1570  *
1571  * @param dev
1572  *  Pointer to struct rte_eth_dev.
1573  *
1574  * @return
1575  *  - On success, zero.
1576  *  - On failure, a negative value.
1577  */
1578 static int
1579 eth_em_interrupt_action(struct rte_eth_dev *dev,
1580                         struct rte_intr_handle *intr_handle)
1581 {
1582         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1583         struct e1000_hw *hw =
1584                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585         struct e1000_interrupt *intr =
1586                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1587         uint32_t tctl, rctl;
1588         struct rte_eth_link link;
1589         int ret;
1590
1591         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1592                 return -1;
1593
1594         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1595         rte_intr_enable(intr_handle);
1596
1597         /* set get_link_status to check register later */
1598         hw->mac.get_link_status = 1;
1599         ret = eth_em_link_update(dev, 0);
1600
1601         /* check if link has changed */
1602         if (ret < 0)
1603                 return 0;
1604
1605         memset(&link, 0, sizeof(link));
1606         rte_em_dev_atomic_read_link_status(dev, &link);
1607         if (link.link_status) {
1608                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1609                              dev->data->port_id, (unsigned)link.link_speed,
1610                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1611                              "full-duplex" : "half-duplex");
1612         } else {
1613                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1614         }
1615         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1616                      pci_dev->addr.domain, pci_dev->addr.bus,
1617                      pci_dev->addr.devid, pci_dev->addr.function);
1618
1619         tctl = E1000_READ_REG(hw, E1000_TCTL);
1620         rctl = E1000_READ_REG(hw, E1000_RCTL);
1621         if (link.link_status) {
1622                 /* enable Tx/Rx */
1623                 tctl |= E1000_TCTL_EN;
1624                 rctl |= E1000_RCTL_EN;
1625         } else {
1626                 /* disable Tx/Rx */
1627                 tctl &= ~E1000_TCTL_EN;
1628                 rctl &= ~E1000_RCTL_EN;
1629         }
1630         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1631         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1632         E1000_WRITE_FLUSH(hw);
1633
1634         return 0;
1635 }
1636
1637 /**
1638  * Interrupt handler which shall be registered at first.
1639  *
1640  * @param handle
1641  *  Pointer to interrupt handle.
1642  * @param param
1643  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1644  *
1645  * @return
1646  *  void
1647  */
1648 static void
1649 eth_em_interrupt_handler(struct rte_intr_handle *handle,
1650                          void *param)
1651 {
1652         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1653
1654         eth_em_interrupt_get_status(dev);
1655         eth_em_interrupt_action(dev, handle);
1656         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1657 }
1658
1659 static int
1660 eth_em_led_on(struct rte_eth_dev *dev)
1661 {
1662         struct e1000_hw *hw;
1663
1664         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1665         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1666 }
1667
1668 static int
1669 eth_em_led_off(struct rte_eth_dev *dev)
1670 {
1671         struct e1000_hw *hw;
1672
1673         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1674         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1675 }
1676
1677 static int
1678 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1679 {
1680         struct e1000_hw *hw;
1681         uint32_t ctrl;
1682         int tx_pause;
1683         int rx_pause;
1684
1685         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1686         fc_conf->pause_time = hw->fc.pause_time;
1687         fc_conf->high_water = hw->fc.high_water;
1688         fc_conf->low_water = hw->fc.low_water;
1689         fc_conf->send_xon = hw->fc.send_xon;
1690         fc_conf->autoneg = hw->mac.autoneg;
1691
1692         /*
1693          * Return rx_pause and tx_pause status according to actual setting of
1694          * the TFCE and RFCE bits in the CTRL register.
1695          */
1696         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1697         if (ctrl & E1000_CTRL_TFCE)
1698                 tx_pause = 1;
1699         else
1700                 tx_pause = 0;
1701
1702         if (ctrl & E1000_CTRL_RFCE)
1703                 rx_pause = 1;
1704         else
1705                 rx_pause = 0;
1706
1707         if (rx_pause && tx_pause)
1708                 fc_conf->mode = RTE_FC_FULL;
1709         else if (rx_pause)
1710                 fc_conf->mode = RTE_FC_RX_PAUSE;
1711         else if (tx_pause)
1712                 fc_conf->mode = RTE_FC_TX_PAUSE;
1713         else
1714                 fc_conf->mode = RTE_FC_NONE;
1715
1716         return 0;
1717 }
1718
1719 static int
1720 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1721 {
1722         struct e1000_hw *hw;
1723         int err;
1724         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1725                 e1000_fc_none,
1726                 e1000_fc_rx_pause,
1727                 e1000_fc_tx_pause,
1728                 e1000_fc_full
1729         };
1730         uint32_t rx_buf_size;
1731         uint32_t max_high_water;
1732         uint32_t rctl;
1733
1734         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1735         if (fc_conf->autoneg != hw->mac.autoneg)
1736                 return -ENOTSUP;
1737         rx_buf_size = em_get_rx_buffer_size(hw);
1738         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1739
1740         /* At least reserve one Ethernet frame for watermark */
1741         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1742         if ((fc_conf->high_water > max_high_water) ||
1743             (fc_conf->high_water < fc_conf->low_water)) {
1744                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1745                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1746                 return -EINVAL;
1747         }
1748
1749         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1750         hw->fc.pause_time     = fc_conf->pause_time;
1751         hw->fc.high_water     = fc_conf->high_water;
1752         hw->fc.low_water      = fc_conf->low_water;
1753         hw->fc.send_xon       = fc_conf->send_xon;
1754
1755         err = e1000_setup_link_generic(hw);
1756         if (err == E1000_SUCCESS) {
1757
1758                 /* check if we want to forward MAC frames - driver doesn't have native
1759                  * capability to do that, so we'll write the registers ourselves */
1760
1761                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1762
1763                 /* set or clear MFLCN.PMCF bit depending on configuration */
1764                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1765                         rctl |= E1000_RCTL_PMCF;
1766                 else
1767                         rctl &= ~E1000_RCTL_PMCF;
1768
1769                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1770                 E1000_WRITE_FLUSH(hw);
1771
1772                 return 0;
1773         }
1774
1775         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1776         return -EIO;
1777 }
1778
1779 static void
1780 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1781                 uint32_t index, __rte_unused uint32_t pool)
1782 {
1783         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1784
1785         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1786 }
1787
1788 static void
1789 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1790 {
1791         uint8_t addr[ETHER_ADDR_LEN];
1792         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1793
1794         memset(addr, 0, sizeof(addr));
1795
1796         e1000_rar_set(hw, addr, index);
1797 }
1798
1799 static int
1800 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1801 {
1802         struct rte_eth_dev_info dev_info;
1803         struct e1000_hw *hw;
1804         uint32_t frame_size;
1805         uint32_t rctl;
1806
1807         eth_em_infos_get(dev, &dev_info);
1808         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1809
1810         /* check that mtu is within the allowed range */
1811         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1812                 return -EINVAL;
1813
1814         /* refuse mtu that requires the support of scattered packets when this
1815          * feature has not been enabled before. */
1816         if (!dev->data->scattered_rx &&
1817             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1818                 return -EINVAL;
1819
1820         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1821         rctl = E1000_READ_REG(hw, E1000_RCTL);
1822
1823         /* switch to jumbo mode if needed */
1824         if (frame_size > ETHER_MAX_LEN) {
1825                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1826                 rctl |= E1000_RCTL_LPE;
1827         } else {
1828                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1829                 rctl &= ~E1000_RCTL_LPE;
1830         }
1831         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1832
1833         /* update max frame size */
1834         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1835         return 0;
1836 }
1837
1838 static int
1839 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1840                         struct ether_addr *mc_addr_set,
1841                         uint32_t nb_mc_addr)
1842 {
1843         struct e1000_hw *hw;
1844
1845         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1846         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1847         return 0;
1848 }
1849
1850 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd.pci_drv);
1851 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1852 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio");