drivers/net/e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 #define EM_EIAC                 0x000DC
  60
  61 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  62
  63
  64 static int eth_em_configure(struct rte_eth_dev *dev);
  65 static int eth_em_start(struct rte_eth_dev *dev);
  66 static void eth_em_stop(struct rte_eth_dev *dev);
  67 static void eth_em_close(struct rte_eth_dev *dev);
  68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  72 static int eth_em_link_update(struct rte_eth_dev *dev,
  73                                 int wait_to_complete);
  74 static void eth_em_stats_get(struct rte_eth_dev *dev,
  75                                 struct rte_eth_stats *rte_stats);
  76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  77 static void eth_em_infos_get(struct rte_eth_dev *dev,
  78                                 struct rte_eth_dev_info *dev_info);
  79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  80                                 struct rte_eth_fc_conf *fc_conf);
  81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  82                                 struct rte_eth_fc_conf *fc_conf);
  83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  84 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  86 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
  87                                    struct rte_intr_handle *handle);
  88 static void eth_em_interrupt_handler(void *param);
  89
  90 static int em_hw_init(struct e1000_hw *hw);
  91 static int em_hardware_init(struct e1000_hw *hw);
  92 static void em_hw_control_acquire(struct e1000_hw *hw);
  93 static void em_hw_control_release(struct e1000_hw *hw);
  94 static void em_init_manageability(struct e1000_hw *hw);
  95 static void em_release_manageability(struct e1000_hw *hw);
  96
  97 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  98
  99 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 100                 uint16_t vlan_id, int on);
 101 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 102 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 103 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 104 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 105 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 106
 107 /*
 108 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 109                                         uint16_t vlan_id, int on);
 110 */
 111
 112 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 113 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 114 static void em_lsc_intr_disable(struct e1000_hw *hw);
 115 static void em_rxq_intr_enable(struct e1000_hw *hw);
 116 static void em_rxq_intr_disable(struct e1000_hw *hw);
 117
 118 static int eth_em_led_on(struct rte_eth_dev *dev);
 119 static int eth_em_led_off(struct rte_eth_dev *dev);
 120
 121 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 122 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 123                 uint32_t index, uint32_t pool);
 124 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 125
 126 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
 127                                    struct ether_addr *mc_addr_set,
 128                                    uint32_t nb_mc_addr);
 129
 130 #define EM_FC_PAUSE_TIME 0x0680
 131 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 132 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 133
 134 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 135
 136 /*
 137  * The set of PCI devices this driver supports
 138  */
 139 static const struct rte_pci_id pci_id_em_map[] = {
 140         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 158         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 159         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 160         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 161         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 162         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 163         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 164         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 165         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 166         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 167         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 168         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 169         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 170         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 171         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
 172         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
 173         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
 174         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
 175         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
 176         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
 177         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
 178         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
 179         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
 180         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
 181         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
 182         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
 183         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
 184         { .vendor_id = 0, /* sentinel */ },
 185 };
 186
 187 static const struct eth_dev_ops eth_em_ops = {
 188         .dev_configure        = eth_em_configure,
 189         .dev_start            = eth_em_start,
 190         .dev_stop             = eth_em_stop,
 191         .dev_close            = eth_em_close,
 192         .promiscuous_enable   = eth_em_promiscuous_enable,
 193         .promiscuous_disable  = eth_em_promiscuous_disable,
 194         .allmulticast_enable  = eth_em_allmulticast_enable,
 195         .allmulticast_disable = eth_em_allmulticast_disable,
 196         .link_update          = eth_em_link_update,
 197         .stats_get            = eth_em_stats_get,
 198         .stats_reset          = eth_em_stats_reset,
 199         .dev_infos_get        = eth_em_infos_get,
 200         .mtu_set              = eth_em_mtu_set,
 201         .vlan_filter_set      = eth_em_vlan_filter_set,
 202         .vlan_offload_set     = eth_em_vlan_offload_set,
 203         .rx_queue_setup       = eth_em_rx_queue_setup,
 204         .rx_queue_release     = eth_em_rx_queue_release,
 205         .rx_queue_count       = eth_em_rx_queue_count,
 206         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 207         .rx_descriptor_status = eth_em_rx_descriptor_status,
 208         .tx_descriptor_status = eth_em_tx_descriptor_status,
 209         .tx_queue_setup       = eth_em_tx_queue_setup,
 210         .tx_queue_release     = eth_em_tx_queue_release,
 211         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 212         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 213         .dev_led_on           = eth_em_led_on,
 214         .dev_led_off          = eth_em_led_off,
 215         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 216         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 217         .mac_addr_add         = eth_em_rar_set,
 218         .mac_addr_remove      = eth_em_rar_clear,
 219         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 220         .rxq_info_get         = em_rxq_info_get,
 221         .txq_info_get         = em_txq_info_get,
 222 };
 223
 224 /**
 225  * Atomically reads the link status information from global
 226  * structure rte_eth_dev.
 227  *
 228  * @param dev
 229  *   - Pointer to the structure rte_eth_dev to read from.
 230  *   - Pointer to the buffer to be saved with the link status.
 231  *
 232  * @return
 233  *   - On success, zero.
 234  *   - On failure, negative value.
 235  */
 236 static inline int
 237 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 238                                 struct rte_eth_link *link)
 239 {
 240         struct rte_eth_link *dst = link;
 241         struct rte_eth_link *src = &(dev->data->dev_link);
 242
 243         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 244                                         *(uint64_t *)src) == 0)
 245                 return -1;
 246
 247         return 0;
 248 }
 249
 250 /**
 251  * Atomically writes the link status information into global
 252  * structure rte_eth_dev.
 253  *
 254  * @param dev
 255  *   - Pointer to the structure rte_eth_dev to read from.
 256  *   - Pointer to the buffer to be saved with the link status.
 257  *
 258  * @return
 259  *   - On success, zero.
 260  *   - On failure, negative value.
 261  */
 262 static inline int
 263 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 264                                 struct rte_eth_link *link)
 265 {
 266         struct rte_eth_link *dst = &(dev->data->dev_link);
 267         struct rte_eth_link *src = link;
 268
 269         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 270                                         *(uint64_t *)src) == 0)
 271                 return -1;
 272
 273         return 0;
 274 }
 275
 276 /**
 277  *  eth_em_dev_is_ich8 - Check for ICH8 device
 278  *  @hw: pointer to the HW structure
 279  *
 280  *  return TRUE for ICH8, otherwise FALSE
 281  **/
 282 static bool
 283 eth_em_dev_is_ich8(struct e1000_hw *hw)
 284 {
 285         DEBUGFUNC("eth_em_dev_is_ich8");
 286
 287         switch (hw->device_id) {
 288         case E1000_DEV_ID_PCH_LPT_I217_LM:
 289         case E1000_DEV_ID_PCH_LPT_I217_V:
 290         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 291         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 292         case E1000_DEV_ID_PCH_I218_V2:
 293         case E1000_DEV_ID_PCH_I218_LM2:
 294         case E1000_DEV_ID_PCH_I218_V3:
 295         case E1000_DEV_ID_PCH_I218_LM3:
 296         case E1000_DEV_ID_PCH_SPT_I219_LM:
 297         case E1000_DEV_ID_PCH_SPT_I219_V:
 298         case E1000_DEV_ID_PCH_SPT_I219_LM2:
 299         case E1000_DEV_ID_PCH_SPT_I219_V2:
 300         case E1000_DEV_ID_PCH_LBG_I219_LM3:
 301         case E1000_DEV_ID_PCH_SPT_I219_LM4:
 302         case E1000_DEV_ID_PCH_SPT_I219_V4:
 303         case E1000_DEV_ID_PCH_SPT_I219_LM5:
 304         case E1000_DEV_ID_PCH_SPT_I219_V5:
 305         case E1000_DEV_ID_PCH_CNP_I219_LM6:
 306         case E1000_DEV_ID_PCH_CNP_I219_V6:
 307         case E1000_DEV_ID_PCH_CNP_I219_LM7:
 308         case E1000_DEV_ID_PCH_CNP_I219_V7:
 309                 return 1;
 310         default:
 311                 return 0;
 312         }
 313 }
 314
 315 static int
 316 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 317 {
 318         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
 319         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 320         struct e1000_adapter *adapter =
 321                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 322         struct e1000_hw *hw =
 323                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 324         struct e1000_vfta * shadow_vfta =
 325                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 326
 327         eth_dev->dev_ops = &eth_em_ops;
 328         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 329         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 330         eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
 331
 332         /* for secondary processes, we don't initialise any further as primary
 333          * has already done this work. Only check we don't need a different
 334          * RX function */
 335         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 336                 if (eth_dev->data->scattered_rx)
 337                         eth_dev->rx_pkt_burst =
 338                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 339                 return 0;
 340         }
 341
 342         rte_eth_copy_pci_info(eth_dev, pci_dev);
 343         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 344
 345         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 346         hw->device_id = pci_dev->id.device_id;
 347         adapter->stopped = 0;
 348
 349         /* For ICH8 support we'll need to map the flash memory BAR */
 350         if (eth_em_dev_is_ich8(hw))
 351                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 352
 353         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 354                         em_hw_init(hw) != 0) {
 355                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 356                         "failed to init HW",
 357                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 358                         pci_dev->id.device_id);
 359                 return -ENODEV;
 360         }
 361
 362         /* Allocate memory for storing MAC addresses */
 363         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 364                         hw->mac.rar_entry_count, 0);
 365         if (eth_dev->data->mac_addrs == NULL) {
 366                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 367                         "store MAC addresses",
 368                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 369                 return -ENOMEM;
 370         }
 371
 372         /* Copy the permanent MAC address */
 373         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 374                 eth_dev->data->mac_addrs);
 375
 376         /* initialize the vfta */
 377         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 378
 379         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 380                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 381                      pci_dev->id.device_id);
 382
 383         rte_intr_callback_register(intr_handle,
 384                                    eth_em_interrupt_handler, eth_dev);
 385
 386         return 0;
 387 }
 388
 389 static int
 390 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 391 {
 392         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
 393         struct e1000_adapter *adapter =
 394                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 395         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 396
 397         PMD_INIT_FUNC_TRACE();
 398
 399         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 400                 return -EPERM;
 401
 402         if (adapter->stopped == 0)
 403                 eth_em_close(eth_dev);
 404
 405         eth_dev->dev_ops = NULL;
 406         eth_dev->rx_pkt_burst = NULL;
 407         eth_dev->tx_pkt_burst = NULL;
 408
 409         rte_free(eth_dev->data->mac_addrs);
 410         eth_dev->data->mac_addrs = NULL;
 411
 412         /* disable uio intr before callback unregister */
 413         rte_intr_disable(intr_handle);
 414         rte_intr_callback_unregister(intr_handle,
 415                                      eth_em_interrupt_handler, eth_dev);
 416
 417         return 0;
 418 }
 419
 420 static struct eth_driver rte_em_pmd = {
 421         .pci_drv = {
 422                 .id_table = pci_id_em_map,
 423                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 424                 .probe = rte_eth_dev_pci_probe,
 425                 .remove = rte_eth_dev_pci_remove,
 426         },
 427         .eth_dev_init = eth_em_dev_init,
 428         .eth_dev_uninit = eth_em_dev_uninit,
 429         .dev_private_size = sizeof(struct e1000_adapter),
 430 };
 431
 432 static int
 433 em_hw_init(struct e1000_hw *hw)
 434 {
 435         int diag;
 436
 437         diag = hw->mac.ops.init_params(hw);
 438         if (diag != 0) {
 439                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 440                 return diag;
 441         }
 442         diag = hw->nvm.ops.init_params(hw);
 443         if (diag != 0) {
 444                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 445                 return diag;
 446         }
 447         diag = hw->phy.ops.init_params(hw);
 448         if (diag != 0) {
 449                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 450                 return diag;
 451         }
 452         (void) e1000_get_bus_info(hw);
 453
 454         hw->mac.autoneg = 1;
 455         hw->phy.autoneg_wait_to_complete = 0;
 456         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 457
 458         e1000_init_script_state_82541(hw, TRUE);
 459         e1000_set_tbi_compatibility_82543(hw, TRUE);
 460
 461         /* Copper options */
 462         if (hw->phy.media_type == e1000_media_type_copper) {
 463                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 464                 hw->phy.disable_polarity_correction = 0;
 465                 hw->phy.ms_type = e1000_ms_hw_default;
 466         }
 467
 468         /*
 469          * Start from a known state, this is important in reading the nvm
 470          * and mac from that.
 471          */
 472         e1000_reset_hw(hw);
 473
 474         /* Make sure we have a good EEPROM before we read from it */
 475         if (e1000_validate_nvm_checksum(hw) < 0) {
 476                 /*
 477                  * Some PCI-E parts fail the first check due to
 478                  * the link being in sleep state, call it again,
 479                  * if it fails a second time its a real issue.
 480                  */
 481                 diag = e1000_validate_nvm_checksum(hw);
 482                 if (diag < 0) {
 483                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 484                         goto error;
 485                 }
 486         }
 487
 488         /* Read the permanent MAC address out of the EEPROM */
 489         diag = e1000_read_mac_addr(hw);
 490         if (diag != 0) {
 491                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 492                 goto error;
 493         }
 494
 495         /* Now initialize the hardware */
 496         diag = em_hardware_init(hw);
 497         if (diag != 0) {
 498                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 499                 goto error;
 500         }
 501
 502         hw->mac.get_link_status = 1;
 503
 504         /* Indicate SOL/IDER usage */
 505         diag = e1000_check_reset_block(hw);
 506         if (diag < 0) {
 507                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 508                         "SOL/IDER session");
 509         }
 510         return 0;
 511
 512 error:
 513         em_hw_control_release(hw);
 514         return diag;
 515 }
 516
 517 static int
 518 eth_em_configure(struct rte_eth_dev *dev)
 519 {
 520         struct e1000_interrupt *intr =
 521                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 522
 523         PMD_INIT_FUNC_TRACE();
 524         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 525         PMD_INIT_FUNC_TRACE();
 526
 527         return 0;
 528 }
 529
 530 static void
 531 em_set_pba(struct e1000_hw *hw)
 532 {
 533         uint32_t pba;
 534
 535         /*
 536          * Packet Buffer Allocation (PBA)
 537          * Writing PBA sets the receive portion of the buffer
 538          * the remainder is used for the transmit buffer.
 539          * Devices before the 82547 had a Packet Buffer of 64K.
 540          * After the 82547 the buffer was reduced to 40K.
 541          */
 542         switch (hw->mac.type) {
 543                 case e1000_82547:
 544                 case e1000_82547_rev_2:
 545                 /* 82547: Total Packet Buffer is 40K */
 546                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 547                         break;
 548                 case e1000_82571:
 549                 case e1000_82572:
 550                 case e1000_80003es2lan:
 551                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 552                         break;
 553                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 554                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 555                         break;
 556                 case e1000_82574:
 557                 case e1000_82583:
 558                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 559                         break;
 560                 case e1000_ich8lan:
 561                         pba = E1000_PBA_8K;
 562                         break;
 563                 case e1000_ich9lan:
 564                 case e1000_ich10lan:
 565                         pba = E1000_PBA_10K;
 566                         break;
 567                 case e1000_pchlan:
 568                 case e1000_pch2lan:
 569                 case e1000_pch_lpt:
 570                 case e1000_pch_spt:
 571                 case e1000_pch_cnp:
 572                         pba = E1000_PBA_26K;
 573                         break;
 574                 default:
 575                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 576         }
 577
 578         E1000_WRITE_REG(hw, E1000_PBA, pba);
 579 }
 580
 581 static int
 582 eth_em_start(struct rte_eth_dev *dev)
 583 {
 584         struct e1000_adapter *adapter =
 585                 E1000_DEV_PRIVATE(dev->data->dev_private);
 586         struct e1000_hw *hw =
 587                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 588         struct rte_pci_device *pci_dev =
 589                 E1000_DEV_TO_PCI(dev);
 590         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 591         int ret, mask;
 592         uint32_t intr_vector = 0;
 593         uint32_t *speeds;
 594         int num_speeds;
 595         bool autoneg;
 596
 597         PMD_INIT_FUNC_TRACE();
 598
 599         eth_em_stop(dev);
 600
 601         e1000_power_up_phy(hw);
 602
 603         /* Set default PBA value */
 604         em_set_pba(hw);
 605
 606         /* Put the address into the Receive Address Array */
 607         e1000_rar_set(hw, hw->mac.addr, 0);
 608
 609         /*
 610          * With the 82571 adapter, RAR[0] may be overwritten
 611          * when the other port is reset, we make a duplicate
 612          * in RAR[14] for that eventuality, this assures
 613          * the interface continues to function.
 614          */
 615         if (hw->mac.type == e1000_82571) {
 616                 e1000_set_laa_state_82571(hw, TRUE);
 617                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 618         }
 619
 620         /* Initialize the hardware */
 621         if (em_hardware_init(hw)) {
 622                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 623                 return -EIO;
 624         }
 625
 626         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 627
 628         /* Configure for OS presence */
 629         em_init_manageability(hw);
 630
 631         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 632                 intr_vector = dev->data->nb_rx_queues;
 633                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 634                         return -1;
 635         }
 636
 637         if (rte_intr_dp_is_en(intr_handle)) {
 638                 intr_handle->intr_vec =
 639                         rte_zmalloc("intr_vec",
 640                                         dev->data->nb_rx_queues * sizeof(int), 0);
 641                 if (intr_handle->intr_vec == NULL) {
 642                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 643                                                 " intr_vec", dev->data->nb_rx_queues);
 644                         return -ENOMEM;
 645                 }
 646
 647                 /* enable rx interrupt */
 648                 em_rxq_intr_enable(hw);
 649         }
 650
 651         eth_em_tx_init(dev);
 652
 653         ret = eth_em_rx_init(dev);
 654         if (ret) {
 655                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 656                 em_dev_clear_queues(dev);
 657                 return ret;
 658         }
 659
 660         e1000_clear_hw_cntrs_base_generic(hw);
 661
 662         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 663                         ETH_VLAN_EXTEND_MASK;
 664         eth_em_vlan_offload_set(dev, mask);
 665
 666         /* Set Interrupt Throttling Rate to maximum allowed value. */
 667         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 668
 669         /* Setup link speed and duplex */
 670         speeds = &dev->data->dev_conf.link_speeds;
 671         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 672                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 673                 hw->mac.autoneg = 1;
 674         } else {
 675                 num_speeds = 0;
 676                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 677
 678                 /* Reset */
 679                 hw->phy.autoneg_advertised = 0;
 680
 681                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 682                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 683                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 684                         num_speeds = -1;
 685                         goto error_invalid_config;
 686                 }
 687                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 688                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 689                         num_speeds++;
 690                 }
 691                 if (*speeds & ETH_LINK_SPEED_10M) {
 692                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 693                         num_speeds++;
 694                 }
 695                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 696                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 697                         num_speeds++;
 698                 }
 699                 if (*speeds & ETH_LINK_SPEED_100M) {
 700                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 701                         num_speeds++;
 702                 }
 703                 if (*speeds & ETH_LINK_SPEED_1G) {
 704                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 705                         num_speeds++;
 706                 }
 707                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 708                         goto error_invalid_config;
 709
 710                 /* Set/reset the mac.autoneg based on the link speed,
 711                  * fixed or not
 712                  */
 713                 if (!autoneg) {
 714                         hw->mac.autoneg = 0;
 715                         hw->mac.forced_speed_duplex =
 716                                         hw->phy.autoneg_advertised;
 717                 } else {
 718                         hw->mac.autoneg = 1;
 719                 }
 720         }
 721
 722         e1000_setup_link(hw);
 723
 724         if (rte_intr_allow_others(intr_handle)) {
 725                 /* check if lsc interrupt is enabled */
 726                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 727                         ret = eth_em_interrupt_setup(dev);
 728                         if (ret) {
 729                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 730                                 em_dev_clear_queues(dev);
 731                                 return ret;
 732                         }
 733                 }
 734         } else {
 735                 rte_intr_callback_unregister(intr_handle,
 736                                                 eth_em_interrupt_handler,
 737                                                 (void *)dev);
 738                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 739                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 740                                      " no intr multiplexn");
 741         }
 742         /* check if rxq interrupt is enabled */
 743         if (dev->data->dev_conf.intr_conf.rxq != 0)
 744                 eth_em_rxq_interrupt_setup(dev);
 745
 746         rte_intr_enable(intr_handle);
 747
 748         adapter->stopped = 0;
 749
 750         PMD_INIT_LOG(DEBUG, "<<");
 751
 752         return 0;
 753
 754 error_invalid_config:
 755         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 756                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 757         em_dev_clear_queues(dev);
 758         return -EINVAL;
 759 }
 760
 761 /*********************************************************************
 762  *
 763  *  This routine disables all traffic on the adapter by issuing a
 764  *  global reset on the MAC.
 765  *
 766  **********************************************************************/
 767 static void
 768 eth_em_stop(struct rte_eth_dev *dev)
 769 {
 770         struct rte_eth_link link;
 771         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 772         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
 773         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 774
 775         em_rxq_intr_disable(hw);
 776         em_lsc_intr_disable(hw);
 777
 778         e1000_reset_hw(hw);
 779         if (hw->mac.type >= e1000_82544)
 780                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 781
 782         /* Power down the phy. Needed to make the link go down */
 783         e1000_power_down_phy(hw);
 784
 785         em_dev_clear_queues(dev);
 786
 787         /* clear the recorded link status */
 788         memset(&link, 0, sizeof(link));
 789         rte_em_dev_atomic_write_link_status(dev, &link);
 790
 791         if (!rte_intr_allow_others(intr_handle))
 792                 /* resume to the default handler */
 793                 rte_intr_callback_register(intr_handle,
 794                                            eth_em_interrupt_handler,
 795                                            (void *)dev);
 796
 797         /* Clean datapath event and queue/vec mapping */
 798         rte_intr_efd_disable(intr_handle);
 799         if (intr_handle->intr_vec != NULL) {
 800                 rte_free(intr_handle->intr_vec);
 801                 intr_handle->intr_vec = NULL;
 802         }
 803 }
 804
 805 static void
 806 eth_em_close(struct rte_eth_dev *dev)
 807 {
 808         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 809         struct e1000_adapter *adapter =
 810                 E1000_DEV_PRIVATE(dev->data->dev_private);
 811
 812         eth_em_stop(dev);
 813         adapter->stopped = 1;
 814         em_dev_free_queues(dev);
 815         e1000_phy_hw_reset(hw);
 816         em_release_manageability(hw);
 817         em_hw_control_release(hw);
 818 }
 819
 820 static int
 821 em_get_rx_buffer_size(struct e1000_hw *hw)
 822 {
 823         uint32_t rx_buf_size;
 824
 825         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 826         return rx_buf_size;
 827 }
 828
 829 /*********************************************************************
 830  *
 831  *  Initialize the hardware
 832  *
 833  **********************************************************************/
 834 static int
 835 em_hardware_init(struct e1000_hw *hw)
 836 {
 837         uint32_t rx_buf_size;
 838         int diag;
 839
 840         /* Issue a global reset */
 841         e1000_reset_hw(hw);
 842
 843         /* Let the firmware know the OS is in control */
 844         em_hw_control_acquire(hw);
 845
 846         /*
 847          * These parameters control the automatic generation (Tx) and
 848          * response (Rx) to Ethernet PAUSE frames.
 849          * - High water mark should allow for at least two standard size (1518)
 850          *   frames to be received after sending an XOFF.
 851          * - Low water mark works best when it is very near the high water mark.
 852          *   This allows the receiver to restart by sending XON when it has
 853          *   drained a bit. Here we use an arbitrary value of 1500 which will
 854          *   restart after one full frame is pulled from the buffer. There
 855          *   could be several smaller frames in the buffer and if so they will
 856          *   not trigger the XON until their total number reduces the buffer
 857          *   by 1500.
 858          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 859          */
 860         rx_buf_size = em_get_rx_buffer_size(hw);
 861
 862         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 863         hw->fc.low_water = hw->fc.high_water - 1500;
 864
 865         if (hw->mac.type == e1000_80003es2lan)
 866                 hw->fc.pause_time = UINT16_MAX;
 867         else
 868                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 869
 870         hw->fc.send_xon = 1;
 871
 872         /* Set Flow control, use the tunable location if sane */
 873         if (em_fc_setting <= e1000_fc_full)
 874                 hw->fc.requested_mode = em_fc_setting;
 875         else
 876                 hw->fc.requested_mode = e1000_fc_none;
 877
 878         /* Workaround: no TX flow ctrl for PCH */
 879         if (hw->mac.type == e1000_pchlan)
 880                 hw->fc.requested_mode = e1000_fc_rx_pause;
 881
 882         /* Override - settings for PCH2LAN, ya its magic :) */
 883         if (hw->mac.type == e1000_pch2lan) {
 884                 hw->fc.high_water = 0x5C20;
 885                 hw->fc.low_water = 0x5048;
 886                 hw->fc.pause_time = 0x0650;
 887                 hw->fc.refresh_time = 0x0400;
 888         } else if (hw->mac.type == e1000_pch_lpt ||
 889                    hw->mac.type == e1000_pch_spt ||
 890                    hw->mac.type == e1000_pch_cnp) {
 891                 hw->fc.requested_mode = e1000_fc_full;
 892         }
 893
 894         diag = e1000_init_hw(hw);
 895         if (diag < 0)
 896                 return diag;
 897         e1000_check_for_link(hw);
 898         return 0;
 899 }
 900
 901 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 902 static void
 903 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 904 {
 905         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 906         struct e1000_hw_stats *stats =
 907                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 908         int pause_frames;
 909
 910         if(hw->phy.media_type == e1000_media_type_copper ||
 911                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 912                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 913                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 914         }
 915
 916         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 917         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 918         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 919         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 920
 921         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 922         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 923         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 924         stats->dc += E1000_READ_REG(hw, E1000_DC);
 925         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 926         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 927         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 928
 929         /*
 930          * For watchdog management we need to know if we have been
 931          * paused during the last interval, so capture that here.
 932          */
 933         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 934         stats->xoffrxc += pause_frames;
 935         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 936         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 937         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 938         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 939         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 940         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 941         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 942         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 943         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 944         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 945         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 946         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 947
 948         /*
 949          * For the 64-bit byte counters the low dword must be read first.
 950          * Both registers clear on the read of the high dword.
 951          */
 952
 953         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 954         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 955         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 956         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 957
 958         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 959         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 960         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 961         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 962         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 963
 964         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 965         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 966
 967         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 968         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 969         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 970         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 971         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 972         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 973         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 974         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 975         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 976         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 977
 978         /* Interrupt Counts */
 979
 980         if (hw->mac.type >= e1000_82571) {
 981                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 982                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 983                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 984                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 985                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 986                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 987                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 988                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 989                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 990         }
 991
 992         if (hw->mac.type >= e1000_82543) {
 993                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 994                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 995                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 996                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 997                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 998                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 999         }
1000
1001         if (rte_stats == NULL)
1002                 return;
1003
1004         /* Rx Errors */
1005         rte_stats->imissed = stats->mpc;
1006         rte_stats->ierrors = stats->crcerrs +
1007                              stats->rlec + stats->ruc + stats->roc +
1008                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1009
1010         /* Tx Errors */
1011         rte_stats->oerrors = stats->ecol + stats->latecol;
1012
1013         rte_stats->ipackets = stats->gprc;
1014         rte_stats->opackets = stats->gptc;
1015         rte_stats->ibytes   = stats->gorc;
1016         rte_stats->obytes   = stats->gotc;
1017 }
1018
1019 static void
1020 eth_em_stats_reset(struct rte_eth_dev *dev)
1021 {
1022         struct e1000_hw_stats *hw_stats =
1023                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1024
1025         /* HW registers are cleared on read */
1026         eth_em_stats_get(dev, NULL);
1027
1028         /* Reset software totals */
1029         memset(hw_stats, 0, sizeof(*hw_stats));
1030 }
1031
1032 static int
1033 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1034 {
1035         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1036         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1037         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1038
1039         em_rxq_intr_enable(hw);
1040         rte_intr_enable(intr_handle);
1041
1042         return 0;
1043 }
1044
1045 static int
1046 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1047 {
1048         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1049
1050         em_rxq_intr_disable(hw);
1051
1052         return 0;
1053 }
1054
1055 static uint32_t
1056 em_get_max_pktlen(const struct e1000_hw *hw)
1057 {
1058         switch (hw->mac.type) {
1059         case e1000_82571:
1060         case e1000_82572:
1061         case e1000_ich9lan:
1062         case e1000_ich10lan:
1063         case e1000_pch2lan:
1064         case e1000_pch_lpt:
1065         case e1000_pch_spt:
1066         case e1000_pch_cnp:
1067         case e1000_82574:
1068         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1069         case e1000_82583:
1070                 return 0x2412;
1071         case e1000_pchlan:
1072                 return 0x1000;
1073         /* Adapters that do not support jumbo frames */
1074         case e1000_ich8lan:
1075                 return ETHER_MAX_LEN;
1076         default:
1077                 return MAX_JUMBO_FRAME_SIZE;
1078         }
1079 }
1080
1081 static void
1082 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1083 {
1084         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1085
1086         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1087         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1088         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1089         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1090         dev_info->rx_offload_capa =
1091                 DEV_RX_OFFLOAD_VLAN_STRIP |
1092                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1093                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1094                 DEV_RX_OFFLOAD_TCP_CKSUM;
1095         dev_info->tx_offload_capa =
1096                 DEV_TX_OFFLOAD_VLAN_INSERT |
1097                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1098                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1099                 DEV_TX_OFFLOAD_TCP_CKSUM;
1100
1101         /*
1102          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1103          * Unfortunatelly, all these nics have just one TX context.
1104          * So we have few choises for TX:
1105          * - Use just one TX queue.
1106          * - Allow cksum offload only for one TX queue.
1107          * - Don't allow TX cksum offload at all.
1108          * For now, option #1 was chosen.
1109          * To use second RX queue we have to use extended RX descriptor
1110          * (Multiple Receive Queues are mutually exclusive with UDP
1111          * fragmentation and are not supported when a legacy receive
1112          * descriptor format is used).
1113          * Which means separate RX routinies - as legacy nics (82540, 82545)
1114          * don't support extended RXD.
1115          * To avoid it we support just one RX queue for now (no RSS).
1116          */
1117
1118         dev_info->max_rx_queues = 1;
1119         dev_info->max_tx_queues = 1;
1120
1121         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1122                 .nb_max = E1000_MAX_RING_DESC,
1123                 .nb_min = E1000_MIN_RING_DESC,
1124                 .nb_align = EM_RXD_ALIGN,
1125         };
1126
1127         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1128                 .nb_max = E1000_MAX_RING_DESC,
1129                 .nb_min = E1000_MIN_RING_DESC,
1130                 .nb_align = EM_TXD_ALIGN,
1131                 .nb_seg_max = EM_TX_MAX_SEG,
1132                 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1133         };
1134
1135         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1136                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1137                         ETH_LINK_SPEED_1G;
1138 }
1139
1140 /* return 0 means link status changed, -1 means not changed */
1141 static int
1142 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1143 {
1144         struct e1000_hw *hw =
1145                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1146         struct rte_eth_link link, old;
1147         int link_check, count;
1148
1149         link_check = 0;
1150         hw->mac.get_link_status = 1;
1151
1152         /* possible wait-to-complete in up to 9 seconds */
1153         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1154                 /* Read the real link status */
1155                 switch (hw->phy.media_type) {
1156                 case e1000_media_type_copper:
1157                         /* Do the work to read phy */
1158                         e1000_check_for_link(hw);
1159                         link_check = !hw->mac.get_link_status;
1160                         break;
1161
1162                 case e1000_media_type_fiber:
1163                         e1000_check_for_link(hw);
1164                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1165                                         E1000_STATUS_LU);
1166                         break;
1167
1168                 case e1000_media_type_internal_serdes:
1169                         e1000_check_for_link(hw);
1170                         link_check = hw->mac.serdes_has_link;
1171                         break;
1172
1173                 default:
1174                         break;
1175                 }
1176                 if (link_check || wait_to_complete == 0)
1177                         break;
1178                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1179         }
1180         memset(&link, 0, sizeof(link));
1181         rte_em_dev_atomic_read_link_status(dev, &link);
1182         old = link;
1183
1184         /* Now we check if a transition has happened */
1185         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1186                 uint16_t duplex, speed;
1187                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1188                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1189                                 ETH_LINK_FULL_DUPLEX :
1190                                 ETH_LINK_HALF_DUPLEX;
1191                 link.link_speed = speed;
1192                 link.link_status = ETH_LINK_UP;
1193                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1194                                 ETH_LINK_SPEED_FIXED);
1195         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1196                 link.link_speed = 0;
1197                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1198                 link.link_status = ETH_LINK_DOWN;
1199                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1200         }
1201         rte_em_dev_atomic_write_link_status(dev, &link);
1202
1203         /* not changed */
1204         if (old.link_status == link.link_status)
1205                 return -1;
1206
1207         /* changed */
1208         return 0;
1209 }
1210
1211 /*
1212  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1213  * For ASF and Pass Through versions of f/w this means
1214  * that the driver is loaded. For AMT version type f/w
1215  * this means that the network i/f is open.
1216  */
1217 static void
1218 em_hw_control_acquire(struct e1000_hw *hw)
1219 {
1220         uint32_t ctrl_ext, swsm;
1221
1222         /* Let firmware know the driver has taken over */
1223         if (hw->mac.type == e1000_82573) {
1224                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1225                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1226
1227         } else {
1228                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1229                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1230                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1231         }
1232 }
1233
1234 /*
1235  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1236  * For ASF and Pass Through versions of f/w this means that the
1237  * driver is no longer loaded. For AMT versions of the
1238  * f/w this means that the network i/f is closed.
1239  */
1240 static void
1241 em_hw_control_release(struct e1000_hw *hw)
1242 {
1243         uint32_t ctrl_ext, swsm;
1244
1245         /* Let firmware taken over control of h/w */
1246         if (hw->mac.type == e1000_82573) {
1247                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1248                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1249         } else {
1250                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1251                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1252                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1253         }
1254 }
1255
1256 /*
1257  * Bit of a misnomer, what this really means is
1258  * to enable OS management of the system... aka
1259  * to disable special hardware management features.
1260  */
1261 static void
1262 em_init_manageability(struct e1000_hw *hw)
1263 {
1264         if (e1000_enable_mng_pass_thru(hw)) {
1265                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1266                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1267
1268                 /* disable hardware interception of ARP */
1269                 manc &= ~(E1000_MANC_ARP_EN);
1270
1271                 /* enable receiving management packets to the host */
1272                 manc |= E1000_MANC_EN_MNG2HOST;
1273                 manc2h |= 1 << 5;  /* Mng Port 623 */
1274                 manc2h |= 1 << 6;  /* Mng Port 664 */
1275                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1276                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1277         }
1278 }
1279
1280 /*
1281  * Give control back to hardware management
1282  * controller if there is one.
1283  */
1284 static void
1285 em_release_manageability(struct e1000_hw *hw)
1286 {
1287         uint32_t manc;
1288
1289         if (e1000_enable_mng_pass_thru(hw)) {
1290                 manc = E1000_READ_REG(hw, E1000_MANC);
1291
1292                 /* re-enable hardware interception of ARP */
1293                 manc |= E1000_MANC_ARP_EN;
1294                 manc &= ~E1000_MANC_EN_MNG2HOST;
1295
1296                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1297         }
1298 }
1299
1300 static void
1301 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1302 {
1303         struct e1000_hw *hw =
1304                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1305         uint32_t rctl;
1306
1307         rctl = E1000_READ_REG(hw, E1000_RCTL);
1308         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1309         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1310 }
1311
1312 static void
1313 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1314 {
1315         struct e1000_hw *hw =
1316                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1317         uint32_t rctl;
1318
1319         rctl = E1000_READ_REG(hw, E1000_RCTL);
1320         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1321         if (dev->data->all_multicast == 1)
1322                 rctl |= E1000_RCTL_MPE;
1323         else
1324                 rctl &= (~E1000_RCTL_MPE);
1325         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1326 }
1327
1328 static void
1329 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1330 {
1331         struct e1000_hw *hw =
1332                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1333         uint32_t rctl;
1334
1335         rctl = E1000_READ_REG(hw, E1000_RCTL);
1336         rctl |= E1000_RCTL_MPE;
1337         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1338 }
1339
1340 static void
1341 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1342 {
1343         struct e1000_hw *hw =
1344                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1345         uint32_t rctl;
1346
1347         if (dev->data->promiscuous == 1)
1348                 return; /* must remain in all_multicast mode */
1349         rctl = E1000_READ_REG(hw, E1000_RCTL);
1350         rctl &= (~E1000_RCTL_MPE);
1351         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1352 }
1353
1354 static int
1355 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1356 {
1357         struct e1000_hw *hw =
1358                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1359         struct e1000_vfta * shadow_vfta =
1360                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1361         uint32_t vfta;
1362         uint32_t vid_idx;
1363         uint32_t vid_bit;
1364
1365         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1366                               E1000_VFTA_ENTRY_MASK);
1367         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1368         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1369         if (on)
1370                 vfta |= vid_bit;
1371         else
1372                 vfta &= ~vid_bit;
1373         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1374
1375         /* update local VFTA copy */
1376         shadow_vfta->vfta[vid_idx] = vfta;
1377
1378         return 0;
1379 }
1380
1381 static void
1382 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1383 {
1384         struct e1000_hw *hw =
1385                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1386         uint32_t reg;
1387
1388         /* Filter Table Disable */
1389         reg = E1000_READ_REG(hw, E1000_RCTL);
1390         reg &= ~E1000_RCTL_CFIEN;
1391         reg &= ~E1000_RCTL_VFE;
1392         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1393 }
1394
1395 static void
1396 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1397 {
1398         struct e1000_hw *hw =
1399                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1400         struct e1000_vfta * shadow_vfta =
1401                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1402         uint32_t reg;
1403         int i;
1404
1405         /* Filter Table Enable, CFI not used for packet acceptance */
1406         reg = E1000_READ_REG(hw, E1000_RCTL);
1407         reg &= ~E1000_RCTL_CFIEN;
1408         reg |= E1000_RCTL_VFE;
1409         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1410
1411         /* restore vfta from local copy */
1412         for (i = 0; i < IGB_VFTA_SIZE; i++)
1413                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1414 }
1415
1416 static void
1417 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1418 {
1419         struct e1000_hw *hw =
1420                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1421         uint32_t reg;
1422
1423         /* VLAN Mode Disable */
1424         reg = E1000_READ_REG(hw, E1000_CTRL);
1425         reg &= ~E1000_CTRL_VME;
1426         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1427
1428 }
1429
1430 static void
1431 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1432 {
1433         struct e1000_hw *hw =
1434                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1435         uint32_t reg;
1436
1437         /* VLAN Mode Enable */
1438         reg = E1000_READ_REG(hw, E1000_CTRL);
1439         reg |= E1000_CTRL_VME;
1440         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1441 }
1442
1443 static void
1444 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1445 {
1446         if(mask & ETH_VLAN_STRIP_MASK){
1447                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1448                         em_vlan_hw_strip_enable(dev);
1449                 else
1450                         em_vlan_hw_strip_disable(dev);
1451         }
1452
1453         if(mask & ETH_VLAN_FILTER_MASK){
1454                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1455                         em_vlan_hw_filter_enable(dev);
1456                 else
1457                         em_vlan_hw_filter_disable(dev);
1458         }
1459 }
1460
1461 /*
1462  * It enables the interrupt mask and then enable the interrupt.
1463  *
1464  * @param dev
1465  *  Pointer to struct rte_eth_dev.
1466  *
1467  * @return
1468  *  - On success, zero.
1469  *  - On failure, a negative value.
1470  */
1471 static int
1472 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1473 {
1474         uint32_t regval;
1475         struct e1000_hw *hw =
1476                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1477
1478         /* clear interrupt */
1479         E1000_READ_REG(hw, E1000_ICR);
1480         regval = E1000_READ_REG(hw, E1000_IMS);
1481         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1482         return 0;
1483 }
1484
1485 /*
1486  * It clears the interrupt causes and enables the interrupt.
1487  * It will be called once only during nic initialized.
1488  *
1489  * @param dev
1490  *  Pointer to struct rte_eth_dev.
1491  *
1492  * @return
1493  *  - On success, zero.
1494  *  - On failure, a negative value.
1495  */
1496 static int
1497 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1498 {
1499         struct e1000_hw *hw =
1500         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1501
1502         E1000_READ_REG(hw, E1000_ICR);
1503         em_rxq_intr_enable(hw);
1504         return 0;
1505 }
1506
1507 /*
1508  * It enable receive packet interrupt.
1509  * @param hw
1510  * Pointer to struct e1000_hw
1511  *
1512  * @return
1513  */
1514 static void
1515 em_rxq_intr_enable(struct e1000_hw *hw)
1516 {
1517         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1518         E1000_WRITE_FLUSH(hw);
1519 }
1520
1521 /*
1522  * It disabled lsc interrupt.
1523  * @param hw
1524  * Pointer to struct e1000_hw
1525  *
1526  * @return
1527  */
1528 static void
1529 em_lsc_intr_disable(struct e1000_hw *hw)
1530 {
1531         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1532         E1000_WRITE_FLUSH(hw);
1533 }
1534
1535 /*
1536  * It disabled receive packet interrupt.
1537  * @param hw
1538  * Pointer to struct e1000_hw
1539  *
1540  * @return
1541  */
1542 static void
1543 em_rxq_intr_disable(struct e1000_hw *hw)
1544 {
1545         E1000_READ_REG(hw, E1000_ICR);
1546         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1547         E1000_WRITE_FLUSH(hw);
1548 }
1549
1550 /*
1551  * It reads ICR and gets interrupt causes, check it and set a bit flag
1552  * to update link status.
1553  *
1554  * @param dev
1555  *  Pointer to struct rte_eth_dev.
1556  *
1557  * @return
1558  *  - On success, zero.
1559  *  - On failure, a negative value.
1560  */
1561 static int
1562 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1563 {
1564         uint32_t icr;
1565         struct e1000_hw *hw =
1566                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1567         struct e1000_interrupt *intr =
1568                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1569
1570         /* read-on-clear nic registers here */
1571         icr = E1000_READ_REG(hw, E1000_ICR);
1572         if (icr & E1000_ICR_LSC) {
1573                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1574         }
1575
1576         return 0;
1577 }
1578
1579 /*
1580  * It executes link_update after knowing an interrupt is prsent.
1581  *
1582  * @param dev
1583  *  Pointer to struct rte_eth_dev.
1584  *
1585  * @return
1586  *  - On success, zero.
1587  *  - On failure, a negative value.
1588  */
1589 static int
1590 eth_em_interrupt_action(struct rte_eth_dev *dev,
1591                         struct rte_intr_handle *intr_handle)
1592 {
1593         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1594         struct e1000_hw *hw =
1595                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1596         struct e1000_interrupt *intr =
1597                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1598         uint32_t tctl, rctl;
1599         struct rte_eth_link link;
1600         int ret;
1601
1602         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1603                 return -1;
1604
1605         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1606         rte_intr_enable(intr_handle);
1607
1608         /* set get_link_status to check register later */
1609         hw->mac.get_link_status = 1;
1610         ret = eth_em_link_update(dev, 0);
1611
1612         /* check if link has changed */
1613         if (ret < 0)
1614                 return 0;
1615
1616         memset(&link, 0, sizeof(link));
1617         rte_em_dev_atomic_read_link_status(dev, &link);
1618         if (link.link_status) {
1619                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1620                              dev->data->port_id, (unsigned)link.link_speed,
1621                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1622                              "full-duplex" : "half-duplex");
1623         } else {
1624                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1625         }
1626         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1627                      pci_dev->addr.domain, pci_dev->addr.bus,
1628                      pci_dev->addr.devid, pci_dev->addr.function);
1629
1630         tctl = E1000_READ_REG(hw, E1000_TCTL);
1631         rctl = E1000_READ_REG(hw, E1000_RCTL);
1632         if (link.link_status) {
1633                 /* enable Tx/Rx */
1634                 tctl |= E1000_TCTL_EN;
1635                 rctl |= E1000_RCTL_EN;
1636         } else {
1637                 /* disable Tx/Rx */
1638                 tctl &= ~E1000_TCTL_EN;
1639                 rctl &= ~E1000_RCTL_EN;
1640         }
1641         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1642         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1643         E1000_WRITE_FLUSH(hw);
1644
1645         return 0;
1646 }
1647
1648 /**
1649  * Interrupt handler which shall be registered at first.
1650  *
1651  * @param handle
1652  *  Pointer to interrupt handle.
1653  * @param param
1654  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1655  *
1656  * @return
1657  *  void
1658  */
1659 static void
1660 eth_em_interrupt_handler(void *param)
1661 {
1662         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1663
1664         eth_em_interrupt_get_status(dev);
1665         eth_em_interrupt_action(dev, dev->intr_handle);
1666         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1667 }
1668
1669 static int
1670 eth_em_led_on(struct rte_eth_dev *dev)
1671 {
1672         struct e1000_hw *hw;
1673
1674         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1675         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1676 }
1677
1678 static int
1679 eth_em_led_off(struct rte_eth_dev *dev)
1680 {
1681         struct e1000_hw *hw;
1682
1683         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1684         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1685 }
1686
1687 static int
1688 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1689 {
1690         struct e1000_hw *hw;
1691         uint32_t ctrl;
1692         int tx_pause;
1693         int rx_pause;
1694
1695         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1696         fc_conf->pause_time = hw->fc.pause_time;
1697         fc_conf->high_water = hw->fc.high_water;
1698         fc_conf->low_water = hw->fc.low_water;
1699         fc_conf->send_xon = hw->fc.send_xon;
1700         fc_conf->autoneg = hw->mac.autoneg;
1701
1702         /*
1703          * Return rx_pause and tx_pause status according to actual setting of
1704          * the TFCE and RFCE bits in the CTRL register.
1705          */
1706         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1707         if (ctrl & E1000_CTRL_TFCE)
1708                 tx_pause = 1;
1709         else
1710                 tx_pause = 0;
1711
1712         if (ctrl & E1000_CTRL_RFCE)
1713                 rx_pause = 1;
1714         else
1715                 rx_pause = 0;
1716
1717         if (rx_pause && tx_pause)
1718                 fc_conf->mode = RTE_FC_FULL;
1719         else if (rx_pause)
1720                 fc_conf->mode = RTE_FC_RX_PAUSE;
1721         else if (tx_pause)
1722                 fc_conf->mode = RTE_FC_TX_PAUSE;
1723         else
1724                 fc_conf->mode = RTE_FC_NONE;
1725
1726         return 0;
1727 }
1728
1729 static int
1730 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1731 {
1732         struct e1000_hw *hw;
1733         int err;
1734         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1735                 e1000_fc_none,
1736                 e1000_fc_rx_pause,
1737                 e1000_fc_tx_pause,
1738                 e1000_fc_full
1739         };
1740         uint32_t rx_buf_size;
1741         uint32_t max_high_water;
1742         uint32_t rctl;
1743
1744         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1745         if (fc_conf->autoneg != hw->mac.autoneg)
1746                 return -ENOTSUP;
1747         rx_buf_size = em_get_rx_buffer_size(hw);
1748         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1749
1750         /* At least reserve one Ethernet frame for watermark */
1751         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1752         if ((fc_conf->high_water > max_high_water) ||
1753             (fc_conf->high_water < fc_conf->low_water)) {
1754                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1755                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1756                 return -EINVAL;
1757         }
1758
1759         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1760         hw->fc.pause_time     = fc_conf->pause_time;
1761         hw->fc.high_water     = fc_conf->high_water;
1762         hw->fc.low_water      = fc_conf->low_water;
1763         hw->fc.send_xon       = fc_conf->send_xon;
1764
1765         err = e1000_setup_link_generic(hw);
1766         if (err == E1000_SUCCESS) {
1767
1768                 /* check if we want to forward MAC frames - driver doesn't have native
1769                  * capability to do that, so we'll write the registers ourselves */
1770
1771                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1772
1773                 /* set or clear MFLCN.PMCF bit depending on configuration */
1774                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1775                         rctl |= E1000_RCTL_PMCF;
1776                 else
1777                         rctl &= ~E1000_RCTL_PMCF;
1778
1779                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1780                 E1000_WRITE_FLUSH(hw);
1781
1782                 return 0;
1783         }
1784
1785         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1786         return -EIO;
1787 }
1788
1789 static void
1790 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1791                 uint32_t index, __rte_unused uint32_t pool)
1792 {
1793         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1794
1795         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1796 }
1797
1798 static void
1799 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1800 {
1801         uint8_t addr[ETHER_ADDR_LEN];
1802         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1803
1804         memset(addr, 0, sizeof(addr));
1805
1806         e1000_rar_set(hw, addr, index);
1807 }
1808
1809 static int
1810 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1811 {
1812         struct rte_eth_dev_info dev_info;
1813         struct e1000_hw *hw;
1814         uint32_t frame_size;
1815         uint32_t rctl;
1816
1817         eth_em_infos_get(dev, &dev_info);
1818         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1819
1820         /* check that mtu is within the allowed range */
1821         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1822                 return -EINVAL;
1823
1824         /* refuse mtu that requires the support of scattered packets when this
1825          * feature has not been enabled before. */
1826         if (!dev->data->scattered_rx &&
1827             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1828                 return -EINVAL;
1829
1830         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1831         rctl = E1000_READ_REG(hw, E1000_RCTL);
1832
1833         /* switch to jumbo mode if needed */
1834         if (frame_size > ETHER_MAX_LEN) {
1835                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1836                 rctl |= E1000_RCTL_LPE;
1837         } else {
1838                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1839                 rctl &= ~E1000_RCTL_LPE;
1840         }
1841         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1842
1843         /* update max frame size */
1844         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1845         return 0;
1846 }
1847
1848 static int
1849 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1850                         struct ether_addr *mc_addr_set,
1851                         uint32_t nb_mc_addr)
1852 {
1853         struct e1000_hw *hw;
1854
1855         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1856         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1857         return 0;
1858 }
1859
1860 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd.pci_drv);
1861 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1862 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio");