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34 #include <sys/queue.h>
44 #include <rte_interrupts.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
48 #include <rte_debug.h>
50 #include <rte_memory.h>
51 #include <rte_memcpy.h>
52 #include <rte_memzone.h>
53 #include <rte_launch.h>
55 #include <rte_per_lcore.h>
56 #include <rte_lcore.h>
57 #include <rte_atomic.h>
58 #include <rte_branch_prediction.h>
60 #include <rte_mempool.h>
61 #include <rte_malloc.h>
63 #include <rte_ether.h>
64 #include <rte_ethdev.h>
65 #include <rte_prefetch.h>
70 #include <rte_string_fns.h>
72 #include "e1000_logs.h"
73 #include "base/e1000_api.h"
74 #include "e1000_ethdev.h"
75 #include "base/e1000_osdep.h"
77 #define E1000_TXD_VLAN_SHIFT 16
79 #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
81 static inline struct rte_mbuf *
82 rte_rxmbuf_alloc(struct rte_mempool *mp)
86 m = __rte_mbuf_raw_alloc(mp);
87 __rte_mbuf_sanity_check_raw(m, 0);
92 * Structure associated with each descriptor of the RX ring of a RX queue.
95 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
99 * Structure associated with each descriptor of the TX ring of a TX queue.
102 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
103 uint16_t next_id; /**< Index of next descriptor in ring. */
104 uint16_t last_id; /**< Index of last scattered descriptor. */
108 * Structure associated with each RX queue.
111 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
112 volatile struct e1000_rx_desc *rx_ring; /**< RX ring virtual address. */
113 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
114 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
115 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
116 struct em_rx_entry *sw_ring; /**< address of RX software ring. */
117 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
118 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
119 uint16_t nb_rx_desc; /**< number of RX descriptors. */
120 uint16_t rx_tail; /**< current value of RDT register. */
121 uint16_t nb_rx_hold; /**< number of held free RX desc. */
122 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
123 uint16_t queue_id; /**< RX queue index. */
124 uint8_t port_id; /**< Device port identifier. */
125 uint8_t pthresh; /**< Prefetch threshold register. */
126 uint8_t hthresh; /**< Host threshold register. */
127 uint8_t wthresh; /**< Write-back threshold register. */
128 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
132 * Hardware context number
135 EM_CTX_0 = 0, /**< CTX0 */
136 EM_CTX_NUM = 1, /**< CTX NUM */
139 /** Offload features */
140 union em_vlan_macip {
143 uint16_t l3_len:9; /**< L3 (IP) Header Length. */
144 uint16_t l2_len:7; /**< L2 (MAC) Header Length. */
146 /**< VLAN Tag Control Identifier (CPU order). */
151 * Compare mask for vlan_macip_len.data,
152 * should be in sync with em_vlan_macip.f layout.
154 #define TX_VLAN_CMP_MASK 0xFFFF0000 /**< VLAN length - 16-bits. */
155 #define TX_MAC_LEN_CMP_MASK 0x0000FE00 /**< MAC length - 7-bits. */
156 #define TX_IP_LEN_CMP_MASK 0x000001FF /**< IP length - 9-bits. */
157 /** MAC+IP length. */
158 #define TX_MACIP_LEN_CMP_MASK (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK)
161 * Structure to check if new context need be built
164 uint64_t flags; /**< ol_flags related to context build. */
165 uint32_t cmp_mask; /**< compare mask */
166 union em_vlan_macip hdrlen; /**< L2 and L3 header lenghts */
170 * Structure associated with each TX queue.
173 volatile struct e1000_data_desc *tx_ring; /**< TX ring address */
174 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
175 struct em_tx_entry *sw_ring; /**< virtual address of SW ring. */
176 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
177 uint16_t nb_tx_desc; /**< number of TX descriptors. */
178 uint16_t tx_tail; /**< Current value of TDT register. */
179 /**< Start freeing TX buffers if there are less free descriptors than
181 uint16_t tx_free_thresh;
182 /**< Number of TX descriptors to use before RS bit is set. */
183 uint16_t tx_rs_thresh;
184 /** Number of TX descriptors used since RS bit was set. */
186 /** Index to last TX descriptor to have been cleaned. */
187 uint16_t last_desc_cleaned;
188 /** Total number of TX descriptors ready to be allocated. */
190 uint16_t queue_id; /**< TX queue index. */
191 uint8_t port_id; /**< Device port identifier. */
192 uint8_t pthresh; /**< Prefetch threshold register. */
193 uint8_t hthresh; /**< Host threshold register. */
194 uint8_t wthresh; /**< Write-back threshold register. */
195 struct em_ctx_info ctx_cache;
196 /**< Hardware context history.*/
200 #define RTE_PMD_USE_PREFETCH
203 #ifdef RTE_PMD_USE_PREFETCH
204 #define rte_em_prefetch(p) rte_prefetch0(p)
206 #define rte_em_prefetch(p) do {} while(0)
209 #ifdef RTE_PMD_PACKET_PREFETCH
210 #define rte_packet_prefetch(p) rte_prefetch1(p)
212 #define rte_packet_prefetch(p) do {} while(0)
215 #ifndef DEFAULT_TX_FREE_THRESH
216 #define DEFAULT_TX_FREE_THRESH 32
217 #endif /* DEFAULT_TX_FREE_THRESH */
219 #ifndef DEFAULT_TX_RS_THRESH
220 #define DEFAULT_TX_RS_THRESH 32
221 #endif /* DEFAULT_TX_RS_THRESH */
224 /*********************************************************************
228 **********************************************************************/
231 * Populates TX context descriptor.
234 em_set_xmit_ctx(struct em_tx_queue* txq,
235 volatile struct e1000_context_desc *ctx_txd,
237 union em_vlan_macip hdrlen)
239 uint32_t cmp_mask, cmd_len;
240 uint16_t ipcse, l2len;
241 struct e1000_context_desc ctx;
244 cmd_len = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C;
246 l2len = hdrlen.f.l2_len;
247 ipcse = (uint16_t)(l2len + hdrlen.f.l3_len);
249 /* setup IPCS* fields */
250 ctx.lower_setup.ip_fields.ipcss = (uint8_t)l2len;
251 ctx.lower_setup.ip_fields.ipcso = (uint8_t)(l2len +
252 offsetof(struct ipv4_hdr, hdr_checksum));
255 * When doing checksum or TCP segmentation with IPv6 headers,
256 * IPCSE field should be set t0 0.
258 if (flags & PKT_TX_IP_CKSUM) {
259 ctx.lower_setup.ip_fields.ipcse =
260 (uint16_t)rte_cpu_to_le_16(ipcse - 1);
261 cmd_len |= E1000_TXD_CMD_IP;
262 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
264 ctx.lower_setup.ip_fields.ipcse = 0;
267 /* setup TUCS* fields */
268 ctx.upper_setup.tcp_fields.tucss = (uint8_t)ipcse;
269 ctx.upper_setup.tcp_fields.tucse = 0;
271 switch (flags & PKT_TX_L4_MASK) {
272 case PKT_TX_UDP_CKSUM:
273 ctx.upper_setup.tcp_fields.tucso = (uint8_t)(ipcse +
274 offsetof(struct udp_hdr, dgram_cksum));
275 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
277 case PKT_TX_TCP_CKSUM:
278 ctx.upper_setup.tcp_fields.tucso = (uint8_t)(ipcse +
279 offsetof(struct tcp_hdr, cksum));
280 cmd_len |= E1000_TXD_CMD_TCP;
281 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
284 ctx.upper_setup.tcp_fields.tucso = 0;
287 ctx.cmd_and_length = rte_cpu_to_le_32(cmd_len);
288 ctx.tcp_seg_setup.data = 0;
292 txq->ctx_cache.flags = flags;
293 txq->ctx_cache.cmp_mask = cmp_mask;
294 txq->ctx_cache.hdrlen = hdrlen;
298 * Check which hardware context can be used. Use the existing match
299 * or create a new context descriptor.
301 static inline uint32_t
302 what_ctx_update(struct em_tx_queue *txq, uint64_t flags,
303 union em_vlan_macip hdrlen)
305 /* If match with the current context */
306 if (likely (txq->ctx_cache.flags == flags &&
307 ((txq->ctx_cache.hdrlen.data ^ hdrlen.data) &
308 txq->ctx_cache.cmp_mask) == 0))
315 /* Reset transmit descriptors after they have been used */
317 em_xmit_cleanup(struct em_tx_queue *txq)
319 struct em_tx_entry *sw_ring = txq->sw_ring;
320 volatile struct e1000_data_desc *txr = txq->tx_ring;
321 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
322 uint16_t nb_tx_desc = txq->nb_tx_desc;
323 uint16_t desc_to_clean_to;
324 uint16_t nb_tx_to_clean;
326 /* Determine the last descriptor needing to be cleaned */
327 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
328 if (desc_to_clean_to >= nb_tx_desc)
329 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
331 /* Check to make sure the last descriptor to clean is done */
332 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
333 if (! (txr[desc_to_clean_to].upper.fields.status & E1000_TXD_STAT_DD))
335 PMD_TX_FREE_LOG(DEBUG,
336 "TX descriptor %4u is not done"
337 "(port=%d queue=%d)", desc_to_clean_to,
338 txq->port_id, txq->queue_id);
339 /* Failed to clean any descriptors, better luck next time */
343 /* Figure out how many descriptors will be cleaned */
344 if (last_desc_cleaned > desc_to_clean_to)
345 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
348 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
351 PMD_TX_FREE_LOG(DEBUG,
352 "Cleaning %4u TX descriptors: %4u to %4u "
353 "(port=%d queue=%d)", nb_tx_to_clean,
354 last_desc_cleaned, desc_to_clean_to, txq->port_id,
358 * The last descriptor to clean is done, so that means all the
359 * descriptors from the last descriptor that was cleaned
360 * up to the last descriptor with the RS bit set
361 * are done. Only reset the threshold descriptor.
363 txr[desc_to_clean_to].upper.fields.status = 0;
365 /* Update the txq to reflect the last descriptor that was cleaned */
366 txq->last_desc_cleaned = desc_to_clean_to;
367 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
373 static inline uint32_t
374 tx_desc_cksum_flags_to_upper(uint64_t ol_flags)
376 static const uint32_t l4_olinfo[2] = {0, E1000_TXD_POPTS_TXSM << 8};
377 static const uint32_t l3_olinfo[2] = {0, E1000_TXD_POPTS_IXSM << 8};
380 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
381 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
386 eth_em_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
389 struct em_tx_queue *txq;
390 struct em_tx_entry *sw_ring;
391 struct em_tx_entry *txe, *txn;
392 volatile struct e1000_data_desc *txr;
393 volatile struct e1000_data_desc *txd;
394 struct rte_mbuf *tx_pkt;
395 struct rte_mbuf *m_seg;
396 uint64_t buf_dma_addr;
398 uint32_t cmd_type_len;
408 union em_vlan_macip hdrlen;
411 sw_ring = txq->sw_ring;
413 tx_id = txq->tx_tail;
414 txe = &sw_ring[tx_id];
416 /* Determine if the descriptor ring needs to be cleaned. */
417 if (txq->nb_tx_free < txq->tx_free_thresh)
418 em_xmit_cleanup(txq);
421 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
425 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
428 * Determine how many (if any) context descriptors
429 * are needed for offload functionality.
431 ol_flags = tx_pkt->ol_flags;
433 /* If hardware offload required */
434 tx_ol_req = (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK));
436 hdrlen.f.vlan_tci = tx_pkt->vlan_tci;
437 hdrlen.f.l2_len = tx_pkt->l2_len;
438 hdrlen.f.l3_len = tx_pkt->l3_len;
439 /* If new context to be built or reuse the exist ctx. */
440 ctx = what_ctx_update(txq, tx_ol_req, hdrlen);
442 /* Only allocate context descriptor if required*/
443 new_ctx = (ctx == EM_CTX_NUM);
447 * Keep track of how many descriptors are used this loop
448 * This will always be the number of segments + the number of
449 * Context descriptors required to transmit the packet
451 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
454 * The number of descriptors that must be allocated for a
455 * packet is the number of segments of that packet, plus 1
456 * Context Descriptor for the hardware offload, if any.
457 * Determine the last TX descriptor to allocate in the TX ring
458 * for the packet, starting from the current position (tx_id)
461 tx_last = (uint16_t) (tx_id + nb_used - 1);
464 if (tx_last >= txq->nb_tx_desc)
465 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
467 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
468 " tx_first=%u tx_last=%u",
469 (unsigned) txq->port_id,
470 (unsigned) txq->queue_id,
471 (unsigned) tx_pkt->pkt_len,
476 * Make sure there are enough TX descriptors available to
477 * transmit the entire packet.
478 * nb_used better be less than or equal to txq->tx_rs_thresh
480 while (unlikely (nb_used > txq->nb_tx_free)) {
481 PMD_TX_FREE_LOG(DEBUG, "Not enough free TX descriptors "
482 "nb_used=%4u nb_free=%4u "
483 "(port=%d queue=%d)",
484 nb_used, txq->nb_tx_free,
485 txq->port_id, txq->queue_id);
487 if (em_xmit_cleanup(txq) != 0) {
488 /* Could not clean any descriptors */
496 * By now there are enough free TX descriptors to transmit
501 * Set common flags of all TX Data Descriptors.
503 * The following bits must be set in all Data Descriptors:
504 * - E1000_TXD_DTYP_DATA
505 * - E1000_TXD_DTYP_DEXT
507 * The following bits must be set in the first Data Descriptor
508 * and are ignored in the other ones:
509 * - E1000_TXD_POPTS_IXSM
510 * - E1000_TXD_POPTS_TXSM
512 * The following bits must be set in the last Data Descriptor
513 * and are ignored in the other ones:
514 * - E1000_TXD_CMD_VLE
515 * - E1000_TXD_CMD_IFCS
517 * The following bits must only be set in the last Data
519 * - E1000_TXD_CMD_EOP
521 * The following bits can be set in any Data Descriptor, but
522 * are only set in the last Data Descriptor:
525 cmd_type_len = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
529 /* Set VLAN Tag offload fields. */
530 if (ol_flags & PKT_TX_VLAN_PKT) {
531 cmd_type_len |= E1000_TXD_CMD_VLE;
532 popts_spec = tx_pkt->vlan_tci << E1000_TXD_VLAN_SHIFT;
537 * Setup the TX Context Descriptor if required
540 volatile struct e1000_context_desc *ctx_txd;
542 ctx_txd = (volatile struct e1000_context_desc *)
545 txn = &sw_ring[txe->next_id];
546 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
548 if (txe->mbuf != NULL) {
549 rte_pktmbuf_free_seg(txe->mbuf);
553 em_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
556 txe->last_id = tx_last;
557 tx_id = txe->next_id;
562 * Setup the TX Data Descriptor,
563 * This path will go through
564 * whatever new/reuse the context descriptor
566 popts_spec |= tx_desc_cksum_flags_to_upper(ol_flags);
572 txn = &sw_ring[txe->next_id];
574 if (txe->mbuf != NULL)
575 rte_pktmbuf_free_seg(txe->mbuf);
579 * Set up Transmit Data Descriptor.
581 slen = m_seg->data_len;
582 buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
584 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
585 txd->lower.data = rte_cpu_to_le_32(cmd_type_len | slen);
586 txd->upper.data = rte_cpu_to_le_32(popts_spec);
588 txe->last_id = tx_last;
589 tx_id = txe->next_id;
592 } while (m_seg != NULL);
595 * The last packet data descriptor needs End Of Packet (EOP)
597 cmd_type_len |= E1000_TXD_CMD_EOP;
598 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
599 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
601 /* Set RS bit only on threshold packets' last descriptor */
602 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
603 PMD_TX_FREE_LOG(DEBUG,
604 "Setting RS bit on TXD id=%4u "
605 "(port=%d queue=%d)",
606 tx_last, txq->port_id, txq->queue_id);
608 cmd_type_len |= E1000_TXD_CMD_RS;
610 /* Update txq RS bit counters */
613 txd->lower.data |= rte_cpu_to_le_32(cmd_type_len);
619 * Set the Transmit Descriptor Tail (TDT)
621 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
622 (unsigned) txq->port_id, (unsigned) txq->queue_id,
623 (unsigned) tx_id, (unsigned) nb_tx);
624 E1000_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
625 txq->tx_tail = tx_id;
630 /*********************************************************************
634 **********************************************************************/
636 static inline uint64_t
637 rx_desc_status_to_pkt_flags(uint32_t rx_status)
641 /* Check if VLAN present */
642 pkt_flags = ((rx_status & E1000_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0);
647 static inline uint64_t
648 rx_desc_error_to_pkt_flags(uint32_t rx_error)
650 uint64_t pkt_flags = 0;
652 if (rx_error & E1000_RXD_ERR_IPE)
653 pkt_flags |= PKT_RX_IP_CKSUM_BAD;
654 if (rx_error & E1000_RXD_ERR_TCPE)
655 pkt_flags |= PKT_RX_L4_CKSUM_BAD;
660 eth_em_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
663 volatile struct e1000_rx_desc *rx_ring;
664 volatile struct e1000_rx_desc *rxdp;
665 struct em_rx_queue *rxq;
666 struct em_rx_entry *sw_ring;
667 struct em_rx_entry *rxe;
668 struct rte_mbuf *rxm;
669 struct rte_mbuf *nmb;
670 struct e1000_rx_desc rxd;
682 rx_id = rxq->rx_tail;
683 rx_ring = rxq->rx_ring;
684 sw_ring = rxq->sw_ring;
685 while (nb_rx < nb_pkts) {
687 * The order of operations here is important as the DD status
688 * bit must not be read after any other descriptor fields.
689 * rx_ring and rxdp are pointing to volatile data so the order
690 * of accesses cannot be reordered by the compiler. If they were
691 * not volatile, they could be reordered which could lead to
692 * using invalid descriptor fields when read from rxd.
694 rxdp = &rx_ring[rx_id];
695 status = rxdp->status;
696 if (! (status & E1000_RXD_STAT_DD))
703 * If the E1000_RXD_STAT_EOP flag is not set, the RX packet is
704 * likely to be invalid and to be dropped by the various
705 * validation checks performed by the network stack.
707 * Allocate a new mbuf to replenish the RX ring descriptor.
708 * If the allocation fails:
709 * - arrange for that RX descriptor to be the first one
710 * being parsed the next time the receive function is
711 * invoked [on the same queue].
713 * - Stop parsing the RX ring and return immediately.
715 * This policy do not drop the packet received in the RX
716 * descriptor for which the allocation of a new mbuf failed.
717 * Thus, it allows that packet to be later retrieved if
718 * mbuf have been freed in the mean time.
719 * As a side effect, holding RX descriptors instead of
720 * systematically giving them back to the NIC may lead to
721 * RX ring exhaustion situations.
722 * However, the NIC can gracefully prevent such situations
723 * to happen by sending specific "back-pressure" flow control
724 * frames to its peer(s).
726 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
727 "status=0x%x pkt_len=%u",
728 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
729 (unsigned) rx_id, (unsigned) status,
730 (unsigned) rte_le_to_cpu_16(rxd.length));
732 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
734 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
736 (unsigned) rxq->port_id,
737 (unsigned) rxq->queue_id);
738 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
743 rxe = &sw_ring[rx_id];
745 if (rx_id == rxq->nb_rx_desc)
748 /* Prefetch next mbuf while processing current one. */
749 rte_em_prefetch(sw_ring[rx_id].mbuf);
752 * When next RX descriptor is on a cache-line boundary,
753 * prefetch the next 4 RX descriptors and the next 8 pointers
756 if ((rx_id & 0x3) == 0) {
757 rte_em_prefetch(&rx_ring[rx_id]);
758 rte_em_prefetch(&sw_ring[rx_id]);
761 /* Rearm RXD: attach new mbuf and reset status to zero. */
766 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
767 rxdp->buffer_addr = dma_addr;
771 * Initialize the returned mbuf.
772 * 1) setup generic mbuf fields:
773 * - number of segments,
776 * - RX port identifier.
777 * 2) integrate hardware offload data, if any:
779 * - IP checksum flag,
780 * - VLAN TCI, if any,
783 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.length) -
785 rxm->data_off = RTE_PKTMBUF_HEADROOM;
786 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
789 rxm->pkt_len = pkt_len;
790 rxm->data_len = pkt_len;
791 rxm->port = rxq->port_id;
793 rxm->ol_flags = rx_desc_status_to_pkt_flags(status);
794 rxm->ol_flags = rxm->ol_flags |
795 rx_desc_error_to_pkt_flags(rxd.errors);
797 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
798 rxm->vlan_tci = rte_le_to_cpu_16(rxd.special);
801 * Store the mbuf address into the next entry of the array
802 * of returned packets.
804 rx_pkts[nb_rx++] = rxm;
806 rxq->rx_tail = rx_id;
809 * If the number of free RX descriptors is greater than the RX free
810 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
812 * Update the RDT with the value of the last processed RX descriptor
813 * minus 1, to guarantee that the RDT register is never equal to the
814 * RDH register, which creates a "full" ring situtation from the
815 * hardware point of view...
817 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
818 if (nb_hold > rxq->rx_free_thresh) {
819 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
820 "nb_hold=%u nb_rx=%u",
821 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
822 (unsigned) rx_id, (unsigned) nb_hold,
824 rx_id = (uint16_t) ((rx_id == 0) ?
825 (rxq->nb_rx_desc - 1) : (rx_id - 1));
826 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
829 rxq->nb_rx_hold = nb_hold;
834 eth_em_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
837 struct em_rx_queue *rxq;
838 volatile struct e1000_rx_desc *rx_ring;
839 volatile struct e1000_rx_desc *rxdp;
840 struct em_rx_entry *sw_ring;
841 struct em_rx_entry *rxe;
842 struct rte_mbuf *first_seg;
843 struct rte_mbuf *last_seg;
844 struct rte_mbuf *rxm;
845 struct rte_mbuf *nmb;
846 struct e1000_rx_desc rxd;
847 uint64_t dma; /* Physical address of mbuf data buffer */
858 rx_id = rxq->rx_tail;
859 rx_ring = rxq->rx_ring;
860 sw_ring = rxq->sw_ring;
863 * Retrieve RX context of current packet, if any.
865 first_seg = rxq->pkt_first_seg;
866 last_seg = rxq->pkt_last_seg;
868 while (nb_rx < nb_pkts) {
871 * The order of operations here is important as the DD status
872 * bit must not be read after any other descriptor fields.
873 * rx_ring and rxdp are pointing to volatile data so the order
874 * of accesses cannot be reordered by the compiler. If they were
875 * not volatile, they could be reordered which could lead to
876 * using invalid descriptor fields when read from rxd.
878 rxdp = &rx_ring[rx_id];
879 status = rxdp->status;
880 if (! (status & E1000_RXD_STAT_DD))
887 * Allocate a new mbuf to replenish the RX ring descriptor.
888 * If the allocation fails:
889 * - arrange for that RX descriptor to be the first one
890 * being parsed the next time the receive function is
891 * invoked [on the same queue].
893 * - Stop parsing the RX ring and return immediately.
895 * This policy does not drop the packet received in the RX
896 * descriptor for which the allocation of a new mbuf failed.
897 * Thus, it allows that packet to be later retrieved if
898 * mbuf have been freed in the mean time.
899 * As a side effect, holding RX descriptors instead of
900 * systematically giving them back to the NIC may lead to
901 * RX ring exhaustion situations.
902 * However, the NIC can gracefully prevent such situations
903 * to happen by sending specific "back-pressure" flow control
904 * frames to its peer(s).
906 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
907 "status=0x%x data_len=%u",
908 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
909 (unsigned) rx_id, (unsigned) status,
910 (unsigned) rte_le_to_cpu_16(rxd.length));
912 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
914 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
915 "queue_id=%u", (unsigned) rxq->port_id,
916 (unsigned) rxq->queue_id);
917 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
922 rxe = &sw_ring[rx_id];
924 if (rx_id == rxq->nb_rx_desc)
927 /* Prefetch next mbuf while processing current one. */
928 rte_em_prefetch(sw_ring[rx_id].mbuf);
931 * When next RX descriptor is on a cache-line boundary,
932 * prefetch the next 4 RX descriptors and the next 8 pointers
935 if ((rx_id & 0x3) == 0) {
936 rte_em_prefetch(&rx_ring[rx_id]);
937 rte_em_prefetch(&sw_ring[rx_id]);
941 * Update RX descriptor with the physical address of the new
942 * data buffer of the new allocated mbuf.
946 dma = rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
947 rxdp->buffer_addr = dma;
951 * Set data length & data buffer address of mbuf.
953 data_len = rte_le_to_cpu_16(rxd.length);
954 rxm->data_len = data_len;
955 rxm->data_off = RTE_PKTMBUF_HEADROOM;
958 * If this is the first buffer of the received packet,
959 * set the pointer to the first mbuf of the packet and
960 * initialize its context.
961 * Otherwise, update the total length and the number of segments
962 * of the current scattered packet, and update the pointer to
963 * the last mbuf of the current packet.
965 if (first_seg == NULL) {
967 first_seg->pkt_len = data_len;
968 first_seg->nb_segs = 1;
970 first_seg->pkt_len += data_len;
971 first_seg->nb_segs++;
972 last_seg->next = rxm;
976 * If this is not the last buffer of the received packet,
977 * update the pointer to the last mbuf of the current scattered
978 * packet and continue to parse the RX ring.
980 if (! (status & E1000_RXD_STAT_EOP)) {
986 * This is the last buffer of the received packet.
987 * If the CRC is not stripped by the hardware:
988 * - Subtract the CRC length from the total packet length.
989 * - If the last buffer only contains the whole CRC or a part
990 * of it, free the mbuf associated to the last buffer.
991 * If part of the CRC is also contained in the previous
992 * mbuf, subtract the length of that CRC part from the
993 * data length of the previous mbuf.
996 if (unlikely(rxq->crc_len > 0)) {
997 first_seg->pkt_len -= ETHER_CRC_LEN;
998 if (data_len <= ETHER_CRC_LEN) {
999 rte_pktmbuf_free_seg(rxm);
1000 first_seg->nb_segs--;
1001 last_seg->data_len = (uint16_t)
1002 (last_seg->data_len -
1003 (ETHER_CRC_LEN - data_len));
1004 last_seg->next = NULL;
1007 (uint16_t) (data_len - ETHER_CRC_LEN);
1011 * Initialize the first mbuf of the returned packet:
1012 * - RX port identifier,
1013 * - hardware offload data, if any:
1014 * - IP checksum flag,
1017 first_seg->port = rxq->port_id;
1019 first_seg->ol_flags = rx_desc_status_to_pkt_flags(status);
1020 first_seg->ol_flags = first_seg->ol_flags |
1021 rx_desc_error_to_pkt_flags(rxd.errors);
1023 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1024 rxm->vlan_tci = rte_le_to_cpu_16(rxd.special);
1026 /* Prefetch data of first segment, if configured to do so. */
1027 rte_packet_prefetch((char *)first_seg->buf_addr +
1028 first_seg->data_off);
1031 * Store the mbuf address into the next entry of the array
1032 * of returned packets.
1034 rx_pkts[nb_rx++] = first_seg;
1037 * Setup receipt context for a new packet.
1043 * Record index of the next RX descriptor to probe.
1045 rxq->rx_tail = rx_id;
1048 * Save receive context.
1050 rxq->pkt_first_seg = first_seg;
1051 rxq->pkt_last_seg = last_seg;
1054 * If the number of free RX descriptors is greater than the RX free
1055 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1057 * Update the RDT with the value of the last processed RX descriptor
1058 * minus 1, to guarantee that the RDT register is never equal to the
1059 * RDH register, which creates a "full" ring situtation from the
1060 * hardware point of view...
1062 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1063 if (nb_hold > rxq->rx_free_thresh) {
1064 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1065 "nb_hold=%u nb_rx=%u",
1066 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1067 (unsigned) rx_id, (unsigned) nb_hold,
1069 rx_id = (uint16_t) ((rx_id == 0) ?
1070 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1071 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1074 rxq->nb_rx_hold = nb_hold;
1078 #define EM_MAX_BUF_SIZE 16384
1079 #define EM_RCTL_FLXBUF_STEP 1024
1082 em_tx_queue_release_mbufs(struct em_tx_queue *txq)
1086 if (txq->sw_ring != NULL) {
1087 for (i = 0; i != txq->nb_tx_desc; i++) {
1088 if (txq->sw_ring[i].mbuf != NULL) {
1089 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1090 txq->sw_ring[i].mbuf = NULL;
1097 em_tx_queue_release(struct em_tx_queue *txq)
1100 em_tx_queue_release_mbufs(txq);
1101 rte_free(txq->sw_ring);
1107 eth_em_tx_queue_release(void *txq)
1109 em_tx_queue_release(txq);
1112 /* (Re)set dynamic em_tx_queue fields to defaults */
1114 em_reset_tx_queue(struct em_tx_queue *txq)
1116 uint16_t i, nb_desc, prev;
1117 static const struct e1000_data_desc txd_init = {
1118 .upper.fields = {.status = E1000_TXD_STAT_DD},
1121 nb_desc = txq->nb_tx_desc;
1123 /* Initialize ring entries */
1125 prev = (uint16_t) (nb_desc - 1);
1127 for (i = 0; i < nb_desc; i++) {
1128 txq->tx_ring[i] = txd_init;
1129 txq->sw_ring[i].mbuf = NULL;
1130 txq->sw_ring[i].last_id = i;
1131 txq->sw_ring[prev].next_id = i;
1136 * Always allow 1 descriptor to be un-allocated to avoid
1137 * a H/W race condition
1139 txq->nb_tx_free = (uint16_t)(nb_desc - 1);
1140 txq->last_desc_cleaned = (uint16_t)(nb_desc - 1);
1141 txq->nb_tx_used = 0;
1144 memset((void*)&txq->ctx_cache, 0, sizeof (txq->ctx_cache));
1148 eth_em_tx_queue_setup(struct rte_eth_dev *dev,
1151 unsigned int socket_id,
1152 const struct rte_eth_txconf *tx_conf)
1154 const struct rte_memzone *tz;
1155 struct em_tx_queue *txq;
1156 struct e1000_hw *hw;
1158 uint16_t tx_rs_thresh, tx_free_thresh;
1160 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1163 * Validate number of transmit descriptors.
1164 * It must not exceed hardware maximum, and must be multiple
1167 if (nb_desc % EM_TXD_ALIGN != 0 ||
1168 (nb_desc > E1000_MAX_RING_DESC) ||
1169 (nb_desc < E1000_MIN_RING_DESC)) {
1173 tx_free_thresh = tx_conf->tx_free_thresh;
1174 if (tx_free_thresh == 0)
1175 tx_free_thresh = (uint16_t)RTE_MIN(nb_desc / 4,
1176 DEFAULT_TX_FREE_THRESH);
1178 tx_rs_thresh = tx_conf->tx_rs_thresh;
1179 if (tx_rs_thresh == 0)
1180 tx_rs_thresh = (uint16_t)RTE_MIN(tx_free_thresh,
1181 DEFAULT_TX_RS_THRESH);
1183 if (tx_free_thresh >= (nb_desc - 3)) {
1184 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
1185 "number of TX descriptors minus 3. "
1186 "(tx_free_thresh=%u port=%d queue=%d)",
1187 (unsigned int)tx_free_thresh,
1188 (int)dev->data->port_id, (int)queue_idx);
1191 if (tx_rs_thresh > tx_free_thresh) {
1192 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
1193 "tx_free_thresh. (tx_free_thresh=%u "
1194 "tx_rs_thresh=%u port=%d queue=%d)",
1195 (unsigned int)tx_free_thresh,
1196 (unsigned int)tx_rs_thresh,
1197 (int)dev->data->port_id,
1203 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1204 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1205 * by the NIC and all descriptors are written back after the NIC
1206 * accumulates WTHRESH descriptors.
1208 if (tx_conf->tx_thresh.wthresh != 0 && tx_rs_thresh != 1) {
1209 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1210 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1211 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1212 (int)dev->data->port_id, (int)queue_idx);
1216 /* Free memory prior to re-allocation if needed... */
1217 if (dev->data->tx_queues[queue_idx] != NULL) {
1218 em_tx_queue_release(dev->data->tx_queues[queue_idx]);
1219 dev->data->tx_queues[queue_idx] = NULL;
1223 * Allocate TX ring hardware descriptors. A memzone large enough to
1224 * handle the maximum ring size is allocated in order to allow for
1225 * resizing in later calls to the queue setup function.
1227 tsize = sizeof(txq->tx_ring[0]) * E1000_MAX_RING_DESC;
1228 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx, tsize,
1229 RTE_CACHE_LINE_SIZE, socket_id);
1233 /* Allocate the tx queue data structure. */
1234 if ((txq = rte_zmalloc("ethdev TX queue", sizeof(*txq),
1235 RTE_CACHE_LINE_SIZE)) == NULL)
1238 /* Allocate software ring */
1239 if ((txq->sw_ring = rte_zmalloc("txq->sw_ring",
1240 sizeof(txq->sw_ring[0]) * nb_desc,
1241 RTE_CACHE_LINE_SIZE)) == NULL) {
1242 em_tx_queue_release(txq);
1246 txq->nb_tx_desc = nb_desc;
1247 txq->tx_free_thresh = tx_free_thresh;
1248 txq->tx_rs_thresh = tx_rs_thresh;
1249 txq->pthresh = tx_conf->tx_thresh.pthresh;
1250 txq->hthresh = tx_conf->tx_thresh.hthresh;
1251 txq->wthresh = tx_conf->tx_thresh.wthresh;
1252 txq->queue_id = queue_idx;
1253 txq->port_id = dev->data->port_id;
1255 txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(queue_idx));
1256 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1257 txq->tx_ring = (struct e1000_data_desc *) tz->addr;
1259 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1260 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1262 em_reset_tx_queue(txq);
1264 dev->data->tx_queues[queue_idx] = txq;
1269 em_rx_queue_release_mbufs(struct em_rx_queue *rxq)
1273 if (rxq->sw_ring != NULL) {
1274 for (i = 0; i != rxq->nb_rx_desc; i++) {
1275 if (rxq->sw_ring[i].mbuf != NULL) {
1276 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1277 rxq->sw_ring[i].mbuf = NULL;
1284 em_rx_queue_release(struct em_rx_queue *rxq)
1287 em_rx_queue_release_mbufs(rxq);
1288 rte_free(rxq->sw_ring);
1294 eth_em_rx_queue_release(void *rxq)
1296 em_rx_queue_release(rxq);
1299 /* Reset dynamic em_rx_queue fields back to defaults */
1301 em_reset_rx_queue(struct em_rx_queue *rxq)
1304 rxq->nb_rx_hold = 0;
1305 rxq->pkt_first_seg = NULL;
1306 rxq->pkt_last_seg = NULL;
1310 eth_em_rx_queue_setup(struct rte_eth_dev *dev,
1313 unsigned int socket_id,
1314 const struct rte_eth_rxconf *rx_conf,
1315 struct rte_mempool *mp)
1317 const struct rte_memzone *rz;
1318 struct em_rx_queue *rxq;
1319 struct e1000_hw *hw;
1322 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1325 * Validate number of receive descriptors.
1326 * It must not exceed hardware maximum, and must be multiple
1329 if (nb_desc % EM_RXD_ALIGN != 0 ||
1330 (nb_desc > E1000_MAX_RING_DESC) ||
1331 (nb_desc < E1000_MIN_RING_DESC)) {
1336 * EM devices don't support drop_en functionality
1338 if (rx_conf->rx_drop_en) {
1339 PMD_INIT_LOG(ERR, "drop_en functionality not supported by "
1344 /* Free memory prior to re-allocation if needed. */
1345 if (dev->data->rx_queues[queue_idx] != NULL) {
1346 em_rx_queue_release(dev->data->rx_queues[queue_idx]);
1347 dev->data->rx_queues[queue_idx] = NULL;
1350 /* Allocate RX ring for max possible mumber of hardware descriptors. */
1351 rsize = sizeof(rxq->rx_ring[0]) * E1000_MAX_RING_DESC;
1352 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx, rsize,
1353 RTE_CACHE_LINE_SIZE, socket_id);
1357 /* Allocate the RX queue data structure. */
1358 if ((rxq = rte_zmalloc("ethdev RX queue", sizeof(*rxq),
1359 RTE_CACHE_LINE_SIZE)) == NULL)
1362 /* Allocate software ring. */
1363 if ((rxq->sw_ring = rte_zmalloc("rxq->sw_ring",
1364 sizeof (rxq->sw_ring[0]) * nb_desc,
1365 RTE_CACHE_LINE_SIZE)) == NULL) {
1366 em_rx_queue_release(rxq);
1371 rxq->nb_rx_desc = nb_desc;
1372 rxq->pthresh = rx_conf->rx_thresh.pthresh;
1373 rxq->hthresh = rx_conf->rx_thresh.hthresh;
1374 rxq->wthresh = rx_conf->rx_thresh.wthresh;
1375 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1376 rxq->queue_id = queue_idx;
1377 rxq->port_id = dev->data->port_id;
1378 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1381 rxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(queue_idx));
1382 rxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(queue_idx));
1383 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1384 rxq->rx_ring = (struct e1000_rx_desc *) rz->addr;
1386 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1387 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
1389 dev->data->rx_queues[queue_idx] = rxq;
1390 em_reset_rx_queue(rxq);
1396 eth_em_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1398 #define EM_RXQ_SCAN_INTERVAL 4
1399 volatile struct e1000_rx_desc *rxdp;
1400 struct em_rx_queue *rxq;
1403 if (rx_queue_id >= dev->data->nb_rx_queues) {
1404 PMD_RX_LOG(DEBUG, "Invalid RX queue_id=%d", rx_queue_id);
1408 rxq = dev->data->rx_queues[rx_queue_id];
1409 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1411 while ((desc < rxq->nb_rx_desc) &&
1412 (rxdp->status & E1000_RXD_STAT_DD)) {
1413 desc += EM_RXQ_SCAN_INTERVAL;
1414 rxdp += EM_RXQ_SCAN_INTERVAL;
1415 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1416 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1417 desc - rxq->nb_rx_desc]);
1424 eth_em_rx_descriptor_done(void *rx_queue, uint16_t offset)
1426 volatile struct e1000_rx_desc *rxdp;
1427 struct em_rx_queue *rxq = rx_queue;
1430 if (unlikely(offset >= rxq->nb_rx_desc))
1432 desc = rxq->rx_tail + offset;
1433 if (desc >= rxq->nb_rx_desc)
1434 desc -= rxq->nb_rx_desc;
1436 rxdp = &rxq->rx_ring[desc];
1437 return !!(rxdp->status & E1000_RXD_STAT_DD);
1441 em_dev_clear_queues(struct rte_eth_dev *dev)
1444 struct em_tx_queue *txq;
1445 struct em_rx_queue *rxq;
1447 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1448 txq = dev->data->tx_queues[i];
1450 em_tx_queue_release_mbufs(txq);
1451 em_reset_tx_queue(txq);
1455 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1456 rxq = dev->data->rx_queues[i];
1458 em_rx_queue_release_mbufs(rxq);
1459 em_reset_rx_queue(rxq);
1465 em_dev_free_queues(struct rte_eth_dev *dev)
1469 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1470 eth_em_rx_queue_release(dev->data->rx_queues[i]);
1471 dev->data->rx_queues[i] = NULL;
1473 dev->data->nb_rx_queues = 0;
1475 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1476 eth_em_tx_queue_release(dev->data->tx_queues[i]);
1477 dev->data->tx_queues[i] = NULL;
1479 dev->data->nb_tx_queues = 0;
1483 * Takes as input/output parameter RX buffer size.
1484 * Returns (BSIZE | BSEX | FLXBUF) fields of RCTL register.
1487 em_rctl_bsize(__rte_unused enum e1000_mac_type hwtyp, uint32_t *bufsz)
1490 * For BSIZE & BSEX all configurable sizes are:
1491 * 16384: rctl |= (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX);
1492 * 8192: rctl |= (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX);
1493 * 4096: rctl |= (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX);
1494 * 2048: rctl |= E1000_RCTL_SZ_2048;
1495 * 1024: rctl |= E1000_RCTL_SZ_1024;
1496 * 512: rctl |= E1000_RCTL_SZ_512;
1497 * 256: rctl |= E1000_RCTL_SZ_256;
1499 static const struct {
1502 } bufsz_to_rctl[] = {
1503 {16384, (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX)},
1504 {8192, (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX)},
1505 {4096, (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX)},
1506 {2048, E1000_RCTL_SZ_2048},
1507 {1024, E1000_RCTL_SZ_1024},
1508 {512, E1000_RCTL_SZ_512},
1509 {256, E1000_RCTL_SZ_256},
1513 uint32_t rctl_bsize;
1515 rctl_bsize = *bufsz;
1518 * Starting from 82571 it is possible to specify RX buffer size
1519 * by RCTL.FLXBUF. When this field is different from zero, the
1520 * RX buffer size = RCTL.FLXBUF * 1K
1521 * (e.g. t is possible to specify RX buffer size 1,2,...,15KB).
1522 * It is working ok on real HW, but by some reason doesn't work
1523 * on VMware emulated 82574L.
1524 * So for now, always use BSIZE/BSEX to setup RX buffer size.
1525 * If you don't plan to use it on VMware emulated 82574L and
1526 * would like to specify RX buffer size in 1K granularity,
1527 * uncomment the following lines:
1528 * ***************************************************************
1529 * if (hwtyp >= e1000_82571 && hwtyp <= e1000_82574 &&
1530 * rctl_bsize >= EM_RCTL_FLXBUF_STEP) {
1531 * rctl_bsize /= EM_RCTL_FLXBUF_STEP;
1532 * *bufsz = rctl_bsize;
1533 * return (rctl_bsize << E1000_RCTL_FLXBUF_SHIFT &
1534 * E1000_RCTL_FLXBUF_MASK);
1536 * ***************************************************************
1539 for (i = 0; i != sizeof(bufsz_to_rctl) / sizeof(bufsz_to_rctl[0]);
1541 if (rctl_bsize >= bufsz_to_rctl[i].bufsz) {
1542 *bufsz = bufsz_to_rctl[i].bufsz;
1543 return bufsz_to_rctl[i].rctl;
1547 /* Should never happen. */
1552 em_alloc_rx_queue_mbufs(struct em_rx_queue *rxq)
1554 struct em_rx_entry *rxe = rxq->sw_ring;
1557 static const struct e1000_rx_desc rxd_init = {
1561 /* Initialize software ring entries */
1562 for (i = 0; i < rxq->nb_rx_desc; i++) {
1563 volatile struct e1000_rx_desc *rxd;
1564 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
1567 PMD_INIT_LOG(ERR, "RX mbuf alloc failed "
1568 "queue_id=%hu", rxq->queue_id);
1573 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
1575 /* Clear HW ring memory */
1576 rxq->rx_ring[i] = rxd_init;
1578 rxd = &rxq->rx_ring[i];
1579 rxd->buffer_addr = dma_addr;
1586 /*********************************************************************
1588 * Enable receive unit.
1590 **********************************************************************/
1592 eth_em_rx_init(struct rte_eth_dev *dev)
1594 struct e1000_hw *hw;
1595 struct em_rx_queue *rxq;
1599 uint32_t rctl_bsize;
1603 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606 * Make sure receives are disabled while setting
1607 * up the descriptor ring.
1609 rctl = E1000_READ_REG(hw, E1000_RCTL);
1610 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
1612 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
1614 /* Disable extended descriptor type. */
1615 rfctl &= ~E1000_RFCTL_EXTEN;
1616 /* Disable accelerated acknowledge */
1617 if (hw->mac.type == e1000_82574)
1618 rfctl |= E1000_RFCTL_ACK_DIS;
1620 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
1623 * XXX TEMPORARY WORKAROUND: on some systems with 82573
1624 * long latencies are observed, like Lenovo X60. This
1625 * change eliminates the problem, but since having positive
1626 * values in RDTR is a known source of problems on other
1627 * platforms another solution is being sought.
1629 if (hw->mac.type == e1000_82573)
1630 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
1632 dev->rx_pkt_burst = (eth_rx_burst_t)eth_em_recv_pkts;
1634 /* Determine RX bufsize. */
1635 rctl_bsize = EM_MAX_BUF_SIZE;
1636 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1639 rxq = dev->data->rx_queues[i];
1640 buf_size = rte_pktmbuf_data_room_size(rxq->mb_pool) -
1641 RTE_PKTMBUF_HEADROOM;
1642 rctl_bsize = RTE_MIN(rctl_bsize, buf_size);
1645 rctl |= em_rctl_bsize(hw->mac.type, &rctl_bsize);
1647 /* Configure and enable each RX queue. */
1648 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1652 rxq = dev->data->rx_queues[i];
1654 /* Allocate buffers for descriptor rings and setup queue */
1655 ret = em_alloc_rx_queue_mbufs(rxq);
1660 * Reset crc_len in case it was changed after queue setup by a
1664 (uint8_t)(dev->data->dev_conf.rxmode.hw_strip_crc ?
1667 bus_addr = rxq->rx_ring_phys_addr;
1668 E1000_WRITE_REG(hw, E1000_RDLEN(i),
1670 sizeof(*rxq->rx_ring));
1671 E1000_WRITE_REG(hw, E1000_RDBAH(i),
1672 (uint32_t)(bus_addr >> 32));
1673 E1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);
1675 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
1676 E1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);
1678 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
1679 rxdctl &= 0xFE000000;
1680 rxdctl |= rxq->pthresh & 0x3F;
1681 rxdctl |= (rxq->hthresh & 0x3F) << 8;
1682 rxdctl |= (rxq->wthresh & 0x3F) << 16;
1683 rxdctl |= E1000_RXDCTL_GRAN;
1684 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
1687 * Due to EM devices not having any sort of hardware
1688 * limit for packet length, jumbo frame of any size
1689 * can be accepted, thus we have to enable scattered
1690 * rx if jumbo frames are enabled (or if buffer size
1691 * is too small to accommodate non-jumbo packets)
1692 * to avoid splitting packets that don't fit into
1695 if (dev->data->dev_conf.rxmode.jumbo_frame ||
1696 rctl_bsize < ETHER_MAX_LEN) {
1697 if (!dev->data->scattered_rx)
1698 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
1700 (eth_rx_burst_t)eth_em_recv_scattered_pkts;
1701 dev->data->scattered_rx = 1;
1705 if (dev->data->dev_conf.rxmode.enable_scatter) {
1706 if (!dev->data->scattered_rx)
1707 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
1708 dev->rx_pkt_burst = eth_em_recv_scattered_pkts;
1709 dev->data->scattered_rx = 1;
1713 * Setup the Checksum Register.
1714 * Receive Full-Packet Checksum Offload is mutually exclusive with RSS.
1716 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
1718 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
1719 rxcsum |= E1000_RXCSUM_IPOFL;
1721 rxcsum &= ~E1000_RXCSUM_IPOFL;
1722 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
1724 /* No MRQ or RSS support for now */
1726 /* Set early receive threshold on appropriate hw */
1727 if ((hw->mac.type == e1000_ich9lan ||
1728 hw->mac.type == e1000_pch2lan ||
1729 hw->mac.type == e1000_ich10lan) &&
1730 dev->data->dev_conf.rxmode.jumbo_frame == 1) {
1731 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
1732 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
1733 E1000_WRITE_REG(hw, E1000_ERT, 0x100 | (1 << 13));
1736 if (hw->mac.type == e1000_pch2lan) {
1737 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1738 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
1740 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
1743 /* Setup the Receive Control Register. */
1744 if (dev->data->dev_conf.rxmode.hw_strip_crc)
1745 rctl |= E1000_RCTL_SECRC; /* Strip Ethernet CRC. */
1747 rctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */
1749 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1750 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
1751 E1000_RCTL_RDMTS_HALF |
1752 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1754 /* Make sure VLAN Filters are off. */
1755 rctl &= ~E1000_RCTL_VFE;
1756 /* Don't store bad packets. */
1757 rctl &= ~E1000_RCTL_SBP;
1758 /* Legacy descriptor type. */
1759 rctl &= ~E1000_RCTL_DTYP_MASK;
1762 * Configure support of jumbo frames, if any.
1764 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1765 rctl |= E1000_RCTL_LPE;
1767 rctl &= ~E1000_RCTL_LPE;
1769 /* Enable Receives. */
1770 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1775 /*********************************************************************
1777 * Enable transmit unit.
1779 **********************************************************************/
1781 eth_em_tx_init(struct rte_eth_dev *dev)
1783 struct e1000_hw *hw;
1784 struct em_tx_queue *txq;
1789 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1791 /* Setup the Base and Length of the Tx Descriptor Rings. */
1792 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1795 txq = dev->data->tx_queues[i];
1796 bus_addr = txq->tx_ring_phys_addr;
1797 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1799 sizeof(*txq->tx_ring));
1800 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1801 (uint32_t)(bus_addr >> 32));
1802 E1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);
1804 /* Setup the HW Tx Head and Tail descriptor pointers. */
1805 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1806 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1808 /* Setup Transmit threshold registers. */
1809 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));
1811 * bit 22 is reserved, on some models should always be 0,
1812 * on others - always 1.
1814 txdctl &= E1000_TXDCTL_COUNT_DESC;
1815 txdctl |= txq->pthresh & 0x3F;
1816 txdctl |= (txq->hthresh & 0x3F) << 8;
1817 txdctl |= (txq->wthresh & 0x3F) << 16;
1818 txdctl |= E1000_TXDCTL_GRAN;
1819 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1822 /* Program the Transmit Control Register. */
1823 tctl = E1000_READ_REG(hw, E1000_TCTL);
1824 tctl &= ~E1000_TCTL_CT;
1825 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1826 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1828 /* This write will effectively turn on the transmit unit. */
1829 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1833 em_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1834 struct rte_eth_rxq_info *qinfo)
1836 struct em_rx_queue *rxq;
1838 rxq = dev->data->rx_queues[queue_id];
1840 qinfo->mp = rxq->mb_pool;
1841 qinfo->scattered_rx = dev->data->scattered_rx;
1842 qinfo->nb_desc = rxq->nb_rx_desc;
1843 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1847 em_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1848 struct rte_eth_txq_info *qinfo)
1850 struct em_tx_queue *txq;
1852 txq = dev->data->tx_queues[queue_id];
1854 qinfo->nb_desc = txq->nb_tx_desc;
1856 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1857 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1858 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1859 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1860 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;