drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "base/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59 #include "igb_regs.h"
  60
  61 /*
  62  * Default values for port configuration
  63  */
  64 #define IGB_DEFAULT_RX_FREE_THRESH  32
  65
  66 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  67 #define IGB_DEFAULT_RX_HTHRESH      8
  68 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  69
  70 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  71 #define IGB_DEFAULT_TX_HTHRESH      1
  72 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  73
  74 #define IGB_HKEY_MAX_INDEX 10
  75
  76 /* Bit shift and mask */
  77 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  78 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  79 #define IGB_8_BIT_WIDTH  CHAR_BIT
  80 #define IGB_8_BIT_MASK   UINT8_MAX
  81
  82 /* Additional timesync values. */
  83 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  84 #define E1000_ETQF_FILTER_1588       3
  85 #define IGB_82576_TSYNC_SHIFT        16
  86 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  87 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  89
  90 #define E1000_VTIVAR_MISC                0x01740
  91 #define E1000_VTIVAR_MISC_MASK           0xFF
  92 #define E1000_VTIVAR_VALID               0x80
  93 #define E1000_VTIVAR_MISC_MAILBOX        0
  94 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  95
  96 /* External VLAN Enable bit mask */
  97 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  98
  99 /* External VLAN Ether Type bit mask and shift */
 100 #define E1000_VET_VET_EXT            0xFFFF0000
 101 #define E1000_VET_VET_EXT_SHIFT      16
 102
 103 static int  eth_igb_configure(struct rte_eth_dev *dev);
 104 static int  eth_igb_start(struct rte_eth_dev *dev);
 105 static void eth_igb_stop(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 107 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 108 static void eth_igb_close(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 113 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 114                                 int wait_to_complete);
 115 static int eth_igb_stats_get(struct rte_eth_dev *dev,
 116                                 struct rte_eth_stats *rte_stats);
 117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 118                               struct rte_eth_xstat *xstats, unsigned n);
 119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
 120                 const uint64_t *ids,
 121                 uint64_t *values, unsigned int n);
 122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 123                                     struct rte_eth_xstat_name *xstats_names,
 124                                     unsigned int size);
 125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
 126                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 127                 unsigned int limit);
 128 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 131                                    char *fw_version, size_t fw_size);
 132 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 133                               struct rte_eth_dev_info *dev_info);
 134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 136                                 struct rte_eth_dev_info *dev_info);
 137 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 138                                 struct rte_eth_fc_conf *fc_conf);
 139 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 140                                 struct rte_eth_fc_conf *fc_conf);
 141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 145                                     struct rte_intr_handle *handle);
 146 static void eth_igb_interrupt_handler(void *param);
 147 static int  igb_hardware_init(struct e1000_hw *hw);
 148 static void igb_hw_control_acquire(struct e1000_hw *hw);
 149 static void igb_hw_control_release(struct e1000_hw *hw);
 150 static void igb_init_manageability(struct e1000_hw *hw);
 151 static void igb_release_manageability(struct e1000_hw *hw);
 152
 153 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154
 155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 156                 uint16_t vlan_id, int on);
 157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 158                                  enum rte_vlan_type vlan_type,
 159                                  uint16_t tpid_id);
 160 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 161
 162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 168
 169 static int eth_igb_led_on(struct rte_eth_dev *dev);
 170 static int eth_igb_led_off(struct rte_eth_dev *dev);
 171
 172 static void igb_intr_disable(struct e1000_hw *hw);
 173 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 174 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 175                            struct ether_addr *mac_addr,
 176                            uint32_t index, uint32_t pool);
 177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 179                 struct ether_addr *addr);
 180
 181 static void igbvf_intr_disable(struct e1000_hw *hw);
 182 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 183 static int igbvf_dev_start(struct rte_eth_dev *dev);
 184 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 185 static void igbvf_dev_close(struct rte_eth_dev *dev);
 186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 190 static int eth_igbvf_link_update(struct e1000_hw *hw);
 191 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 192                                 struct rte_eth_stats *rte_stats);
 193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 194                                 struct rte_eth_xstat *xstats, unsigned n);
 195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 196                                       struct rte_eth_xstat_name *xstats_names,
 197                                       unsigned limit);
 198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 200                 uint16_t vlan_id, int on);
 201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 204                 struct ether_addr *addr);
 205 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 206 static int igbvf_get_regs(struct rte_eth_dev *dev,
 207                 struct rte_dev_reg_info *regs);
 208
 209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 210                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 211                                    uint16_t reta_size);
 212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 213                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 214                                   uint16_t reta_size);
 215
 216 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 217                         struct rte_eth_syn_filter *filter);
 218 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 219                         enum rte_filter_op filter_op,
 220                         void *arg);
 221 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 222                         struct rte_eth_ntuple_filter *ntuple_filter);
 223 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 224                         struct rte_eth_ntuple_filter *ntuple_filter);
 225 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 226                         struct rte_eth_flex_filter *filter);
 227 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 228                         enum rte_filter_op filter_op,
 229                         void *arg);
 230 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 231                         struct rte_eth_ntuple_filter *ntuple_filter);
 232 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 233                         struct rte_eth_ntuple_filter *ntuple_filter);
 234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 235                         struct rte_eth_ntuple_filter *filter);
 236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 237                                 enum rte_filter_op filter_op,
 238                                 void *arg);
 239 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 240                                 enum rte_filter_op filter_op,
 241                                 void *arg);
 242 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 243                         struct rte_eth_ethertype_filter *filter);
 244 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 245                      enum rte_filter_type filter_type,
 246                      enum rte_filter_op filter_op,
 247                      void *arg);
 248 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 249 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 250                 struct rte_dev_reg_info *regs);
 251 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 252 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 253                 struct rte_dev_eeprom_info *eeprom);
 254 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 255                 struct rte_dev_eeprom_info *eeprom);
 256 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 257                                     struct ether_addr *mc_addr_set,
 258                                     uint32_t nb_mc_addr);
 259 static int igb_timesync_enable(struct rte_eth_dev *dev);
 260 static int igb_timesync_disable(struct rte_eth_dev *dev);
 261 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 262                                           struct timespec *timestamp,
 263                                           uint32_t flags);
 264 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 265                                           struct timespec *timestamp);
 266 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 267 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 268                                   struct timespec *timestamp);
 269 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 270                                    const struct timespec *timestamp);
 271 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 272                                         uint16_t queue_id);
 273 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 274                                          uint16_t queue_id);
 275 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 276                                        uint8_t queue, uint8_t msix_vector);
 277 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 278                                uint8_t index, uint8_t offset);
 279 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 280 static void eth_igbvf_interrupt_handler(void *param);
 281 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 282 static int igb_filter_restore(struct rte_eth_dev *dev);
 283
 284 /*
 285  * Define VF Stats MACRO for Non "cleared on read" register
 286  */
 287 #define UPDATE_VF_STAT(reg, last, cur)            \
 288 {                                                 \
 289         u32 latest = E1000_READ_REG(hw, reg);     \
 290         cur += (latest - last) & UINT_MAX;        \
 291         last = latest;                            \
 292 }
 293
 294 #define IGB_FC_PAUSE_TIME 0x0680
 295 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 296 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 297
 298 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 299
 300 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 301
 302 /*
 303  * The set of PCI devices this driver supports
 304  */
 305 static const struct rte_pci_id pci_id_igb_map[] = {
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 314
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 318
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 325
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 347         { .vendor_id = 0, /* sentinel */ },
 348 };
 349
 350 /*
 351  * The set of PCI devices this driver supports (for 82576&I350 VF)
 352  */
 353 static const struct rte_pci_id pci_id_igbvf_map[] = {
 354         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 356         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 357         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 358         { .vendor_id = 0, /* sentinel */ },
 359 };
 360
 361 static const struct rte_eth_desc_lim rx_desc_lim = {
 362         .nb_max = E1000_MAX_RING_DESC,
 363         .nb_min = E1000_MIN_RING_DESC,
 364         .nb_align = IGB_RXD_ALIGN,
 365 };
 366
 367 static const struct rte_eth_desc_lim tx_desc_lim = {
 368         .nb_max = E1000_MAX_RING_DESC,
 369         .nb_min = E1000_MIN_RING_DESC,
 370         .nb_align = IGB_RXD_ALIGN,
 371         .nb_seg_max = IGB_TX_MAX_SEG,
 372         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 373 };
 374
 375 static const struct eth_dev_ops eth_igb_ops = {
 376         .dev_configure        = eth_igb_configure,
 377         .dev_start            = eth_igb_start,
 378         .dev_stop             = eth_igb_stop,
 379         .dev_set_link_up      = eth_igb_dev_set_link_up,
 380         .dev_set_link_down    = eth_igb_dev_set_link_down,
 381         .dev_close            = eth_igb_close,
 382         .promiscuous_enable   = eth_igb_promiscuous_enable,
 383         .promiscuous_disable  = eth_igb_promiscuous_disable,
 384         .allmulticast_enable  = eth_igb_allmulticast_enable,
 385         .allmulticast_disable = eth_igb_allmulticast_disable,
 386         .link_update          = eth_igb_link_update,
 387         .stats_get            = eth_igb_stats_get,
 388         .xstats_get           = eth_igb_xstats_get,
 389         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 390         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 391         .xstats_get_names     = eth_igb_xstats_get_names,
 392         .stats_reset          = eth_igb_stats_reset,
 393         .xstats_reset         = eth_igb_xstats_reset,
 394         .fw_version_get       = eth_igb_fw_version_get,
 395         .dev_infos_get        = eth_igb_infos_get,
 396         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 397         .mtu_set              = eth_igb_mtu_set,
 398         .vlan_filter_set      = eth_igb_vlan_filter_set,
 399         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 400         .vlan_offload_set     = eth_igb_vlan_offload_set,
 401         .rx_queue_setup       = eth_igb_rx_queue_setup,
 402         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 403         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 404         .rx_queue_release     = eth_igb_rx_queue_release,
 405         .rx_queue_count       = eth_igb_rx_queue_count,
 406         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 407         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 408         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 409         .tx_queue_setup       = eth_igb_tx_queue_setup,
 410         .tx_queue_release     = eth_igb_tx_queue_release,
 411         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 412         .dev_led_on           = eth_igb_led_on,
 413         .dev_led_off          = eth_igb_led_off,
 414         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 415         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 416         .mac_addr_add         = eth_igb_rar_set,
 417         .mac_addr_remove      = eth_igb_rar_clear,
 418         .mac_addr_set         = eth_igb_default_mac_addr_set,
 419         .reta_update          = eth_igb_rss_reta_update,
 420         .reta_query           = eth_igb_rss_reta_query,
 421         .rss_hash_update      = eth_igb_rss_hash_update,
 422         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 423         .filter_ctrl          = eth_igb_filter_ctrl,
 424         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 425         .rxq_info_get         = igb_rxq_info_get,
 426         .txq_info_get         = igb_txq_info_get,
 427         .timesync_enable      = igb_timesync_enable,
 428         .timesync_disable     = igb_timesync_disable,
 429         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 430         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 431         .get_reg              = eth_igb_get_regs,
 432         .get_eeprom_length    = eth_igb_get_eeprom_length,
 433         .get_eeprom           = eth_igb_get_eeprom,
 434         .set_eeprom           = eth_igb_set_eeprom,
 435         .timesync_adjust_time = igb_timesync_adjust_time,
 436         .timesync_read_time   = igb_timesync_read_time,
 437         .timesync_write_time  = igb_timesync_write_time,
 438 };
 439
 440 /*
 441  * dev_ops for virtual function, bare necessities for basic vf
 442  * operation have been implemented
 443  */
 444 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 445         .dev_configure        = igbvf_dev_configure,
 446         .dev_start            = igbvf_dev_start,
 447         .dev_stop             = igbvf_dev_stop,
 448         .dev_close            = igbvf_dev_close,
 449         .promiscuous_enable   = igbvf_promiscuous_enable,
 450         .promiscuous_disable  = igbvf_promiscuous_disable,
 451         .allmulticast_enable  = igbvf_allmulticast_enable,
 452         .allmulticast_disable = igbvf_allmulticast_disable,
 453         .link_update          = eth_igb_link_update,
 454         .stats_get            = eth_igbvf_stats_get,
 455         .xstats_get           = eth_igbvf_xstats_get,
 456         .xstats_get_names     = eth_igbvf_xstats_get_names,
 457         .stats_reset          = eth_igbvf_stats_reset,
 458         .xstats_reset         = eth_igbvf_stats_reset,
 459         .vlan_filter_set      = igbvf_vlan_filter_set,
 460         .dev_infos_get        = eth_igbvf_infos_get,
 461         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 462         .rx_queue_setup       = eth_igb_rx_queue_setup,
 463         .rx_queue_release     = eth_igb_rx_queue_release,
 464         .tx_queue_setup       = eth_igb_tx_queue_setup,
 465         .tx_queue_release     = eth_igb_tx_queue_release,
 466         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 467         .rxq_info_get         = igb_rxq_info_get,
 468         .txq_info_get         = igb_txq_info_get,
 469         .mac_addr_set         = igbvf_default_mac_addr_set,
 470         .get_reg              = igbvf_get_regs,
 471 };
 472
 473 /* store statistics names and its offset in stats structure */
 474 struct rte_igb_xstats_name_off {
 475         char name[RTE_ETH_XSTATS_NAME_SIZE];
 476         unsigned offset;
 477 };
 478
 479 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 480         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 481         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 482         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 483         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 484         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 485         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 486         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 487                 ecol)},
 488         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 489         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 490         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 491         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 492         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 493         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 494         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 495         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 496         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 497         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 498         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 499                 fcruc)},
 500         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 501         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 502         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 503         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 504         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 505                 prc1023)},
 506         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 507                 prc1522)},
 508         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 509         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 510         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 511         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 512         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 513         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 514         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 515         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 516         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 517         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 518         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 519         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 520         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 521         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 522         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 523         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 524         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 525         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 526                 ptc1023)},
 527         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 528                 ptc1522)},
 529         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 530         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 531         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 532         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 533         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 534         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 535         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 536
 537         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 538 };
 539
 540 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 541                 sizeof(rte_igb_stats_strings[0]))
 542
 543 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 544         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 545         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 546         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 547         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 548         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 549 };
 550
 551 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 552                 sizeof(rte_igbvf_stats_strings[0]))
 553
 554 /**
 555  * Atomically reads the link status information from global
 556  * structure rte_eth_dev.
 557  *
 558  * @param dev
 559  *   - Pointer to the structure rte_eth_dev to read from.
 560  *   - Pointer to the buffer to be saved with the link status.
 561  *
 562  * @return
 563  *   - On success, zero.
 564  *   - On failure, negative value.
 565  */
 566 static inline int
 567 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 568                                 struct rte_eth_link *link)
 569 {
 570         struct rte_eth_link *dst = link;
 571         struct rte_eth_link *src = &(dev->data->dev_link);
 572
 573         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 574                                         *(uint64_t *)src) == 0)
 575                 return -1;
 576
 577         return 0;
 578 }
 579
 580 /**
 581  * Atomically writes the link status information into global
 582  * structure rte_eth_dev.
 583  *
 584  * @param dev
 585  *   - Pointer to the structure rte_eth_dev to read from.
 586  *   - Pointer to the buffer to be saved with the link status.
 587  *
 588  * @return
 589  *   - On success, zero.
 590  *   - On failure, negative value.
 591  */
 592 static inline int
 593 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 594                                 struct rte_eth_link *link)
 595 {
 596         struct rte_eth_link *dst = &(dev->data->dev_link);
 597         struct rte_eth_link *src = link;
 598
 599         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 600                                         *(uint64_t *)src) == 0)
 601                 return -1;
 602
 603         return 0;
 604 }
 605
 606 static inline void
 607 igb_intr_enable(struct rte_eth_dev *dev)
 608 {
 609         struct e1000_interrupt *intr =
 610                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 611         struct e1000_hw *hw =
 612                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 613
 614         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 615         E1000_WRITE_FLUSH(hw);
 616 }
 617
 618 static void
 619 igb_intr_disable(struct e1000_hw *hw)
 620 {
 621         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 622         E1000_WRITE_FLUSH(hw);
 623 }
 624
 625 static inline void
 626 igbvf_intr_enable(struct rte_eth_dev *dev)
 627 {
 628         struct e1000_hw *hw =
 629                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 630
 631         /* only for mailbox */
 632         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 633         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 634         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 635         E1000_WRITE_FLUSH(hw);
 636 }
 637
 638 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 639 static void
 640 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 641 {
 642         uint32_t tmp = 0;
 643
 644         /* mailbox */
 645         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 646         tmp |= E1000_VTIVAR_VALID;
 647         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 648 }
 649
 650 static void
 651 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 652 {
 653         struct e1000_hw *hw =
 654                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 655
 656         /* Configure VF other cause ivar */
 657         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 658 }
 659
 660 static inline int32_t
 661 igb_pf_reset_hw(struct e1000_hw *hw)
 662 {
 663         uint32_t ctrl_ext;
 664         int32_t status;
 665
 666         status = e1000_reset_hw(hw);
 667
 668         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 669         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 670         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 671         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 672         E1000_WRITE_FLUSH(hw);
 673
 674         return status;
 675 }
 676
 677 static void
 678 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 679 {
 680         struct e1000_hw *hw =
 681                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 682
 683
 684         hw->vendor_id = pci_dev->id.vendor_id;
 685         hw->device_id = pci_dev->id.device_id;
 686         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 687         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 688
 689         e1000_set_mac_type(hw);
 690
 691         /* need to check if it is a vf device below */
 692 }
 693
 694 static int
 695 igb_reset_swfw_lock(struct e1000_hw *hw)
 696 {
 697         int ret_val;
 698
 699         /*
 700          * Do mac ops initialization manually here, since we will need
 701          * some function pointers set by this call.
 702          */
 703         ret_val = e1000_init_mac_params(hw);
 704         if (ret_val)
 705                 return ret_val;
 706
 707         /*
 708          * SMBI lock should not fail in this early stage. If this is the case,
 709          * it is due to an improper exit of the application.
 710          * So force the release of the faulty lock.
 711          */
 712         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 713                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 714         }
 715         e1000_put_hw_semaphore_generic(hw);
 716
 717         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 718                 uint16_t mask;
 719
 720                 /*
 721                  * Phy lock should not fail in this early stage. If this is the case,
 722                  * it is due to an improper exit of the application.
 723                  * So force the release of the faulty lock.
 724                  */
 725                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 726                 if (hw->bus.func > E1000_FUNC_1)
 727                         mask <<= 2;
 728                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 729                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 730                                     hw->bus.func);
 731                 }
 732                 hw->mac.ops.release_swfw_sync(hw, mask);
 733
 734                 /*
 735                  * This one is more tricky since it is common to all ports; but
 736                  * swfw_sync retries last long enough (1s) to be almost sure that if
 737                  * lock can not be taken it is due to an improper lock of the
 738                  * semaphore.
 739                  */
 740                 mask = E1000_SWFW_EEP_SM;
 741                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 742                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 743                 }
 744                 hw->mac.ops.release_swfw_sync(hw, mask);
 745         }
 746
 747         return E1000_SUCCESS;
 748 }
 749
 750 /* Remove all ntuple filters of the device */
 751 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 752 {
 753         struct e1000_filter_info *filter_info =
 754                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 755         struct e1000_5tuple_filter *p_5tuple;
 756         struct e1000_2tuple_filter *p_2tuple;
 757
 758         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 759                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 760                         p_5tuple, entries);
 761                         rte_free(p_5tuple);
 762         }
 763         filter_info->fivetuple_mask = 0;
 764         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 765                 TAILQ_REMOVE(&filter_info->twotuple_list,
 766                         p_2tuple, entries);
 767                         rte_free(p_2tuple);
 768         }
 769         filter_info->twotuple_mask = 0;
 770
 771         return 0;
 772 }
 773
 774 /* Remove all flex filters of the device */
 775 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 776 {
 777         struct e1000_filter_info *filter_info =
 778                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 779         struct e1000_flex_filter *p_flex;
 780
 781         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 782                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 783                 rte_free(p_flex);
 784         }
 785         filter_info->flex_mask = 0;
 786
 787         return 0;
 788 }
 789
 790 static int
 791 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 792 {
 793         int error = 0;
 794         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 795         struct e1000_hw *hw =
 796                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 797         struct e1000_vfta * shadow_vfta =
 798                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 799         struct e1000_filter_info *filter_info =
 800                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 801         struct e1000_adapter *adapter =
 802                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 803
 804         uint32_t ctrl_ext;
 805
 806         eth_dev->dev_ops = &eth_igb_ops;
 807         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 808         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 809         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 810
 811         /* for secondary processes, we don't initialise any further as primary
 812          * has already done this work. Only check we don't need a different
 813          * RX function */
 814         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 815                 if (eth_dev->data->scattered_rx)
 816                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 817                 return 0;
 818         }
 819
 820         rte_eth_copy_pci_info(eth_dev, pci_dev);
 821         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 822
 823         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 824
 825         igb_identify_hardware(eth_dev, pci_dev);
 826         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 827                 error = -EIO;
 828                 goto err_late;
 829         }
 830
 831         e1000_get_bus_info(hw);
 832
 833         /* Reset any pending lock */
 834         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 835                 error = -EIO;
 836                 goto err_late;
 837         }
 838
 839         /* Finish initialization */
 840         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 841                 error = -EIO;
 842                 goto err_late;
 843         }
 844
 845         hw->mac.autoneg = 1;
 846         hw->phy.autoneg_wait_to_complete = 0;
 847         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 848
 849         /* Copper options */
 850         if (hw->phy.media_type == e1000_media_type_copper) {
 851                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 852                 hw->phy.disable_polarity_correction = 0;
 853                 hw->phy.ms_type = e1000_ms_hw_default;
 854         }
 855
 856         /*
 857          * Start from a known state, this is important in reading the nvm
 858          * and mac from that.
 859          */
 860         igb_pf_reset_hw(hw);
 861
 862         /* Make sure we have a good EEPROM before we read from it */
 863         if (e1000_validate_nvm_checksum(hw) < 0) {
 864                 /*
 865                  * Some PCI-E parts fail the first check due to
 866                  * the link being in sleep state, call it again,
 867                  * if it fails a second time its a real issue.
 868                  */
 869                 if (e1000_validate_nvm_checksum(hw) < 0) {
 870                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 871                         error = -EIO;
 872                         goto err_late;
 873                 }
 874         }
 875
 876         /* Read the permanent MAC address out of the EEPROM */
 877         if (e1000_read_mac_addr(hw) != 0) {
 878                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 879                 error = -EIO;
 880                 goto err_late;
 881         }
 882
 883         /* Allocate memory for storing MAC addresses */
 884         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 885                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 886         if (eth_dev->data->mac_addrs == NULL) {
 887                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 888                                                 "store MAC addresses",
 889                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 890                 error = -ENOMEM;
 891                 goto err_late;
 892         }
 893
 894         /* Copy the permanent MAC address */
 895         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 896
 897         /* initialize the vfta */
 898         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 899
 900         /* Now initialize the hardware */
 901         if (igb_hardware_init(hw) != 0) {
 902                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 903                 rte_free(eth_dev->data->mac_addrs);
 904                 eth_dev->data->mac_addrs = NULL;
 905                 error = -ENODEV;
 906                 goto err_late;
 907         }
 908         hw->mac.get_link_status = 1;
 909         adapter->stopped = 0;
 910
 911         /* Indicate SOL/IDER usage */
 912         if (e1000_check_reset_block(hw) < 0) {
 913                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 914                                         "SOL/IDER session");
 915         }
 916
 917         /* initialize PF if max_vfs not zero */
 918         igb_pf_host_init(eth_dev);
 919
 920         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 921         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 922         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 923         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 924         E1000_WRITE_FLUSH(hw);
 925
 926         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 927                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 928                      pci_dev->id.device_id);
 929
 930         rte_intr_callback_register(&pci_dev->intr_handle,
 931                                    eth_igb_interrupt_handler,
 932                                    (void *)eth_dev);
 933
 934         /* enable uio/vfio intr/eventfd mapping */
 935         rte_intr_enable(&pci_dev->intr_handle);
 936
 937         /* enable support intr */
 938         igb_intr_enable(eth_dev);
 939
 940         /* initialize filter info */
 941         memset(filter_info, 0,
 942                sizeof(struct e1000_filter_info));
 943
 944         TAILQ_INIT(&filter_info->flex_list);
 945         TAILQ_INIT(&filter_info->twotuple_list);
 946         TAILQ_INIT(&filter_info->fivetuple_list);
 947
 948         TAILQ_INIT(&igb_filter_ntuple_list);
 949         TAILQ_INIT(&igb_filter_ethertype_list);
 950         TAILQ_INIT(&igb_filter_syn_list);
 951         TAILQ_INIT(&igb_filter_flex_list);
 952         TAILQ_INIT(&igb_flow_list);
 953
 954         return 0;
 955
 956 err_late:
 957         igb_hw_control_release(hw);
 958
 959         return error;
 960 }
 961
 962 static int
 963 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 964 {
 965         struct rte_pci_device *pci_dev;
 966         struct rte_intr_handle *intr_handle;
 967         struct e1000_hw *hw;
 968         struct e1000_adapter *adapter =
 969                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 970         struct e1000_filter_info *filter_info =
 971                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 972
 973         PMD_INIT_FUNC_TRACE();
 974
 975         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 976                 return -EPERM;
 977
 978         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 979         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 980         intr_handle = &pci_dev->intr_handle;
 981
 982         if (adapter->stopped == 0)
 983                 eth_igb_close(eth_dev);
 984
 985         eth_dev->dev_ops = NULL;
 986         eth_dev->rx_pkt_burst = NULL;
 987         eth_dev->tx_pkt_burst = NULL;
 988
 989         /* Reset any pending lock */
 990         igb_reset_swfw_lock(hw);
 991
 992         rte_free(eth_dev->data->mac_addrs);
 993         eth_dev->data->mac_addrs = NULL;
 994
 995         /* uninitialize PF if max_vfs not zero */
 996         igb_pf_host_uninit(eth_dev);
 997
 998         /* disable uio intr before callback unregister */
 999         rte_intr_disable(intr_handle);
1000         rte_intr_callback_unregister(intr_handle,
1001                                      eth_igb_interrupt_handler, eth_dev);
1002
1003         /* clear the SYN filter info */
1004         filter_info->syn_info = 0;
1005
1006         /* clear the ethertype filters info */
1007         filter_info->ethertype_mask = 0;
1008         memset(filter_info->ethertype_filters, 0,
1009                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1010
1011         /* remove all ntuple filters of the device */
1012         igb_ntuple_filter_uninit(eth_dev);
1013
1014         /* remove all flex filters of the device */
1015         igb_flex_filter_uninit(eth_dev);
1016
1017         /* clear all the filters list */
1018         igb_filterlist_flush(eth_dev);
1019
1020         return 0;
1021 }
1022
1023 /*
1024  * Virtual Function device init
1025  */
1026 static int
1027 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
1028 {
1029         struct rte_pci_device *pci_dev;
1030         struct rte_intr_handle *intr_handle;
1031         struct e1000_adapter *adapter =
1032                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1033         struct e1000_hw *hw =
1034                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1035         int diag;
1036         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
1037
1038         PMD_INIT_FUNC_TRACE();
1039
1040         eth_dev->dev_ops = &igbvf_eth_dev_ops;
1041         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
1042         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
1043         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
1044
1045         /* for secondary processes, we don't initialise any further as primary
1046          * has already done this work. Only check we don't need a different
1047          * RX function */
1048         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1049                 if (eth_dev->data->scattered_rx)
1050                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
1051                 return 0;
1052         }
1053
1054         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1055         rte_eth_copy_pci_info(eth_dev, pci_dev);
1056         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1057
1058         hw->device_id = pci_dev->id.device_id;
1059         hw->vendor_id = pci_dev->id.vendor_id;
1060         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1061         adapter->stopped = 0;
1062
1063         /* Initialize the shared code (base driver) */
1064         diag = e1000_setup_init_funcs(hw, TRUE);
1065         if (diag != 0) {
1066                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1067                         diag);
1068                 return -EIO;
1069         }
1070
1071         /* init_mailbox_params */
1072         hw->mbx.ops.init_params(hw);
1073
1074         /* Disable the interrupts for VF */
1075         igbvf_intr_disable(hw);
1076
1077         diag = hw->mac.ops.reset_hw(hw);
1078
1079         /* Allocate memory for storing MAC addresses */
1080         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1081                 hw->mac.rar_entry_count, 0);
1082         if (eth_dev->data->mac_addrs == NULL) {
1083                 PMD_INIT_LOG(ERR,
1084                         "Failed to allocate %d bytes needed to store MAC "
1085                         "addresses",
1086                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1087                 return -ENOMEM;
1088         }
1089
1090         /* Generate a random MAC address, if none was assigned by PF. */
1091         if (is_zero_ether_addr(perm_addr)) {
1092                 eth_random_addr(perm_addr->addr_bytes);
1093                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1094                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1095                              "%02x:%02x:%02x:%02x:%02x:%02x",
1096                              perm_addr->addr_bytes[0],
1097                              perm_addr->addr_bytes[1],
1098                              perm_addr->addr_bytes[2],
1099                              perm_addr->addr_bytes[3],
1100                              perm_addr->addr_bytes[4],
1101                              perm_addr->addr_bytes[5]);
1102         }
1103
1104         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1105         if (diag) {
1106                 rte_free(eth_dev->data->mac_addrs);
1107                 eth_dev->data->mac_addrs = NULL;
1108                 return diag;
1109         }
1110         /* Copy the permanent MAC address */
1111         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1112                         &eth_dev->data->mac_addrs[0]);
1113
1114         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1115                      "mac.type=%s",
1116                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1117                      pci_dev->id.device_id, "igb_mac_82576_vf");
1118
1119         intr_handle = &pci_dev->intr_handle;
1120         rte_intr_callback_register(intr_handle,
1121                                    eth_igbvf_interrupt_handler, eth_dev);
1122
1123         return 0;
1124 }
1125
1126 static int
1127 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1128 {
1129         struct e1000_adapter *adapter =
1130                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1131         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1132
1133         PMD_INIT_FUNC_TRACE();
1134
1135         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1136                 return -EPERM;
1137
1138         if (adapter->stopped == 0)
1139                 igbvf_dev_close(eth_dev);
1140
1141         eth_dev->dev_ops = NULL;
1142         eth_dev->rx_pkt_burst = NULL;
1143         eth_dev->tx_pkt_burst = NULL;
1144
1145         rte_free(eth_dev->data->mac_addrs);
1146         eth_dev->data->mac_addrs = NULL;
1147
1148         /* disable uio intr before callback unregister */
1149         rte_intr_disable(&pci_dev->intr_handle);
1150         rte_intr_callback_unregister(&pci_dev->intr_handle,
1151                                      eth_igbvf_interrupt_handler,
1152                                      (void *)eth_dev);
1153
1154         return 0;
1155 }
1156
1157 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1158         struct rte_pci_device *pci_dev)
1159 {
1160         return rte_eth_dev_pci_generic_probe(pci_dev,
1161                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1162 }
1163
1164 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1165 {
1166         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1167 }
1168
1169 static struct rte_pci_driver rte_igb_pmd = {
1170         .id_table = pci_id_igb_map,
1171         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1172                      RTE_PCI_DRV_IOVA_AS_VA,
1173         .probe = eth_igb_pci_probe,
1174         .remove = eth_igb_pci_remove,
1175 };
1176
1177
1178 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1179         struct rte_pci_device *pci_dev)
1180 {
1181         return rte_eth_dev_pci_generic_probe(pci_dev,
1182                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1183 }
1184
1185 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1186 {
1187         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1188 }
1189
1190 /*
1191  * virtual function driver struct
1192  */
1193 static struct rte_pci_driver rte_igbvf_pmd = {
1194         .id_table = pci_id_igbvf_map,
1195         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1196         .probe = eth_igbvf_pci_probe,
1197         .remove = eth_igbvf_pci_remove,
1198 };
1199
1200 static void
1201 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1202 {
1203         struct e1000_hw *hw =
1204                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1205         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1206         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1207         rctl |= E1000_RCTL_VFE;
1208         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1209 }
1210
1211 static int
1212 igb_check_mq_mode(struct rte_eth_dev *dev)
1213 {
1214         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1215         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1216         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1217         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1218
1219         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1220             tx_mq_mode == ETH_MQ_TX_DCB ||
1221             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1222                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1223                 return -EINVAL;
1224         }
1225         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1226                 /* Check multi-queue mode.
1227                  * To no break software we accept ETH_MQ_RX_NONE as this might
1228                  * be used to turn off VLAN filter.
1229                  */
1230
1231                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1232                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1233                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1234                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1235                 } else {
1236                         /* Only support one queue on VFs.
1237                          * RSS together with SRIOV is not supported.
1238                          */
1239                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1240                                         " wrong mq_mode rx %d.",
1241                                         rx_mq_mode);
1242                         return -EINVAL;
1243                 }
1244                 /* TX mode is not used here, so mode might be ignored.*/
1245                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1246                         /* SRIOV only works in VMDq enable mode */
1247                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1248                                         " TX mode %d is not supported. "
1249                                         " Driver will behave as %d mode.",
1250                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1251                 }
1252
1253                 /* check valid queue number */
1254                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1255                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1256                                         " only support one queue on VFs.");
1257                         return -EINVAL;
1258                 }
1259         } else {
1260                 /* To no break software that set invalid mode, only display
1261                  * warning if invalid mode is used.
1262                  */
1263                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1264                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1265                     rx_mq_mode != ETH_MQ_RX_RSS) {
1266                         /* RSS together with VMDq not supported*/
1267                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1268                                      rx_mq_mode);
1269                         return -EINVAL;
1270                 }
1271
1272                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1273                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1274                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1275                                         " Due to txmode is meaningless in this"
1276                                         " driver, just ignore.",
1277                                         tx_mq_mode);
1278                 }
1279         }
1280         return 0;
1281 }
1282
1283 static int
1284 eth_igb_configure(struct rte_eth_dev *dev)
1285 {
1286         struct e1000_interrupt *intr =
1287                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1288         int ret;
1289
1290         PMD_INIT_FUNC_TRACE();
1291
1292         /* multipe queue mode checking */
1293         ret  = igb_check_mq_mode(dev);
1294         if (ret != 0) {
1295                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1296                             ret);
1297                 return ret;
1298         }
1299
1300         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1301         PMD_INIT_FUNC_TRACE();
1302
1303         return 0;
1304 }
1305
1306 static int
1307 eth_igb_start(struct rte_eth_dev *dev)
1308 {
1309         struct e1000_hw *hw =
1310                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1311         struct e1000_adapter *adapter =
1312                 E1000_DEV_PRIVATE(dev->data->dev_private);
1313         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1314         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1315         int ret, mask;
1316         uint32_t intr_vector = 0;
1317         uint32_t ctrl_ext;
1318         uint32_t *speeds;
1319         int num_speeds;
1320         bool autoneg;
1321
1322         PMD_INIT_FUNC_TRACE();
1323
1324         /* disable uio/vfio intr/eventfd mapping */
1325         rte_intr_disable(intr_handle);
1326
1327         /* Power up the phy. Needed to make the link go Up */
1328         eth_igb_dev_set_link_up(dev);
1329
1330         /*
1331          * Packet Buffer Allocation (PBA)
1332          * Writing PBA sets the receive portion of the buffer
1333          * the remainder is used for the transmit buffer.
1334          */
1335         if (hw->mac.type == e1000_82575) {
1336                 uint32_t pba;
1337
1338                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1339                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1340         }
1341
1342         /* Put the address into the Receive Address Array */
1343         e1000_rar_set(hw, hw->mac.addr, 0);
1344
1345         /* Initialize the hardware */
1346         if (igb_hardware_init(hw)) {
1347                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1348                 return -EIO;
1349         }
1350         adapter->stopped = 0;
1351
1352         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1353
1354         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1355         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1356         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1357         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1358         E1000_WRITE_FLUSH(hw);
1359
1360         /* configure PF module if SRIOV enabled */
1361         igb_pf_host_configure(dev);
1362
1363         /* check and configure queue intr-vector mapping */
1364         if ((rte_intr_cap_multiple(intr_handle) ||
1365              !RTE_ETH_DEV_SRIOV(dev).active) &&
1366             dev->data->dev_conf.intr_conf.rxq != 0) {
1367                 intr_vector = dev->data->nb_rx_queues;
1368                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1369                         return -1;
1370         }
1371
1372         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1373                 intr_handle->intr_vec =
1374                         rte_zmalloc("intr_vec",
1375                                     dev->data->nb_rx_queues * sizeof(int), 0);
1376                 if (intr_handle->intr_vec == NULL) {
1377                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1378                                      " intr_vec", dev->data->nb_rx_queues);
1379                         return -ENOMEM;
1380                 }
1381         }
1382
1383         /* confiugre msix for rx interrupt */
1384         eth_igb_configure_msix_intr(dev);
1385
1386         /* Configure for OS presence */
1387         igb_init_manageability(hw);
1388
1389         eth_igb_tx_init(dev);
1390
1391         /* This can fail when allocating mbufs for descriptor rings */
1392         ret = eth_igb_rx_init(dev);
1393         if (ret) {
1394                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1395                 igb_dev_clear_queues(dev);
1396                 return ret;
1397         }
1398
1399         e1000_clear_hw_cntrs_base_generic(hw);
1400
1401         /*
1402          * VLAN Offload Settings
1403          */
1404         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1405                         ETH_VLAN_EXTEND_MASK;
1406         eth_igb_vlan_offload_set(dev, mask);
1407
1408         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1409                 /* Enable VLAN filter since VMDq always use VLAN filter */
1410                 igb_vmdq_vlan_hw_filter_enable(dev);
1411         }
1412
1413         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1414                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1415                 (hw->mac.type == e1000_i211)) {
1416                 /* Configure EITR with the maximum possible value (0xFFFF) */
1417                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1418         }
1419
1420         /* Setup link speed and duplex */
1421         speeds = &dev->data->dev_conf.link_speeds;
1422         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1423                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1424                 hw->mac.autoneg = 1;
1425         } else {
1426                 num_speeds = 0;
1427                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1428
1429                 /* Reset */
1430                 hw->phy.autoneg_advertised = 0;
1431
1432                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1433                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1434                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1435                         num_speeds = -1;
1436                         goto error_invalid_config;
1437                 }
1438                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1439                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1440                         num_speeds++;
1441                 }
1442                 if (*speeds & ETH_LINK_SPEED_10M) {
1443                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1444                         num_speeds++;
1445                 }
1446                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1447                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1448                         num_speeds++;
1449                 }
1450                 if (*speeds & ETH_LINK_SPEED_100M) {
1451                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1452                         num_speeds++;
1453                 }
1454                 if (*speeds & ETH_LINK_SPEED_1G) {
1455                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1456                         num_speeds++;
1457                 }
1458                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1459                         goto error_invalid_config;
1460
1461                 /* Set/reset the mac.autoneg based on the link speed,
1462                  * fixed or not
1463                  */
1464                 if (!autoneg) {
1465                         hw->mac.autoneg = 0;
1466                         hw->mac.forced_speed_duplex =
1467                                         hw->phy.autoneg_advertised;
1468                 } else {
1469                         hw->mac.autoneg = 1;
1470                 }
1471         }
1472
1473         e1000_setup_link(hw);
1474
1475         if (rte_intr_allow_others(intr_handle)) {
1476                 /* check if lsc interrupt is enabled */
1477                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1478                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1479                 else
1480                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1481         } else {
1482                 rte_intr_callback_unregister(intr_handle,
1483                                              eth_igb_interrupt_handler,
1484                                              (void *)dev);
1485                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1486                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1487                                      " no intr multiplex");
1488         }
1489
1490         /* check if rxq interrupt is enabled */
1491         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1492             rte_intr_dp_is_en(intr_handle))
1493                 eth_igb_rxq_interrupt_setup(dev);
1494
1495         /* enable uio/vfio intr/eventfd mapping */
1496         rte_intr_enable(intr_handle);
1497
1498         /* resume enabled intr since hw reset */
1499         igb_intr_enable(dev);
1500
1501         /* restore all types filter */
1502         igb_filter_restore(dev);
1503
1504         PMD_INIT_LOG(DEBUG, "<<");
1505
1506         return 0;
1507
1508 error_invalid_config:
1509         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1510                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1511         igb_dev_clear_queues(dev);
1512         return -EINVAL;
1513 }
1514
1515 /*********************************************************************
1516  *
1517  *  This routine disables all traffic on the adapter by issuing a
1518  *  global reset on the MAC.
1519  *
1520  **********************************************************************/
1521 static void
1522 eth_igb_stop(struct rte_eth_dev *dev)
1523 {
1524         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1525         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1526         struct rte_eth_link link;
1527         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1528
1529         igb_intr_disable(hw);
1530
1531         /* disable intr eventfd mapping */
1532         rte_intr_disable(intr_handle);
1533
1534         igb_pf_reset_hw(hw);
1535         E1000_WRITE_REG(hw, E1000_WUC, 0);
1536
1537         /* Set bit for Go Link disconnect */
1538         if (hw->mac.type >= e1000_82580) {
1539                 uint32_t phpm_reg;
1540
1541                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1542                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1543                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1544         }
1545
1546         /* Power down the phy. Needed to make the link go Down */
1547         eth_igb_dev_set_link_down(dev);
1548
1549         igb_dev_clear_queues(dev);
1550
1551         /* clear the recorded link status */
1552         memset(&link, 0, sizeof(link));
1553         rte_igb_dev_atomic_write_link_status(dev, &link);
1554
1555         if (!rte_intr_allow_others(intr_handle))
1556                 /* resume to the default handler */
1557                 rte_intr_callback_register(intr_handle,
1558                                            eth_igb_interrupt_handler,
1559                                            (void *)dev);
1560
1561         /* Clean datapath event and queue/vec mapping */
1562         rte_intr_efd_disable(intr_handle);
1563         if (intr_handle->intr_vec != NULL) {
1564                 rte_free(intr_handle->intr_vec);
1565                 intr_handle->intr_vec = NULL;
1566         }
1567 }
1568
1569 static int
1570 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1571 {
1572         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1573
1574         if (hw->phy.media_type == e1000_media_type_copper)
1575                 e1000_power_up_phy(hw);
1576         else
1577                 e1000_power_up_fiber_serdes_link(hw);
1578
1579         return 0;
1580 }
1581
1582 static int
1583 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1584 {
1585         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1586
1587         if (hw->phy.media_type == e1000_media_type_copper)
1588                 e1000_power_down_phy(hw);
1589         else
1590                 e1000_shutdown_fiber_serdes_link(hw);
1591
1592         return 0;
1593 }
1594
1595 static void
1596 eth_igb_close(struct rte_eth_dev *dev)
1597 {
1598         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599         struct e1000_adapter *adapter =
1600                 E1000_DEV_PRIVATE(dev->data->dev_private);
1601         struct rte_eth_link link;
1602         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1603         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1604
1605         eth_igb_stop(dev);
1606         adapter->stopped = 1;
1607
1608         e1000_phy_hw_reset(hw);
1609         igb_release_manageability(hw);
1610         igb_hw_control_release(hw);
1611
1612         /* Clear bit for Go Link disconnect */
1613         if (hw->mac.type >= e1000_82580) {
1614                 uint32_t phpm_reg;
1615
1616                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1617                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1618                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1619         }
1620
1621         igb_dev_free_queues(dev);
1622
1623         if (intr_handle->intr_vec) {
1624                 rte_free(intr_handle->intr_vec);
1625                 intr_handle->intr_vec = NULL;
1626         }
1627
1628         memset(&link, 0, sizeof(link));
1629         rte_igb_dev_atomic_write_link_status(dev, &link);
1630 }
1631
1632 static int
1633 igb_get_rx_buffer_size(struct e1000_hw *hw)
1634 {
1635         uint32_t rx_buf_size;
1636         if (hw->mac.type == e1000_82576) {
1637                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1638         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1639                 /* PBS needs to be translated according to a lookup table */
1640                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1641                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1642                 rx_buf_size = (rx_buf_size << 10);
1643         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1644                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1645         } else {
1646                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1647         }
1648
1649         return rx_buf_size;
1650 }
1651
1652 /*********************************************************************
1653  *
1654  *  Initialize the hardware
1655  *
1656  **********************************************************************/
1657 static int
1658 igb_hardware_init(struct e1000_hw *hw)
1659 {
1660         uint32_t rx_buf_size;
1661         int diag;
1662
1663         /* Let the firmware know the OS is in control */
1664         igb_hw_control_acquire(hw);
1665
1666         /*
1667          * These parameters control the automatic generation (Tx) and
1668          * response (Rx) to Ethernet PAUSE frames.
1669          * - High water mark should allow for at least two standard size (1518)
1670          *   frames to be received after sending an XOFF.
1671          * - Low water mark works best when it is very near the high water mark.
1672          *   This allows the receiver to restart by sending XON when it has
1673          *   drained a bit. Here we use an arbitrary value of 1500 which will
1674          *   restart after one full frame is pulled from the buffer. There
1675          *   could be several smaller frames in the buffer and if so they will
1676          *   not trigger the XON until their total number reduces the buffer
1677          *   by 1500.
1678          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1679          */
1680         rx_buf_size = igb_get_rx_buffer_size(hw);
1681
1682         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1683         hw->fc.low_water = hw->fc.high_water - 1500;
1684         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1685         hw->fc.send_xon = 1;
1686
1687         /* Set Flow control, use the tunable location if sane */
1688         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1689                 hw->fc.requested_mode = igb_fc_setting;
1690         else
1691                 hw->fc.requested_mode = e1000_fc_none;
1692
1693         /* Issue a global reset */
1694         igb_pf_reset_hw(hw);
1695         E1000_WRITE_REG(hw, E1000_WUC, 0);
1696
1697         diag = e1000_init_hw(hw);
1698         if (diag < 0)
1699                 return diag;
1700
1701         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1702         e1000_get_phy_info(hw);
1703         e1000_check_for_link(hw);
1704
1705         return 0;
1706 }
1707
1708 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1709 static void
1710 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1711 {
1712         int pause_frames;
1713
1714         uint64_t old_gprc  = stats->gprc;
1715         uint64_t old_gptc  = stats->gptc;
1716         uint64_t old_tpr   = stats->tpr;
1717         uint64_t old_tpt   = stats->tpt;
1718         uint64_t old_rpthc = stats->rpthc;
1719         uint64_t old_hgptc = stats->hgptc;
1720
1721         if(hw->phy.media_type == e1000_media_type_copper ||
1722             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1723                 stats->symerrs +=
1724                     E1000_READ_REG(hw,E1000_SYMERRS);
1725                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1726         }
1727
1728         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1729         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1730         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1731         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1732
1733         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1734         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1735         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1736         stats->dc += E1000_READ_REG(hw, E1000_DC);
1737         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1738         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1739         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1740         /*
1741         ** For watchdog management we need to know if we have been
1742         ** paused during the last interval, so capture that here.
1743         */
1744         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1745         stats->xoffrxc += pause_frames;
1746         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1747         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1748         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1749         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1750         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1751         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1752         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1753         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1754         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1755         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1756         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1757         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1758
1759         /* For the 64-bit byte counters the low dword must be read first. */
1760         /* Both registers clear on the read of the high dword */
1761
1762         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1763         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1764         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1765         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1766         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1767         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1768         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1769
1770         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1771         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1772         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1773         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1774         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1775
1776         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1777         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1778
1779         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1780         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1781         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1782         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1783         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1784         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1785
1786         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1787         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1788         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1789         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1790         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1791         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1792         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1793         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1794
1795         /* Interrupt Counts */
1796
1797         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1798         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1799         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1800         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1801         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1802         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1803         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1804         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1805         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1806
1807         /* Host to Card Statistics */
1808
1809         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1810         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1811         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1812         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1813         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1814         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1815         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1816         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1817         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1818         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1819         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1820         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1821         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1822         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1823         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1824         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1825
1826         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1827         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1828         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1829         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1830         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1831         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1832 }
1833
1834 static int
1835 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1836 {
1837         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1838         struct e1000_hw_stats *stats =
1839                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1840
1841         igb_read_stats_registers(hw, stats);
1842
1843         if (rte_stats == NULL)
1844                 return -EINVAL;
1845
1846         /* Rx Errors */
1847         rte_stats->imissed = stats->mpc;
1848         rte_stats->ierrors = stats->crcerrs +
1849                              stats->rlec + stats->ruc + stats->roc +
1850                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1851
1852         /* Tx Errors */
1853         rte_stats->oerrors = stats->ecol + stats->latecol;
1854
1855         rte_stats->ipackets = stats->gprc;
1856         rte_stats->opackets = stats->gptc;
1857         rte_stats->ibytes   = stats->gorc;
1858         rte_stats->obytes   = stats->gotc;
1859         return 0;
1860 }
1861
1862 static void
1863 eth_igb_stats_reset(struct rte_eth_dev *dev)
1864 {
1865         struct e1000_hw_stats *hw_stats =
1866                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1867
1868         /* HW registers are cleared on read */
1869         eth_igb_stats_get(dev, NULL);
1870
1871         /* Reset software totals */
1872         memset(hw_stats, 0, sizeof(*hw_stats));
1873 }
1874
1875 static void
1876 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1877 {
1878         struct e1000_hw_stats *stats =
1879                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1880
1881         /* HW registers are cleared on read */
1882         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1883
1884         /* Reset software totals */
1885         memset(stats, 0, sizeof(*stats));
1886 }
1887
1888 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1889         struct rte_eth_xstat_name *xstats_names,
1890         __rte_unused unsigned int size)
1891 {
1892         unsigned i;
1893
1894         if (xstats_names == NULL)
1895                 return IGB_NB_XSTATS;
1896
1897         /* Note: limit checked in rte_eth_xstats_names() */
1898
1899         for (i = 0; i < IGB_NB_XSTATS; i++) {
1900                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1901                          "%s", rte_igb_stats_strings[i].name);
1902         }
1903
1904         return IGB_NB_XSTATS;
1905 }
1906
1907 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1908                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1909                 unsigned int limit)
1910 {
1911         unsigned int i;
1912
1913         if (!ids) {
1914                 if (xstats_names == NULL)
1915                         return IGB_NB_XSTATS;
1916
1917                 for (i = 0; i < IGB_NB_XSTATS; i++)
1918                         snprintf(xstats_names[i].name,
1919                                         sizeof(xstats_names[i].name),
1920                                         "%s", rte_igb_stats_strings[i].name);
1921
1922                 return IGB_NB_XSTATS;
1923
1924         } else {
1925                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1926
1927                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1928                                 IGB_NB_XSTATS);
1929
1930                 for (i = 0; i < limit; i++) {
1931                         if (ids[i] >= IGB_NB_XSTATS) {
1932                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1933                                 return -1;
1934                         }
1935                         strcpy(xstats_names[i].name,
1936                                         xstats_names_copy[ids[i]].name);
1937                 }
1938                 return limit;
1939         }
1940 }
1941
1942 static int
1943 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1944                    unsigned n)
1945 {
1946         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1947         struct e1000_hw_stats *hw_stats =
1948                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1949         unsigned i;
1950
1951         if (n < IGB_NB_XSTATS)
1952                 return IGB_NB_XSTATS;
1953
1954         igb_read_stats_registers(hw, hw_stats);
1955
1956         /* If this is a reset xstats is NULL, and we have cleared the
1957          * registers by reading them.
1958          */
1959         if (!xstats)
1960                 return 0;
1961
1962         /* Extended stats */
1963         for (i = 0; i < IGB_NB_XSTATS; i++) {
1964                 xstats[i].id = i;
1965                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1966                         rte_igb_stats_strings[i].offset);
1967         }
1968
1969         return IGB_NB_XSTATS;
1970 }
1971
1972 static int
1973 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1974                 uint64_t *values, unsigned int n)
1975 {
1976         unsigned int i;
1977
1978         if (!ids) {
1979                 struct e1000_hw *hw =
1980                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1981                 struct e1000_hw_stats *hw_stats =
1982                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1983
1984                 if (n < IGB_NB_XSTATS)
1985                         return IGB_NB_XSTATS;
1986
1987                 igb_read_stats_registers(hw, hw_stats);
1988
1989                 /* If this is a reset xstats is NULL, and we have cleared the
1990                  * registers by reading them.
1991                  */
1992                 if (!values)
1993                         return 0;
1994
1995                 /* Extended stats */
1996                 for (i = 0; i < IGB_NB_XSTATS; i++)
1997                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1998                                         rte_igb_stats_strings[i].offset);
1999
2000                 return IGB_NB_XSTATS;
2001
2002         } else {
2003                 uint64_t values_copy[IGB_NB_XSTATS];
2004
2005                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2006                                 IGB_NB_XSTATS);
2007
2008                 for (i = 0; i < n; i++) {
2009                         if (ids[i] >= IGB_NB_XSTATS) {
2010                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2011                                 return -1;
2012                         }
2013                         values[i] = values_copy[ids[i]];
2014                 }
2015                 return n;
2016         }
2017 }
2018
2019 static void
2020 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2021 {
2022         /* Good Rx packets, include VF loopback */
2023         UPDATE_VF_STAT(E1000_VFGPRC,
2024             hw_stats->last_gprc, hw_stats->gprc);
2025
2026         /* Good Rx octets, include VF loopback */
2027         UPDATE_VF_STAT(E1000_VFGORC,
2028             hw_stats->last_gorc, hw_stats->gorc);
2029
2030         /* Good Tx packets, include VF loopback */
2031         UPDATE_VF_STAT(E1000_VFGPTC,
2032             hw_stats->last_gptc, hw_stats->gptc);
2033
2034         /* Good Tx octets, include VF loopback */
2035         UPDATE_VF_STAT(E1000_VFGOTC,
2036             hw_stats->last_gotc, hw_stats->gotc);
2037
2038         /* Rx Multicst packets */
2039         UPDATE_VF_STAT(E1000_VFMPRC,
2040             hw_stats->last_mprc, hw_stats->mprc);
2041
2042         /* Good Rx loopback packets */
2043         UPDATE_VF_STAT(E1000_VFGPRLBC,
2044             hw_stats->last_gprlbc, hw_stats->gprlbc);
2045
2046         /* Good Rx loopback octets */
2047         UPDATE_VF_STAT(E1000_VFGORLBC,
2048             hw_stats->last_gorlbc, hw_stats->gorlbc);
2049
2050         /* Good Tx loopback packets */
2051         UPDATE_VF_STAT(E1000_VFGPTLBC,
2052             hw_stats->last_gptlbc, hw_stats->gptlbc);
2053
2054         /* Good Tx loopback octets */
2055         UPDATE_VF_STAT(E1000_VFGOTLBC,
2056             hw_stats->last_gotlbc, hw_stats->gotlbc);
2057 }
2058
2059 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2060                                      struct rte_eth_xstat_name *xstats_names,
2061                                      __rte_unused unsigned limit)
2062 {
2063         unsigned i;
2064
2065         if (xstats_names != NULL)
2066                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2067                         snprintf(xstats_names[i].name,
2068                                 sizeof(xstats_names[i].name), "%s",
2069                                 rte_igbvf_stats_strings[i].name);
2070                 }
2071         return IGBVF_NB_XSTATS;
2072 }
2073
2074 static int
2075 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2076                      unsigned n)
2077 {
2078         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2080                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2081         unsigned i;
2082
2083         if (n < IGBVF_NB_XSTATS)
2084                 return IGBVF_NB_XSTATS;
2085
2086         igbvf_read_stats_registers(hw, hw_stats);
2087
2088         if (!xstats)
2089                 return 0;
2090
2091         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2092                 xstats[i].id = i;
2093                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2094                         rte_igbvf_stats_strings[i].offset);
2095         }
2096
2097         return IGBVF_NB_XSTATS;
2098 }
2099
2100 static int
2101 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2102 {
2103         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2104         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2105                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2106
2107         igbvf_read_stats_registers(hw, hw_stats);
2108
2109         if (rte_stats == NULL)
2110                 return -EINVAL;
2111
2112         rte_stats->ipackets = hw_stats->gprc;
2113         rte_stats->ibytes = hw_stats->gorc;
2114         rte_stats->opackets = hw_stats->gptc;
2115         rte_stats->obytes = hw_stats->gotc;
2116         return 0;
2117 }
2118
2119 static void
2120 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2121 {
2122         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2123                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2124
2125         /* Sync HW register to the last stats */
2126         eth_igbvf_stats_get(dev, NULL);
2127
2128         /* reset HW current stats*/
2129         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2130                offsetof(struct e1000_vf_stats, gprc));
2131 }
2132
2133 static int
2134 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2135                        size_t fw_size)
2136 {
2137         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2138         struct e1000_fw_version fw;
2139         int ret;
2140
2141         e1000_get_fw_version(hw, &fw);
2142
2143         switch (hw->mac.type) {
2144         case e1000_i210:
2145         case e1000_i211:
2146                 if (!(e1000_get_flash_presence_i210(hw))) {
2147                         ret = snprintf(fw_version, fw_size,
2148                                  "%2d.%2d-%d",
2149                                  fw.invm_major, fw.invm_minor,
2150                                  fw.invm_img_type);
2151                         break;
2152                 }
2153                 /* fall through */
2154         default:
2155                 /* if option rom is valid, display its version too */
2156                 if (fw.or_valid) {
2157                         ret = snprintf(fw_version, fw_size,
2158                                  "%d.%d, 0x%08x, %d.%d.%d",
2159                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2160                                  fw.or_major, fw.or_build, fw.or_patch);
2161                 /* no option rom */
2162                 } else {
2163                         if (fw.etrack_id != 0X0000) {
2164                                 ret = snprintf(fw_version, fw_size,
2165                                          "%d.%d, 0x%08x",
2166                                          fw.eep_major, fw.eep_minor,
2167                                          fw.etrack_id);
2168                         } else {
2169                                 ret = snprintf(fw_version, fw_size,
2170                                          "%d.%d.%d",
2171                                          fw.eep_major, fw.eep_minor,
2172                                          fw.eep_build);
2173                         }
2174                 }
2175                 break;
2176         }
2177
2178         ret += 1; /* add the size of '\0' */
2179         if (fw_size < (u32)ret)
2180                 return ret;
2181         else
2182                 return 0;
2183 }
2184
2185 static void
2186 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2187 {
2188         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2189
2190         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2191         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2192         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2193         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2194         dev_info->rx_offload_capa =
2195                 DEV_RX_OFFLOAD_VLAN_STRIP |
2196                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2197                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2198                 DEV_RX_OFFLOAD_TCP_CKSUM;
2199         dev_info->tx_offload_capa =
2200                 DEV_TX_OFFLOAD_VLAN_INSERT |
2201                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2202                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2203                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2204                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2205                 DEV_TX_OFFLOAD_TCP_TSO;
2206
2207         switch (hw->mac.type) {
2208         case e1000_82575:
2209                 dev_info->max_rx_queues = 4;
2210                 dev_info->max_tx_queues = 4;
2211                 dev_info->max_vmdq_pools = 0;
2212                 break;
2213
2214         case e1000_82576:
2215                 dev_info->max_rx_queues = 16;
2216                 dev_info->max_tx_queues = 16;
2217                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2218                 dev_info->vmdq_queue_num = 16;
2219                 break;
2220
2221         case e1000_82580:
2222                 dev_info->max_rx_queues = 8;
2223                 dev_info->max_tx_queues = 8;
2224                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2225                 dev_info->vmdq_queue_num = 8;
2226                 break;
2227
2228         case e1000_i350:
2229                 dev_info->max_rx_queues = 8;
2230                 dev_info->max_tx_queues = 8;
2231                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2232                 dev_info->vmdq_queue_num = 8;
2233                 break;
2234
2235         case e1000_i354:
2236                 dev_info->max_rx_queues = 8;
2237                 dev_info->max_tx_queues = 8;
2238                 break;
2239
2240         case e1000_i210:
2241                 dev_info->max_rx_queues = 4;
2242                 dev_info->max_tx_queues = 4;
2243                 dev_info->max_vmdq_pools = 0;
2244                 break;
2245
2246         case e1000_i211:
2247                 dev_info->max_rx_queues = 2;
2248                 dev_info->max_tx_queues = 2;
2249                 dev_info->max_vmdq_pools = 0;
2250                 break;
2251
2252         default:
2253                 /* Should not happen */
2254                 break;
2255         }
2256         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2257         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2258         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2259
2260         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2261                 .rx_thresh = {
2262                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2263                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2264                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2265                 },
2266                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2267                 .rx_drop_en = 0,
2268         };
2269
2270         dev_info->default_txconf = (struct rte_eth_txconf) {
2271                 .tx_thresh = {
2272                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2273                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2274                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2275                 },
2276                 .txq_flags = 0,
2277         };
2278
2279         dev_info->rx_desc_lim = rx_desc_lim;
2280         dev_info->tx_desc_lim = tx_desc_lim;
2281
2282         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2283                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2284                         ETH_LINK_SPEED_1G;
2285 }
2286
2287 static const uint32_t *
2288 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2289 {
2290         static const uint32_t ptypes[] = {
2291                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2292                 RTE_PTYPE_L2_ETHER,
2293                 RTE_PTYPE_L3_IPV4,
2294                 RTE_PTYPE_L3_IPV4_EXT,
2295                 RTE_PTYPE_L3_IPV6,
2296                 RTE_PTYPE_L3_IPV6_EXT,
2297                 RTE_PTYPE_L4_TCP,
2298                 RTE_PTYPE_L4_UDP,
2299                 RTE_PTYPE_L4_SCTP,
2300                 RTE_PTYPE_TUNNEL_IP,
2301                 RTE_PTYPE_INNER_L3_IPV6,
2302                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2303                 RTE_PTYPE_INNER_L4_TCP,
2304                 RTE_PTYPE_INNER_L4_UDP,
2305                 RTE_PTYPE_UNKNOWN
2306         };
2307
2308         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2309             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2310                 return ptypes;
2311         return NULL;
2312 }
2313
2314 static void
2315 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2316 {
2317         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2318
2319         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2320         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2321         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2322         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2323         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2324                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2325                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2326                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2327         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2328                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2329                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2330                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2331                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2332                                 DEV_TX_OFFLOAD_TCP_TSO;
2333         switch (hw->mac.type) {
2334         case e1000_vfadapt:
2335                 dev_info->max_rx_queues = 2;
2336                 dev_info->max_tx_queues = 2;
2337                 break;
2338         case e1000_vfadapt_i350:
2339                 dev_info->max_rx_queues = 1;
2340                 dev_info->max_tx_queues = 1;
2341                 break;
2342         default:
2343                 /* Should not happen */
2344                 break;
2345         }
2346
2347         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2348                 .rx_thresh = {
2349                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2350                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2351                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2352                 },
2353                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2354                 .rx_drop_en = 0,
2355         };
2356
2357         dev_info->default_txconf = (struct rte_eth_txconf) {
2358                 .tx_thresh = {
2359                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2360                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2361                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2362                 },
2363                 .txq_flags = 0,
2364         };
2365
2366         dev_info->rx_desc_lim = rx_desc_lim;
2367         dev_info->tx_desc_lim = tx_desc_lim;
2368 }
2369
2370 /* return 0 means link status changed, -1 means not changed */
2371 static int
2372 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2373 {
2374         struct e1000_hw *hw =
2375                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2376         struct rte_eth_link link, old;
2377         int link_check, count;
2378
2379         link_check = 0;
2380         hw->mac.get_link_status = 1;
2381
2382         /* possible wait-to-complete in up to 9 seconds */
2383         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2384                 /* Read the real link status */
2385                 switch (hw->phy.media_type) {
2386                 case e1000_media_type_copper:
2387                         /* Do the work to read phy */
2388                         e1000_check_for_link(hw);
2389                         link_check = !hw->mac.get_link_status;
2390                         break;
2391
2392                 case e1000_media_type_fiber:
2393                         e1000_check_for_link(hw);
2394                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2395                                       E1000_STATUS_LU);
2396                         break;
2397
2398                 case e1000_media_type_internal_serdes:
2399                         e1000_check_for_link(hw);
2400                         link_check = hw->mac.serdes_has_link;
2401                         break;
2402
2403                 /* VF device is type_unknown */
2404                 case e1000_media_type_unknown:
2405                         eth_igbvf_link_update(hw);
2406                         link_check = !hw->mac.get_link_status;
2407                         break;
2408
2409                 default:
2410                         break;
2411                 }
2412                 if (link_check || wait_to_complete == 0)
2413                         break;
2414                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2415         }
2416         memset(&link, 0, sizeof(link));
2417         rte_igb_dev_atomic_read_link_status(dev, &link);
2418         old = link;
2419
2420         /* Now we check if a transition has happened */
2421         if (link_check) {
2422                 uint16_t duplex, speed;
2423                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2424                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2425                                 ETH_LINK_FULL_DUPLEX :
2426                                 ETH_LINK_HALF_DUPLEX;
2427                 link.link_speed = speed;
2428                 link.link_status = ETH_LINK_UP;
2429                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2430                                 ETH_LINK_SPEED_FIXED);
2431         } else if (!link_check) {
2432                 link.link_speed = 0;
2433                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2434                 link.link_status = ETH_LINK_DOWN;
2435                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2436         }
2437         rte_igb_dev_atomic_write_link_status(dev, &link);
2438
2439         /* not changed */
2440         if (old.link_status == link.link_status)
2441                 return -1;
2442
2443         /* changed */
2444         return 0;
2445 }
2446
2447 /*
2448  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2449  * For ASF and Pass Through versions of f/w this means
2450  * that the driver is loaded.
2451  */
2452 static void
2453 igb_hw_control_acquire(struct e1000_hw *hw)
2454 {
2455         uint32_t ctrl_ext;
2456
2457         /* Let firmware know the driver has taken over */
2458         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2459         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2460 }
2461
2462 /*
2463  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2464  * For ASF and Pass Through versions of f/w this means that the
2465  * driver is no longer loaded.
2466  */
2467 static void
2468 igb_hw_control_release(struct e1000_hw *hw)
2469 {
2470         uint32_t ctrl_ext;
2471
2472         /* Let firmware taken over control of h/w */
2473         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2474         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2475                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2476 }
2477
2478 /*
2479  * Bit of a misnomer, what this really means is
2480  * to enable OS management of the system... aka
2481  * to disable special hardware management features.
2482  */
2483 static void
2484 igb_init_manageability(struct e1000_hw *hw)
2485 {
2486         if (e1000_enable_mng_pass_thru(hw)) {
2487                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2488                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2489
2490                 /* disable hardware interception of ARP */
2491                 manc &= ~(E1000_MANC_ARP_EN);
2492
2493                 /* enable receiving management packets to the host */
2494                 manc |= E1000_MANC_EN_MNG2HOST;
2495                 manc2h |= 1 << 5;  /* Mng Port 623 */
2496                 manc2h |= 1 << 6;  /* Mng Port 664 */
2497                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2498                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2499         }
2500 }
2501
2502 static void
2503 igb_release_manageability(struct e1000_hw *hw)
2504 {
2505         if (e1000_enable_mng_pass_thru(hw)) {
2506                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2507
2508                 manc |= E1000_MANC_ARP_EN;
2509                 manc &= ~E1000_MANC_EN_MNG2HOST;
2510
2511                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2512         }
2513 }
2514
2515 static void
2516 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2517 {
2518         struct e1000_hw *hw =
2519                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2520         uint32_t rctl;
2521
2522         rctl = E1000_READ_REG(hw, E1000_RCTL);
2523         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2524         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2525 }
2526
2527 static void
2528 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2529 {
2530         struct e1000_hw *hw =
2531                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2532         uint32_t rctl;
2533
2534         rctl = E1000_READ_REG(hw, E1000_RCTL);
2535         rctl &= (~E1000_RCTL_UPE);
2536         if (dev->data->all_multicast == 1)
2537                 rctl |= E1000_RCTL_MPE;
2538         else
2539                 rctl &= (~E1000_RCTL_MPE);
2540         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2541 }
2542
2543 static void
2544 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2545 {
2546         struct e1000_hw *hw =
2547                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2548         uint32_t rctl;
2549
2550         rctl = E1000_READ_REG(hw, E1000_RCTL);
2551         rctl |= E1000_RCTL_MPE;
2552         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2553 }
2554
2555 static void
2556 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2557 {
2558         struct e1000_hw *hw =
2559                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2560         uint32_t rctl;
2561
2562         if (dev->data->promiscuous == 1)
2563                 return; /* must remain in all_multicast mode */
2564         rctl = E1000_READ_REG(hw, E1000_RCTL);
2565         rctl &= (~E1000_RCTL_MPE);
2566         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2567 }
2568
2569 static int
2570 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2571 {
2572         struct e1000_hw *hw =
2573                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2574         struct e1000_vfta * shadow_vfta =
2575                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2576         uint32_t vfta;
2577         uint32_t vid_idx;
2578         uint32_t vid_bit;
2579
2580         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2581                               E1000_VFTA_ENTRY_MASK);
2582         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2583         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2584         if (on)
2585                 vfta |= vid_bit;
2586         else
2587                 vfta &= ~vid_bit;
2588         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2589
2590         /* update local VFTA copy */
2591         shadow_vfta->vfta[vid_idx] = vfta;
2592
2593         return 0;
2594 }
2595
2596 static int
2597 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2598                       enum rte_vlan_type vlan_type,
2599                       uint16_t tpid)
2600 {
2601         struct e1000_hw *hw =
2602                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2603         uint32_t reg, qinq;
2604
2605         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2606         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2607
2608         /* only outer TPID of double VLAN can be configured*/
2609         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2610                 reg = E1000_READ_REG(hw, E1000_VET);
2611                 reg = (reg & (~E1000_VET_VET_EXT)) |
2612                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2613                 E1000_WRITE_REG(hw, E1000_VET, reg);
2614
2615                 return 0;
2616         }
2617
2618         /* all other TPID values are read-only*/
2619         PMD_DRV_LOG(ERR, "Not supported");
2620
2621         return -ENOTSUP;
2622 }
2623
2624 static void
2625 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2626 {
2627         struct e1000_hw *hw =
2628                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2629         uint32_t reg;
2630
2631         /* Filter Table Disable */
2632         reg = E1000_READ_REG(hw, E1000_RCTL);
2633         reg &= ~E1000_RCTL_CFIEN;
2634         reg &= ~E1000_RCTL_VFE;
2635         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2636 }
2637
2638 static void
2639 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2640 {
2641         struct e1000_hw *hw =
2642                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2643         struct e1000_vfta * shadow_vfta =
2644                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2645         uint32_t reg;
2646         int i;
2647
2648         /* Filter Table Enable, CFI not used for packet acceptance */
2649         reg = E1000_READ_REG(hw, E1000_RCTL);
2650         reg &= ~E1000_RCTL_CFIEN;
2651         reg |= E1000_RCTL_VFE;
2652         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2653
2654         /* restore VFTA table */
2655         for (i = 0; i < IGB_VFTA_SIZE; i++)
2656                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2657 }
2658
2659 static void
2660 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2661 {
2662         struct e1000_hw *hw =
2663                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2664         uint32_t reg;
2665
2666         /* VLAN Mode Disable */
2667         reg = E1000_READ_REG(hw, E1000_CTRL);
2668         reg &= ~E1000_CTRL_VME;
2669         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2670 }
2671
2672 static void
2673 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2674 {
2675         struct e1000_hw *hw =
2676                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2677         uint32_t reg;
2678
2679         /* VLAN Mode Enable */
2680         reg = E1000_READ_REG(hw, E1000_CTRL);
2681         reg |= E1000_CTRL_VME;
2682         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2683 }
2684
2685 static void
2686 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2687 {
2688         struct e1000_hw *hw =
2689                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2690         uint32_t reg;
2691
2692         /* CTRL_EXT: Extended VLAN */
2693         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2694         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2695         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2696
2697         /* Update maximum packet length */
2698         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2699                 E1000_WRITE_REG(hw, E1000_RLPML,
2700                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2701                                                 VLAN_TAG_SIZE);
2702 }
2703
2704 static void
2705 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2706 {
2707         struct e1000_hw *hw =
2708                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2709         uint32_t reg;
2710
2711         /* CTRL_EXT: Extended VLAN */
2712         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2713         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2714         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2715
2716         /* Update maximum packet length */
2717         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2718                 E1000_WRITE_REG(hw, E1000_RLPML,
2719                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2720                                                 2 * VLAN_TAG_SIZE);
2721 }
2722
2723 static void
2724 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2725 {
2726         if(mask & ETH_VLAN_STRIP_MASK){
2727                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2728                         igb_vlan_hw_strip_enable(dev);
2729                 else
2730                         igb_vlan_hw_strip_disable(dev);
2731         }
2732
2733         if(mask & ETH_VLAN_FILTER_MASK){
2734                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2735                         igb_vlan_hw_filter_enable(dev);
2736                 else
2737                         igb_vlan_hw_filter_disable(dev);
2738         }
2739
2740         if(mask & ETH_VLAN_EXTEND_MASK){
2741                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2742                         igb_vlan_hw_extend_enable(dev);
2743                 else
2744                         igb_vlan_hw_extend_disable(dev);
2745         }
2746 }
2747
2748
2749 /**
2750  * It enables the interrupt mask and then enable the interrupt.
2751  *
2752  * @param dev
2753  *  Pointer to struct rte_eth_dev.
2754  * @param on
2755  *  Enable or Disable
2756  *
2757  * @return
2758  *  - On success, zero.
2759  *  - On failure, a negative value.
2760  */
2761 static int
2762 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2763 {
2764         struct e1000_interrupt *intr =
2765                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2766
2767         if (on)
2768                 intr->mask |= E1000_ICR_LSC;
2769         else
2770                 intr->mask &= ~E1000_ICR_LSC;
2771
2772         return 0;
2773 }
2774
2775 /* It clears the interrupt causes and enables the interrupt.
2776  * It will be called once only during nic initialized.
2777  *
2778  * @param dev
2779  *  Pointer to struct rte_eth_dev.
2780  *
2781  * @return
2782  *  - On success, zero.
2783  *  - On failure, a negative value.
2784  */
2785 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2786 {
2787         uint32_t mask, regval;
2788         struct e1000_hw *hw =
2789                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2790         struct rte_eth_dev_info dev_info;
2791
2792         memset(&dev_info, 0, sizeof(dev_info));
2793         eth_igb_infos_get(dev, &dev_info);
2794
2795         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2796         regval = E1000_READ_REG(hw, E1000_EIMS);
2797         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2798
2799         return 0;
2800 }
2801
2802 /*
2803  * It reads ICR and gets interrupt causes, check it and set a bit flag
2804  * to update link status.
2805  *
2806  * @param dev
2807  *  Pointer to struct rte_eth_dev.
2808  *
2809  * @return
2810  *  - On success, zero.
2811  *  - On failure, a negative value.
2812  */
2813 static int
2814 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2815 {
2816         uint32_t icr;
2817         struct e1000_hw *hw =
2818                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2819         struct e1000_interrupt *intr =
2820                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2821
2822         igb_intr_disable(hw);
2823
2824         /* read-on-clear nic registers here */
2825         icr = E1000_READ_REG(hw, E1000_ICR);
2826
2827         intr->flags = 0;
2828         if (icr & E1000_ICR_LSC) {
2829                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2830         }
2831
2832         if (icr & E1000_ICR_VMMB)
2833                 intr->flags |= E1000_FLAG_MAILBOX;
2834
2835         return 0;
2836 }
2837
2838 /*
2839  * It executes link_update after knowing an interrupt is prsent.
2840  *
2841  * @param dev
2842  *  Pointer to struct rte_eth_dev.
2843  *
2844  * @return
2845  *  - On success, zero.
2846  *  - On failure, a negative value.
2847  */
2848 static int
2849 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2850                          struct rte_intr_handle *intr_handle)
2851 {
2852         struct e1000_hw *hw =
2853                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2854         struct e1000_interrupt *intr =
2855                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2856         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2857         uint32_t tctl, rctl;
2858         struct rte_eth_link link;
2859         int ret;
2860
2861         if (intr->flags & E1000_FLAG_MAILBOX) {
2862                 igb_pf_mbx_process(dev);
2863                 intr->flags &= ~E1000_FLAG_MAILBOX;
2864         }
2865
2866         igb_intr_enable(dev);
2867         rte_intr_enable(intr_handle);
2868
2869         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2870                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2871
2872                 /* set get_link_status to check register later */
2873                 hw->mac.get_link_status = 1;
2874                 ret = eth_igb_link_update(dev, 0);
2875
2876                 /* check if link has changed */
2877                 if (ret < 0)
2878                         return 0;
2879
2880                 memset(&link, 0, sizeof(link));
2881                 rte_igb_dev_atomic_read_link_status(dev, &link);
2882                 if (link.link_status) {
2883                         PMD_INIT_LOG(INFO,
2884                                      " Port %d: Link Up - speed %u Mbps - %s",
2885                                      dev->data->port_id,
2886                                      (unsigned)link.link_speed,
2887                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2888                                      "full-duplex" : "half-duplex");
2889                 } else {
2890                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2891                                      dev->data->port_id);
2892                 }
2893
2894                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2895                              pci_dev->addr.domain,
2896                              pci_dev->addr.bus,
2897                              pci_dev->addr.devid,
2898                              pci_dev->addr.function);
2899                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2900                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2901                 if (link.link_status) {
2902                         /* enable Tx/Rx */
2903                         tctl |= E1000_TCTL_EN;
2904                         rctl |= E1000_RCTL_EN;
2905                 } else {
2906                         /* disable Tx/Rx */
2907                         tctl &= ~E1000_TCTL_EN;
2908                         rctl &= ~E1000_RCTL_EN;
2909                 }
2910                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2911                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2912                 E1000_WRITE_FLUSH(hw);
2913                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2914                                               NULL, NULL);
2915         }
2916
2917         return 0;
2918 }
2919
2920 /**
2921  * Interrupt handler which shall be registered at first.
2922  *
2923  * @param handle
2924  *  Pointer to interrupt handle.
2925  * @param param
2926  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2927  *
2928  * @return
2929  *  void
2930  */
2931 static void
2932 eth_igb_interrupt_handler(void *param)
2933 {
2934         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2935
2936         eth_igb_interrupt_get_status(dev);
2937         eth_igb_interrupt_action(dev, dev->intr_handle);
2938 }
2939
2940 static int
2941 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2942 {
2943         uint32_t eicr;
2944         struct e1000_hw *hw =
2945                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2946         struct e1000_interrupt *intr =
2947                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2948
2949         igbvf_intr_disable(hw);
2950
2951         /* read-on-clear nic registers here */
2952         eicr = E1000_READ_REG(hw, E1000_EICR);
2953         intr->flags = 0;
2954
2955         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2956                 intr->flags |= E1000_FLAG_MAILBOX;
2957
2958         return 0;
2959 }
2960
2961 void igbvf_mbx_process(struct rte_eth_dev *dev)
2962 {
2963         struct e1000_hw *hw =
2964                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2965         struct e1000_mbx_info *mbx = &hw->mbx;
2966         u32 in_msg = 0;
2967
2968         if (mbx->ops.read(hw, &in_msg, 1, 0))
2969                 return;
2970
2971         /* PF reset VF event */
2972         if (in_msg == E1000_PF_CONTROL_MSG)
2973                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2974                                               NULL, NULL);
2975 }
2976
2977 static int
2978 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2979 {
2980         struct e1000_interrupt *intr =
2981                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2982
2983         if (intr->flags & E1000_FLAG_MAILBOX) {
2984                 igbvf_mbx_process(dev);
2985                 intr->flags &= ~E1000_FLAG_MAILBOX;
2986         }
2987
2988         igbvf_intr_enable(dev);
2989         rte_intr_enable(intr_handle);
2990
2991         return 0;
2992 }
2993
2994 static void
2995 eth_igbvf_interrupt_handler(void *param)
2996 {
2997         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2998
2999         eth_igbvf_interrupt_get_status(dev);
3000         eth_igbvf_interrupt_action(dev, dev->intr_handle);
3001 }
3002
3003 static int
3004 eth_igb_led_on(struct rte_eth_dev *dev)
3005 {
3006         struct e1000_hw *hw;
3007
3008         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3009         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3010 }
3011
3012 static int
3013 eth_igb_led_off(struct rte_eth_dev *dev)
3014 {
3015         struct e1000_hw *hw;
3016
3017         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3018         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3019 }
3020
3021 static int
3022 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3023 {
3024         struct e1000_hw *hw;
3025         uint32_t ctrl;
3026         int tx_pause;
3027         int rx_pause;
3028
3029         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3030         fc_conf->pause_time = hw->fc.pause_time;
3031         fc_conf->high_water = hw->fc.high_water;
3032         fc_conf->low_water = hw->fc.low_water;
3033         fc_conf->send_xon = hw->fc.send_xon;
3034         fc_conf->autoneg = hw->mac.autoneg;
3035
3036         /*
3037          * Return rx_pause and tx_pause status according to actual setting of
3038          * the TFCE and RFCE bits in the CTRL register.
3039          */
3040         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3041         if (ctrl & E1000_CTRL_TFCE)
3042                 tx_pause = 1;
3043         else
3044                 tx_pause = 0;
3045
3046         if (ctrl & E1000_CTRL_RFCE)
3047                 rx_pause = 1;
3048         else
3049                 rx_pause = 0;
3050
3051         if (rx_pause && tx_pause)
3052                 fc_conf->mode = RTE_FC_FULL;
3053         else if (rx_pause)
3054                 fc_conf->mode = RTE_FC_RX_PAUSE;
3055         else if (tx_pause)
3056                 fc_conf->mode = RTE_FC_TX_PAUSE;
3057         else
3058                 fc_conf->mode = RTE_FC_NONE;
3059
3060         return 0;
3061 }
3062
3063 static int
3064 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3065 {
3066         struct e1000_hw *hw;
3067         int err;
3068         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3069                 e1000_fc_none,
3070                 e1000_fc_rx_pause,
3071                 e1000_fc_tx_pause,
3072                 e1000_fc_full
3073         };
3074         uint32_t rx_buf_size;
3075         uint32_t max_high_water;
3076         uint32_t rctl;
3077
3078         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3079         if (fc_conf->autoneg != hw->mac.autoneg)
3080                 return -ENOTSUP;
3081         rx_buf_size = igb_get_rx_buffer_size(hw);
3082         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3083
3084         /* At least reserve one Ethernet frame for watermark */
3085         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3086         if ((fc_conf->high_water > max_high_water) ||
3087             (fc_conf->high_water < fc_conf->low_water)) {
3088                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3089                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3090                 return -EINVAL;
3091         }
3092
3093         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3094         hw->fc.pause_time     = fc_conf->pause_time;
3095         hw->fc.high_water     = fc_conf->high_water;
3096         hw->fc.low_water      = fc_conf->low_water;
3097         hw->fc.send_xon       = fc_conf->send_xon;
3098
3099         err = e1000_setup_link_generic(hw);
3100         if (err == E1000_SUCCESS) {
3101
3102                 /* check if we want to forward MAC frames - driver doesn't have native
3103                  * capability to do that, so we'll write the registers ourselves */
3104
3105                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3106
3107                 /* set or clear MFLCN.PMCF bit depending on configuration */
3108                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3109                         rctl |= E1000_RCTL_PMCF;
3110                 else
3111                         rctl &= ~E1000_RCTL_PMCF;
3112
3113                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3114                 E1000_WRITE_FLUSH(hw);
3115
3116                 return 0;
3117         }
3118
3119         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3120         return -EIO;
3121 }
3122
3123 #define E1000_RAH_POOLSEL_SHIFT      (18)
3124 static int
3125 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3126                 uint32_t index, uint32_t pool)
3127 {
3128         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3129         uint32_t rah;
3130
3131         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3132         rah = E1000_READ_REG(hw, E1000_RAH(index));
3133         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3134         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3135         return 0;
3136 }
3137
3138 static void
3139 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3140 {
3141         uint8_t addr[ETHER_ADDR_LEN];
3142         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3143
3144         memset(addr, 0, sizeof(addr));
3145
3146         e1000_rar_set(hw, addr, index);
3147 }
3148
3149 static void
3150 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3151                                 struct ether_addr *addr)
3152 {
3153         eth_igb_rar_clear(dev, 0);
3154
3155         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3156 }
3157 /*
3158  * Virtual Function operations
3159  */
3160 static void
3161 igbvf_intr_disable(struct e1000_hw *hw)
3162 {
3163         PMD_INIT_FUNC_TRACE();
3164
3165         /* Clear interrupt mask to stop from interrupts being generated */
3166         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3167
3168         E1000_WRITE_FLUSH(hw);
3169 }
3170
3171 static void
3172 igbvf_stop_adapter(struct rte_eth_dev *dev)
3173 {
3174         u32 reg_val;
3175         u16 i;
3176         struct rte_eth_dev_info dev_info;
3177         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3178
3179         memset(&dev_info, 0, sizeof(dev_info));
3180         eth_igbvf_infos_get(dev, &dev_info);
3181
3182         /* Clear interrupt mask to stop from interrupts being generated */
3183         igbvf_intr_disable(hw);
3184
3185         /* Clear any pending interrupts, flush previous writes */
3186         E1000_READ_REG(hw, E1000_EICR);
3187
3188         /* Disable the transmit unit.  Each queue must be disabled. */
3189         for (i = 0; i < dev_info.max_tx_queues; i++)
3190                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3191
3192         /* Disable the receive unit by stopping each queue */
3193         for (i = 0; i < dev_info.max_rx_queues; i++) {
3194                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3195                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3196                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3197                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3198                         ;
3199         }
3200
3201         /* flush all queues disables */
3202         E1000_WRITE_FLUSH(hw);
3203         msec_delay(2);
3204 }
3205
3206 static int eth_igbvf_link_update(struct e1000_hw *hw)
3207 {
3208         struct e1000_mbx_info *mbx = &hw->mbx;
3209         struct e1000_mac_info *mac = &hw->mac;
3210         int ret_val = E1000_SUCCESS;
3211
3212         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3213
3214         /*
3215          * We only want to run this if there has been a rst asserted.
3216          * in this case that could mean a link change, device reset,
3217          * or a virtual function reset
3218          */
3219
3220         /* If we were hit with a reset or timeout drop the link */
3221         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3222                 mac->get_link_status = TRUE;
3223
3224         if (!mac->get_link_status)
3225                 goto out;
3226
3227         /* if link status is down no point in checking to see if pf is up */
3228         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3229                 goto out;
3230
3231         /* if we passed all the tests above then the link is up and we no
3232          * longer need to check for link */
3233         mac->get_link_status = FALSE;
3234
3235 out:
3236         return ret_val;
3237 }
3238
3239
3240 static int
3241 igbvf_dev_configure(struct rte_eth_dev *dev)
3242 {
3243         struct rte_eth_conf* conf = &dev->data->dev_conf;
3244
3245         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3246                      dev->data->port_id);
3247
3248         /*
3249          * VF has no ability to enable/disable HW CRC
3250          * Keep the persistent behavior the same as Host PF
3251          */
3252 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3253         if (!conf->rxmode.hw_strip_crc) {
3254                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3255                 conf->rxmode.hw_strip_crc = 1;
3256         }
3257 #else
3258         if (conf->rxmode.hw_strip_crc) {
3259                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3260                 conf->rxmode.hw_strip_crc = 0;
3261         }
3262 #endif
3263
3264         return 0;
3265 }
3266
3267 static int
3268 igbvf_dev_start(struct rte_eth_dev *dev)
3269 {
3270         struct e1000_hw *hw =
3271                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3272         struct e1000_adapter *adapter =
3273                 E1000_DEV_PRIVATE(dev->data->dev_private);
3274         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3275         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3276         int ret;
3277         uint32_t intr_vector = 0;
3278
3279         PMD_INIT_FUNC_TRACE();
3280
3281         hw->mac.ops.reset_hw(hw);
3282         adapter->stopped = 0;
3283
3284         /* Set all vfta */
3285         igbvf_set_vfta_all(dev,1);
3286
3287         eth_igbvf_tx_init(dev);
3288
3289         /* This can fail when allocating mbufs for descriptor rings */
3290         ret = eth_igbvf_rx_init(dev);
3291         if (ret) {
3292                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3293                 igb_dev_clear_queues(dev);
3294                 return ret;
3295         }
3296
3297         /* check and configure queue intr-vector mapping */
3298         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3299                 intr_vector = dev->data->nb_rx_queues;
3300                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3301                 if (ret)
3302                         return ret;
3303         }
3304
3305         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3306                 intr_handle->intr_vec =
3307                         rte_zmalloc("intr_vec",
3308                                     dev->data->nb_rx_queues * sizeof(int), 0);
3309                 if (!intr_handle->intr_vec) {
3310                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3311                                      " intr_vec", dev->data->nb_rx_queues);
3312                         return -ENOMEM;
3313                 }
3314         }
3315
3316         eth_igbvf_configure_msix_intr(dev);
3317
3318         /* enable uio/vfio intr/eventfd mapping */
3319         rte_intr_enable(intr_handle);
3320
3321         /* resume enabled intr since hw reset */
3322         igbvf_intr_enable(dev);
3323
3324         return 0;
3325 }
3326
3327 static void
3328 igbvf_dev_stop(struct rte_eth_dev *dev)
3329 {
3330         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3331         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3332
3333         PMD_INIT_FUNC_TRACE();
3334
3335         igbvf_stop_adapter(dev);
3336
3337         /*
3338           * Clear what we set, but we still keep shadow_vfta to
3339           * restore after device starts
3340           */
3341         igbvf_set_vfta_all(dev,0);
3342
3343         igb_dev_clear_queues(dev);
3344
3345         /* disable intr eventfd mapping */
3346         rte_intr_disable(intr_handle);
3347
3348         /* Clean datapath event and queue/vec mapping */
3349         rte_intr_efd_disable(intr_handle);
3350         if (intr_handle->intr_vec) {
3351                 rte_free(intr_handle->intr_vec);
3352                 intr_handle->intr_vec = NULL;
3353         }
3354 }
3355
3356 static void
3357 igbvf_dev_close(struct rte_eth_dev *dev)
3358 {
3359         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360         struct e1000_adapter *adapter =
3361                 E1000_DEV_PRIVATE(dev->data->dev_private);
3362         struct ether_addr addr;
3363
3364         PMD_INIT_FUNC_TRACE();
3365
3366         e1000_reset_hw(hw);
3367
3368         igbvf_dev_stop(dev);
3369         adapter->stopped = 1;
3370         igb_dev_free_queues(dev);
3371
3372         /**
3373          * reprogram the RAR with a zero mac address,
3374          * to ensure that the VF traffic goes to the PF
3375          * after stop, close and detach of the VF.
3376          **/
3377
3378         memset(&addr, 0, sizeof(addr));
3379         igbvf_default_mac_addr_set(dev, &addr);
3380 }
3381
3382 static void
3383 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3384 {
3385         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3386
3387         /* Set both unicast and multicast promisc */
3388         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3389 }
3390
3391 static void
3392 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3393 {
3394         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3395
3396         /* If in allmulticast mode leave multicast promisc */
3397         if (dev->data->all_multicast == 1)
3398                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3399         else
3400                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3401 }
3402
3403 static void
3404 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3405 {
3406         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3407
3408         /* In promiscuous mode multicast promisc already set */
3409         if (dev->data->promiscuous == 0)
3410                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3411 }
3412
3413 static void
3414 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3415 {
3416         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3417
3418         /* In promiscuous mode leave multicast promisc enabled */
3419         if (dev->data->promiscuous == 0)
3420                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3421 }
3422
3423 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3424 {
3425         struct e1000_mbx_info *mbx = &hw->mbx;
3426         uint32_t msgbuf[2];
3427         s32 err;
3428
3429         /* After set vlan, vlan strip will also be enabled in igb driver*/
3430         msgbuf[0] = E1000_VF_SET_VLAN;
3431         msgbuf[1] = vid;
3432         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3433         if (on)
3434                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3435
3436         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3437         if (err)
3438                 goto mbx_err;
3439
3440         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3441         if (err)
3442                 goto mbx_err;
3443
3444         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3445         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3446                 err = -EINVAL;
3447
3448 mbx_err:
3449         return err;
3450 }
3451
3452 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3453 {
3454         struct e1000_hw *hw =
3455                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3456         struct e1000_vfta * shadow_vfta =
3457                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3458         int i = 0, j = 0, vfta = 0, mask = 1;
3459
3460         for (i = 0; i < IGB_VFTA_SIZE; i++){
3461                 vfta = shadow_vfta->vfta[i];
3462                 if(vfta){
3463                         mask = 1;
3464                         for (j = 0; j < 32; j++){
3465                                 if(vfta & mask)
3466                                         igbvf_set_vfta(hw,
3467                                                 (uint16_t)((i<<5)+j), on);
3468                                 mask<<=1;
3469                         }
3470                 }
3471         }
3472
3473 }
3474
3475 static int
3476 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3477 {
3478         struct e1000_hw *hw =
3479                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3480         struct e1000_vfta * shadow_vfta =
3481                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3482         uint32_t vid_idx = 0;
3483         uint32_t vid_bit = 0;
3484         int ret = 0;
3485
3486         PMD_INIT_FUNC_TRACE();
3487
3488         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3489         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3490         if(ret){
3491                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3492                 return ret;
3493         }
3494         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3495         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3496
3497         /*Save what we set and retore it after device reset*/
3498         if (on)
3499                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3500         else
3501                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3502
3503         return 0;
3504 }
3505
3506 static void
3507 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3508 {
3509         struct e1000_hw *hw =
3510                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3511
3512         /* index is not used by rar_set() */
3513         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3514 }
3515
3516
3517 static int
3518 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3519                         struct rte_eth_rss_reta_entry64 *reta_conf,
3520                         uint16_t reta_size)
3521 {
3522         uint8_t i, j, mask;
3523         uint32_t reta, r;
3524         uint16_t idx, shift;
3525         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3526
3527         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3528                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3529                         "(%d) doesn't match the number hardware can supported "
3530                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3531                 return -EINVAL;
3532         }
3533
3534         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3535                 idx = i / RTE_RETA_GROUP_SIZE;
3536                 shift = i % RTE_RETA_GROUP_SIZE;
3537                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3538                                                 IGB_4_BIT_MASK);
3539                 if (!mask)
3540                         continue;
3541                 if (mask == IGB_4_BIT_MASK)
3542                         r = 0;
3543                 else
3544                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3545                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3546                         if (mask & (0x1 << j))
3547                                 reta |= reta_conf[idx].reta[shift + j] <<
3548                                                         (CHAR_BIT * j);
3549                         else
3550                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3551                 }
3552                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3553         }
3554
3555         return 0;
3556 }
3557
3558 static int
3559 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3560                        struct rte_eth_rss_reta_entry64 *reta_conf,
3561                        uint16_t reta_size)
3562 {
3563         uint8_t i, j, mask;
3564         uint32_t reta;
3565         uint16_t idx, shift;
3566         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3567
3568         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3569                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3570                         "(%d) doesn't match the number hardware can supported "
3571                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3572                 return -EINVAL;
3573         }
3574
3575         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3576                 idx = i / RTE_RETA_GROUP_SIZE;
3577                 shift = i % RTE_RETA_GROUP_SIZE;
3578                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3579                                                 IGB_4_BIT_MASK);
3580                 if (!mask)
3581                         continue;
3582                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3583                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3584                         if (mask & (0x1 << j))
3585                                 reta_conf[idx].reta[shift + j] =
3586                                         ((reta >> (CHAR_BIT * j)) &
3587                                                 IGB_8_BIT_MASK);
3588                 }
3589         }
3590
3591         return 0;
3592 }
3593
3594 int
3595 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3596                         struct rte_eth_syn_filter *filter,
3597                         bool add)
3598 {
3599         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3600         struct e1000_filter_info *filter_info =
3601                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3602         uint32_t synqf, rfctl;
3603
3604         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3605                 return -EINVAL;
3606
3607         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3608
3609         if (add) {
3610                 if (synqf & E1000_SYN_FILTER_ENABLE)
3611                         return -EINVAL;
3612
3613                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3614                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3615
3616                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3617                 if (filter->hig_pri)
3618                         rfctl |= E1000_RFCTL_SYNQFP;
3619                 else
3620                         rfctl &= ~E1000_RFCTL_SYNQFP;
3621
3622                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3623         } else {
3624                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3625                         return -ENOENT;
3626                 synqf = 0;
3627         }
3628
3629         filter_info->syn_info = synqf;
3630         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3631         E1000_WRITE_FLUSH(hw);
3632         return 0;
3633 }
3634
3635 static int
3636 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3637                         struct rte_eth_syn_filter *filter)
3638 {
3639         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3640         uint32_t synqf, rfctl;
3641
3642         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3643         if (synqf & E1000_SYN_FILTER_ENABLE) {
3644                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3645                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3646                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3647                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3648                 return 0;
3649         }
3650
3651         return -ENOENT;
3652 }
3653
3654 static int
3655 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3656                         enum rte_filter_op filter_op,
3657                         void *arg)
3658 {
3659         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3660         int ret;
3661
3662         MAC_TYPE_FILTER_SUP(hw->mac.type);
3663
3664         if (filter_op == RTE_ETH_FILTER_NOP)
3665                 return 0;
3666
3667         if (arg == NULL) {
3668                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3669                             filter_op);
3670                 return -EINVAL;
3671         }
3672
3673         switch (filter_op) {
3674         case RTE_ETH_FILTER_ADD:
3675                 ret = eth_igb_syn_filter_set(dev,
3676                                 (struct rte_eth_syn_filter *)arg,
3677                                 TRUE);
3678                 break;
3679         case RTE_ETH_FILTER_DELETE:
3680                 ret = eth_igb_syn_filter_set(dev,
3681                                 (struct rte_eth_syn_filter *)arg,
3682                                 FALSE);
3683                 break;
3684         case RTE_ETH_FILTER_GET:
3685                 ret = eth_igb_syn_filter_get(dev,
3686                                 (struct rte_eth_syn_filter *)arg);
3687                 break;
3688         default:
3689                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3690                 ret = -EINVAL;
3691                 break;
3692         }
3693
3694         return ret;
3695 }
3696
3697 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3698 static inline int
3699 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3700                         struct e1000_2tuple_filter_info *filter_info)
3701 {
3702         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3703                 return -EINVAL;
3704         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3705                 return -EINVAL;  /* filter index is out of range. */
3706         if (filter->tcp_flags > TCP_FLAG_ALL)
3707                 return -EINVAL;  /* flags is invalid. */
3708
3709         switch (filter->dst_port_mask) {
3710         case UINT16_MAX:
3711                 filter_info->dst_port_mask = 0;
3712                 filter_info->dst_port = filter->dst_port;
3713                 break;
3714         case 0:
3715                 filter_info->dst_port_mask = 1;
3716                 break;
3717         default:
3718                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3719                 return -EINVAL;
3720         }
3721
3722         switch (filter->proto_mask) {
3723         case UINT8_MAX:
3724                 filter_info->proto_mask = 0;
3725                 filter_info->proto = filter->proto;
3726                 break;
3727         case 0:
3728                 filter_info->proto_mask = 1;
3729                 break;
3730         default:
3731                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3732                 return -EINVAL;
3733         }
3734
3735         filter_info->priority = (uint8_t)filter->priority;
3736         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3737                 filter_info->tcp_flags = filter->tcp_flags;
3738         else
3739                 filter_info->tcp_flags = 0;
3740
3741         return 0;
3742 }
3743
3744 static inline struct e1000_2tuple_filter *
3745 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3746                         struct e1000_2tuple_filter_info *key)
3747 {
3748         struct e1000_2tuple_filter *it;
3749
3750         TAILQ_FOREACH(it, filter_list, entries) {
3751                 if (memcmp(key, &it->filter_info,
3752                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3753                         return it;
3754                 }
3755         }
3756         return NULL;
3757 }
3758
3759 /* inject a igb 2tuple filter to HW */
3760 static inline void
3761 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3762                            struct e1000_2tuple_filter *filter)
3763 {
3764         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3765         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3766         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3767         int i;
3768
3769         i = filter->index;
3770         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3771         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3772                 imir |= E1000_IMIR_PORT_BP;
3773         else
3774                 imir &= ~E1000_IMIR_PORT_BP;
3775
3776         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3777
3778         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3779         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3780         ttqf |= (uint32_t)(filter->filter_info.proto &
3781                                                 E1000_TTQF_PROTOCOL_MASK);
3782         if (filter->filter_info.proto_mask == 0)
3783                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3784
3785         /* tcp flags bits setting. */
3786         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3787                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3788                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3789                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3790                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3791                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3792                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3793                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3794                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3795                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3796                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3797                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3798                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3799         } else {
3800                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3801         }
3802         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3803         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3804         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3805 }
3806
3807 /*
3808  * igb_add_2tuple_filter - add a 2tuple filter
3809  *
3810  * @param
3811  * dev: Pointer to struct rte_eth_dev.
3812  * ntuple_filter: ponter to the filter that will be added.
3813  *
3814  * @return
3815  *    - On success, zero.
3816  *    - On failure, a negative value.
3817  */
3818 static int
3819 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3820                         struct rte_eth_ntuple_filter *ntuple_filter)
3821 {
3822         struct e1000_filter_info *filter_info =
3823                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3824         struct e1000_2tuple_filter *filter;
3825         int i, ret;
3826
3827         filter = rte_zmalloc("e1000_2tuple_filter",
3828                         sizeof(struct e1000_2tuple_filter), 0);
3829         if (filter == NULL)
3830                 return -ENOMEM;
3831
3832         ret = ntuple_filter_to_2tuple(ntuple_filter,
3833                                       &filter->filter_info);
3834         if (ret < 0) {
3835                 rte_free(filter);
3836                 return ret;
3837         }
3838         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3839                                          &filter->filter_info) != NULL) {
3840                 PMD_DRV_LOG(ERR, "filter exists.");
3841                 rte_free(filter);
3842                 return -EEXIST;
3843         }
3844         filter->queue = ntuple_filter->queue;
3845
3846         /*
3847          * look for an unused 2tuple filter index,
3848          * and insert the filter to list.
3849          */
3850         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3851                 if (!(filter_info->twotuple_mask & (1 << i))) {
3852                         filter_info->twotuple_mask |= 1 << i;
3853                         filter->index = i;
3854                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3855                                           filter,
3856                                           entries);
3857                         break;
3858                 }
3859         }
3860         if (i >= E1000_MAX_TTQF_FILTERS) {
3861                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3862                 rte_free(filter);
3863                 return -ENOSYS;
3864         }
3865
3866         igb_inject_2uple_filter(dev, filter);
3867         return 0;
3868 }
3869
3870 int
3871 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3872                         struct e1000_2tuple_filter *filter)
3873 {
3874         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3875         struct e1000_filter_info *filter_info =
3876                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3877
3878         filter_info->twotuple_mask &= ~(1 << filter->index);
3879         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3880         rte_free(filter);
3881
3882         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3883         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3884         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3885         return 0;
3886 }
3887
3888 /*
3889  * igb_remove_2tuple_filter - remove a 2tuple filter
3890  *
3891  * @param
3892  * dev: Pointer to struct rte_eth_dev.
3893  * ntuple_filter: ponter to the filter that will be removed.
3894  *
3895  * @return
3896  *    - On success, zero.
3897  *    - On failure, a negative value.
3898  */
3899 static int
3900 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3901                         struct rte_eth_ntuple_filter *ntuple_filter)
3902 {
3903         struct e1000_filter_info *filter_info =
3904                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3905         struct e1000_2tuple_filter_info filter_2tuple;
3906         struct e1000_2tuple_filter *filter;
3907         int ret;
3908
3909         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3910         ret = ntuple_filter_to_2tuple(ntuple_filter,
3911                                       &filter_2tuple);
3912         if (ret < 0)
3913                 return ret;
3914
3915         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3916                                          &filter_2tuple);
3917         if (filter == NULL) {
3918                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3919                 return -ENOENT;
3920         }
3921
3922         igb_delete_2tuple_filter(dev, filter);
3923
3924         return 0;
3925 }
3926
3927 /* inject a igb flex filter to HW */
3928 static inline void
3929 igb_inject_flex_filter(struct rte_eth_dev *dev,
3930                            struct e1000_flex_filter *filter)
3931 {
3932         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3933         uint32_t wufc, queueing;
3934         uint32_t reg_off;
3935         uint8_t i, j = 0;
3936
3937         wufc = E1000_READ_REG(hw, E1000_WUFC);
3938         if (filter->index < E1000_MAX_FHFT)
3939                 reg_off = E1000_FHFT(filter->index);
3940         else
3941                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3942
3943         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3944                         (E1000_WUFC_FLX0 << filter->index));
3945         queueing = filter->filter_info.len |
3946                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3947                 (filter->filter_info.priority <<
3948                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3949         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3950                         queueing);
3951
3952         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3953                 E1000_WRITE_REG(hw, reg_off,
3954                                 filter->filter_info.dwords[j]);
3955                 reg_off += sizeof(uint32_t);
3956                 E1000_WRITE_REG(hw, reg_off,
3957                                 filter->filter_info.dwords[++j]);
3958                 reg_off += sizeof(uint32_t);
3959                 E1000_WRITE_REG(hw, reg_off,
3960                         (uint32_t)filter->filter_info.mask[i]);
3961                 reg_off += sizeof(uint32_t) * 2;
3962                 ++j;
3963         }
3964 }
3965
3966 static inline struct e1000_flex_filter *
3967 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3968                         struct e1000_flex_filter_info *key)
3969 {
3970         struct e1000_flex_filter *it;
3971
3972         TAILQ_FOREACH(it, filter_list, entries) {
3973                 if (memcmp(key, &it->filter_info,
3974                         sizeof(struct e1000_flex_filter_info)) == 0)
3975                         return it;
3976         }
3977
3978         return NULL;
3979 }
3980
3981 /* remove a flex byte filter
3982  * @param
3983  * dev: Pointer to struct rte_eth_dev.
3984  * filter: the pointer of the filter will be removed.
3985  */
3986 void
3987 igb_remove_flex_filter(struct rte_eth_dev *dev,
3988                         struct e1000_flex_filter *filter)
3989 {
3990         struct e1000_filter_info *filter_info =
3991                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3992         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3993         uint32_t wufc, i;
3994         uint32_t reg_off;
3995
3996         wufc = E1000_READ_REG(hw, E1000_WUFC);
3997         if (filter->index < E1000_MAX_FHFT)
3998                 reg_off = E1000_FHFT(filter->index);
3999         else
4000                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4001
4002         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4003                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4004
4005         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4006                 (~(E1000_WUFC_FLX0 << filter->index)));
4007
4008         filter_info->flex_mask &= ~(1 << filter->index);
4009         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4010         rte_free(filter);
4011 }
4012
4013 int
4014 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4015                         struct rte_eth_flex_filter *filter,
4016                         bool add)
4017 {
4018         struct e1000_filter_info *filter_info =
4019                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4020         struct e1000_flex_filter *flex_filter, *it;
4021         uint32_t mask;
4022         uint8_t shift, i;
4023
4024         flex_filter = rte_zmalloc("e1000_flex_filter",
4025                         sizeof(struct e1000_flex_filter), 0);
4026         if (flex_filter == NULL)
4027                 return -ENOMEM;
4028
4029         flex_filter->filter_info.len = filter->len;
4030         flex_filter->filter_info.priority = filter->priority;
4031         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4032         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4033                 mask = 0;
4034                 /* reverse bits in flex filter's mask*/
4035                 for (shift = 0; shift < CHAR_BIT; shift++) {
4036                         if (filter->mask[i] & (0x01 << shift))
4037                                 mask |= (0x80 >> shift);
4038                 }
4039                 flex_filter->filter_info.mask[i] = mask;
4040         }
4041
4042         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4043                                 &flex_filter->filter_info);
4044         if (it == NULL && !add) {
4045                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4046                 rte_free(flex_filter);
4047                 return -ENOENT;
4048         }
4049         if (it != NULL && add) {
4050                 PMD_DRV_LOG(ERR, "filter exists.");
4051                 rte_free(flex_filter);
4052                 return -EEXIST;
4053         }
4054
4055         if (add) {
4056                 flex_filter->queue = filter->queue;
4057                 /*
4058                  * look for an unused flex filter index
4059                  * and insert the filter into the list.
4060                  */
4061                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4062                         if (!(filter_info->flex_mask & (1 << i))) {
4063                                 filter_info->flex_mask |= 1 << i;
4064                                 flex_filter->index = i;
4065                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4066                                         flex_filter,
4067                                         entries);
4068                                 break;
4069                         }
4070                 }
4071                 if (i >= E1000_MAX_FLEX_FILTERS) {
4072                         PMD_DRV_LOG(ERR, "flex filters are full.");
4073                         rte_free(flex_filter);
4074                         return -ENOSYS;
4075                 }
4076
4077                 igb_inject_flex_filter(dev, flex_filter);
4078
4079         } else {
4080                 igb_remove_flex_filter(dev, it);
4081                 rte_free(flex_filter);
4082         }
4083
4084         return 0;
4085 }
4086
4087 static int
4088 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4089                         struct rte_eth_flex_filter *filter)
4090 {
4091         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4092         struct e1000_filter_info *filter_info =
4093                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4094         struct e1000_flex_filter flex_filter, *it;
4095         uint32_t wufc, queueing, wufc_en = 0;
4096
4097         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4098         flex_filter.filter_info.len = filter->len;
4099         flex_filter.filter_info.priority = filter->priority;
4100         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4101         memcpy(flex_filter.filter_info.mask, filter->mask,
4102                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4103
4104         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4105                                 &flex_filter.filter_info);
4106         if (it == NULL) {
4107                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4108                 return -ENOENT;
4109         }
4110
4111         wufc = E1000_READ_REG(hw, E1000_WUFC);
4112         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4113
4114         if ((wufc & wufc_en) == wufc_en) {
4115                 uint32_t reg_off = 0;
4116                 if (it->index < E1000_MAX_FHFT)
4117                         reg_off = E1000_FHFT(it->index);
4118                 else
4119                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4120
4121                 queueing = E1000_READ_REG(hw,
4122                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4123                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4124                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4125                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4126                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4127                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4128                 return 0;
4129         }
4130         return -ENOENT;
4131 }
4132
4133 static int
4134 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4135                         enum rte_filter_op filter_op,
4136                         void *arg)
4137 {
4138         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4139         struct rte_eth_flex_filter *filter;
4140         int ret = 0;
4141
4142         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4143
4144         if (filter_op == RTE_ETH_FILTER_NOP)
4145                 return ret;
4146
4147         if (arg == NULL) {
4148                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4149                             filter_op);
4150                 return -EINVAL;
4151         }
4152
4153         filter = (struct rte_eth_flex_filter *)arg;
4154         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4155             || filter->len % sizeof(uint64_t) != 0) {
4156                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4157                 return -EINVAL;
4158         }
4159         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4160                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4161                 return -EINVAL;
4162         }
4163
4164         switch (filter_op) {
4165         case RTE_ETH_FILTER_ADD:
4166                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4167                 break;
4168         case RTE_ETH_FILTER_DELETE:
4169                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4170                 break;
4171         case RTE_ETH_FILTER_GET:
4172                 ret = eth_igb_get_flex_filter(dev, filter);
4173                 break;
4174         default:
4175                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4176                 ret = -EINVAL;
4177                 break;
4178         }
4179
4180         return ret;
4181 }
4182
4183 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4184 static inline int
4185 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4186                         struct e1000_5tuple_filter_info *filter_info)
4187 {
4188         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4189                 return -EINVAL;
4190         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4191                 return -EINVAL;  /* filter index is out of range. */
4192         if (filter->tcp_flags > TCP_FLAG_ALL)
4193                 return -EINVAL;  /* flags is invalid. */
4194
4195         switch (filter->dst_ip_mask) {
4196         case UINT32_MAX:
4197                 filter_info->dst_ip_mask = 0;
4198                 filter_info->dst_ip = filter->dst_ip;
4199                 break;
4200         case 0:
4201                 filter_info->dst_ip_mask = 1;
4202                 break;
4203         default:
4204                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4205                 return -EINVAL;
4206         }
4207
4208         switch (filter->src_ip_mask) {
4209         case UINT32_MAX:
4210                 filter_info->src_ip_mask = 0;
4211                 filter_info->src_ip = filter->src_ip;
4212                 break;
4213         case 0:
4214                 filter_info->src_ip_mask = 1;
4215                 break;
4216         default:
4217                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4218                 return -EINVAL;
4219         }
4220
4221         switch (filter->dst_port_mask) {
4222         case UINT16_MAX:
4223                 filter_info->dst_port_mask = 0;
4224                 filter_info->dst_port = filter->dst_port;
4225                 break;
4226         case 0:
4227                 filter_info->dst_port_mask = 1;
4228                 break;
4229         default:
4230                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4231                 return -EINVAL;
4232         }
4233
4234         switch (filter->src_port_mask) {
4235         case UINT16_MAX:
4236                 filter_info->src_port_mask = 0;
4237                 filter_info->src_port = filter->src_port;
4238                 break;
4239         case 0:
4240                 filter_info->src_port_mask = 1;
4241                 break;
4242         default:
4243                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4244                 return -EINVAL;
4245         }
4246
4247         switch (filter->proto_mask) {
4248         case UINT8_MAX:
4249                 filter_info->proto_mask = 0;
4250                 filter_info->proto = filter->proto;
4251                 break;
4252         case 0:
4253                 filter_info->proto_mask = 1;
4254                 break;
4255         default:
4256                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4257                 return -EINVAL;
4258         }
4259
4260         filter_info->priority = (uint8_t)filter->priority;
4261         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4262                 filter_info->tcp_flags = filter->tcp_flags;
4263         else
4264                 filter_info->tcp_flags = 0;
4265
4266         return 0;
4267 }
4268
4269 static inline struct e1000_5tuple_filter *
4270 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4271                         struct e1000_5tuple_filter_info *key)
4272 {
4273         struct e1000_5tuple_filter *it;
4274
4275         TAILQ_FOREACH(it, filter_list, entries) {
4276                 if (memcmp(key, &it->filter_info,
4277                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4278                         return it;
4279                 }
4280         }
4281         return NULL;
4282 }
4283
4284 /* inject a igb 5-tuple filter to HW */
4285 static inline void
4286 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4287                            struct e1000_5tuple_filter *filter)
4288 {
4289         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4290         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4291         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4292         uint8_t i;
4293
4294         i = filter->index;
4295         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4296         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4297                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4298         if (filter->filter_info.dst_ip_mask == 0)
4299                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4300         if (filter->filter_info.src_port_mask == 0)
4301                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4302         if (filter->filter_info.proto_mask == 0)
4303                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4304         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4305                 E1000_FTQF_QUEUE_MASK;
4306         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4307         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4308         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4309         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4310
4311         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4312         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4313
4314         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4315         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4316                 imir |= E1000_IMIR_PORT_BP;
4317         else
4318                 imir &= ~E1000_IMIR_PORT_BP;
4319         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4320
4321         /* tcp flags bits setting. */
4322         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4323                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4324                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4325                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4326                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4327                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4328                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4329                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4330                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4331                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4332                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4333                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4334                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4335         } else {
4336                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4337         }
4338         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4339         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4340 }
4341
4342 /*
4343  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4344  *
4345  * @param
4346  * dev: Pointer to struct rte_eth_dev.
4347  * ntuple_filter: ponter to the filter that will be added.
4348  *
4349  * @return
4350  *    - On success, zero.
4351  *    - On failure, a negative value.
4352  */
4353 static int
4354 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4355                         struct rte_eth_ntuple_filter *ntuple_filter)
4356 {
4357         struct e1000_filter_info *filter_info =
4358                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4359         struct e1000_5tuple_filter *filter;
4360         uint8_t i;
4361         int ret;
4362
4363         filter = rte_zmalloc("e1000_5tuple_filter",
4364                         sizeof(struct e1000_5tuple_filter), 0);
4365         if (filter == NULL)
4366                 return -ENOMEM;
4367
4368         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4369                                             &filter->filter_info);
4370         if (ret < 0) {
4371                 rte_free(filter);
4372                 return ret;
4373         }
4374
4375         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4376                                          &filter->filter_info) != NULL) {
4377                 PMD_DRV_LOG(ERR, "filter exists.");
4378                 rte_free(filter);
4379                 return -EEXIST;
4380         }
4381         filter->queue = ntuple_filter->queue;
4382
4383         /*
4384          * look for an unused 5tuple filter index,
4385          * and insert the filter to list.
4386          */
4387         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4388                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4389                         filter_info->fivetuple_mask |= 1 << i;
4390                         filter->index = i;
4391                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4392                                           filter,
4393                                           entries);
4394                         break;
4395                 }
4396         }
4397         if (i >= E1000_MAX_FTQF_FILTERS) {
4398                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4399                 rte_free(filter);
4400                 return -ENOSYS;
4401         }
4402
4403         igb_inject_5tuple_filter_82576(dev, filter);
4404         return 0;
4405 }
4406
4407 int
4408 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4409                                 struct e1000_5tuple_filter *filter)
4410 {
4411         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4412         struct e1000_filter_info *filter_info =
4413                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4414
4415         filter_info->fivetuple_mask &= ~(1 << filter->index);
4416         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4417         rte_free(filter);
4418
4419         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4420                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4421         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4422         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4423         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4424         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4425         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4426         return 0;
4427 }
4428
4429 /*
4430  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4431  *
4432  * @param
4433  * dev: Pointer to struct rte_eth_dev.
4434  * ntuple_filter: ponter to the filter that will be removed.
4435  *
4436  * @return
4437  *    - On success, zero.
4438  *    - On failure, a negative value.
4439  */
4440 static int
4441 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4442                                 struct rte_eth_ntuple_filter *ntuple_filter)
4443 {
4444         struct e1000_filter_info *filter_info =
4445                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4446         struct e1000_5tuple_filter_info filter_5tuple;
4447         struct e1000_5tuple_filter *filter;
4448         int ret;
4449
4450         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4451         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4452                                             &filter_5tuple);
4453         if (ret < 0)
4454                 return ret;
4455
4456         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4457                                          &filter_5tuple);
4458         if (filter == NULL) {
4459                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4460                 return -ENOENT;
4461         }
4462
4463         igb_delete_5tuple_filter_82576(dev, filter);
4464
4465         return 0;
4466 }
4467
4468 static int
4469 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4470 {
4471         uint32_t rctl;
4472         struct e1000_hw *hw;
4473         struct rte_eth_dev_info dev_info;
4474         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4475                                      VLAN_TAG_SIZE);
4476
4477         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4478
4479 #ifdef RTE_LIBRTE_82571_SUPPORT
4480         /* XXX: not bigger than max_rx_pktlen */
4481         if (hw->mac.type == e1000_82571)
4482                 return -ENOTSUP;
4483 #endif
4484         eth_igb_infos_get(dev, &dev_info);
4485
4486         /* check that mtu is within the allowed range */
4487         if ((mtu < ETHER_MIN_MTU) ||
4488             (frame_size > dev_info.max_rx_pktlen))
4489                 return -EINVAL;
4490
4491         /* refuse mtu that requires the support of scattered packets when this
4492          * feature has not been enabled before. */
4493         if (!dev->data->scattered_rx &&
4494             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4495                 return -EINVAL;
4496
4497         rctl = E1000_READ_REG(hw, E1000_RCTL);
4498
4499         /* switch to jumbo mode if needed */
4500         if (frame_size > ETHER_MAX_LEN) {
4501                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4502                 rctl |= E1000_RCTL_LPE;
4503         } else {
4504                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4505                 rctl &= ~E1000_RCTL_LPE;
4506         }
4507         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4508
4509         /* update max frame size */
4510         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4511
4512         E1000_WRITE_REG(hw, E1000_RLPML,
4513                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4514
4515         return 0;
4516 }
4517
4518 /*
4519  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4520  *
4521  * @param
4522  * dev: Pointer to struct rte_eth_dev.
4523  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4524  * add: if true, add filter, if false, remove filter
4525  *
4526  * @return
4527  *    - On success, zero.
4528  *    - On failure, a negative value.
4529  */
4530 int
4531 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4532                         struct rte_eth_ntuple_filter *ntuple_filter,
4533                         bool add)
4534 {
4535         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4536         int ret;
4537
4538         switch (ntuple_filter->flags) {
4539         case RTE_5TUPLE_FLAGS:
4540         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4541                 if (hw->mac.type != e1000_82576)
4542                         return -ENOTSUP;
4543                 if (add)
4544                         ret = igb_add_5tuple_filter_82576(dev,
4545                                                           ntuple_filter);
4546                 else
4547                         ret = igb_remove_5tuple_filter_82576(dev,
4548                                                              ntuple_filter);
4549                 break;
4550         case RTE_2TUPLE_FLAGS:
4551         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4552                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4553                         hw->mac.type != e1000_i210 &&
4554                         hw->mac.type != e1000_i211)
4555                         return -ENOTSUP;
4556                 if (add)
4557                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4558                 else
4559                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4560                 break;
4561         default:
4562                 ret = -EINVAL;
4563                 break;
4564         }
4565
4566         return ret;
4567 }
4568
4569 /*
4570  * igb_get_ntuple_filter - get a ntuple filter
4571  *
4572  * @param
4573  * dev: Pointer to struct rte_eth_dev.
4574  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4575  *
4576  * @return
4577  *    - On success, zero.
4578  *    - On failure, a negative value.
4579  */
4580 static int
4581 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4582                         struct rte_eth_ntuple_filter *ntuple_filter)
4583 {
4584         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4585         struct e1000_filter_info *filter_info =
4586                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4587         struct e1000_5tuple_filter_info filter_5tuple;
4588         struct e1000_2tuple_filter_info filter_2tuple;
4589         struct e1000_5tuple_filter *p_5tuple_filter;
4590         struct e1000_2tuple_filter *p_2tuple_filter;
4591         int ret;
4592
4593         switch (ntuple_filter->flags) {
4594         case RTE_5TUPLE_FLAGS:
4595         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4596                 if (hw->mac.type != e1000_82576)
4597                         return -ENOTSUP;
4598                 memset(&filter_5tuple,
4599                         0,
4600                         sizeof(struct e1000_5tuple_filter_info));
4601                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4602                                                     &filter_5tuple);
4603                 if (ret < 0)
4604                         return ret;
4605                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4606                                         &filter_info->fivetuple_list,
4607                                         &filter_5tuple);
4608                 if (p_5tuple_filter == NULL) {
4609                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4610                         return -ENOENT;
4611                 }
4612                 ntuple_filter->queue = p_5tuple_filter->queue;
4613                 break;
4614         case RTE_2TUPLE_FLAGS:
4615         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4616                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4617                         return -ENOTSUP;
4618                 memset(&filter_2tuple,
4619                         0,
4620                         sizeof(struct e1000_2tuple_filter_info));
4621                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4622                 if (ret < 0)
4623                         return ret;
4624                 p_2tuple_filter = igb_2tuple_filter_lookup(
4625                                         &filter_info->twotuple_list,
4626                                         &filter_2tuple);
4627                 if (p_2tuple_filter == NULL) {
4628                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4629                         return -ENOENT;
4630                 }
4631                 ntuple_filter->queue = p_2tuple_filter->queue;
4632                 break;
4633         default:
4634                 ret = -EINVAL;
4635                 break;
4636         }
4637
4638         return 0;
4639 }
4640
4641 /*
4642  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4643  * @dev: pointer to rte_eth_dev structure
4644  * @filter_op:operation will be taken.
4645  * @arg: a pointer to specific structure corresponding to the filter_op
4646  */
4647 static int
4648 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4649                                 enum rte_filter_op filter_op,
4650                                 void *arg)
4651 {
4652         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4653         int ret;
4654
4655         MAC_TYPE_FILTER_SUP(hw->mac.type);
4656
4657         if (filter_op == RTE_ETH_FILTER_NOP)
4658                 return 0;
4659
4660         if (arg == NULL) {
4661                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4662                             filter_op);
4663                 return -EINVAL;
4664         }
4665
4666         switch (filter_op) {
4667         case RTE_ETH_FILTER_ADD:
4668                 ret = igb_add_del_ntuple_filter(dev,
4669                         (struct rte_eth_ntuple_filter *)arg,
4670                         TRUE);
4671                 break;
4672         case RTE_ETH_FILTER_DELETE:
4673                 ret = igb_add_del_ntuple_filter(dev,
4674                         (struct rte_eth_ntuple_filter *)arg,
4675                         FALSE);
4676                 break;
4677         case RTE_ETH_FILTER_GET:
4678                 ret = igb_get_ntuple_filter(dev,
4679                         (struct rte_eth_ntuple_filter *)arg);
4680                 break;
4681         default:
4682                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4683                 ret = -EINVAL;
4684                 break;
4685         }
4686         return ret;
4687 }
4688
4689 static inline int
4690 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4691                         uint16_t ethertype)
4692 {
4693         int i;
4694
4695         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4696                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4697                     (filter_info->ethertype_mask & (1 << i)))
4698                         return i;
4699         }
4700         return -1;
4701 }
4702
4703 static inline int
4704 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4705                         uint16_t ethertype, uint32_t etqf)
4706 {
4707         int i;
4708
4709         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4710                 if (!(filter_info->ethertype_mask & (1 << i))) {
4711                         filter_info->ethertype_mask |= 1 << i;
4712                         filter_info->ethertype_filters[i].ethertype = ethertype;
4713                         filter_info->ethertype_filters[i].etqf = etqf;
4714                         return i;
4715                 }
4716         }
4717         return -1;
4718 }
4719
4720 int
4721 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4722                         uint8_t idx)
4723 {
4724         if (idx >= E1000_MAX_ETQF_FILTERS)
4725                 return -1;
4726         filter_info->ethertype_mask &= ~(1 << idx);
4727         filter_info->ethertype_filters[idx].ethertype = 0;
4728         filter_info->ethertype_filters[idx].etqf = 0;
4729         return idx;
4730 }
4731
4732
4733 int
4734 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4735                         struct rte_eth_ethertype_filter *filter,
4736                         bool add)
4737 {
4738         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4739         struct e1000_filter_info *filter_info =
4740                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4741         uint32_t etqf = 0;
4742         int ret;
4743
4744         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4745                 filter->ether_type == ETHER_TYPE_IPv6) {
4746                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4747                         " ethertype filter.", filter->ether_type);
4748                 return -EINVAL;
4749         }
4750
4751         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4752                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4753                 return -EINVAL;
4754         }
4755         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4756                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4757                 return -EINVAL;
4758         }
4759
4760         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4761         if (ret >= 0 && add) {
4762                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4763                             filter->ether_type);
4764                 return -EEXIST;
4765         }
4766         if (ret < 0 && !add) {
4767                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4768                             filter->ether_type);
4769                 return -ENOENT;
4770         }
4771
4772         if (add) {
4773                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4774                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4775                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4776                 ret = igb_ethertype_filter_insert(filter_info,
4777                                 filter->ether_type, etqf);
4778                 if (ret < 0) {
4779                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4780                         return -ENOSYS;
4781                 }
4782         } else {
4783                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4784                 if (ret < 0)
4785                         return -ENOSYS;
4786         }
4787         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4788         E1000_WRITE_FLUSH(hw);
4789
4790         return 0;
4791 }
4792
4793 static int
4794 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4795                         struct rte_eth_ethertype_filter *filter)
4796 {
4797         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4798         struct e1000_filter_info *filter_info =
4799                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4800         uint32_t etqf;
4801         int ret;
4802
4803         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4804         if (ret < 0) {
4805                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4806                             filter->ether_type);
4807                 return -ENOENT;
4808         }
4809
4810         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4811         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4812                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4813                 filter->flags = 0;
4814                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4815                                 E1000_ETQF_QUEUE_SHIFT;
4816                 return 0;
4817         }
4818
4819         return -ENOENT;
4820 }
4821
4822 /*
4823  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4824  * @dev: pointer to rte_eth_dev structure
4825  * @filter_op:operation will be taken.
4826  * @arg: a pointer to specific structure corresponding to the filter_op
4827  */
4828 static int
4829 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4830                                 enum rte_filter_op filter_op,
4831                                 void *arg)
4832 {
4833         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4834         int ret;
4835
4836         MAC_TYPE_FILTER_SUP(hw->mac.type);
4837
4838         if (filter_op == RTE_ETH_FILTER_NOP)
4839                 return 0;
4840
4841         if (arg == NULL) {
4842                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4843                             filter_op);
4844                 return -EINVAL;
4845         }
4846
4847         switch (filter_op) {
4848         case RTE_ETH_FILTER_ADD:
4849                 ret = igb_add_del_ethertype_filter(dev,
4850                         (struct rte_eth_ethertype_filter *)arg,
4851                         TRUE);
4852                 break;
4853         case RTE_ETH_FILTER_DELETE:
4854                 ret = igb_add_del_ethertype_filter(dev,
4855                         (struct rte_eth_ethertype_filter *)arg,
4856                         FALSE);
4857                 break;
4858         case RTE_ETH_FILTER_GET:
4859                 ret = igb_get_ethertype_filter(dev,
4860                         (struct rte_eth_ethertype_filter *)arg);
4861                 break;
4862         default:
4863                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4864                 ret = -EINVAL;
4865                 break;
4866         }
4867         return ret;
4868 }
4869
4870 static int
4871 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4872                      enum rte_filter_type filter_type,
4873                      enum rte_filter_op filter_op,
4874                      void *arg)
4875 {
4876         int ret = 0;
4877
4878         switch (filter_type) {
4879         case RTE_ETH_FILTER_NTUPLE:
4880                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4881                 break;
4882         case RTE_ETH_FILTER_ETHERTYPE:
4883                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4884                 break;
4885         case RTE_ETH_FILTER_SYN:
4886                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4887                 break;
4888         case RTE_ETH_FILTER_FLEXIBLE:
4889                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4890                 break;
4891         case RTE_ETH_FILTER_GENERIC:
4892                 if (filter_op != RTE_ETH_FILTER_GET)
4893                         return -EINVAL;
4894                 *(const void **)arg = &igb_flow_ops;
4895                 break;
4896         default:
4897                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4898                                                         filter_type);
4899                 break;
4900         }
4901
4902         return ret;
4903 }
4904
4905 static int
4906 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4907                          struct ether_addr *mc_addr_set,
4908                          uint32_t nb_mc_addr)
4909 {
4910         struct e1000_hw *hw;
4911
4912         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4913         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4914         return 0;
4915 }
4916
4917 static uint64_t
4918 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4919 {
4920         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4921         uint64_t systime_cycles;
4922
4923         switch (hw->mac.type) {
4924         case e1000_i210:
4925         case e1000_i211:
4926                 /*
4927                  * Need to read System Time Residue Register to be able
4928                  * to read the other two registers.
4929                  */
4930                 E1000_READ_REG(hw, E1000_SYSTIMR);
4931                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4932                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4933                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4934                                 * NSEC_PER_SEC;
4935                 break;
4936         case e1000_82580:
4937         case e1000_i350:
4938         case e1000_i354:
4939                 /*
4940                  * Need to read System Time Residue Register to be able
4941                  * to read the other two registers.
4942                  */
4943                 E1000_READ_REG(hw, E1000_SYSTIMR);
4944                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4945                 /* Only the 8 LSB are valid. */
4946                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4947                                 & 0xff) << 32;
4948                 break;
4949         default:
4950                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4951                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4952                                 << 32;
4953                 break;
4954         }
4955
4956         return systime_cycles;
4957 }
4958
4959 static uint64_t
4960 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4961 {
4962         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4963         uint64_t rx_tstamp_cycles;
4964
4965         switch (hw->mac.type) {
4966         case e1000_i210:
4967         case e1000_i211:
4968                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4969                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4970                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4971                                 * NSEC_PER_SEC;
4972                 break;
4973         case e1000_82580:
4974         case e1000_i350:
4975         case e1000_i354:
4976                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4977                 /* Only the 8 LSB are valid. */
4978                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4979                                 & 0xff) << 32;
4980                 break;
4981         default:
4982                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4983                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4984                                 << 32;
4985                 break;
4986         }
4987
4988         return rx_tstamp_cycles;
4989 }
4990
4991 static uint64_t
4992 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4993 {
4994         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4995         uint64_t tx_tstamp_cycles;
4996
4997         switch (hw->mac.type) {
4998         case e1000_i210:
4999         case e1000_i211:
5000                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5001                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5002                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5003                                 * NSEC_PER_SEC;
5004                 break;
5005         case e1000_82580:
5006         case e1000_i350:
5007         case e1000_i354:
5008                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5009                 /* Only the 8 LSB are valid. */
5010                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5011                                 & 0xff) << 32;
5012                 break;
5013         default:
5014                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5015                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5016                                 << 32;
5017                 break;
5018         }
5019
5020         return tx_tstamp_cycles;
5021 }
5022
5023 static void
5024 igb_start_timecounters(struct rte_eth_dev *dev)
5025 {
5026         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5027         struct e1000_adapter *adapter =
5028                 (struct e1000_adapter *)dev->data->dev_private;
5029         uint32_t incval = 1;
5030         uint32_t shift = 0;
5031         uint64_t mask = E1000_CYCLECOUNTER_MASK;
5032
5033         switch (hw->mac.type) {
5034         case e1000_82580:
5035         case e1000_i350:
5036         case e1000_i354:
5037                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5038                 mask = (1ULL << 40) - 1;
5039                 /* fall-through */
5040         case e1000_i210:
5041         case e1000_i211:
5042                 /*
5043                  * Start incrementing the register
5044                  * used to timestamp PTP packets.
5045                  */
5046                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5047                 break;
5048         case e1000_82576:
5049                 incval = E1000_INCVALUE_82576;
5050                 shift = IGB_82576_TSYNC_SHIFT;
5051                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5052                                 E1000_INCPERIOD_82576 | incval);
5053                 break;
5054         default:
5055                 /* Not supported */
5056                 return;
5057         }
5058
5059         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5060         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5061         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5062
5063         adapter->systime_tc.cc_mask = mask;
5064         adapter->systime_tc.cc_shift = shift;
5065         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5066
5067         adapter->rx_tstamp_tc.cc_mask = mask;
5068         adapter->rx_tstamp_tc.cc_shift = shift;
5069         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5070
5071         adapter->tx_tstamp_tc.cc_mask = mask;
5072         adapter->tx_tstamp_tc.cc_shift = shift;
5073         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5074 }
5075
5076 static int
5077 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5078 {
5079         struct e1000_adapter *adapter =
5080                         (struct e1000_adapter *)dev->data->dev_private;
5081
5082         adapter->systime_tc.nsec += delta;
5083         adapter->rx_tstamp_tc.nsec += delta;
5084         adapter->tx_tstamp_tc.nsec += delta;
5085
5086         return 0;
5087 }
5088
5089 static int
5090 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5091 {
5092         uint64_t ns;
5093         struct e1000_adapter *adapter =
5094                         (struct e1000_adapter *)dev->data->dev_private;
5095
5096         ns = rte_timespec_to_ns(ts);
5097
5098         /* Set the timecounters to a new value. */
5099         adapter->systime_tc.nsec = ns;
5100         adapter->rx_tstamp_tc.nsec = ns;
5101         adapter->tx_tstamp_tc.nsec = ns;
5102
5103         return 0;
5104 }
5105
5106 static int
5107 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5108 {
5109         uint64_t ns, systime_cycles;
5110         struct e1000_adapter *adapter =
5111                         (struct e1000_adapter *)dev->data->dev_private;
5112
5113         systime_cycles = igb_read_systime_cyclecounter(dev);
5114         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5115         *ts = rte_ns_to_timespec(ns);
5116
5117         return 0;
5118 }
5119
5120 static int
5121 igb_timesync_enable(struct rte_eth_dev *dev)
5122 {
5123         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5124         uint32_t tsync_ctl;
5125         uint32_t tsauxc;
5126
5127         /* Stop the timesync system time. */
5128         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5129         /* Reset the timesync system time value. */
5130         switch (hw->mac.type) {
5131         case e1000_82580:
5132         case e1000_i350:
5133         case e1000_i354:
5134         case e1000_i210:
5135         case e1000_i211:
5136                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5137                 /* fall-through */
5138         case e1000_82576:
5139                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5140                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5141                 break;
5142         default:
5143                 /* Not supported. */
5144                 return -ENOTSUP;
5145         }
5146
5147         /* Enable system time for it isn't on by default. */
5148         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5149         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5150         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5151
5152         igb_start_timecounters(dev);
5153
5154         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5155         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5156                         (ETHER_TYPE_1588 |
5157                          E1000_ETQF_FILTER_ENABLE |
5158                          E1000_ETQF_1588));
5159
5160         /* Enable timestamping of received PTP packets. */
5161         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5162         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5163         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5164
5165         /* Enable Timestamping of transmitted PTP packets. */
5166         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5167         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5168         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5169
5170         return 0;
5171 }
5172
5173 static int
5174 igb_timesync_disable(struct rte_eth_dev *dev)
5175 {
5176         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5177         uint32_t tsync_ctl;
5178
5179         /* Disable timestamping of transmitted PTP packets. */
5180         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5181         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5182         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5183
5184         /* Disable timestamping of received PTP packets. */
5185         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5186         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5187         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5188
5189         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5190         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5191
5192         /* Stop incrementating the System Time registers. */
5193         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5194
5195         return 0;
5196 }
5197
5198 static int
5199 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5200                                struct timespec *timestamp,
5201                                uint32_t flags __rte_unused)
5202 {
5203         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5204         struct e1000_adapter *adapter =
5205                         (struct e1000_adapter *)dev->data->dev_private;
5206         uint32_t tsync_rxctl;
5207         uint64_t rx_tstamp_cycles;
5208         uint64_t ns;
5209
5210         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5211         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5212                 return -EINVAL;
5213
5214         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5215         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5216         *timestamp = rte_ns_to_timespec(ns);
5217
5218         return  0;
5219 }
5220
5221 static int
5222 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5223                                struct timespec *timestamp)
5224 {
5225         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5226         struct e1000_adapter *adapter =
5227                         (struct e1000_adapter *)dev->data->dev_private;
5228         uint32_t tsync_txctl;
5229         uint64_t tx_tstamp_cycles;
5230         uint64_t ns;
5231
5232         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5233         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5234                 return -EINVAL;
5235
5236         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5237         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5238         *timestamp = rte_ns_to_timespec(ns);
5239
5240         return  0;
5241 }
5242
5243 static int
5244 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5245 {
5246         int count = 0;
5247         int g_ind = 0;
5248         const struct reg_info *reg_group;
5249
5250         while ((reg_group = igb_regs[g_ind++]))
5251                 count += igb_reg_group_count(reg_group);
5252
5253         return count;
5254 }
5255
5256 static int
5257 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5258 {
5259         int count = 0;
5260         int g_ind = 0;
5261         const struct reg_info *reg_group;
5262
5263         while ((reg_group = igbvf_regs[g_ind++]))
5264                 count += igb_reg_group_count(reg_group);
5265
5266         return count;
5267 }
5268
5269 static int
5270 eth_igb_get_regs(struct rte_eth_dev *dev,
5271         struct rte_dev_reg_info *regs)
5272 {
5273         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5274         uint32_t *data = regs->data;
5275         int g_ind = 0;
5276         int count = 0;
5277         const struct reg_info *reg_group;
5278
5279         if (data == NULL) {
5280                 regs->length = eth_igb_get_reg_length(dev);
5281                 regs->width = sizeof(uint32_t);
5282                 return 0;
5283         }
5284
5285         /* Support only full register dump */
5286         if ((regs->length == 0) ||
5287             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5288                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5289                         hw->device_id;
5290                 while ((reg_group = igb_regs[g_ind++]))
5291                         count += igb_read_regs_group(dev, &data[count],
5292                                                         reg_group);
5293                 return 0;
5294         }
5295
5296         return -ENOTSUP;
5297 }
5298
5299 static int
5300 igbvf_get_regs(struct rte_eth_dev *dev,
5301         struct rte_dev_reg_info *regs)
5302 {
5303         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5304         uint32_t *data = regs->data;
5305         int g_ind = 0;
5306         int count = 0;
5307         const struct reg_info *reg_group;
5308
5309         if (data == NULL) {
5310                 regs->length = igbvf_get_reg_length(dev);
5311                 regs->width = sizeof(uint32_t);
5312                 return 0;
5313         }
5314
5315         /* Support only full register dump */
5316         if ((regs->length == 0) ||
5317             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5318                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5319                         hw->device_id;
5320                 while ((reg_group = igbvf_regs[g_ind++]))
5321                         count += igb_read_regs_group(dev, &data[count],
5322                                                         reg_group);
5323                 return 0;
5324         }
5325
5326         return -ENOTSUP;
5327 }
5328
5329 static int
5330 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5331 {
5332         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5333
5334         /* Return unit is byte count */
5335         return hw->nvm.word_size * 2;
5336 }
5337
5338 static int
5339 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5340         struct rte_dev_eeprom_info *in_eeprom)
5341 {
5342         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5343         struct e1000_nvm_info *nvm = &hw->nvm;
5344         uint16_t *data = in_eeprom->data;
5345         int first, length;
5346
5347         first = in_eeprom->offset >> 1;
5348         length = in_eeprom->length >> 1;
5349         if ((first >= hw->nvm.word_size) ||
5350             ((first + length) >= hw->nvm.word_size))
5351                 return -EINVAL;
5352
5353         in_eeprom->magic = hw->vendor_id |
5354                 ((uint32_t)hw->device_id << 16);
5355
5356         if ((nvm->ops.read) == NULL)
5357                 return -ENOTSUP;
5358
5359         return nvm->ops.read(hw, first, length, data);
5360 }
5361
5362 static int
5363 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5364         struct rte_dev_eeprom_info *in_eeprom)
5365 {
5366         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5367         struct e1000_nvm_info *nvm = &hw->nvm;
5368         uint16_t *data = in_eeprom->data;
5369         int first, length;
5370
5371         first = in_eeprom->offset >> 1;
5372         length = in_eeprom->length >> 1;
5373         if ((first >= hw->nvm.word_size) ||
5374             ((first + length) >= hw->nvm.word_size))
5375                 return -EINVAL;
5376
5377         in_eeprom->magic = (uint32_t)hw->vendor_id |
5378                 ((uint32_t)hw->device_id << 16);
5379
5380         if ((nvm->ops.write) == NULL)
5381                 return -ENOTSUP;
5382         return nvm->ops.write(hw,  first, length, data);
5383 }
5384
5385 static int
5386 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5387 {
5388         struct e1000_hw *hw =
5389                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5390         uint32_t mask = 1 << queue_id;
5391
5392         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5393         E1000_WRITE_FLUSH(hw);
5394
5395         return 0;
5396 }
5397
5398 static int
5399 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5400 {
5401         struct e1000_hw *hw =
5402                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5403         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5404         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5405         uint32_t mask = 1 << queue_id;
5406         uint32_t regval;
5407
5408         regval = E1000_READ_REG(hw, E1000_EIMS);
5409         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5410         E1000_WRITE_FLUSH(hw);
5411
5412         rte_intr_enable(intr_handle);
5413
5414         return 0;
5415 }
5416
5417 static void
5418 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5419                    uint8_t index, uint8_t offset)
5420 {
5421         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5422
5423         /* clear bits */
5424         val &= ~((uint32_t)0xFF << offset);
5425
5426         /* write vector and valid bit */
5427         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5428
5429         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5430 }
5431
5432 static void
5433 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5434                            uint8_t queue, uint8_t msix_vector)
5435 {
5436         uint32_t tmp = 0;
5437
5438         if (hw->mac.type == e1000_82575) {
5439                 if (direction == 0)
5440                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5441                 else if (direction == 1)
5442                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5443                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5444         } else if (hw->mac.type == e1000_82576) {
5445                 if ((direction == 0) || (direction == 1))
5446                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5447                                            ((queue & 0x8) << 1) +
5448                                            8 * direction);
5449         } else if ((hw->mac.type == e1000_82580) ||
5450                         (hw->mac.type == e1000_i350) ||
5451                         (hw->mac.type == e1000_i354) ||
5452                         (hw->mac.type == e1000_i210) ||
5453                         (hw->mac.type == e1000_i211)) {
5454                 if ((direction == 0) || (direction == 1))
5455                         eth_igb_write_ivar(hw, msix_vector,
5456                                            queue >> 1,
5457                                            ((queue & 0x1) << 4) +
5458                                            8 * direction);
5459         }
5460 }
5461
5462 /* Sets up the hardware to generate MSI-X interrupts properly
5463  * @hw
5464  *  board private structure
5465  */
5466 static void
5467 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5468 {
5469         int queue_id;
5470         uint32_t tmpval, regval, intr_mask;
5471         struct e1000_hw *hw =
5472                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5473         uint32_t vec = E1000_MISC_VEC_ID;
5474         uint32_t base = E1000_MISC_VEC_ID;
5475         uint32_t misc_shift = 0;
5476         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5477         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5478
5479         /* won't configure msix register if no mapping is done
5480          * between intr vector and event fd
5481          */
5482         if (!rte_intr_dp_is_en(intr_handle))
5483                 return;
5484
5485         if (rte_intr_allow_others(intr_handle)) {
5486                 vec = base = E1000_RX_VEC_START;
5487                 misc_shift = 1;
5488         }
5489
5490         /* set interrupt vector for other causes */
5491         if (hw->mac.type == e1000_82575) {
5492                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5493                 /* enable MSI-X PBA support */
5494                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5495
5496                 /* Auto-Mask interrupts upon ICR read */
5497                 tmpval |= E1000_CTRL_EXT_EIAME;
5498                 tmpval |= E1000_CTRL_EXT_IRCA;
5499
5500                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5501
5502                 /* enable msix_other interrupt */
5503                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5504                 regval = E1000_READ_REG(hw, E1000_EIAC);
5505                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5506                 regval = E1000_READ_REG(hw, E1000_EIAM);
5507                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5508         } else if ((hw->mac.type == e1000_82576) ||
5509                         (hw->mac.type == e1000_82580) ||
5510                         (hw->mac.type == e1000_i350) ||
5511                         (hw->mac.type == e1000_i354) ||
5512                         (hw->mac.type == e1000_i210) ||
5513                         (hw->mac.type == e1000_i211)) {
5514                 /* turn on MSI-X capability first */
5515                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5516                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5517                                         E1000_GPIE_NSICR);
5518                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5519                         misc_shift;
5520                 regval = E1000_READ_REG(hw, E1000_EIAC);
5521                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5522
5523                 /* enable msix_other interrupt */
5524                 regval = E1000_READ_REG(hw, E1000_EIMS);
5525                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5526                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5527                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5528         }
5529
5530         /* use EIAM to auto-mask when MSI-X interrupt
5531          * is asserted, this saves a register write for every interrupt
5532          */
5533         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5534                 misc_shift;
5535         regval = E1000_READ_REG(hw, E1000_EIAM);
5536         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5537
5538         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5539                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5540                 intr_handle->intr_vec[queue_id] = vec;
5541                 if (vec < base + intr_handle->nb_efd - 1)
5542                         vec++;
5543         }
5544
5545         E1000_WRITE_FLUSH(hw);
5546 }
5547
5548 /* restore n-tuple filter */
5549 static inline void
5550 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5551 {
5552         struct e1000_filter_info *filter_info =
5553                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5554         struct e1000_5tuple_filter *p_5tuple;
5555         struct e1000_2tuple_filter *p_2tuple;
5556
5557         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5558                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5559         }
5560
5561         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5562                 igb_inject_2uple_filter(dev, p_2tuple);
5563         }
5564 }
5565
5566 /* restore SYN filter */
5567 static inline void
5568 igb_syn_filter_restore(struct rte_eth_dev *dev)
5569 {
5570         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5571         struct e1000_filter_info *filter_info =
5572                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5573         uint32_t synqf;
5574
5575         synqf = filter_info->syn_info;
5576
5577         if (synqf & E1000_SYN_FILTER_ENABLE) {
5578                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5579                 E1000_WRITE_FLUSH(hw);
5580         }
5581 }
5582
5583 /* restore ethernet type filter */
5584 static inline void
5585 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5586 {
5587         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5588         struct e1000_filter_info *filter_info =
5589                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5590         int i;
5591
5592         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5593                 if (filter_info->ethertype_mask & (1 << i)) {
5594                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5595                                 filter_info->ethertype_filters[i].etqf);
5596                         E1000_WRITE_FLUSH(hw);
5597                 }
5598         }
5599 }
5600
5601 /* restore flex byte filter */
5602 static inline void
5603 igb_flex_filter_restore(struct rte_eth_dev *dev)
5604 {
5605         struct e1000_filter_info *filter_info =
5606                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5607         struct e1000_flex_filter *flex_filter;
5608
5609         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5610                 igb_inject_flex_filter(dev, flex_filter);
5611         }
5612 }
5613
5614 /* restore all types filter */
5615 static int
5616 igb_filter_restore(struct rte_eth_dev *dev)
5617 {
5618         igb_ntuple_filter_restore(dev);
5619         igb_ethertype_filter_restore(dev);
5620         igb_syn_filter_restore(dev);
5621         igb_flex_filter_restore(dev);
5622
5623         return 0;
5624 }
5625
5626 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5627 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5628 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5629 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5630 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5631 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");