drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64
  65 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  66 #define IGB_DEFAULT_RX_HTHRESH      8
  67 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  68
  69 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  70 #define IGB_DEFAULT_TX_HTHRESH      1
  71 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  72
  73 #define IGB_HKEY_MAX_INDEX 10
  74
  75 /* Bit shift and mask */
  76 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  77 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  78 #define IGB_8_BIT_WIDTH  CHAR_BIT
  79 #define IGB_8_BIT_MASK   UINT8_MAX
  80
  81 /* Additional timesync values. */
  82 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  83 #define E1000_ETQF_FILTER_1588       3
  84 #define IGB_82576_TSYNC_SHIFT        16
  85 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  86 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  88
  89 static int  eth_igb_configure(struct rte_eth_dev *dev);
  90 static int  eth_igb_start(struct rte_eth_dev *dev);
  91 static void eth_igb_stop(struct rte_eth_dev *dev);
  92 static void eth_igb_close(struct rte_eth_dev *dev);
  93 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  94 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  95 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  96 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  97 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  98                                 int wait_to_complete);
  99 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 100                                 struct rte_eth_stats *rte_stats);
 101 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 102                               struct rte_eth_xstats *xstats, unsigned n);
 103 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 104 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 105 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 106                               struct rte_eth_dev_info *dev_info);
 107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 108 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_dev_info *dev_info);
 110 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 113                                 struct rte_eth_fc_conf *fc_conf);
 114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 118 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 119                                                         void *param);
 120 static int  igb_hardware_init(struct e1000_hw *hw);
 121 static void igb_hw_control_acquire(struct e1000_hw *hw);
 122 static void igb_hw_control_release(struct e1000_hw *hw);
 123 static void igb_init_manageability(struct e1000_hw *hw);
 124 static void igb_release_manageability(struct e1000_hw *hw);
 125
 126 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 127
 128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 129                 uint16_t vlan_id, int on);
 130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 131                                  enum rte_vlan_type vlan_type,
 132                                  uint16_t tpid_id);
 133 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134
 135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 141
 142 static int eth_igb_led_on(struct rte_eth_dev *dev);
 143 static int eth_igb_led_off(struct rte_eth_dev *dev);
 144
 145 static void igb_intr_disable(struct e1000_hw *hw);
 146 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 147 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 148                 struct ether_addr *mac_addr,
 149                 uint32_t index, uint32_t pool);
 150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 151 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 152                 struct ether_addr *addr);
 153
 154 static void igbvf_intr_disable(struct e1000_hw *hw);
 155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 156 static int igbvf_dev_start(struct rte_eth_dev *dev);
 157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 158 static void igbvf_dev_close(struct rte_eth_dev *dev);
 159 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 160 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 161 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 162 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 163 static int eth_igbvf_link_update(struct e1000_hw *hw);
 164 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_stats *rte_stats);
 166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 167                                 struct rte_eth_xstats *xstats, unsigned n);
 168 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 169 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 170                 uint16_t vlan_id, int on);
 171 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 172 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 173 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 174                 struct ether_addr *addr);
 175 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 176 static int igbvf_get_regs(struct rte_eth_dev *dev,
 177                 struct rte_dev_reg_info *regs);
 178
 179 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 180                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 181                                    uint16_t reta_size);
 182 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 183                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                   uint16_t reta_size);
 185
 186 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 187                         struct rte_eth_syn_filter *filter,
 188                         bool add);
 189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 190                         struct rte_eth_syn_filter *filter);
 191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 192                         enum rte_filter_op filter_op,
 193                         void *arg);
 194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 195                         struct rte_eth_ntuple_filter *ntuple_filter);
 196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 197                         struct rte_eth_ntuple_filter *ntuple_filter);
 198 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 199                         struct rte_eth_flex_filter *filter,
 200                         bool add);
 201 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 202                         struct rte_eth_flex_filter *filter);
 203 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 204                         enum rte_filter_op filter_op,
 205                         void *arg);
 206 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 207                         struct rte_eth_ntuple_filter *ntuple_filter);
 208 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 209                         struct rte_eth_ntuple_filter *ntuple_filter);
 210 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 211                         struct rte_eth_ntuple_filter *filter,
 212                         bool add);
 213 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 214                         struct rte_eth_ntuple_filter *filter);
 215 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 216                                 enum rte_filter_op filter_op,
 217                                 void *arg);
 218 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 219                         struct rte_eth_ethertype_filter *filter,
 220                         bool add);
 221 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 222                                 enum rte_filter_op filter_op,
 223                                 void *arg);
 224 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 225                         struct rte_eth_ethertype_filter *filter);
 226 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 227                      enum rte_filter_type filter_type,
 228                      enum rte_filter_op filter_op,
 229                      void *arg);
 230 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 231 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 232                 struct rte_dev_reg_info *regs);
 233 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 234 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 235                 struct rte_dev_eeprom_info *eeprom);
 236 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 237                 struct rte_dev_eeprom_info *eeprom);
 238 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 239                                     struct ether_addr *mc_addr_set,
 240                                     uint32_t nb_mc_addr);
 241 static int igb_timesync_enable(struct rte_eth_dev *dev);
 242 static int igb_timesync_disable(struct rte_eth_dev *dev);
 243 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 244                                           struct timespec *timestamp,
 245                                           uint32_t flags);
 246 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 247                                           struct timespec *timestamp);
 248 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 249 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 250                                   struct timespec *timestamp);
 251 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 252                                    const struct timespec *timestamp);
 253 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 254                                         uint16_t queue_id);
 255 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 256                                          uint16_t queue_id);
 257 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 258                                        uint8_t queue, uint8_t msix_vector);
 259 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 260                                uint8_t index, uint8_t offset);
 261 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 262
 263 /*
 264  * Define VF Stats MACRO for Non "cleared on read" register
 265  */
 266 #define UPDATE_VF_STAT(reg, last, cur)            \
 267 {                                                 \
 268         u32 latest = E1000_READ_REG(hw, reg);     \
 269         cur += (latest - last) & UINT_MAX;        \
 270         last = latest;                            \
 271 }
 272
 273 #define IGB_FC_PAUSE_TIME 0x0680
 274 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 275 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 276
 277 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 278
 279 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 280
 281 /*
 282  * The set of PCI devices this driver supports
 283  */
 284 static const struct rte_pci_id pci_id_igb_map[] = {
 285
 286 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 287 #include "rte_pci_dev_ids.h"
 288
 289 {0},
 290 };
 291
 292 /*
 293  * The set of PCI devices this driver supports (for 82576&I350 VF)
 294  */
 295 static const struct rte_pci_id pci_id_igbvf_map[] = {
 296
 297 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 298 #include "rte_pci_dev_ids.h"
 299
 300 {0},
 301 };
 302
 303 static const struct rte_eth_desc_lim rx_desc_lim = {
 304         .nb_max = E1000_MAX_RING_DESC,
 305         .nb_min = E1000_MIN_RING_DESC,
 306         .nb_align = IGB_RXD_ALIGN,
 307 };
 308
 309 static const struct rte_eth_desc_lim tx_desc_lim = {
 310         .nb_max = E1000_MAX_RING_DESC,
 311         .nb_min = E1000_MIN_RING_DESC,
 312         .nb_align = IGB_RXD_ALIGN,
 313 };
 314
 315 static const struct eth_dev_ops eth_igb_ops = {
 316         .dev_configure        = eth_igb_configure,
 317         .dev_start            = eth_igb_start,
 318         .dev_stop             = eth_igb_stop,
 319         .dev_close            = eth_igb_close,
 320         .promiscuous_enable   = eth_igb_promiscuous_enable,
 321         .promiscuous_disable  = eth_igb_promiscuous_disable,
 322         .allmulticast_enable  = eth_igb_allmulticast_enable,
 323         .allmulticast_disable = eth_igb_allmulticast_disable,
 324         .link_update          = eth_igb_link_update,
 325         .stats_get            = eth_igb_stats_get,
 326         .xstats_get           = eth_igb_xstats_get,
 327         .stats_reset          = eth_igb_stats_reset,
 328         .xstats_reset         = eth_igb_xstats_reset,
 329         .dev_infos_get        = eth_igb_infos_get,
 330         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 331         .mtu_set              = eth_igb_mtu_set,
 332         .vlan_filter_set      = eth_igb_vlan_filter_set,
 333         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 334         .vlan_offload_set     = eth_igb_vlan_offload_set,
 335         .rx_queue_setup       = eth_igb_rx_queue_setup,
 336         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 337         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 338         .rx_queue_release     = eth_igb_rx_queue_release,
 339         .rx_queue_count       = eth_igb_rx_queue_count,
 340         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 341         .tx_queue_setup       = eth_igb_tx_queue_setup,
 342         .tx_queue_release     = eth_igb_tx_queue_release,
 343         .dev_led_on           = eth_igb_led_on,
 344         .dev_led_off          = eth_igb_led_off,
 345         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 346         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 347         .mac_addr_add         = eth_igb_rar_set,
 348         .mac_addr_remove      = eth_igb_rar_clear,
 349         .mac_addr_set         = eth_igb_default_mac_addr_set,
 350         .reta_update          = eth_igb_rss_reta_update,
 351         .reta_query           = eth_igb_rss_reta_query,
 352         .rss_hash_update      = eth_igb_rss_hash_update,
 353         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 354         .filter_ctrl          = eth_igb_filter_ctrl,
 355         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 356         .rxq_info_get         = igb_rxq_info_get,
 357         .txq_info_get         = igb_txq_info_get,
 358         .timesync_enable      = igb_timesync_enable,
 359         .timesync_disable     = igb_timesync_disable,
 360         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 361         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 362         .get_reg_length       = eth_igb_get_reg_length,
 363         .get_reg              = eth_igb_get_regs,
 364         .get_eeprom_length    = eth_igb_get_eeprom_length,
 365         .get_eeprom           = eth_igb_get_eeprom,
 366         .set_eeprom           = eth_igb_set_eeprom,
 367         .timesync_adjust_time = igb_timesync_adjust_time,
 368         .timesync_read_time   = igb_timesync_read_time,
 369         .timesync_write_time  = igb_timesync_write_time,
 370 };
 371
 372 /*
 373  * dev_ops for virtual function, bare necessities for basic vf
 374  * operation have been implemented
 375  */
 376 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 377         .dev_configure        = igbvf_dev_configure,
 378         .dev_start            = igbvf_dev_start,
 379         .dev_stop             = igbvf_dev_stop,
 380         .dev_close            = igbvf_dev_close,
 381         .promiscuous_enable   = igbvf_promiscuous_enable,
 382         .promiscuous_disable  = igbvf_promiscuous_disable,
 383         .allmulticast_enable  = igbvf_allmulticast_enable,
 384         .allmulticast_disable = igbvf_allmulticast_disable,
 385         .link_update          = eth_igb_link_update,
 386         .stats_get            = eth_igbvf_stats_get,
 387         .xstats_get           = eth_igbvf_xstats_get,
 388         .stats_reset          = eth_igbvf_stats_reset,
 389         .xstats_reset         = eth_igbvf_stats_reset,
 390         .vlan_filter_set      = igbvf_vlan_filter_set,
 391         .dev_infos_get        = eth_igbvf_infos_get,
 392         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 393         .rx_queue_setup       = eth_igb_rx_queue_setup,
 394         .rx_queue_release     = eth_igb_rx_queue_release,
 395         .tx_queue_setup       = eth_igb_tx_queue_setup,
 396         .tx_queue_release     = eth_igb_tx_queue_release,
 397         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 398         .rxq_info_get         = igb_rxq_info_get,
 399         .txq_info_get         = igb_txq_info_get,
 400         .mac_addr_set         = igbvf_default_mac_addr_set,
 401         .get_reg_length       = igbvf_get_reg_length,
 402         .get_reg              = igbvf_get_regs,
 403 };
 404
 405 /* store statistics names and its offset in stats structure */
 406 struct rte_igb_xstats_name_off {
 407         char name[RTE_ETH_XSTATS_NAME_SIZE];
 408         unsigned offset;
 409 };
 410
 411 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 412         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 413         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 414         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 415         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 416         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 417         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 418         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 419                 ecol)},
 420         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 421         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 422         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 423         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 424         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 425         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 426         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 427         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 428         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 429         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 430         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 431                 fcruc)},
 432         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 433         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 434         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 435         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 436         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 437                 prc1023)},
 438         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 439                 prc1522)},
 440         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 441         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 442         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 443         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 444         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 445         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 446         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 447         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 448         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 449         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 450         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 451         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 452         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 453         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 454         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 455         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 456         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 457         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 458                 ptc1023)},
 459         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 460                 ptc1522)},
 461         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 462         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 463         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 464         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 465         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 466         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 467         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 468
 469         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 470 };
 471
 472 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 473                 sizeof(rte_igb_stats_strings[0]))
 474
 475 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 476         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 477         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 478         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 479         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 480         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 481 };
 482
 483 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 484                 sizeof(rte_igbvf_stats_strings[0]))
 485
 486 /**
 487  * Atomically reads the link status information from global
 488  * structure rte_eth_dev.
 489  *
 490  * @param dev
 491  *   - Pointer to the structure rte_eth_dev to read from.
 492  *   - Pointer to the buffer to be saved with the link status.
 493  *
 494  * @return
 495  *   - On success, zero.
 496  *   - On failure, negative value.
 497  */
 498 static inline int
 499 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 500                                 struct rte_eth_link *link)
 501 {
 502         struct rte_eth_link *dst = link;
 503         struct rte_eth_link *src = &(dev->data->dev_link);
 504
 505         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 506                                         *(uint64_t *)src) == 0)
 507                 return -1;
 508
 509         return 0;
 510 }
 511
 512 /**
 513  * Atomically writes the link status information into global
 514  * structure rte_eth_dev.
 515  *
 516  * @param dev
 517  *   - Pointer to the structure rte_eth_dev to read from.
 518  *   - Pointer to the buffer to be saved with the link status.
 519  *
 520  * @return
 521  *   - On success, zero.
 522  *   - On failure, negative value.
 523  */
 524 static inline int
 525 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 526                                 struct rte_eth_link *link)
 527 {
 528         struct rte_eth_link *dst = &(dev->data->dev_link);
 529         struct rte_eth_link *src = link;
 530
 531         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 532                                         *(uint64_t *)src) == 0)
 533                 return -1;
 534
 535         return 0;
 536 }
 537
 538 static inline void
 539 igb_intr_enable(struct rte_eth_dev *dev)
 540 {
 541         struct e1000_interrupt *intr =
 542                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 543         struct e1000_hw *hw =
 544                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 545
 546         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 547         E1000_WRITE_FLUSH(hw);
 548 }
 549
 550 static void
 551 igb_intr_disable(struct e1000_hw *hw)
 552 {
 553         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 554         E1000_WRITE_FLUSH(hw);
 555 }
 556
 557 static inline int32_t
 558 igb_pf_reset_hw(struct e1000_hw *hw)
 559 {
 560         uint32_t ctrl_ext;
 561         int32_t status;
 562
 563         status = e1000_reset_hw(hw);
 564
 565         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 566         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 567         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 568         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 569         E1000_WRITE_FLUSH(hw);
 570
 571         return status;
 572 }
 573
 574 static void
 575 igb_identify_hardware(struct rte_eth_dev *dev)
 576 {
 577         struct e1000_hw *hw =
 578                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 579
 580         hw->vendor_id = dev->pci_dev->id.vendor_id;
 581         hw->device_id = dev->pci_dev->id.device_id;
 582         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 583         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 584
 585         e1000_set_mac_type(hw);
 586
 587         /* need to check if it is a vf device below */
 588 }
 589
 590 static int
 591 igb_reset_swfw_lock(struct e1000_hw *hw)
 592 {
 593         int ret_val;
 594
 595         /*
 596          * Do mac ops initialization manually here, since we will need
 597          * some function pointers set by this call.
 598          */
 599         ret_val = e1000_init_mac_params(hw);
 600         if (ret_val)
 601                 return ret_val;
 602
 603         /*
 604          * SMBI lock should not fail in this early stage. If this is the case,
 605          * it is due to an improper exit of the application.
 606          * So force the release of the faulty lock.
 607          */
 608         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 609                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 610         }
 611         e1000_put_hw_semaphore_generic(hw);
 612
 613         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 614                 uint16_t mask;
 615
 616                 /*
 617                  * Phy lock should not fail in this early stage. If this is the case,
 618                  * it is due to an improper exit of the application.
 619                  * So force the release of the faulty lock.
 620                  */
 621                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 622                 if (hw->bus.func > E1000_FUNC_1)
 623                         mask <<= 2;
 624                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 625                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 626                                     hw->bus.func);
 627                 }
 628                 hw->mac.ops.release_swfw_sync(hw, mask);
 629
 630                 /*
 631                  * This one is more tricky since it is common to all ports; but
 632                  * swfw_sync retries last long enough (1s) to be almost sure that if
 633                  * lock can not be taken it is due to an improper lock of the
 634                  * semaphore.
 635                  */
 636                 mask = E1000_SWFW_EEP_SM;
 637                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 638                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 639                 }
 640                 hw->mac.ops.release_swfw_sync(hw, mask);
 641         }
 642
 643         return E1000_SUCCESS;
 644 }
 645
 646 static int
 647 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 648 {
 649         int error = 0;
 650         struct rte_pci_device *pci_dev;
 651         struct e1000_hw *hw =
 652                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 653         struct e1000_vfta * shadow_vfta =
 654                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 655         struct e1000_filter_info *filter_info =
 656                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 657         struct e1000_adapter *adapter =
 658                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 659
 660         uint32_t ctrl_ext;
 661
 662         pci_dev = eth_dev->pci_dev;
 663
 664         eth_dev->dev_ops = &eth_igb_ops;
 665         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 666         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 667
 668         /* for secondary processes, we don't initialise any further as primary
 669          * has already done this work. Only check we don't need a different
 670          * RX function */
 671         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 672                 if (eth_dev->data->scattered_rx)
 673                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 674                 return 0;
 675         }
 676
 677         rte_eth_copy_pci_info(eth_dev, pci_dev);
 678
 679         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 680
 681         igb_identify_hardware(eth_dev);
 682         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 683                 error = -EIO;
 684                 goto err_late;
 685         }
 686
 687         e1000_get_bus_info(hw);
 688
 689         /* Reset any pending lock */
 690         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 691                 error = -EIO;
 692                 goto err_late;
 693         }
 694
 695         /* Finish initialization */
 696         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 697                 error = -EIO;
 698                 goto err_late;
 699         }
 700
 701         hw->mac.autoneg = 1;
 702         hw->phy.autoneg_wait_to_complete = 0;
 703         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 704
 705         /* Copper options */
 706         if (hw->phy.media_type == e1000_media_type_copper) {
 707                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 708                 hw->phy.disable_polarity_correction = 0;
 709                 hw->phy.ms_type = e1000_ms_hw_default;
 710         }
 711
 712         /*
 713          * Start from a known state, this is important in reading the nvm
 714          * and mac from that.
 715          */
 716         igb_pf_reset_hw(hw);
 717
 718         /* Make sure we have a good EEPROM before we read from it */
 719         if (e1000_validate_nvm_checksum(hw) < 0) {
 720                 /*
 721                  * Some PCI-E parts fail the first check due to
 722                  * the link being in sleep state, call it again,
 723                  * if it fails a second time its a real issue.
 724                  */
 725                 if (e1000_validate_nvm_checksum(hw) < 0) {
 726                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 727                         error = -EIO;
 728                         goto err_late;
 729                 }
 730         }
 731
 732         /* Read the permanent MAC address out of the EEPROM */
 733         if (e1000_read_mac_addr(hw) != 0) {
 734                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 735                 error = -EIO;
 736                 goto err_late;
 737         }
 738
 739         /* Allocate memory for storing MAC addresses */
 740         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 741                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 742         if (eth_dev->data->mac_addrs == NULL) {
 743                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 744                                                 "store MAC addresses",
 745                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 746                 error = -ENOMEM;
 747                 goto err_late;
 748         }
 749
 750         /* Copy the permanent MAC address */
 751         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 752
 753         /* initialize the vfta */
 754         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 755
 756         /* Now initialize the hardware */
 757         if (igb_hardware_init(hw) != 0) {
 758                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 759                 rte_free(eth_dev->data->mac_addrs);
 760                 eth_dev->data->mac_addrs = NULL;
 761                 error = -ENODEV;
 762                 goto err_late;
 763         }
 764         hw->mac.get_link_status = 1;
 765         adapter->stopped = 0;
 766
 767         /* Indicate SOL/IDER usage */
 768         if (e1000_check_reset_block(hw) < 0) {
 769                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 770                                         "SOL/IDER session");
 771         }
 772
 773         /* initialize PF if max_vfs not zero */
 774         igb_pf_host_init(eth_dev);
 775
 776         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 777         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 778         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 779         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 780         E1000_WRITE_FLUSH(hw);
 781
 782         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 783                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 784                      pci_dev->id.device_id);
 785
 786         rte_intr_callback_register(&pci_dev->intr_handle,
 787                                    eth_igb_interrupt_handler,
 788                                    (void *)eth_dev);
 789
 790         /* enable uio/vfio intr/eventfd mapping */
 791         rte_intr_enable(&pci_dev->intr_handle);
 792
 793         /* enable support intr */
 794         igb_intr_enable(eth_dev);
 795
 796         TAILQ_INIT(&filter_info->flex_list);
 797         filter_info->flex_mask = 0;
 798         TAILQ_INIT(&filter_info->twotuple_list);
 799         filter_info->twotuple_mask = 0;
 800         TAILQ_INIT(&filter_info->fivetuple_list);
 801         filter_info->fivetuple_mask = 0;
 802
 803         return 0;
 804
 805 err_late:
 806         igb_hw_control_release(hw);
 807
 808         return error;
 809 }
 810
 811 static int
 812 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 813 {
 814         struct rte_pci_device *pci_dev;
 815         struct e1000_hw *hw;
 816         struct e1000_adapter *adapter =
 817                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 818
 819         PMD_INIT_FUNC_TRACE();
 820
 821         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 822                 return -EPERM;
 823
 824         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 825         pci_dev = eth_dev->pci_dev;
 826
 827         if (adapter->stopped == 0)
 828                 eth_igb_close(eth_dev);
 829
 830         eth_dev->dev_ops = NULL;
 831         eth_dev->rx_pkt_burst = NULL;
 832         eth_dev->tx_pkt_burst = NULL;
 833
 834         /* Reset any pending lock */
 835         igb_reset_swfw_lock(hw);
 836
 837         rte_free(eth_dev->data->mac_addrs);
 838         eth_dev->data->mac_addrs = NULL;
 839
 840         /* uninitialize PF if max_vfs not zero */
 841         igb_pf_host_uninit(eth_dev);
 842
 843         /* disable uio intr before callback unregister */
 844         rte_intr_disable(&(pci_dev->intr_handle));
 845         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 846                 eth_igb_interrupt_handler, (void *)eth_dev);
 847
 848         return 0;
 849 }
 850
 851 /*
 852  * Virtual Function device init
 853  */
 854 static int
 855 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 856 {
 857         struct rte_pci_device *pci_dev;
 858         struct e1000_adapter *adapter =
 859                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 860         struct e1000_hw *hw =
 861                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 862         int diag;
 863         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 864
 865         PMD_INIT_FUNC_TRACE();
 866
 867         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 868         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 869         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 870
 871         /* for secondary processes, we don't initialise any further as primary
 872          * has already done this work. Only check we don't need a different
 873          * RX function */
 874         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 875                 if (eth_dev->data->scattered_rx)
 876                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 877                 return 0;
 878         }
 879
 880         pci_dev = eth_dev->pci_dev;
 881
 882         rte_eth_copy_pci_info(eth_dev, pci_dev);
 883
 884         hw->device_id = pci_dev->id.device_id;
 885         hw->vendor_id = pci_dev->id.vendor_id;
 886         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 887         adapter->stopped = 0;
 888
 889         /* Initialize the shared code (base driver) */
 890         diag = e1000_setup_init_funcs(hw, TRUE);
 891         if (diag != 0) {
 892                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 893                         diag);
 894                 return -EIO;
 895         }
 896
 897         /* init_mailbox_params */
 898         hw->mbx.ops.init_params(hw);
 899
 900         /* Disable the interrupts for VF */
 901         igbvf_intr_disable(hw);
 902
 903         diag = hw->mac.ops.reset_hw(hw);
 904
 905         /* Allocate memory for storing MAC addresses */
 906         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 907                 hw->mac.rar_entry_count, 0);
 908         if (eth_dev->data->mac_addrs == NULL) {
 909                 PMD_INIT_LOG(ERR,
 910                         "Failed to allocate %d bytes needed to store MAC "
 911                         "addresses",
 912                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 913                 return -ENOMEM;
 914         }
 915
 916         /* Generate a random MAC address, if none was assigned by PF. */
 917         if (is_zero_ether_addr(perm_addr)) {
 918                 eth_random_addr(perm_addr->addr_bytes);
 919                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
 920                 if (diag) {
 921                         rte_free(eth_dev->data->mac_addrs);
 922                         eth_dev->data->mac_addrs = NULL;
 923                         return diag;
 924                 }
 925                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
 926                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
 927                              "%02x:%02x:%02x:%02x:%02x:%02x",
 928                              perm_addr->addr_bytes[0],
 929                              perm_addr->addr_bytes[1],
 930                              perm_addr->addr_bytes[2],
 931                              perm_addr->addr_bytes[3],
 932                              perm_addr->addr_bytes[4],
 933                              perm_addr->addr_bytes[5]);
 934         }
 935
 936         /* Copy the permanent MAC address */
 937         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 938                         &eth_dev->data->mac_addrs[0]);
 939
 940         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 941                      "mac.type=%s",
 942                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 943                      pci_dev->id.device_id, "igb_mac_82576_vf");
 944
 945         return 0;
 946 }
 947
 948 static int
 949 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
 950 {
 951         struct e1000_adapter *adapter =
 952                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 953
 954         PMD_INIT_FUNC_TRACE();
 955
 956         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 957                 return -EPERM;
 958
 959         if (adapter->stopped == 0)
 960                 igbvf_dev_close(eth_dev);
 961
 962         eth_dev->dev_ops = NULL;
 963         eth_dev->rx_pkt_burst = NULL;
 964         eth_dev->tx_pkt_burst = NULL;
 965
 966         rte_free(eth_dev->data->mac_addrs);
 967         eth_dev->data->mac_addrs = NULL;
 968
 969         return 0;
 970 }
 971
 972 static struct eth_driver rte_igb_pmd = {
 973         .pci_drv = {
 974                 .name = "rte_igb_pmd",
 975                 .id_table = pci_id_igb_map,
 976                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 977                         RTE_PCI_DRV_DETACHABLE,
 978         },
 979         .eth_dev_init = eth_igb_dev_init,
 980         .eth_dev_uninit = eth_igb_dev_uninit,
 981         .dev_private_size = sizeof(struct e1000_adapter),
 982 };
 983
 984 /*
 985  * virtual function driver struct
 986  */
 987 static struct eth_driver rte_igbvf_pmd = {
 988         .pci_drv = {
 989                 .name = "rte_igbvf_pmd",
 990                 .id_table = pci_id_igbvf_map,
 991                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
 992         },
 993         .eth_dev_init = eth_igbvf_dev_init,
 994         .eth_dev_uninit = eth_igbvf_dev_uninit,
 995         .dev_private_size = sizeof(struct e1000_adapter),
 996 };
 997
 998 static int
 999 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1000 {
1001         rte_eth_driver_register(&rte_igb_pmd);
1002         return 0;
1003 }
1004
1005 static void
1006 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1007 {
1008         struct e1000_hw *hw =
1009                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1010         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1011         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1012         rctl |= E1000_RCTL_VFE;
1013         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1014 }
1015
1016 /*
1017  * VF Driver initialization routine.
1018  * Invoked one at EAL init time.
1019  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
1020  */
1021 static int
1022 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1023 {
1024         PMD_INIT_FUNC_TRACE();
1025
1026         rte_eth_driver_register(&rte_igbvf_pmd);
1027         return 0;
1028 }
1029
1030 static int
1031 igb_check_mq_mode(struct rte_eth_dev *dev)
1032 {
1033         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1034         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1035         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1036         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1037
1038         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1039             tx_mq_mode == ETH_MQ_TX_DCB ||
1040             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1041                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1042                 return -EINVAL;
1043         }
1044         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1045                 /* Check multi-queue mode.
1046                  * To no break software we accept ETH_MQ_RX_NONE as this might
1047                  * be used to turn off VLAN filter.
1048                  */
1049
1050                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1051                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1052                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1053                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1054                 } else {
1055                         /* Only support one queue on VFs.
1056                          * RSS together with SRIOV is not supported.
1057                          */
1058                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1059                                         " wrong mq_mode rx %d.",
1060                                         rx_mq_mode);
1061                         return -EINVAL;
1062                 }
1063                 /* TX mode is not used here, so mode might be ignored.*/
1064                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1065                         /* SRIOV only works in VMDq enable mode */
1066                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1067                                         " TX mode %d is not supported. "
1068                                         " Driver will behave as %d mode.",
1069                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1070                 }
1071
1072                 /* check valid queue number */
1073                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1074                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1075                                         " only support one queue on VFs.");
1076                         return -EINVAL;
1077                 }
1078         } else {
1079                 /* To no break software that set invalid mode, only display
1080                  * warning if invalid mode is used.
1081                  */
1082                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1083                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1084                     rx_mq_mode != ETH_MQ_RX_RSS) {
1085                         /* RSS together with VMDq not supported*/
1086                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1087                                      rx_mq_mode);
1088                         return -EINVAL;
1089                 }
1090
1091                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1092                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1093                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1094                                         " Due to txmode is meaningless in this"
1095                                         " driver, just ignore.",
1096                                         tx_mq_mode);
1097                 }
1098         }
1099         return 0;
1100 }
1101
1102 static int
1103 eth_igb_configure(struct rte_eth_dev *dev)
1104 {
1105         struct e1000_interrupt *intr =
1106                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1107         int ret;
1108
1109         PMD_INIT_FUNC_TRACE();
1110
1111         /* multipe queue mode checking */
1112         ret  = igb_check_mq_mode(dev);
1113         if (ret != 0) {
1114                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1115                             ret);
1116                 return ret;
1117         }
1118
1119         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1120         PMD_INIT_FUNC_TRACE();
1121
1122         return 0;
1123 }
1124
1125 static int
1126 eth_igb_start(struct rte_eth_dev *dev)
1127 {
1128         struct e1000_hw *hw =
1129                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1130         struct e1000_adapter *adapter =
1131                 E1000_DEV_PRIVATE(dev->data->dev_private);
1132         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1133         int ret, mask;
1134         uint32_t intr_vector = 0;
1135         uint32_t ctrl_ext;
1136
1137         PMD_INIT_FUNC_TRACE();
1138
1139         /* disable uio/vfio intr/eventfd mapping */
1140         rte_intr_disable(intr_handle);
1141
1142         /* Power up the phy. Needed to make the link go Up */
1143         e1000_power_up_phy(hw);
1144
1145         /*
1146          * Packet Buffer Allocation (PBA)
1147          * Writing PBA sets the receive portion of the buffer
1148          * the remainder is used for the transmit buffer.
1149          */
1150         if (hw->mac.type == e1000_82575) {
1151                 uint32_t pba;
1152
1153                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1154                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1155         }
1156
1157         /* Put the address into the Receive Address Array */
1158         e1000_rar_set(hw, hw->mac.addr, 0);
1159
1160         /* Initialize the hardware */
1161         if (igb_hardware_init(hw)) {
1162                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1163                 return -EIO;
1164         }
1165         adapter->stopped = 0;
1166
1167         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1168
1169         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1170         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1171         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1172         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1173         E1000_WRITE_FLUSH(hw);
1174
1175         /* configure PF module if SRIOV enabled */
1176         igb_pf_host_configure(dev);
1177
1178         /* check and configure queue intr-vector mapping */
1179         if ((rte_intr_cap_multiple(intr_handle) ||
1180              !RTE_ETH_DEV_SRIOV(dev).active) &&
1181             dev->data->dev_conf.intr_conf.rxq != 0) {
1182                 intr_vector = dev->data->nb_rx_queues;
1183                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1184                         return -1;
1185         }
1186
1187         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1188                 intr_handle->intr_vec =
1189                         rte_zmalloc("intr_vec",
1190                                     dev->data->nb_rx_queues * sizeof(int), 0);
1191                 if (intr_handle->intr_vec == NULL) {
1192                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1193                                      " intr_vec\n", dev->data->nb_rx_queues);
1194                         return -ENOMEM;
1195                 }
1196         }
1197
1198         /* confiugre msix for rx interrupt */
1199         eth_igb_configure_msix_intr(dev);
1200
1201         /* Configure for OS presence */
1202         igb_init_manageability(hw);
1203
1204         eth_igb_tx_init(dev);
1205
1206         /* This can fail when allocating mbufs for descriptor rings */
1207         ret = eth_igb_rx_init(dev);
1208         if (ret) {
1209                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1210                 igb_dev_clear_queues(dev);
1211                 return ret;
1212         }
1213
1214         e1000_clear_hw_cntrs_base_generic(hw);
1215
1216         /*
1217          * VLAN Offload Settings
1218          */
1219         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1220                         ETH_VLAN_EXTEND_MASK;
1221         eth_igb_vlan_offload_set(dev, mask);
1222
1223         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1224                 /* Enable VLAN filter since VMDq always use VLAN filter */
1225                 igb_vmdq_vlan_hw_filter_enable(dev);
1226         }
1227
1228         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1229                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1230                 (hw->mac.type == e1000_i211)) {
1231                 /* Configure EITR with the maximum possible value (0xFFFF) */
1232                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1233         }
1234
1235         /* Setup link speed and duplex */
1236         switch (dev->data->dev_conf.link_speed) {
1237         case ETH_LINK_SPEED_AUTONEG:
1238                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1239                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1240                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1241                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
1242                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1243                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
1244                 else
1245                         goto error_invalid_config;
1246                 break;
1247         case ETH_LINK_SPEED_10:
1248                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1249                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
1250                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1251                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
1252                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1253                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
1254                 else
1255                         goto error_invalid_config;
1256                 break;
1257         case ETH_LINK_SPEED_100:
1258                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1259                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
1260                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1261                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
1262                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1263                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
1264                 else
1265                         goto error_invalid_config;
1266                 break;
1267         case ETH_LINK_SPEED_1000:
1268                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
1269                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
1270                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
1271                 else
1272                         goto error_invalid_config;
1273                 break;
1274         case ETH_LINK_SPEED_10000:
1275         default:
1276                 goto error_invalid_config;
1277         }
1278         e1000_setup_link(hw);
1279
1280         if (rte_intr_allow_others(intr_handle)) {
1281                 /* check if lsc interrupt is enabled */
1282                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1283                         eth_igb_lsc_interrupt_setup(dev);
1284         } else {
1285                 rte_intr_callback_unregister(intr_handle,
1286                                              eth_igb_interrupt_handler,
1287                                              (void *)dev);
1288                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1289                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1290                                      " no intr multiplex\n");
1291         }
1292
1293         /* check if rxq interrupt is enabled */
1294         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1295             rte_intr_dp_is_en(intr_handle))
1296                 eth_igb_rxq_interrupt_setup(dev);
1297
1298         /* enable uio/vfio intr/eventfd mapping */
1299         rte_intr_enable(intr_handle);
1300
1301         /* resume enabled intr since hw reset */
1302         igb_intr_enable(dev);
1303
1304         PMD_INIT_LOG(DEBUG, "<<");
1305
1306         return 0;
1307
1308 error_invalid_config:
1309         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
1310                      dev->data->dev_conf.link_speed,
1311                      dev->data->dev_conf.link_duplex, dev->data->port_id);
1312         igb_dev_clear_queues(dev);
1313         return -EINVAL;
1314 }
1315
1316 /*********************************************************************
1317  *
1318  *  This routine disables all traffic on the adapter by issuing a
1319  *  global reset on the MAC.
1320  *
1321  **********************************************************************/
1322 static void
1323 eth_igb_stop(struct rte_eth_dev *dev)
1324 {
1325         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1326         struct e1000_filter_info *filter_info =
1327                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1328         struct rte_eth_link link;
1329         struct e1000_flex_filter *p_flex;
1330         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1331         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1332         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1333
1334         igb_intr_disable(hw);
1335
1336         /* disable intr eventfd mapping */
1337         rte_intr_disable(intr_handle);
1338
1339         igb_pf_reset_hw(hw);
1340         E1000_WRITE_REG(hw, E1000_WUC, 0);
1341
1342         /* Set bit for Go Link disconnect */
1343         if (hw->mac.type >= e1000_82580) {
1344                 uint32_t phpm_reg;
1345
1346                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1347                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1348                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1349         }
1350
1351         /* Power down the phy. Needed to make the link go Down */
1352         if (hw->phy.media_type == e1000_media_type_copper)
1353                 e1000_power_down_phy(hw);
1354         else
1355                 e1000_shutdown_fiber_serdes_link(hw);
1356
1357         igb_dev_clear_queues(dev);
1358
1359         /* clear the recorded link status */
1360         memset(&link, 0, sizeof(link));
1361         rte_igb_dev_atomic_write_link_status(dev, &link);
1362
1363         /* Remove all flex filters of the device */
1364         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1365                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1366                 rte_free(p_flex);
1367         }
1368         filter_info->flex_mask = 0;
1369
1370         /* Remove all ntuple filters of the device */
1371         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1372              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1373                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1374                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1375                              p_5tuple, entries);
1376                 rte_free(p_5tuple);
1377         }
1378         filter_info->fivetuple_mask = 0;
1379         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1380              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1381                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1382                 TAILQ_REMOVE(&filter_info->twotuple_list,
1383                              p_2tuple, entries);
1384                 rte_free(p_2tuple);
1385         }
1386         filter_info->twotuple_mask = 0;
1387
1388         if (!rte_intr_allow_others(intr_handle))
1389                 /* resume to the default handler */
1390                 rte_intr_callback_register(intr_handle,
1391                                            eth_igb_interrupt_handler,
1392                                            (void *)dev);
1393
1394         /* Clean datapath event and queue/vec mapping */
1395         rte_intr_efd_disable(intr_handle);
1396         if (intr_handle->intr_vec != NULL) {
1397                 rte_free(intr_handle->intr_vec);
1398                 intr_handle->intr_vec = NULL;
1399         }
1400 }
1401
1402 static void
1403 eth_igb_close(struct rte_eth_dev *dev)
1404 {
1405         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1406         struct e1000_adapter *adapter =
1407                 E1000_DEV_PRIVATE(dev->data->dev_private);
1408         struct rte_eth_link link;
1409         struct rte_pci_device *pci_dev;
1410
1411         eth_igb_stop(dev);
1412         adapter->stopped = 1;
1413
1414         e1000_phy_hw_reset(hw);
1415         igb_release_manageability(hw);
1416         igb_hw_control_release(hw);
1417
1418         /* Clear bit for Go Link disconnect */
1419         if (hw->mac.type >= e1000_82580) {
1420                 uint32_t phpm_reg;
1421
1422                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1423                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1424                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1425         }
1426
1427         igb_dev_free_queues(dev);
1428
1429         pci_dev = dev->pci_dev;
1430         if (pci_dev->intr_handle.intr_vec) {
1431                 rte_free(pci_dev->intr_handle.intr_vec);
1432                 pci_dev->intr_handle.intr_vec = NULL;
1433         }
1434
1435         memset(&link, 0, sizeof(link));
1436         rte_igb_dev_atomic_write_link_status(dev, &link);
1437 }
1438
1439 static int
1440 igb_get_rx_buffer_size(struct e1000_hw *hw)
1441 {
1442         uint32_t rx_buf_size;
1443         if (hw->mac.type == e1000_82576) {
1444                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1445         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1446                 /* PBS needs to be translated according to a lookup table */
1447                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1448                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1449                 rx_buf_size = (rx_buf_size << 10);
1450         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1451                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1452         } else {
1453                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1454         }
1455
1456         return rx_buf_size;
1457 }
1458
1459 /*********************************************************************
1460  *
1461  *  Initialize the hardware
1462  *
1463  **********************************************************************/
1464 static int
1465 igb_hardware_init(struct e1000_hw *hw)
1466 {
1467         uint32_t rx_buf_size;
1468         int diag;
1469
1470         /* Let the firmware know the OS is in control */
1471         igb_hw_control_acquire(hw);
1472
1473         /*
1474          * These parameters control the automatic generation (Tx) and
1475          * response (Rx) to Ethernet PAUSE frames.
1476          * - High water mark should allow for at least two standard size (1518)
1477          *   frames to be received after sending an XOFF.
1478          * - Low water mark works best when it is very near the high water mark.
1479          *   This allows the receiver to restart by sending XON when it has
1480          *   drained a bit. Here we use an arbitrary value of 1500 which will
1481          *   restart after one full frame is pulled from the buffer. There
1482          *   could be several smaller frames in the buffer and if so they will
1483          *   not trigger the XON until their total number reduces the buffer
1484          *   by 1500.
1485          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1486          */
1487         rx_buf_size = igb_get_rx_buffer_size(hw);
1488
1489         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1490         hw->fc.low_water = hw->fc.high_water - 1500;
1491         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1492         hw->fc.send_xon = 1;
1493
1494         /* Set Flow control, use the tunable location if sane */
1495         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1496                 hw->fc.requested_mode = igb_fc_setting;
1497         else
1498                 hw->fc.requested_mode = e1000_fc_none;
1499
1500         /* Issue a global reset */
1501         igb_pf_reset_hw(hw);
1502         E1000_WRITE_REG(hw, E1000_WUC, 0);
1503
1504         diag = e1000_init_hw(hw);
1505         if (diag < 0)
1506                 return diag;
1507
1508         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1509         e1000_get_phy_info(hw);
1510         e1000_check_for_link(hw);
1511
1512         return 0;
1513 }
1514
1515 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1516 static void
1517 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1518 {
1519         int pause_frames;
1520
1521         uint64_t old_gprc  = stats->gprc;
1522         uint64_t old_gptc  = stats->gptc;
1523         uint64_t old_tpr   = stats->tpr;
1524         uint64_t old_tpt   = stats->tpt;
1525         uint64_t old_rpthc = stats->rpthc;
1526         uint64_t old_hgptc = stats->hgptc;
1527
1528         if(hw->phy.media_type == e1000_media_type_copper ||
1529             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1530                 stats->symerrs +=
1531                     E1000_READ_REG(hw,E1000_SYMERRS);
1532                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1533         }
1534
1535         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1536         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1537         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1538         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1539
1540         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1541         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1542         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1543         stats->dc += E1000_READ_REG(hw, E1000_DC);
1544         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1545         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1546         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1547         /*
1548         ** For watchdog management we need to know if we have been
1549         ** paused during the last interval, so capture that here.
1550         */
1551         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1552         stats->xoffrxc += pause_frames;
1553         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1554         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1555         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1556         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1557         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1558         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1559         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1560         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1561         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1562         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1563         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1564         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1565
1566         /* For the 64-bit byte counters the low dword must be read first. */
1567         /* Both registers clear on the read of the high dword */
1568
1569         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1570         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1571         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1572         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1573         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1574         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1575         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1576
1577         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1578         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1579         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1580         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1581         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1582
1583         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1584         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1585
1586         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1587         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1588         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1589         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1590         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1591         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1592
1593         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1594         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1595         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1596         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1597         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1598         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1599         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1600         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1601
1602         /* Interrupt Counts */
1603
1604         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1605         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1606         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1607         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1608         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1609         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1610         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1611         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1612         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1613
1614         /* Host to Card Statistics */
1615
1616         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1617         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1618         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1619         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1620         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1621         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1622         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1623         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1624         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1625         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1626         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1627         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1628         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1629         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1630         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1631         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1632
1633         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1634         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1635         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1636         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1637         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1638         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1639 }
1640
1641 static void
1642 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1643 {
1644         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1645         struct e1000_hw_stats *stats =
1646                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1647
1648         igb_read_stats_registers(hw, stats);
1649
1650         if (rte_stats == NULL)
1651                 return;
1652
1653         /* Rx Errors */
1654         rte_stats->imissed = stats->mpc;
1655         rte_stats->ierrors = stats->crcerrs +
1656                              stats->rlec + stats->ruc + stats->roc +
1657                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1658
1659         /* Tx Errors */
1660         rte_stats->oerrors = stats->ecol + stats->latecol;
1661
1662         rte_stats->ipackets = stats->gprc;
1663         rte_stats->opackets = stats->gptc;
1664         rte_stats->ibytes   = stats->gorc;
1665         rte_stats->obytes   = stats->gotc;
1666 }
1667
1668 static void
1669 eth_igb_stats_reset(struct rte_eth_dev *dev)
1670 {
1671         struct e1000_hw_stats *hw_stats =
1672                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1673
1674         /* HW registers are cleared on read */
1675         eth_igb_stats_get(dev, NULL);
1676
1677         /* Reset software totals */
1678         memset(hw_stats, 0, sizeof(*hw_stats));
1679 }
1680
1681 static void
1682 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1683 {
1684         struct e1000_hw_stats *stats =
1685                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1686
1687         /* HW registers are cleared on read */
1688         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1689
1690         /* Reset software totals */
1691         memset(stats, 0, sizeof(*stats));
1692 }
1693
1694 static int
1695 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1696                    unsigned n)
1697 {
1698         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1699         struct e1000_hw_stats *hw_stats =
1700                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1701         unsigned i;
1702
1703         if (n < IGB_NB_XSTATS)
1704                 return IGB_NB_XSTATS;
1705
1706         igb_read_stats_registers(hw, hw_stats);
1707
1708         /* If this is a reset xstats is NULL, and we have cleared the
1709          * registers by reading them.
1710          */
1711         if (!xstats)
1712                 return 0;
1713
1714         /* Extended stats */
1715         for (i = 0; i < IGB_NB_XSTATS; i++) {
1716                 snprintf(xstats[i].name, sizeof(xstats[i].name),
1717                          "%s", rte_igb_stats_strings[i].name);
1718                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1719                         rte_igb_stats_strings[i].offset);
1720         }
1721
1722         return IGB_NB_XSTATS;
1723 }
1724
1725 static void
1726 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1727 {
1728         /* Good Rx packets, include VF loopback */
1729         UPDATE_VF_STAT(E1000_VFGPRC,
1730             hw_stats->last_gprc, hw_stats->gprc);
1731
1732         /* Good Rx octets, include VF loopback */
1733         UPDATE_VF_STAT(E1000_VFGORC,
1734             hw_stats->last_gorc, hw_stats->gorc);
1735
1736         /* Good Tx packets, include VF loopback */
1737         UPDATE_VF_STAT(E1000_VFGPTC,
1738             hw_stats->last_gptc, hw_stats->gptc);
1739
1740         /* Good Tx octets, include VF loopback */
1741         UPDATE_VF_STAT(E1000_VFGOTC,
1742             hw_stats->last_gotc, hw_stats->gotc);
1743
1744         /* Rx Multicst packets */
1745         UPDATE_VF_STAT(E1000_VFMPRC,
1746             hw_stats->last_mprc, hw_stats->mprc);
1747
1748         /* Good Rx loopback packets */
1749         UPDATE_VF_STAT(E1000_VFGPRLBC,
1750             hw_stats->last_gprlbc, hw_stats->gprlbc);
1751
1752         /* Good Rx loopback octets */
1753         UPDATE_VF_STAT(E1000_VFGORLBC,
1754             hw_stats->last_gorlbc, hw_stats->gorlbc);
1755
1756         /* Good Tx loopback packets */
1757         UPDATE_VF_STAT(E1000_VFGPTLBC,
1758             hw_stats->last_gptlbc, hw_stats->gptlbc);
1759
1760         /* Good Tx loopback octets */
1761         UPDATE_VF_STAT(E1000_VFGOTLBC,
1762             hw_stats->last_gotlbc, hw_stats->gotlbc);
1763 }
1764
1765 static int
1766 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1767                      unsigned n)
1768 {
1769         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1770         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1771                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1772         unsigned i;
1773
1774         if (n < IGBVF_NB_XSTATS)
1775                 return IGBVF_NB_XSTATS;
1776
1777         igbvf_read_stats_registers(hw, hw_stats);
1778
1779         if (!xstats)
1780                 return 0;
1781
1782         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1783                 snprintf(xstats[i].name, sizeof(xstats[i].name), "%s",
1784                          rte_igbvf_stats_strings[i].name);
1785                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1786                         rte_igbvf_stats_strings[i].offset);
1787         }
1788
1789         return IGBVF_NB_XSTATS;
1790 }
1791
1792 static void
1793 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1794 {
1795         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1796         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1797                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1798
1799         igbvf_read_stats_registers(hw, hw_stats);
1800
1801         if (rte_stats == NULL)
1802                 return;
1803
1804         rte_stats->ipackets = hw_stats->gprc;
1805         rte_stats->ibytes = hw_stats->gorc;
1806         rte_stats->opackets = hw_stats->gptc;
1807         rte_stats->obytes = hw_stats->gotc;
1808         rte_stats->imcasts = hw_stats->mprc;
1809         rte_stats->ilbpackets = hw_stats->gprlbc;
1810         rte_stats->ilbbytes = hw_stats->gorlbc;
1811         rte_stats->olbpackets = hw_stats->gptlbc;
1812         rte_stats->olbbytes = hw_stats->gotlbc;
1813 }
1814
1815 static void
1816 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1817 {
1818         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1819                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1820
1821         /* Sync HW register to the last stats */
1822         eth_igbvf_stats_get(dev, NULL);
1823
1824         /* reset HW current stats*/
1825         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1826                offsetof(struct e1000_vf_stats, gprc));
1827 }
1828
1829 static void
1830 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1831 {
1832         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833
1834         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1835         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1836         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1837         dev_info->rx_offload_capa =
1838                 DEV_RX_OFFLOAD_VLAN_STRIP |
1839                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1840                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1841                 DEV_RX_OFFLOAD_TCP_CKSUM;
1842         dev_info->tx_offload_capa =
1843                 DEV_TX_OFFLOAD_VLAN_INSERT |
1844                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1845                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1846                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1847                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1848                 DEV_TX_OFFLOAD_TCP_TSO;
1849
1850         switch (hw->mac.type) {
1851         case e1000_82575:
1852                 dev_info->max_rx_queues = 4;
1853                 dev_info->max_tx_queues = 4;
1854                 dev_info->max_vmdq_pools = 0;
1855                 break;
1856
1857         case e1000_82576:
1858                 dev_info->max_rx_queues = 16;
1859                 dev_info->max_tx_queues = 16;
1860                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1861                 dev_info->vmdq_queue_num = 16;
1862                 break;
1863
1864         case e1000_82580:
1865                 dev_info->max_rx_queues = 8;
1866                 dev_info->max_tx_queues = 8;
1867                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1868                 dev_info->vmdq_queue_num = 8;
1869                 break;
1870
1871         case e1000_i350:
1872                 dev_info->max_rx_queues = 8;
1873                 dev_info->max_tx_queues = 8;
1874                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1875                 dev_info->vmdq_queue_num = 8;
1876                 break;
1877
1878         case e1000_i354:
1879                 dev_info->max_rx_queues = 8;
1880                 dev_info->max_tx_queues = 8;
1881                 break;
1882
1883         case e1000_i210:
1884                 dev_info->max_rx_queues = 4;
1885                 dev_info->max_tx_queues = 4;
1886                 dev_info->max_vmdq_pools = 0;
1887                 break;
1888
1889         case e1000_i211:
1890                 dev_info->max_rx_queues = 2;
1891                 dev_info->max_tx_queues = 2;
1892                 dev_info->max_vmdq_pools = 0;
1893                 break;
1894
1895         default:
1896                 /* Should not happen */
1897                 break;
1898         }
1899         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1900         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1901         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1902
1903         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1904                 .rx_thresh = {
1905                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1906                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1907                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1908                 },
1909                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1910                 .rx_drop_en = 0,
1911         };
1912
1913         dev_info->default_txconf = (struct rte_eth_txconf) {
1914                 .tx_thresh = {
1915                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1916                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1917                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1918                 },
1919                 .txq_flags = 0,
1920         };
1921
1922         dev_info->rx_desc_lim = rx_desc_lim;
1923         dev_info->tx_desc_lim = tx_desc_lim;
1924 }
1925
1926 static const uint32_t *
1927 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
1928 {
1929         static const uint32_t ptypes[] = {
1930                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
1931                 RTE_PTYPE_L2_ETHER,
1932                 RTE_PTYPE_L3_IPV4,
1933                 RTE_PTYPE_L3_IPV4_EXT,
1934                 RTE_PTYPE_L3_IPV6,
1935                 RTE_PTYPE_L3_IPV6_EXT,
1936                 RTE_PTYPE_L4_TCP,
1937                 RTE_PTYPE_L4_UDP,
1938                 RTE_PTYPE_L4_SCTP,
1939                 RTE_PTYPE_TUNNEL_IP,
1940                 RTE_PTYPE_INNER_L3_IPV6,
1941                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1942                 RTE_PTYPE_INNER_L4_TCP,
1943                 RTE_PTYPE_INNER_L4_UDP,
1944                 RTE_PTYPE_UNKNOWN
1945         };
1946
1947         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
1948             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
1949                 return ptypes;
1950         return NULL;
1951 }
1952
1953 static void
1954 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1955 {
1956         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1957
1958         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1959         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1960         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1961         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1962                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1963                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1964                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1965         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1966                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1967                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1968                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1969                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1970                                 DEV_TX_OFFLOAD_TCP_TSO;
1971         switch (hw->mac.type) {
1972         case e1000_vfadapt:
1973                 dev_info->max_rx_queues = 2;
1974                 dev_info->max_tx_queues = 2;
1975                 break;
1976         case e1000_vfadapt_i350:
1977                 dev_info->max_rx_queues = 1;
1978                 dev_info->max_tx_queues = 1;
1979                 break;
1980         default:
1981                 /* Should not happen */
1982                 break;
1983         }
1984
1985         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1986                 .rx_thresh = {
1987                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1988                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1989                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1990                 },
1991                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1992                 .rx_drop_en = 0,
1993         };
1994
1995         dev_info->default_txconf = (struct rte_eth_txconf) {
1996                 .tx_thresh = {
1997                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1998                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1999                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2000                 },
2001                 .txq_flags = 0,
2002         };
2003
2004         dev_info->rx_desc_lim = rx_desc_lim;
2005         dev_info->tx_desc_lim = tx_desc_lim;
2006 }
2007
2008 /* return 0 means link status changed, -1 means not changed */
2009 static int
2010 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2011 {
2012         struct e1000_hw *hw =
2013                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2014         struct rte_eth_link link, old;
2015         int link_check, count;
2016
2017         link_check = 0;
2018         hw->mac.get_link_status = 1;
2019
2020         /* possible wait-to-complete in up to 9 seconds */
2021         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2022                 /* Read the real link status */
2023                 switch (hw->phy.media_type) {
2024                 case e1000_media_type_copper:
2025                         /* Do the work to read phy */
2026                         e1000_check_for_link(hw);
2027                         link_check = !hw->mac.get_link_status;
2028                         break;
2029
2030                 case e1000_media_type_fiber:
2031                         e1000_check_for_link(hw);
2032                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2033                                       E1000_STATUS_LU);
2034                         break;
2035
2036                 case e1000_media_type_internal_serdes:
2037                         e1000_check_for_link(hw);
2038                         link_check = hw->mac.serdes_has_link;
2039                         break;
2040
2041                 /* VF device is type_unknown */
2042                 case e1000_media_type_unknown:
2043                         eth_igbvf_link_update(hw);
2044                         link_check = !hw->mac.get_link_status;
2045                         break;
2046
2047                 default:
2048                         break;
2049                 }
2050                 if (link_check || wait_to_complete == 0)
2051                         break;
2052                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2053         }
2054         memset(&link, 0, sizeof(link));
2055         rte_igb_dev_atomic_read_link_status(dev, &link);
2056         old = link;
2057
2058         /* Now we check if a transition has happened */
2059         if (link_check) {
2060                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
2061                                           &link.link_duplex);
2062                 link.link_status = ETH_LINK_UP;
2063         } else if (!link_check) {
2064                 link.link_speed = 0;
2065                 link.link_duplex = 0;
2066                 link.link_status = ETH_LINK_DOWN;
2067         }
2068         rte_igb_dev_atomic_write_link_status(dev, &link);
2069
2070         /* not changed */
2071         if (old.link_status == link.link_status)
2072                 return -1;
2073
2074         /* changed */
2075         return 0;
2076 }
2077
2078 /*
2079  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2080  * For ASF and Pass Through versions of f/w this means
2081  * that the driver is loaded.
2082  */
2083 static void
2084 igb_hw_control_acquire(struct e1000_hw *hw)
2085 {
2086         uint32_t ctrl_ext;
2087
2088         /* Let firmware know the driver has taken over */
2089         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2090         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2091 }
2092
2093 /*
2094  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2095  * For ASF and Pass Through versions of f/w this means that the
2096  * driver is no longer loaded.
2097  */
2098 static void
2099 igb_hw_control_release(struct e1000_hw *hw)
2100 {
2101         uint32_t ctrl_ext;
2102
2103         /* Let firmware taken over control of h/w */
2104         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2105         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2106                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2107 }
2108
2109 /*
2110  * Bit of a misnomer, what this really means is
2111  * to enable OS management of the system... aka
2112  * to disable special hardware management features.
2113  */
2114 static void
2115 igb_init_manageability(struct e1000_hw *hw)
2116 {
2117         if (e1000_enable_mng_pass_thru(hw)) {
2118                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2119                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2120
2121                 /* disable hardware interception of ARP */
2122                 manc &= ~(E1000_MANC_ARP_EN);
2123
2124                 /* enable receiving management packets to the host */
2125                 manc |= E1000_MANC_EN_MNG2HOST;
2126                 manc2h |= 1 << 5;  /* Mng Port 623 */
2127                 manc2h |= 1 << 6;  /* Mng Port 664 */
2128                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2129                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2130         }
2131 }
2132
2133 static void
2134 igb_release_manageability(struct e1000_hw *hw)
2135 {
2136         if (e1000_enable_mng_pass_thru(hw)) {
2137                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2138
2139                 manc |= E1000_MANC_ARP_EN;
2140                 manc &= ~E1000_MANC_EN_MNG2HOST;
2141
2142                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2143         }
2144 }
2145
2146 static void
2147 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2148 {
2149         struct e1000_hw *hw =
2150                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2151         uint32_t rctl;
2152
2153         rctl = E1000_READ_REG(hw, E1000_RCTL);
2154         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2155         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2156 }
2157
2158 static void
2159 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2160 {
2161         struct e1000_hw *hw =
2162                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2163         uint32_t rctl;
2164
2165         rctl = E1000_READ_REG(hw, E1000_RCTL);
2166         rctl &= (~E1000_RCTL_UPE);
2167         if (dev->data->all_multicast == 1)
2168                 rctl |= E1000_RCTL_MPE;
2169         else
2170                 rctl &= (~E1000_RCTL_MPE);
2171         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2172 }
2173
2174 static void
2175 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2176 {
2177         struct e1000_hw *hw =
2178                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2179         uint32_t rctl;
2180
2181         rctl = E1000_READ_REG(hw, E1000_RCTL);
2182         rctl |= E1000_RCTL_MPE;
2183         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2184 }
2185
2186 static void
2187 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2188 {
2189         struct e1000_hw *hw =
2190                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2191         uint32_t rctl;
2192
2193         if (dev->data->promiscuous == 1)
2194                 return; /* must remain in all_multicast mode */
2195         rctl = E1000_READ_REG(hw, E1000_RCTL);
2196         rctl &= (~E1000_RCTL_MPE);
2197         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2198 }
2199
2200 static int
2201 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2202 {
2203         struct e1000_hw *hw =
2204                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2205         struct e1000_vfta * shadow_vfta =
2206                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2207         uint32_t vfta;
2208         uint32_t vid_idx;
2209         uint32_t vid_bit;
2210
2211         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2212                               E1000_VFTA_ENTRY_MASK);
2213         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2214         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2215         if (on)
2216                 vfta |= vid_bit;
2217         else
2218                 vfta &= ~vid_bit;
2219         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2220
2221         /* update local VFTA copy */
2222         shadow_vfta->vfta[vid_idx] = vfta;
2223
2224         return 0;
2225 }
2226
2227 static int
2228 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2229                       enum rte_vlan_type vlan_type,
2230                       uint16_t tpid)
2231 {
2232         struct e1000_hw *hw =
2233                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2234         uint32_t reg = ETHER_TYPE_VLAN;
2235         int ret = 0;
2236
2237         switch (vlan_type) {
2238         case ETH_VLAN_TYPE_INNER:
2239                 reg |= (tpid << 16);
2240                 E1000_WRITE_REG(hw, E1000_VET, reg);
2241                 break;
2242         default:
2243                 ret = -EINVAL;
2244                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
2245                 break;
2246         }
2247
2248         return ret;
2249 }
2250
2251 static void
2252 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2253 {
2254         struct e1000_hw *hw =
2255                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2256         uint32_t reg;
2257
2258         /* Filter Table Disable */
2259         reg = E1000_READ_REG(hw, E1000_RCTL);
2260         reg &= ~E1000_RCTL_CFIEN;
2261         reg &= ~E1000_RCTL_VFE;
2262         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2263 }
2264
2265 static void
2266 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2267 {
2268         struct e1000_hw *hw =
2269                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2270         struct e1000_vfta * shadow_vfta =
2271                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2272         uint32_t reg;
2273         int i;
2274
2275         /* Filter Table Enable, CFI not used for packet acceptance */
2276         reg = E1000_READ_REG(hw, E1000_RCTL);
2277         reg &= ~E1000_RCTL_CFIEN;
2278         reg |= E1000_RCTL_VFE;
2279         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2280
2281         /* restore VFTA table */
2282         for (i = 0; i < IGB_VFTA_SIZE; i++)
2283                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2284 }
2285
2286 static void
2287 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2288 {
2289         struct e1000_hw *hw =
2290                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2291         uint32_t reg;
2292
2293         /* VLAN Mode Disable */
2294         reg = E1000_READ_REG(hw, E1000_CTRL);
2295         reg &= ~E1000_CTRL_VME;
2296         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2297 }
2298
2299 static void
2300 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2301 {
2302         struct e1000_hw *hw =
2303                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2304         uint32_t reg;
2305
2306         /* VLAN Mode Enable */
2307         reg = E1000_READ_REG(hw, E1000_CTRL);
2308         reg |= E1000_CTRL_VME;
2309         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2310 }
2311
2312 static void
2313 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2314 {
2315         struct e1000_hw *hw =
2316                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2317         uint32_t reg;
2318
2319         /* CTRL_EXT: Extended VLAN */
2320         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2321         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2322         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2323
2324         /* Update maximum packet length */
2325         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2326                 E1000_WRITE_REG(hw, E1000_RLPML,
2327                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2328                                                 VLAN_TAG_SIZE);
2329 }
2330
2331 static void
2332 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2333 {
2334         struct e1000_hw *hw =
2335                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2336         uint32_t reg;
2337
2338         /* CTRL_EXT: Extended VLAN */
2339         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2340         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2341         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2342
2343         /* Update maximum packet length */
2344         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2345                 E1000_WRITE_REG(hw, E1000_RLPML,
2346                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2347                                                 2 * VLAN_TAG_SIZE);
2348 }
2349
2350 static void
2351 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2352 {
2353         if(mask & ETH_VLAN_STRIP_MASK){
2354                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2355                         igb_vlan_hw_strip_enable(dev);
2356                 else
2357                         igb_vlan_hw_strip_disable(dev);
2358         }
2359
2360         if(mask & ETH_VLAN_FILTER_MASK){
2361                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2362                         igb_vlan_hw_filter_enable(dev);
2363                 else
2364                         igb_vlan_hw_filter_disable(dev);
2365         }
2366
2367         if(mask & ETH_VLAN_EXTEND_MASK){
2368                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2369                         igb_vlan_hw_extend_enable(dev);
2370                 else
2371                         igb_vlan_hw_extend_disable(dev);
2372         }
2373 }
2374
2375
2376 /**
2377  * It enables the interrupt mask and then enable the interrupt.
2378  *
2379  * @param dev
2380  *  Pointer to struct rte_eth_dev.
2381  *
2382  * @return
2383  *  - On success, zero.
2384  *  - On failure, a negative value.
2385  */
2386 static int
2387 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2388 {
2389         struct e1000_interrupt *intr =
2390                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2391
2392         intr->mask |= E1000_ICR_LSC;
2393
2394         return 0;
2395 }
2396
2397 /* It clears the interrupt causes and enables the interrupt.
2398  * It will be called once only during nic initialized.
2399  *
2400  * @param dev
2401  *  Pointer to struct rte_eth_dev.
2402  *
2403  * @return
2404  *  - On success, zero.
2405  *  - On failure, a negative value.
2406  */
2407 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2408 {
2409         uint32_t mask, regval;
2410         struct e1000_hw *hw =
2411                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2412         struct rte_eth_dev_info dev_info;
2413
2414         memset(&dev_info, 0, sizeof(dev_info));
2415         eth_igb_infos_get(dev, &dev_info);
2416
2417         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2418         regval = E1000_READ_REG(hw, E1000_EIMS);
2419         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2420
2421         return 0;
2422 }
2423
2424 /*
2425  * It reads ICR and gets interrupt causes, check it and set a bit flag
2426  * to update link status.
2427  *
2428  * @param dev
2429  *  Pointer to struct rte_eth_dev.
2430  *
2431  * @return
2432  *  - On success, zero.
2433  *  - On failure, a negative value.
2434  */
2435 static int
2436 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2437 {
2438         uint32_t icr;
2439         struct e1000_hw *hw =
2440                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2441         struct e1000_interrupt *intr =
2442                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2443
2444         igb_intr_disable(hw);
2445
2446         /* read-on-clear nic registers here */
2447         icr = E1000_READ_REG(hw, E1000_ICR);
2448
2449         intr->flags = 0;
2450         if (icr & E1000_ICR_LSC) {
2451                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2452         }
2453
2454         if (icr & E1000_ICR_VMMB)
2455                 intr->flags |= E1000_FLAG_MAILBOX;
2456
2457         return 0;
2458 }
2459
2460 /*
2461  * It executes link_update after knowing an interrupt is prsent.
2462  *
2463  * @param dev
2464  *  Pointer to struct rte_eth_dev.
2465  *
2466  * @return
2467  *  - On success, zero.
2468  *  - On failure, a negative value.
2469  */
2470 static int
2471 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2472 {
2473         struct e1000_hw *hw =
2474                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2475         struct e1000_interrupt *intr =
2476                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2477         uint32_t tctl, rctl;
2478         struct rte_eth_link link;
2479         int ret;
2480
2481         if (intr->flags & E1000_FLAG_MAILBOX) {
2482                 igb_pf_mbx_process(dev);
2483                 intr->flags &= ~E1000_FLAG_MAILBOX;
2484         }
2485
2486         igb_intr_enable(dev);
2487         rte_intr_enable(&(dev->pci_dev->intr_handle));
2488
2489         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2490                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2491
2492                 /* set get_link_status to check register later */
2493                 hw->mac.get_link_status = 1;
2494                 ret = eth_igb_link_update(dev, 0);
2495
2496                 /* check if link has changed */
2497                 if (ret < 0)
2498                         return 0;
2499
2500                 memset(&link, 0, sizeof(link));
2501                 rte_igb_dev_atomic_read_link_status(dev, &link);
2502                 if (link.link_status) {
2503                         PMD_INIT_LOG(INFO,
2504                                      " Port %d: Link Up - speed %u Mbps - %s",
2505                                      dev->data->port_id,
2506                                      (unsigned)link.link_speed,
2507                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2508                                      "full-duplex" : "half-duplex");
2509                 } else {
2510                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2511                                      dev->data->port_id);
2512                 }
2513
2514                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2515                              dev->pci_dev->addr.domain,
2516                              dev->pci_dev->addr.bus,
2517                              dev->pci_dev->addr.devid,
2518                              dev->pci_dev->addr.function);
2519                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2520                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2521                 if (link.link_status) {
2522                         /* enable Tx/Rx */
2523                         tctl |= E1000_TCTL_EN;
2524                         rctl |= E1000_RCTL_EN;
2525                 } else {
2526                         /* disable Tx/Rx */
2527                         tctl &= ~E1000_TCTL_EN;
2528                         rctl &= ~E1000_RCTL_EN;
2529                 }
2530                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2531                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2532                 E1000_WRITE_FLUSH(hw);
2533                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2534         }
2535
2536         return 0;
2537 }
2538
2539 /**
2540  * Interrupt handler which shall be registered at first.
2541  *
2542  * @param handle
2543  *  Pointer to interrupt handle.
2544  * @param param
2545  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2546  *
2547  * @return
2548  *  void
2549  */
2550 static void
2551 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2552                                                         void *param)
2553 {
2554         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2555
2556         eth_igb_interrupt_get_status(dev);
2557         eth_igb_interrupt_action(dev);
2558 }
2559
2560 static int
2561 eth_igb_led_on(struct rte_eth_dev *dev)
2562 {
2563         struct e1000_hw *hw;
2564
2565         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2566         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2567 }
2568
2569 static int
2570 eth_igb_led_off(struct rte_eth_dev *dev)
2571 {
2572         struct e1000_hw *hw;
2573
2574         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2575         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2576 }
2577
2578 static int
2579 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2580 {
2581         struct e1000_hw *hw;
2582         uint32_t ctrl;
2583         int tx_pause;
2584         int rx_pause;
2585
2586         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2587         fc_conf->pause_time = hw->fc.pause_time;
2588         fc_conf->high_water = hw->fc.high_water;
2589         fc_conf->low_water = hw->fc.low_water;
2590         fc_conf->send_xon = hw->fc.send_xon;
2591         fc_conf->autoneg = hw->mac.autoneg;
2592
2593         /*
2594          * Return rx_pause and tx_pause status according to actual setting of
2595          * the TFCE and RFCE bits in the CTRL register.
2596          */
2597         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2598         if (ctrl & E1000_CTRL_TFCE)
2599                 tx_pause = 1;
2600         else
2601                 tx_pause = 0;
2602
2603         if (ctrl & E1000_CTRL_RFCE)
2604                 rx_pause = 1;
2605         else
2606                 rx_pause = 0;
2607
2608         if (rx_pause && tx_pause)
2609                 fc_conf->mode = RTE_FC_FULL;
2610         else if (rx_pause)
2611                 fc_conf->mode = RTE_FC_RX_PAUSE;
2612         else if (tx_pause)
2613                 fc_conf->mode = RTE_FC_TX_PAUSE;
2614         else
2615                 fc_conf->mode = RTE_FC_NONE;
2616
2617         return 0;
2618 }
2619
2620 static int
2621 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2622 {
2623         struct e1000_hw *hw;
2624         int err;
2625         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2626                 e1000_fc_none,
2627                 e1000_fc_rx_pause,
2628                 e1000_fc_tx_pause,
2629                 e1000_fc_full
2630         };
2631         uint32_t rx_buf_size;
2632         uint32_t max_high_water;
2633         uint32_t rctl;
2634
2635         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2636         if (fc_conf->autoneg != hw->mac.autoneg)
2637                 return -ENOTSUP;
2638         rx_buf_size = igb_get_rx_buffer_size(hw);
2639         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2640
2641         /* At least reserve one Ethernet frame for watermark */
2642         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2643         if ((fc_conf->high_water > max_high_water) ||
2644             (fc_conf->high_water < fc_conf->low_water)) {
2645                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2646                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2647                 return -EINVAL;
2648         }
2649
2650         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2651         hw->fc.pause_time     = fc_conf->pause_time;
2652         hw->fc.high_water     = fc_conf->high_water;
2653         hw->fc.low_water      = fc_conf->low_water;
2654         hw->fc.send_xon       = fc_conf->send_xon;
2655
2656         err = e1000_setup_link_generic(hw);
2657         if (err == E1000_SUCCESS) {
2658
2659                 /* check if we want to forward MAC frames - driver doesn't have native
2660                  * capability to do that, so we'll write the registers ourselves */
2661
2662                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2663
2664                 /* set or clear MFLCN.PMCF bit depending on configuration */
2665                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2666                         rctl |= E1000_RCTL_PMCF;
2667                 else
2668                         rctl &= ~E1000_RCTL_PMCF;
2669
2670                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2671                 E1000_WRITE_FLUSH(hw);
2672
2673                 return 0;
2674         }
2675
2676         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2677         return -EIO;
2678 }
2679
2680 #define E1000_RAH_POOLSEL_SHIFT      (18)
2681 static void
2682 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2683                 uint32_t index, __rte_unused uint32_t pool)
2684 {
2685         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2686         uint32_t rah;
2687
2688         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2689         rah = E1000_READ_REG(hw, E1000_RAH(index));
2690         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2691         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2692 }
2693
2694 static void
2695 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2696 {
2697         uint8_t addr[ETHER_ADDR_LEN];
2698         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2699
2700         memset(addr, 0, sizeof(addr));
2701
2702         e1000_rar_set(hw, addr, index);
2703 }
2704
2705 static void
2706 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2707                                 struct ether_addr *addr)
2708 {
2709         eth_igb_rar_clear(dev, 0);
2710
2711         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2712 }
2713 /*
2714  * Virtual Function operations
2715  */
2716 static void
2717 igbvf_intr_disable(struct e1000_hw *hw)
2718 {
2719         PMD_INIT_FUNC_TRACE();
2720
2721         /* Clear interrupt mask to stop from interrupts being generated */
2722         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2723
2724         E1000_WRITE_FLUSH(hw);
2725 }
2726
2727 static void
2728 igbvf_stop_adapter(struct rte_eth_dev *dev)
2729 {
2730         u32 reg_val;
2731         u16 i;
2732         struct rte_eth_dev_info dev_info;
2733         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2734
2735         memset(&dev_info, 0, sizeof(dev_info));
2736         eth_igbvf_infos_get(dev, &dev_info);
2737
2738         /* Clear interrupt mask to stop from interrupts being generated */
2739         igbvf_intr_disable(hw);
2740
2741         /* Clear any pending interrupts, flush previous writes */
2742         E1000_READ_REG(hw, E1000_EICR);
2743
2744         /* Disable the transmit unit.  Each queue must be disabled. */
2745         for (i = 0; i < dev_info.max_tx_queues; i++)
2746                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2747
2748         /* Disable the receive unit by stopping each queue */
2749         for (i = 0; i < dev_info.max_rx_queues; i++) {
2750                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2751                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2752                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2753                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2754                         ;
2755         }
2756
2757         /* flush all queues disables */
2758         E1000_WRITE_FLUSH(hw);
2759         msec_delay(2);
2760 }
2761
2762 static int eth_igbvf_link_update(struct e1000_hw *hw)
2763 {
2764         struct e1000_mbx_info *mbx = &hw->mbx;
2765         struct e1000_mac_info *mac = &hw->mac;
2766         int ret_val = E1000_SUCCESS;
2767
2768         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2769
2770         /*
2771          * We only want to run this if there has been a rst asserted.
2772          * in this case that could mean a link change, device reset,
2773          * or a virtual function reset
2774          */
2775
2776         /* If we were hit with a reset or timeout drop the link */
2777         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2778                 mac->get_link_status = TRUE;
2779
2780         if (!mac->get_link_status)
2781                 goto out;
2782
2783         /* if link status is down no point in checking to see if pf is up */
2784         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2785                 goto out;
2786
2787         /* if we passed all the tests above then the link is up and we no
2788          * longer need to check for link */
2789         mac->get_link_status = FALSE;
2790
2791 out:
2792         return ret_val;
2793 }
2794
2795
2796 static int
2797 igbvf_dev_configure(struct rte_eth_dev *dev)
2798 {
2799         struct rte_eth_conf* conf = &dev->data->dev_conf;
2800
2801         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2802                      dev->data->port_id);
2803
2804         /*
2805          * VF has no ability to enable/disable HW CRC
2806          * Keep the persistent behavior the same as Host PF
2807          */
2808 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2809         if (!conf->rxmode.hw_strip_crc) {
2810                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2811                 conf->rxmode.hw_strip_crc = 1;
2812         }
2813 #else
2814         if (conf->rxmode.hw_strip_crc) {
2815                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2816                 conf->rxmode.hw_strip_crc = 0;
2817         }
2818 #endif
2819
2820         return 0;
2821 }
2822
2823 static int
2824 igbvf_dev_start(struct rte_eth_dev *dev)
2825 {
2826         struct e1000_hw *hw =
2827                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2828         struct e1000_adapter *adapter =
2829                 E1000_DEV_PRIVATE(dev->data->dev_private);
2830         int ret;
2831
2832         PMD_INIT_FUNC_TRACE();
2833
2834         hw->mac.ops.reset_hw(hw);
2835         adapter->stopped = 0;
2836
2837         /* Set all vfta */
2838         igbvf_set_vfta_all(dev,1);
2839
2840         eth_igbvf_tx_init(dev);
2841
2842         /* This can fail when allocating mbufs for descriptor rings */
2843         ret = eth_igbvf_rx_init(dev);
2844         if (ret) {
2845                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2846                 igb_dev_clear_queues(dev);
2847                 return ret;
2848         }
2849
2850         return 0;
2851 }
2852
2853 static void
2854 igbvf_dev_stop(struct rte_eth_dev *dev)
2855 {
2856         PMD_INIT_FUNC_TRACE();
2857
2858         igbvf_stop_adapter(dev);
2859
2860         /*
2861           * Clear what we set, but we still keep shadow_vfta to
2862           * restore after device starts
2863           */
2864         igbvf_set_vfta_all(dev,0);
2865
2866         igb_dev_clear_queues(dev);
2867 }
2868
2869 static void
2870 igbvf_dev_close(struct rte_eth_dev *dev)
2871 {
2872         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2873         struct e1000_adapter *adapter =
2874                 E1000_DEV_PRIVATE(dev->data->dev_private);
2875         struct ether_addr addr;
2876
2877         PMD_INIT_FUNC_TRACE();
2878
2879         e1000_reset_hw(hw);
2880
2881         igbvf_dev_stop(dev);
2882         adapter->stopped = 1;
2883         igb_dev_free_queues(dev);
2884
2885         /**
2886          * reprogram the RAR with a zero mac address,
2887          * to ensure that the VF traffic goes to the PF
2888          * after stop, close and detach of the VF.
2889          **/
2890
2891         memset(&addr, 0, sizeof(addr));
2892         igbvf_default_mac_addr_set(dev, &addr);
2893 }
2894
2895 static void
2896 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
2897 {
2898         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2899
2900         /* Set both unicast and multicast promisc */
2901         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
2902 }
2903
2904 static void
2905 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
2906 {
2907         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2908
2909         /* If in allmulticast mode leave multicast promisc */
2910         if (dev->data->all_multicast == 1)
2911                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
2912         else
2913                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
2914 }
2915
2916 static void
2917 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
2918 {
2919         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2920
2921         /* In promiscuous mode multicast promisc already set */
2922         if (dev->data->promiscuous == 0)
2923                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
2924 }
2925
2926 static void
2927 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
2928 {
2929         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2930
2931         /* In promiscuous mode leave multicast promisc enabled */
2932         if (dev->data->promiscuous == 0)
2933                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
2934 }
2935
2936 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2937 {
2938         struct e1000_mbx_info *mbx = &hw->mbx;
2939         uint32_t msgbuf[2];
2940         s32 err;
2941
2942         /* After set vlan, vlan strip will also be enabled in igb driver*/
2943         msgbuf[0] = E1000_VF_SET_VLAN;
2944         msgbuf[1] = vid;
2945         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2946         if (on)
2947                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2948
2949         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
2950         if (err)
2951                 goto mbx_err;
2952
2953         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
2954         if (err)
2955                 goto mbx_err;
2956
2957         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
2958         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
2959                 err = -EINVAL;
2960
2961 mbx_err:
2962         return err;
2963 }
2964
2965 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2966 {
2967         struct e1000_hw *hw =
2968                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2969         struct e1000_vfta * shadow_vfta =
2970                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2971         int i = 0, j = 0, vfta = 0, mask = 1;
2972
2973         for (i = 0; i < IGB_VFTA_SIZE; i++){
2974                 vfta = shadow_vfta->vfta[i];
2975                 if(vfta){
2976                         mask = 1;
2977                         for (j = 0; j < 32; j++){
2978                                 if(vfta & mask)
2979                                         igbvf_set_vfta(hw,
2980                                                 (uint16_t)((i<<5)+j), on);
2981                                 mask<<=1;
2982                         }
2983                 }
2984         }
2985
2986 }
2987
2988 static int
2989 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2990 {
2991         struct e1000_hw *hw =
2992                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2993         struct e1000_vfta * shadow_vfta =
2994                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2995         uint32_t vid_idx = 0;
2996         uint32_t vid_bit = 0;
2997         int ret = 0;
2998
2999         PMD_INIT_FUNC_TRACE();
3000
3001         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3002         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3003         if(ret){
3004                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3005                 return ret;
3006         }
3007         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3008         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3009
3010         /*Save what we set and retore it after device reset*/
3011         if (on)
3012                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3013         else
3014                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3015
3016         return 0;
3017 }
3018
3019 static void
3020 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3021 {
3022         struct e1000_hw *hw =
3023                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3024
3025         /* index is not used by rar_set() */
3026         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3027 }
3028
3029
3030 static int
3031 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3032                         struct rte_eth_rss_reta_entry64 *reta_conf,
3033                         uint16_t reta_size)
3034 {
3035         uint8_t i, j, mask;
3036         uint32_t reta, r;
3037         uint16_t idx, shift;
3038         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3039
3040         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3041                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3042                         "(%d) doesn't match the number hardware can supported "
3043                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3044                 return -EINVAL;
3045         }
3046
3047         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3048                 idx = i / RTE_RETA_GROUP_SIZE;
3049                 shift = i % RTE_RETA_GROUP_SIZE;
3050                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3051                                                 IGB_4_BIT_MASK);
3052                 if (!mask)
3053                         continue;
3054                 if (mask == IGB_4_BIT_MASK)
3055                         r = 0;
3056                 else
3057                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3058                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3059                         if (mask & (0x1 << j))
3060                                 reta |= reta_conf[idx].reta[shift + j] <<
3061                                                         (CHAR_BIT * j);
3062                         else
3063                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3064                 }
3065                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3066         }
3067
3068         return 0;
3069 }
3070
3071 static int
3072 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3073                        struct rte_eth_rss_reta_entry64 *reta_conf,
3074                        uint16_t reta_size)
3075 {
3076         uint8_t i, j, mask;
3077         uint32_t reta;
3078         uint16_t idx, shift;
3079         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3080
3081         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3082                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3083                         "(%d) doesn't match the number hardware can supported "
3084                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3085                 return -EINVAL;
3086         }
3087
3088         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3089                 idx = i / RTE_RETA_GROUP_SIZE;
3090                 shift = i % RTE_RETA_GROUP_SIZE;
3091                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3092                                                 IGB_4_BIT_MASK);
3093                 if (!mask)
3094                         continue;
3095                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3096                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3097                         if (mask & (0x1 << j))
3098                                 reta_conf[idx].reta[shift + j] =
3099                                         ((reta >> (CHAR_BIT * j)) &
3100                                                 IGB_8_BIT_MASK);
3101                 }
3102         }
3103
3104         return 0;
3105 }
3106
3107 #define MAC_TYPE_FILTER_SUP(type)    do {\
3108         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3109                 (type) != e1000_82576)\
3110                 return -ENOTSUP;\
3111 } while (0)
3112
3113 static int
3114 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3115                         struct rte_eth_syn_filter *filter,
3116                         bool add)
3117 {
3118         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3119         uint32_t synqf, rfctl;
3120
3121         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3122                 return -EINVAL;
3123
3124         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3125
3126         if (add) {
3127                 if (synqf & E1000_SYN_FILTER_ENABLE)
3128                         return -EINVAL;
3129
3130                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3131                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3132
3133                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3134                 if (filter->hig_pri)
3135                         rfctl |= E1000_RFCTL_SYNQFP;
3136                 else
3137                         rfctl &= ~E1000_RFCTL_SYNQFP;
3138
3139                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3140         } else {
3141                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3142                         return -ENOENT;
3143                 synqf = 0;
3144         }
3145
3146         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3147         E1000_WRITE_FLUSH(hw);
3148         return 0;
3149 }
3150
3151 static int
3152 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3153                         struct rte_eth_syn_filter *filter)
3154 {
3155         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3156         uint32_t synqf, rfctl;
3157
3158         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3159         if (synqf & E1000_SYN_FILTER_ENABLE) {
3160                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3161                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3162                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3163                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3164                 return 0;
3165         }
3166
3167         return -ENOENT;
3168 }
3169
3170 static int
3171 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3172                         enum rte_filter_op filter_op,
3173                         void *arg)
3174 {
3175         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3176         int ret;
3177
3178         MAC_TYPE_FILTER_SUP(hw->mac.type);
3179
3180         if (filter_op == RTE_ETH_FILTER_NOP)
3181                 return 0;
3182
3183         if (arg == NULL) {
3184                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3185                             filter_op);
3186                 return -EINVAL;
3187         }
3188
3189         switch (filter_op) {
3190         case RTE_ETH_FILTER_ADD:
3191                 ret = eth_igb_syn_filter_set(dev,
3192                                 (struct rte_eth_syn_filter *)arg,
3193                                 TRUE);
3194                 break;
3195         case RTE_ETH_FILTER_DELETE:
3196                 ret = eth_igb_syn_filter_set(dev,
3197                                 (struct rte_eth_syn_filter *)arg,
3198                                 FALSE);
3199                 break;
3200         case RTE_ETH_FILTER_GET:
3201                 ret = eth_igb_syn_filter_get(dev,
3202                                 (struct rte_eth_syn_filter *)arg);
3203                 break;
3204         default:
3205                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3206                 ret = -EINVAL;
3207                 break;
3208         }
3209
3210         return ret;
3211 }
3212
3213 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3214         if ((type) != e1000_82580 && (type) != e1000_i350)\
3215                 return -ENOSYS; \
3216 } while (0)
3217
3218 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3219 static inline int
3220 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3221                         struct e1000_2tuple_filter_info *filter_info)
3222 {
3223         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3224                 return -EINVAL;
3225         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3226                 return -EINVAL;  /* filter index is out of range. */
3227         if (filter->tcp_flags > TCP_FLAG_ALL)
3228                 return -EINVAL;  /* flags is invalid. */
3229
3230         switch (filter->dst_port_mask) {
3231         case UINT16_MAX:
3232                 filter_info->dst_port_mask = 0;
3233                 filter_info->dst_port = filter->dst_port;
3234                 break;
3235         case 0:
3236                 filter_info->dst_port_mask = 1;
3237                 break;
3238         default:
3239                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3240                 return -EINVAL;
3241         }
3242
3243         switch (filter->proto_mask) {
3244         case UINT8_MAX:
3245                 filter_info->proto_mask = 0;
3246                 filter_info->proto = filter->proto;
3247                 break;
3248         case 0:
3249                 filter_info->proto_mask = 1;
3250                 break;
3251         default:
3252                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3253                 return -EINVAL;
3254         }
3255
3256         filter_info->priority = (uint8_t)filter->priority;
3257         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3258                 filter_info->tcp_flags = filter->tcp_flags;
3259         else
3260                 filter_info->tcp_flags = 0;
3261
3262         return 0;
3263 }
3264
3265 static inline struct e1000_2tuple_filter *
3266 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3267                         struct e1000_2tuple_filter_info *key)
3268 {
3269         struct e1000_2tuple_filter *it;
3270
3271         TAILQ_FOREACH(it, filter_list, entries) {
3272                 if (memcmp(key, &it->filter_info,
3273                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3274                         return it;
3275                 }
3276         }
3277         return NULL;
3278 }
3279
3280 /*
3281  * igb_add_2tuple_filter - add a 2tuple filter
3282  *
3283  * @param
3284  * dev: Pointer to struct rte_eth_dev.
3285  * ntuple_filter: ponter to the filter that will be added.
3286  *
3287  * @return
3288  *    - On success, zero.
3289  *    - On failure, a negative value.
3290  */
3291 static int
3292 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3293                         struct rte_eth_ntuple_filter *ntuple_filter)
3294 {
3295         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3296         struct e1000_filter_info *filter_info =
3297                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3298         struct e1000_2tuple_filter *filter;
3299         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3300         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3301         int i, ret;
3302
3303         filter = rte_zmalloc("e1000_2tuple_filter",
3304                         sizeof(struct e1000_2tuple_filter), 0);
3305         if (filter == NULL)
3306                 return -ENOMEM;
3307
3308         ret = ntuple_filter_to_2tuple(ntuple_filter,
3309                                       &filter->filter_info);
3310         if (ret < 0) {
3311                 rte_free(filter);
3312                 return ret;
3313         }
3314         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3315                                          &filter->filter_info) != NULL) {
3316                 PMD_DRV_LOG(ERR, "filter exists.");
3317                 rte_free(filter);
3318                 return -EEXIST;
3319         }
3320         filter->queue = ntuple_filter->queue;
3321
3322         /*
3323          * look for an unused 2tuple filter index,
3324          * and insert the filter to list.
3325          */
3326         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3327                 if (!(filter_info->twotuple_mask & (1 << i))) {
3328                         filter_info->twotuple_mask |= 1 << i;
3329                         filter->index = i;
3330                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3331                                           filter,
3332                                           entries);
3333                         break;
3334                 }
3335         }
3336         if (i >= E1000_MAX_TTQF_FILTERS) {
3337                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3338                 rte_free(filter);
3339                 return -ENOSYS;
3340         }
3341
3342         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3343         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3344                 imir |= E1000_IMIR_PORT_BP;
3345         else
3346                 imir &= ~E1000_IMIR_PORT_BP;
3347
3348         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3349
3350         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3351         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3352         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3353         if (filter->filter_info.proto_mask == 0)
3354                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3355
3356         /* tcp flags bits setting. */
3357         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3358                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3359                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3360                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3361                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3362                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3363                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3364                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3365                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3366                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3367                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3368                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3369                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3370         } else
3371                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3372         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3373         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3374         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3375         return 0;
3376 }
3377
3378 /*
3379  * igb_remove_2tuple_filter - remove a 2tuple filter
3380  *
3381  * @param
3382  * dev: Pointer to struct rte_eth_dev.
3383  * ntuple_filter: ponter to the filter that will be removed.
3384  *
3385  * @return
3386  *    - On success, zero.
3387  *    - On failure, a negative value.
3388  */
3389 static int
3390 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3391                         struct rte_eth_ntuple_filter *ntuple_filter)
3392 {
3393         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3394         struct e1000_filter_info *filter_info =
3395                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3396         struct e1000_2tuple_filter_info filter_2tuple;
3397         struct e1000_2tuple_filter *filter;
3398         int ret;
3399
3400         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3401         ret = ntuple_filter_to_2tuple(ntuple_filter,
3402                                       &filter_2tuple);
3403         if (ret < 0)
3404                 return ret;
3405
3406         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3407                                          &filter_2tuple);
3408         if (filter == NULL) {
3409                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3410                 return -ENOENT;
3411         }
3412
3413         filter_info->twotuple_mask &= ~(1 << filter->index);
3414         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3415         rte_free(filter);
3416
3417         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3418         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3419         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3420         return 0;
3421 }
3422
3423 static inline struct e1000_flex_filter *
3424 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3425                         struct e1000_flex_filter_info *key)
3426 {
3427         struct e1000_flex_filter *it;
3428
3429         TAILQ_FOREACH(it, filter_list, entries) {
3430                 if (memcmp(key, &it->filter_info,
3431                         sizeof(struct e1000_flex_filter_info)) == 0)
3432                         return it;
3433         }
3434
3435         return NULL;
3436 }
3437
3438 static int
3439 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3440                         struct rte_eth_flex_filter *filter,
3441                         bool add)
3442 {
3443         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3444         struct e1000_filter_info *filter_info =
3445                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3446         struct e1000_flex_filter *flex_filter, *it;
3447         uint32_t wufc, queueing, mask;
3448         uint32_t reg_off;
3449         uint8_t shift, i, j = 0;
3450
3451         flex_filter = rte_zmalloc("e1000_flex_filter",
3452                         sizeof(struct e1000_flex_filter), 0);
3453         if (flex_filter == NULL)
3454                 return -ENOMEM;
3455
3456         flex_filter->filter_info.len = filter->len;
3457         flex_filter->filter_info.priority = filter->priority;
3458         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3459         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3460                 mask = 0;
3461                 /* reverse bits in flex filter's mask*/
3462                 for (shift = 0; shift < CHAR_BIT; shift++) {
3463                         if (filter->mask[i] & (0x01 << shift))
3464                                 mask |= (0x80 >> shift);
3465                 }
3466                 flex_filter->filter_info.mask[i] = mask;
3467         }
3468
3469         wufc = E1000_READ_REG(hw, E1000_WUFC);
3470         if (flex_filter->index < E1000_MAX_FHFT)
3471                 reg_off = E1000_FHFT(flex_filter->index);
3472         else
3473                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3474
3475         if (add) {
3476                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3477                                 &flex_filter->filter_info) != NULL) {
3478                         PMD_DRV_LOG(ERR, "filter exists.");
3479                         rte_free(flex_filter);
3480                         return -EEXIST;
3481                 }
3482                 flex_filter->queue = filter->queue;
3483                 /*
3484                  * look for an unused flex filter index
3485                  * and insert the filter into the list.
3486                  */
3487                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3488                         if (!(filter_info->flex_mask & (1 << i))) {
3489                                 filter_info->flex_mask |= 1 << i;
3490                                 flex_filter->index = i;
3491                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3492                                         flex_filter,
3493                                         entries);
3494                                 break;
3495                         }
3496                 }
3497                 if (i >= E1000_MAX_FLEX_FILTERS) {
3498                         PMD_DRV_LOG(ERR, "flex filters are full.");
3499                         rte_free(flex_filter);
3500                         return -ENOSYS;
3501                 }
3502
3503                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3504                                 (E1000_WUFC_FLX0 << flex_filter->index));
3505                 queueing = filter->len |
3506                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3507                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3508                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3509                                 queueing);
3510                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3511                         E1000_WRITE_REG(hw, reg_off,
3512                                         flex_filter->filter_info.dwords[j]);
3513                         reg_off += sizeof(uint32_t);
3514                         E1000_WRITE_REG(hw, reg_off,
3515                                         flex_filter->filter_info.dwords[++j]);
3516                         reg_off += sizeof(uint32_t);
3517                         E1000_WRITE_REG(hw, reg_off,
3518                                 (uint32_t)flex_filter->filter_info.mask[i]);
3519                         reg_off += sizeof(uint32_t) * 2;
3520                         ++j;
3521                 }
3522         } else {
3523                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3524                                 &flex_filter->filter_info);
3525                 if (it == NULL) {
3526                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3527                         rte_free(flex_filter);
3528                         return -ENOENT;
3529                 }
3530
3531                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3532                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3533                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3534                         (~(E1000_WUFC_FLX0 << it->index)));
3535
3536                 filter_info->flex_mask &= ~(1 << it->index);
3537                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3538                 rte_free(it);
3539                 rte_free(flex_filter);
3540         }
3541
3542         return 0;
3543 }
3544
3545 static int
3546 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3547                         struct rte_eth_flex_filter *filter)
3548 {
3549         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3550         struct e1000_filter_info *filter_info =
3551                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3552         struct e1000_flex_filter flex_filter, *it;
3553         uint32_t wufc, queueing, wufc_en = 0;
3554
3555         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3556         flex_filter.filter_info.len = filter->len;
3557         flex_filter.filter_info.priority = filter->priority;
3558         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3559         memcpy(flex_filter.filter_info.mask, filter->mask,
3560                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3561
3562         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3563                                 &flex_filter.filter_info);
3564         if (it == NULL) {
3565                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3566                 return -ENOENT;
3567         }
3568
3569         wufc = E1000_READ_REG(hw, E1000_WUFC);
3570         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3571
3572         if ((wufc & wufc_en) == wufc_en) {
3573                 uint32_t reg_off = 0;
3574                 if (it->index < E1000_MAX_FHFT)
3575                         reg_off = E1000_FHFT(it->index);
3576                 else
3577                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3578
3579                 queueing = E1000_READ_REG(hw,
3580                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3581                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3582                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3583                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3584                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3585                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3586                 return 0;
3587         }
3588         return -ENOENT;
3589 }
3590
3591 static int
3592 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3593                         enum rte_filter_op filter_op,
3594                         void *arg)
3595 {
3596         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3597         struct rte_eth_flex_filter *filter;
3598         int ret = 0;
3599
3600         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3601
3602         if (filter_op == RTE_ETH_FILTER_NOP)
3603                 return ret;
3604
3605         if (arg == NULL) {
3606                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3607                             filter_op);
3608                 return -EINVAL;
3609         }
3610
3611         filter = (struct rte_eth_flex_filter *)arg;
3612         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3613             || filter->len % sizeof(uint64_t) != 0) {
3614                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3615                 return -EINVAL;
3616         }
3617         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3618                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3619                 return -EINVAL;
3620         }
3621
3622         switch (filter_op) {
3623         case RTE_ETH_FILTER_ADD:
3624                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3625                 break;
3626         case RTE_ETH_FILTER_DELETE:
3627                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3628                 break;
3629         case RTE_ETH_FILTER_GET:
3630                 ret = eth_igb_get_flex_filter(dev, filter);
3631                 break;
3632         default:
3633                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3634                 ret = -EINVAL;
3635                 break;
3636         }
3637
3638         return ret;
3639 }
3640
3641 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3642 static inline int
3643 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3644                         struct e1000_5tuple_filter_info *filter_info)
3645 {
3646         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3647                 return -EINVAL;
3648         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3649                 return -EINVAL;  /* filter index is out of range. */
3650         if (filter->tcp_flags > TCP_FLAG_ALL)
3651                 return -EINVAL;  /* flags is invalid. */
3652
3653         switch (filter->dst_ip_mask) {
3654         case UINT32_MAX:
3655                 filter_info->dst_ip_mask = 0;
3656                 filter_info->dst_ip = filter->dst_ip;
3657                 break;
3658         case 0:
3659                 filter_info->dst_ip_mask = 1;
3660                 break;
3661         default:
3662                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3663                 return -EINVAL;
3664         }
3665
3666         switch (filter->src_ip_mask) {
3667         case UINT32_MAX:
3668                 filter_info->src_ip_mask = 0;
3669                 filter_info->src_ip = filter->src_ip;
3670                 break;
3671         case 0:
3672                 filter_info->src_ip_mask = 1;
3673                 break;
3674         default:
3675                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3676                 return -EINVAL;
3677         }
3678
3679         switch (filter->dst_port_mask) {
3680         case UINT16_MAX:
3681                 filter_info->dst_port_mask = 0;
3682                 filter_info->dst_port = filter->dst_port;
3683                 break;
3684         case 0:
3685                 filter_info->dst_port_mask = 1;
3686                 break;
3687         default:
3688                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3689                 return -EINVAL;
3690         }
3691
3692         switch (filter->src_port_mask) {
3693         case UINT16_MAX:
3694                 filter_info->src_port_mask = 0;
3695                 filter_info->src_port = filter->src_port;
3696                 break;
3697         case 0:
3698                 filter_info->src_port_mask = 1;
3699                 break;
3700         default:
3701                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3702                 return -EINVAL;
3703         }
3704
3705         switch (filter->proto_mask) {
3706         case UINT8_MAX:
3707                 filter_info->proto_mask = 0;
3708                 filter_info->proto = filter->proto;
3709                 break;
3710         case 0:
3711                 filter_info->proto_mask = 1;
3712                 break;
3713         default:
3714                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3715                 return -EINVAL;
3716         }
3717
3718         filter_info->priority = (uint8_t)filter->priority;
3719         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3720                 filter_info->tcp_flags = filter->tcp_flags;
3721         else
3722                 filter_info->tcp_flags = 0;
3723
3724         return 0;
3725 }
3726
3727 static inline struct e1000_5tuple_filter *
3728 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3729                         struct e1000_5tuple_filter_info *key)
3730 {
3731         struct e1000_5tuple_filter *it;
3732
3733         TAILQ_FOREACH(it, filter_list, entries) {
3734                 if (memcmp(key, &it->filter_info,
3735                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3736                         return it;
3737                 }
3738         }
3739         return NULL;
3740 }
3741
3742 /*
3743  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3744  *
3745  * @param
3746  * dev: Pointer to struct rte_eth_dev.
3747  * ntuple_filter: ponter to the filter that will be added.
3748  *
3749  * @return
3750  *    - On success, zero.
3751  *    - On failure, a negative value.
3752  */
3753 static int
3754 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3755                         struct rte_eth_ntuple_filter *ntuple_filter)
3756 {
3757         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3758         struct e1000_filter_info *filter_info =
3759                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3760         struct e1000_5tuple_filter *filter;
3761         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3762         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3763         uint8_t i;
3764         int ret;
3765
3766         filter = rte_zmalloc("e1000_5tuple_filter",
3767                         sizeof(struct e1000_5tuple_filter), 0);
3768         if (filter == NULL)
3769                 return -ENOMEM;
3770
3771         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3772                                             &filter->filter_info);
3773         if (ret < 0) {
3774                 rte_free(filter);
3775                 return ret;
3776         }
3777
3778         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3779                                          &filter->filter_info) != NULL) {
3780                 PMD_DRV_LOG(ERR, "filter exists.");
3781                 rte_free(filter);
3782                 return -EEXIST;
3783         }
3784         filter->queue = ntuple_filter->queue;
3785
3786         /*
3787          * look for an unused 5tuple filter index,
3788          * and insert the filter to list.
3789          */
3790         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3791                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3792                         filter_info->fivetuple_mask |= 1 << i;
3793                         filter->index = i;
3794                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3795                                           filter,
3796                                           entries);
3797                         break;
3798                 }
3799         }
3800         if (i >= E1000_MAX_FTQF_FILTERS) {
3801                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3802                 rte_free(filter);
3803                 return -ENOSYS;
3804         }
3805
3806         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3807         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3808                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3809         if (filter->filter_info.dst_ip_mask == 0)
3810                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3811         if (filter->filter_info.src_port_mask == 0)
3812                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3813         if (filter->filter_info.proto_mask == 0)
3814                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3815         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3816                 E1000_FTQF_QUEUE_MASK;
3817         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3818         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3819         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3820         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3821
3822         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3823         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3824
3825         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3826         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3827                 imir |= E1000_IMIR_PORT_BP;
3828         else
3829                 imir &= ~E1000_IMIR_PORT_BP;
3830         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3831
3832         /* tcp flags bits setting. */
3833         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3834                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3835                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3836                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3837                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3838                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3839                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3840                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3841                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3842                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3843                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3844                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3845                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3846         } else
3847                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3848         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3849         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3850         return 0;
3851 }
3852
3853 /*
3854  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3855  *
3856  * @param
3857  * dev: Pointer to struct rte_eth_dev.
3858  * ntuple_filter: ponter to the filter that will be removed.
3859  *
3860  * @return
3861  *    - On success, zero.
3862  *    - On failure, a negative value.
3863  */
3864 static int
3865 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3866                                 struct rte_eth_ntuple_filter *ntuple_filter)
3867 {
3868         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3869         struct e1000_filter_info *filter_info =
3870                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3871         struct e1000_5tuple_filter_info filter_5tuple;
3872         struct e1000_5tuple_filter *filter;
3873         int ret;
3874
3875         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3876         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3877                                             &filter_5tuple);
3878         if (ret < 0)
3879                 return ret;
3880
3881         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3882                                          &filter_5tuple);
3883         if (filter == NULL) {
3884                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3885                 return -ENOENT;
3886         }
3887
3888         filter_info->fivetuple_mask &= ~(1 << filter->index);
3889         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3890         rte_free(filter);
3891
3892         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3893                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3894         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3895         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3896         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3897         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3898         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3899         return 0;
3900 }
3901
3902 static int
3903 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3904 {
3905         uint32_t rctl;
3906         struct e1000_hw *hw;
3907         struct rte_eth_dev_info dev_info;
3908         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3909                                      VLAN_TAG_SIZE);
3910
3911         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3912
3913 #ifdef RTE_LIBRTE_82571_SUPPORT
3914         /* XXX: not bigger than max_rx_pktlen */
3915         if (hw->mac.type == e1000_82571)
3916                 return -ENOTSUP;
3917 #endif
3918         eth_igb_infos_get(dev, &dev_info);
3919
3920         /* check that mtu is within the allowed range */
3921         if ((mtu < ETHER_MIN_MTU) ||
3922             (frame_size > dev_info.max_rx_pktlen))
3923                 return -EINVAL;
3924
3925         /* refuse mtu that requires the support of scattered packets when this
3926          * feature has not been enabled before. */
3927         if (!dev->data->scattered_rx &&
3928             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3929                 return -EINVAL;
3930
3931         rctl = E1000_READ_REG(hw, E1000_RCTL);
3932
3933         /* switch to jumbo mode if needed */
3934         if (frame_size > ETHER_MAX_LEN) {
3935                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3936                 rctl |= E1000_RCTL_LPE;
3937         } else {
3938                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3939                 rctl &= ~E1000_RCTL_LPE;
3940         }
3941         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3942
3943         /* update max frame size */
3944         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3945
3946         E1000_WRITE_REG(hw, E1000_RLPML,
3947                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3948
3949         return 0;
3950 }
3951
3952 /*
3953  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3954  *
3955  * @param
3956  * dev: Pointer to struct rte_eth_dev.
3957  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3958  * add: if true, add filter, if false, remove filter
3959  *
3960  * @return
3961  *    - On success, zero.
3962  *    - On failure, a negative value.
3963  */
3964 static int
3965 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3966                         struct rte_eth_ntuple_filter *ntuple_filter,
3967                         bool add)
3968 {
3969         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3970         int ret;
3971
3972         switch (ntuple_filter->flags) {
3973         case RTE_5TUPLE_FLAGS:
3974         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3975                 if (hw->mac.type != e1000_82576)
3976                         return -ENOTSUP;
3977                 if (add)
3978                         ret = igb_add_5tuple_filter_82576(dev,
3979                                                           ntuple_filter);
3980                 else
3981                         ret = igb_remove_5tuple_filter_82576(dev,
3982                                                              ntuple_filter);
3983                 break;
3984         case RTE_2TUPLE_FLAGS:
3985         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3986                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3987                         return -ENOTSUP;
3988                 if (add)
3989                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3990                 else
3991                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3992                 break;
3993         default:
3994                 ret = -EINVAL;
3995                 break;
3996         }
3997
3998         return ret;
3999 }
4000
4001 /*
4002  * igb_get_ntuple_filter - get a ntuple filter
4003  *
4004  * @param
4005  * dev: Pointer to struct rte_eth_dev.
4006  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4007  *
4008  * @return
4009  *    - On success, zero.
4010  *    - On failure, a negative value.
4011  */
4012 static int
4013 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4014                         struct rte_eth_ntuple_filter *ntuple_filter)
4015 {
4016         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4017         struct e1000_filter_info *filter_info =
4018                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4019         struct e1000_5tuple_filter_info filter_5tuple;
4020         struct e1000_2tuple_filter_info filter_2tuple;
4021         struct e1000_5tuple_filter *p_5tuple_filter;
4022         struct e1000_2tuple_filter *p_2tuple_filter;
4023         int ret;
4024
4025         switch (ntuple_filter->flags) {
4026         case RTE_5TUPLE_FLAGS:
4027         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4028                 if (hw->mac.type != e1000_82576)
4029                         return -ENOTSUP;
4030                 memset(&filter_5tuple,
4031                         0,
4032                         sizeof(struct e1000_5tuple_filter_info));
4033                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4034                                                     &filter_5tuple);
4035                 if (ret < 0)
4036                         return ret;
4037                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4038                                         &filter_info->fivetuple_list,
4039                                         &filter_5tuple);
4040                 if (p_5tuple_filter == NULL) {
4041                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4042                         return -ENOENT;
4043                 }
4044                 ntuple_filter->queue = p_5tuple_filter->queue;
4045                 break;
4046         case RTE_2TUPLE_FLAGS:
4047         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4048                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4049                         return -ENOTSUP;
4050                 memset(&filter_2tuple,
4051                         0,
4052                         sizeof(struct e1000_2tuple_filter_info));
4053                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4054                 if (ret < 0)
4055                         return ret;
4056                 p_2tuple_filter = igb_2tuple_filter_lookup(
4057                                         &filter_info->twotuple_list,
4058                                         &filter_2tuple);
4059                 if (p_2tuple_filter == NULL) {
4060                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4061                         return -ENOENT;
4062                 }
4063                 ntuple_filter->queue = p_2tuple_filter->queue;
4064                 break;
4065         default:
4066                 ret = -EINVAL;
4067                 break;
4068         }
4069
4070         return 0;
4071 }
4072
4073 /*
4074  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4075  * @dev: pointer to rte_eth_dev structure
4076  * @filter_op:operation will be taken.
4077  * @arg: a pointer to specific structure corresponding to the filter_op
4078  */
4079 static int
4080 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4081                                 enum rte_filter_op filter_op,
4082                                 void *arg)
4083 {
4084         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4085         int ret;
4086
4087         MAC_TYPE_FILTER_SUP(hw->mac.type);
4088
4089         if (filter_op == RTE_ETH_FILTER_NOP)
4090                 return 0;
4091
4092         if (arg == NULL) {
4093                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4094                             filter_op);
4095                 return -EINVAL;
4096         }
4097
4098         switch (filter_op) {
4099         case RTE_ETH_FILTER_ADD:
4100                 ret = igb_add_del_ntuple_filter(dev,
4101                         (struct rte_eth_ntuple_filter *)arg,
4102                         TRUE);
4103                 break;
4104         case RTE_ETH_FILTER_DELETE:
4105                 ret = igb_add_del_ntuple_filter(dev,
4106                         (struct rte_eth_ntuple_filter *)arg,
4107                         FALSE);
4108                 break;
4109         case RTE_ETH_FILTER_GET:
4110                 ret = igb_get_ntuple_filter(dev,
4111                         (struct rte_eth_ntuple_filter *)arg);
4112                 break;
4113         default:
4114                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4115                 ret = -EINVAL;
4116                 break;
4117         }
4118         return ret;
4119 }
4120
4121 static inline int
4122 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4123                         uint16_t ethertype)
4124 {
4125         int i;
4126
4127         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4128                 if (filter_info->ethertype_filters[i] == ethertype &&
4129                     (filter_info->ethertype_mask & (1 << i)))
4130                         return i;
4131         }
4132         return -1;
4133 }
4134
4135 static inline int
4136 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4137                         uint16_t ethertype)
4138 {
4139         int i;
4140
4141         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4142                 if (!(filter_info->ethertype_mask & (1 << i))) {
4143                         filter_info->ethertype_mask |= 1 << i;
4144                         filter_info->ethertype_filters[i] = ethertype;
4145                         return i;
4146                 }
4147         }
4148         return -1;
4149 }
4150
4151 static inline int
4152 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4153                         uint8_t idx)
4154 {
4155         if (idx >= E1000_MAX_ETQF_FILTERS)
4156                 return -1;
4157         filter_info->ethertype_mask &= ~(1 << idx);
4158         filter_info->ethertype_filters[idx] = 0;
4159         return idx;
4160 }
4161
4162
4163 static int
4164 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4165                         struct rte_eth_ethertype_filter *filter,
4166                         bool add)
4167 {
4168         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4169         struct e1000_filter_info *filter_info =
4170                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4171         uint32_t etqf = 0;
4172         int ret;
4173
4174         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4175                 filter->ether_type == ETHER_TYPE_IPv6) {
4176                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4177                         " ethertype filter.", filter->ether_type);
4178                 return -EINVAL;
4179         }
4180
4181         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4182                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4183                 return -EINVAL;
4184         }
4185         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4186                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4187                 return -EINVAL;
4188         }
4189
4190         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4191         if (ret >= 0 && add) {
4192                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4193                             filter->ether_type);
4194                 return -EEXIST;
4195         }
4196         if (ret < 0 && !add) {
4197                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4198                             filter->ether_type);
4199                 return -ENOENT;
4200         }
4201
4202         if (add) {
4203                 ret = igb_ethertype_filter_insert(filter_info,
4204                         filter->ether_type);
4205                 if (ret < 0) {
4206                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4207                         return -ENOSYS;
4208                 }
4209
4210                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4211                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4212                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4213         } else {
4214                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4215                 if (ret < 0)
4216                         return -ENOSYS;
4217         }
4218         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4219         E1000_WRITE_FLUSH(hw);
4220
4221         return 0;
4222 }
4223
4224 static int
4225 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4226                         struct rte_eth_ethertype_filter *filter)
4227 {
4228         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4229         struct e1000_filter_info *filter_info =
4230                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4231         uint32_t etqf;
4232         int ret;
4233
4234         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4235         if (ret < 0) {
4236                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4237                             filter->ether_type);
4238                 return -ENOENT;
4239         }
4240
4241         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4242         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4243                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4244                 filter->flags = 0;
4245                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4246                                 E1000_ETQF_QUEUE_SHIFT;
4247                 return 0;
4248         }
4249
4250         return -ENOENT;
4251 }
4252
4253 /*
4254  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4255  * @dev: pointer to rte_eth_dev structure
4256  * @filter_op:operation will be taken.
4257  * @arg: a pointer to specific structure corresponding to the filter_op
4258  */
4259 static int
4260 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4261                                 enum rte_filter_op filter_op,
4262                                 void *arg)
4263 {
4264         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4265         int ret;
4266
4267         MAC_TYPE_FILTER_SUP(hw->mac.type);
4268
4269         if (filter_op == RTE_ETH_FILTER_NOP)
4270                 return 0;
4271
4272         if (arg == NULL) {
4273                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4274                             filter_op);
4275                 return -EINVAL;
4276         }
4277
4278         switch (filter_op) {
4279         case RTE_ETH_FILTER_ADD:
4280                 ret = igb_add_del_ethertype_filter(dev,
4281                         (struct rte_eth_ethertype_filter *)arg,
4282                         TRUE);
4283                 break;
4284         case RTE_ETH_FILTER_DELETE:
4285                 ret = igb_add_del_ethertype_filter(dev,
4286                         (struct rte_eth_ethertype_filter *)arg,
4287                         FALSE);
4288                 break;
4289         case RTE_ETH_FILTER_GET:
4290                 ret = igb_get_ethertype_filter(dev,
4291                         (struct rte_eth_ethertype_filter *)arg);
4292                 break;
4293         default:
4294                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4295                 ret = -EINVAL;
4296                 break;
4297         }
4298         return ret;
4299 }
4300
4301 static int
4302 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4303                      enum rte_filter_type filter_type,
4304                      enum rte_filter_op filter_op,
4305                      void *arg)
4306 {
4307         int ret = -EINVAL;
4308
4309         switch (filter_type) {
4310         case RTE_ETH_FILTER_NTUPLE:
4311                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4312                 break;
4313         case RTE_ETH_FILTER_ETHERTYPE:
4314                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4315                 break;
4316         case RTE_ETH_FILTER_SYN:
4317                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4318                 break;
4319         case RTE_ETH_FILTER_FLEXIBLE:
4320                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4321                 break;
4322         default:
4323                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4324                                                         filter_type);
4325                 break;
4326         }
4327
4328         return ret;
4329 }
4330
4331 static int
4332 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4333                          struct ether_addr *mc_addr_set,
4334                          uint32_t nb_mc_addr)
4335 {
4336         struct e1000_hw *hw;
4337
4338         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4339         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4340         return 0;
4341 }
4342
4343 static uint64_t
4344 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4345 {
4346         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4347         uint64_t systime_cycles;
4348
4349         switch (hw->mac.type) {
4350         case e1000_i210:
4351         case e1000_i211:
4352                 /*
4353                  * Need to read System Time Residue Register to be able
4354                  * to read the other two registers.
4355                  */
4356                 E1000_READ_REG(hw, E1000_SYSTIMR);
4357                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4358                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4359                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4360                                 * NSEC_PER_SEC;
4361                 break;
4362         case e1000_82580:
4363         case e1000_i350:
4364         case e1000_i354:
4365                 /*
4366                  * Need to read System Time Residue Register to be able
4367                  * to read the other two registers.
4368                  */
4369                 E1000_READ_REG(hw, E1000_SYSTIMR);
4370                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4371                 /* Only the 8 LSB are valid. */
4372                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4373                                 & 0xff) << 32;
4374                 break;
4375         default:
4376                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4377                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4378                                 << 32;
4379                 break;
4380         }
4381
4382         return systime_cycles;
4383 }
4384
4385 static uint64_t
4386 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4387 {
4388         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4389         uint64_t rx_tstamp_cycles;
4390
4391         switch (hw->mac.type) {
4392         case e1000_i210:
4393         case e1000_i211:
4394                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4395                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4396                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4397                                 * NSEC_PER_SEC;
4398                 break;
4399         case e1000_82580:
4400         case e1000_i350:
4401         case e1000_i354:
4402                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4403                 /* Only the 8 LSB are valid. */
4404                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4405                                 & 0xff) << 32;
4406                 break;
4407         default:
4408                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4409                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4410                                 << 32;
4411                 break;
4412         }
4413
4414         return rx_tstamp_cycles;
4415 }
4416
4417 static uint64_t
4418 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4419 {
4420         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4421         uint64_t tx_tstamp_cycles;
4422
4423         switch (hw->mac.type) {
4424         case e1000_i210:
4425         case e1000_i211:
4426                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4427                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4428                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4429                                 * NSEC_PER_SEC;
4430                 break;
4431         case e1000_82580:
4432         case e1000_i350:
4433         case e1000_i354:
4434                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4435                 /* Only the 8 LSB are valid. */
4436                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4437                                 & 0xff) << 32;
4438                 break;
4439         default:
4440                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4441                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4442                                 << 32;
4443                 break;
4444         }
4445
4446         return tx_tstamp_cycles;
4447 }
4448
4449 static void
4450 igb_start_timecounters(struct rte_eth_dev *dev)
4451 {
4452         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4453         struct e1000_adapter *adapter =
4454                 (struct e1000_adapter *)dev->data->dev_private;
4455         uint32_t incval = 1;
4456         uint32_t shift = 0;
4457         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4458
4459         switch (hw->mac.type) {
4460         case e1000_82580:
4461         case e1000_i350:
4462         case e1000_i354:
4463                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4464                 mask = (1ULL << 40) - 1;
4465                 /* fall-through */
4466         case e1000_i210:
4467         case e1000_i211:
4468                 /*
4469                  * Start incrementing the register
4470                  * used to timestamp PTP packets.
4471                  */
4472                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4473                 break;
4474         case e1000_82576:
4475                 incval = E1000_INCVALUE_82576;
4476                 shift = IGB_82576_TSYNC_SHIFT;
4477                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4478                                 E1000_INCPERIOD_82576 | incval);
4479                 break;
4480         default:
4481                 /* Not supported */
4482                 return;
4483         }
4484
4485         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4486         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4487         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4488
4489         adapter->systime_tc.cc_mask = mask;
4490         adapter->systime_tc.cc_shift = shift;
4491         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4492
4493         adapter->rx_tstamp_tc.cc_mask = mask;
4494         adapter->rx_tstamp_tc.cc_shift = shift;
4495         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4496
4497         adapter->tx_tstamp_tc.cc_mask = mask;
4498         adapter->tx_tstamp_tc.cc_shift = shift;
4499         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4500 }
4501
4502 static int
4503 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4504 {
4505         struct e1000_adapter *adapter =
4506                         (struct e1000_adapter *)dev->data->dev_private;
4507
4508         adapter->systime_tc.nsec += delta;
4509         adapter->rx_tstamp_tc.nsec += delta;
4510         adapter->tx_tstamp_tc.nsec += delta;
4511
4512         return 0;
4513 }
4514
4515 static int
4516 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4517 {
4518         uint64_t ns;
4519         struct e1000_adapter *adapter =
4520                         (struct e1000_adapter *)dev->data->dev_private;
4521
4522         ns = rte_timespec_to_ns(ts);
4523
4524         /* Set the timecounters to a new value. */
4525         adapter->systime_tc.nsec = ns;
4526         adapter->rx_tstamp_tc.nsec = ns;
4527         adapter->tx_tstamp_tc.nsec = ns;
4528
4529         return 0;
4530 }
4531
4532 static int
4533 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4534 {
4535         uint64_t ns, systime_cycles;
4536         struct e1000_adapter *adapter =
4537                         (struct e1000_adapter *)dev->data->dev_private;
4538
4539         systime_cycles = igb_read_systime_cyclecounter(dev);
4540         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4541         *ts = rte_ns_to_timespec(ns);
4542
4543         return 0;
4544 }
4545
4546 static int
4547 igb_timesync_enable(struct rte_eth_dev *dev)
4548 {
4549         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4550         uint32_t tsync_ctl;
4551         uint32_t tsauxc;
4552
4553         /* Stop the timesync system time. */
4554         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4555         /* Reset the timesync system time value. */
4556         switch (hw->mac.type) {
4557         case e1000_82580:
4558         case e1000_i350:
4559         case e1000_i354:
4560         case e1000_i210:
4561         case e1000_i211:
4562                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4563                 /* fall-through */
4564         case e1000_82576:
4565                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4566                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4567                 break;
4568         default:
4569                 /* Not supported. */
4570                 return -ENOTSUP;
4571         }
4572
4573         /* Enable system time for it isn't on by default. */
4574         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4575         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4576         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4577
4578         igb_start_timecounters(dev);
4579
4580         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4581         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4582                         (ETHER_TYPE_1588 |
4583                          E1000_ETQF_FILTER_ENABLE |
4584                          E1000_ETQF_1588));
4585
4586         /* Enable timestamping of received PTP packets. */
4587         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4588         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4589         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4590
4591         /* Enable Timestamping of transmitted PTP packets. */
4592         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4593         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4594         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4595
4596         return 0;
4597 }
4598
4599 static int
4600 igb_timesync_disable(struct rte_eth_dev *dev)
4601 {
4602         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4603         uint32_t tsync_ctl;
4604
4605         /* Disable timestamping of transmitted PTP packets. */
4606         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4607         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4608         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4609
4610         /* Disable timestamping of received PTP packets. */
4611         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4612         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4613         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4614
4615         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4616         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4617
4618         /* Stop incrementating the System Time registers. */
4619         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4620
4621         return 0;
4622 }
4623
4624 static int
4625 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4626                                struct timespec *timestamp,
4627                                uint32_t flags __rte_unused)
4628 {
4629         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4630         struct e1000_adapter *adapter =
4631                         (struct e1000_adapter *)dev->data->dev_private;
4632         uint32_t tsync_rxctl;
4633         uint64_t rx_tstamp_cycles;
4634         uint64_t ns;
4635
4636         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4637         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4638                 return -EINVAL;
4639
4640         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4641         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4642         *timestamp = rte_ns_to_timespec(ns);
4643
4644         return  0;
4645 }
4646
4647 static int
4648 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4649                                struct timespec *timestamp)
4650 {
4651         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4652         struct e1000_adapter *adapter =
4653                         (struct e1000_adapter *)dev->data->dev_private;
4654         uint32_t tsync_txctl;
4655         uint64_t tx_tstamp_cycles;
4656         uint64_t ns;
4657
4658         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4659         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4660                 return -EINVAL;
4661
4662         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4663         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4664         *timestamp = rte_ns_to_timespec(ns);
4665
4666         return  0;
4667 }
4668
4669 static int
4670 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4671 {
4672         int count = 0;
4673         int g_ind = 0;
4674         const struct reg_info *reg_group;
4675
4676         while ((reg_group = igb_regs[g_ind++]))
4677                 count += igb_reg_group_count(reg_group);
4678
4679         return count;
4680 }
4681
4682 static int
4683 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4684 {
4685         int count = 0;
4686         int g_ind = 0;
4687         const struct reg_info *reg_group;
4688
4689         while ((reg_group = igbvf_regs[g_ind++]))
4690                 count += igb_reg_group_count(reg_group);
4691
4692         return count;
4693 }
4694
4695 static int
4696 eth_igb_get_regs(struct rte_eth_dev *dev,
4697         struct rte_dev_reg_info *regs)
4698 {
4699         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4700         uint32_t *data = regs->data;
4701         int g_ind = 0;
4702         int count = 0;
4703         const struct reg_info *reg_group;
4704
4705         /* Support only full register dump */
4706         if ((regs->length == 0) ||
4707             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4708                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4709                         hw->device_id;
4710                 while ((reg_group = igb_regs[g_ind++]))
4711                         count += igb_read_regs_group(dev, &data[count],
4712                                                         reg_group);
4713                 return 0;
4714         }
4715
4716         return -ENOTSUP;
4717 }
4718
4719 static int
4720 igbvf_get_regs(struct rte_eth_dev *dev,
4721         struct rte_dev_reg_info *regs)
4722 {
4723         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4724         uint32_t *data = regs->data;
4725         int g_ind = 0;
4726         int count = 0;
4727         const struct reg_info *reg_group;
4728
4729         /* Support only full register dump */
4730         if ((regs->length == 0) ||
4731             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4732                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4733                         hw->device_id;
4734                 while ((reg_group = igbvf_regs[g_ind++]))
4735                         count += igb_read_regs_group(dev, &data[count],
4736                                                         reg_group);
4737                 return 0;
4738         }
4739
4740         return -ENOTSUP;
4741 }
4742
4743 static int
4744 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4745 {
4746         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4747
4748         /* Return unit is byte count */
4749         return hw->nvm.word_size * 2;
4750 }
4751
4752 static int
4753 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4754         struct rte_dev_eeprom_info *in_eeprom)
4755 {
4756         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4757         struct e1000_nvm_info *nvm = &hw->nvm;
4758         uint16_t *data = in_eeprom->data;
4759         int first, length;
4760
4761         first = in_eeprom->offset >> 1;
4762         length = in_eeprom->length >> 1;
4763         if ((first >= hw->nvm.word_size) ||
4764             ((first + length) >= hw->nvm.word_size))
4765                 return -EINVAL;
4766
4767         in_eeprom->magic = hw->vendor_id |
4768                 ((uint32_t)hw->device_id << 16);
4769
4770         if ((nvm->ops.read) == NULL)
4771                 return -ENOTSUP;
4772
4773         return nvm->ops.read(hw, first, length, data);
4774 }
4775
4776 static int
4777 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4778         struct rte_dev_eeprom_info *in_eeprom)
4779 {
4780         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4781         struct e1000_nvm_info *nvm = &hw->nvm;
4782         uint16_t *data = in_eeprom->data;
4783         int first, length;
4784
4785         first = in_eeprom->offset >> 1;
4786         length = in_eeprom->length >> 1;
4787         if ((first >= hw->nvm.word_size) ||
4788             ((first + length) >= hw->nvm.word_size))
4789                 return -EINVAL;
4790
4791         in_eeprom->magic = (uint32_t)hw->vendor_id |
4792                 ((uint32_t)hw->device_id << 16);
4793
4794         if ((nvm->ops.write) == NULL)
4795                 return -ENOTSUP;
4796         return nvm->ops.write(hw,  first, length, data);
4797 }
4798
4799 static struct rte_driver pmd_igb_drv = {
4800         .type = PMD_PDEV,
4801         .init = rte_igb_pmd_init,
4802 };
4803
4804 static struct rte_driver pmd_igbvf_drv = {
4805         .type = PMD_PDEV,
4806         .init = rte_igbvf_pmd_init,
4807 };
4808
4809 static int
4810 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4811 {
4812         struct e1000_hw *hw =
4813                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4814         uint32_t mask = 1 << queue_id;
4815
4816         E1000_WRITE_REG(hw, E1000_EIMC, mask);
4817         E1000_WRITE_FLUSH(hw);
4818
4819         return 0;
4820 }
4821
4822 static int
4823 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4824 {
4825         struct e1000_hw *hw =
4826                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4827         uint32_t mask = 1 << queue_id;
4828         uint32_t regval;
4829
4830         regval = E1000_READ_REG(hw, E1000_EIMS);
4831         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4832         E1000_WRITE_FLUSH(hw);
4833
4834         rte_intr_enable(&dev->pci_dev->intr_handle);
4835
4836         return 0;
4837 }
4838
4839 static void
4840 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
4841                    uint8_t index, uint8_t offset)
4842 {
4843         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4844
4845         /* clear bits */
4846         val &= ~((uint32_t)0xFF << offset);
4847
4848         /* write vector and valid bit */
4849         val |= (msix_vector | E1000_IVAR_VALID) << offset;
4850
4851         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4852 }
4853
4854 static void
4855 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4856                            uint8_t queue, uint8_t msix_vector)
4857 {
4858         uint32_t tmp = 0;
4859
4860         if (hw->mac.type == e1000_82575) {
4861                 if (direction == 0)
4862                         tmp = E1000_EICR_RX_QUEUE0 << queue;
4863                 else if (direction == 1)
4864                         tmp = E1000_EICR_TX_QUEUE0 << queue;
4865                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4866         } else if (hw->mac.type == e1000_82576) {
4867                 if ((direction == 0) || (direction == 1))
4868                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4869                                            ((queue & 0x8) << 1) +
4870                                            8 * direction);
4871         } else if ((hw->mac.type == e1000_82580) ||
4872                         (hw->mac.type == e1000_i350) ||
4873                         (hw->mac.type == e1000_i354) ||
4874                         (hw->mac.type == e1000_i210) ||
4875                         (hw->mac.type == e1000_i211)) {
4876                 if ((direction == 0) || (direction == 1))
4877                         eth_igb_write_ivar(hw, msix_vector,
4878                                            queue >> 1,
4879                                            ((queue & 0x1) << 4) +
4880                                            8 * direction);
4881         }
4882 }
4883
4884 /* Sets up the hardware to generate MSI-X interrupts properly
4885  * @hw
4886  *  board private structure
4887  */
4888 static void
4889 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4890 {
4891         int queue_id;
4892         uint32_t tmpval, regval, intr_mask;
4893         struct e1000_hw *hw =
4894                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4895         uint32_t vec = E1000_MISC_VEC_ID;
4896         uint32_t base = E1000_MISC_VEC_ID;
4897         uint32_t misc_shift = 0;
4898
4899         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4900
4901         /* won't configure msix register if no mapping is done
4902          * between intr vector and event fd
4903          */
4904         if (!rte_intr_dp_is_en(intr_handle))
4905                 return;
4906
4907         if (rte_intr_allow_others(intr_handle)) {
4908                 vec = base = E1000_RX_VEC_START;
4909                 misc_shift = 1;
4910         }
4911
4912         /* set interrupt vector for other causes */
4913         if (hw->mac.type == e1000_82575) {
4914                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4915                 /* enable MSI-X PBA support */
4916                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4917
4918                 /* Auto-Mask interrupts upon ICR read */
4919                 tmpval |= E1000_CTRL_EXT_EIAME;
4920                 tmpval |= E1000_CTRL_EXT_IRCA;
4921
4922                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4923
4924                 /* enable msix_other interrupt */
4925                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4926                 regval = E1000_READ_REG(hw, E1000_EIAC);
4927                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4928                 regval = E1000_READ_REG(hw, E1000_EIAM);
4929                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4930         } else if ((hw->mac.type == e1000_82576) ||
4931                         (hw->mac.type == e1000_82580) ||
4932                         (hw->mac.type == e1000_i350) ||
4933                         (hw->mac.type == e1000_i354) ||
4934                         (hw->mac.type == e1000_i210) ||
4935                         (hw->mac.type == e1000_i211)) {
4936                 /* turn on MSI-X capability first */
4937                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4938                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
4939                                         E1000_GPIE_NSICR);
4940                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4941                         misc_shift;
4942                 regval = E1000_READ_REG(hw, E1000_EIAC);
4943                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4944
4945                 /* enable msix_other interrupt */
4946                 regval = E1000_READ_REG(hw, E1000_EIMS);
4947                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4948                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4949                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4950         }
4951
4952         /* use EIAM to auto-mask when MSI-X interrupt
4953          * is asserted, this saves a register write for every interrupt
4954          */
4955         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4956                 misc_shift;
4957         regval = E1000_READ_REG(hw, E1000_EIAM);
4958         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
4959
4960         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
4961                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
4962                 intr_handle->intr_vec[queue_id] = vec;
4963                 if (vec < base + intr_handle->nb_efd - 1)
4964                         vec++;
4965         }
4966
4967         E1000_WRITE_FLUSH(hw);
4968 }
4969
4970 PMD_REGISTER_DRIVER(pmd_igb_drv);
4971 PMD_REGISTER_DRIVER(pmd_igbvf_drv);