drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64
  65 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  66 #define IGB_DEFAULT_RX_HTHRESH      8
  67 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  68
  69 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  70 #define IGB_DEFAULT_TX_HTHRESH      1
  71 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  72
  73 #define IGB_HKEY_MAX_INDEX 10
  74
  75 /* Bit shift and mask */
  76 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  77 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  78 #define IGB_8_BIT_WIDTH  CHAR_BIT
  79 #define IGB_8_BIT_MASK   UINT8_MAX
  80
  81 /* Additional timesync values. */
  82 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  83 #define E1000_ETQF_FILTER_1588       3
  84 #define IGB_82576_TSYNC_SHIFT        16
  85 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  86 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  88
  89 #define E1000_VTIVAR_MISC                0x01740
  90 #define E1000_VTIVAR_MISC_MASK           0xFF
  91 #define E1000_VTIVAR_VALID               0x80
  92 #define E1000_VTIVAR_MISC_MAILBOX        0
  93 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  94
  95 /* External VLAN Enable bit mask */
  96 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  97
  98 /* External VLAN Ether Type bit mask and shift */
  99 #define E1000_VET_VET_EXT            0xFFFF0000
 100 #define E1000_VET_VET_EXT_SHIFT      16
 101
 102 static int  eth_igb_configure(struct rte_eth_dev *dev);
 103 static int  eth_igb_start(struct rte_eth_dev *dev);
 104 static void eth_igb_stop(struct rte_eth_dev *dev);
 105 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 107 static void eth_igb_close(struct rte_eth_dev *dev);
 108 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 110 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 112 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 113                                 int wait_to_complete);
 114 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 115                                 struct rte_eth_stats *rte_stats);
 116 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 117                               struct rte_eth_xstat *xstats, unsigned n);
 118 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 119                                     struct rte_eth_xstat_name *xstats_names,
 120                                     unsigned limit);
 121 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 122 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 123 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 124                               struct rte_eth_dev_info *dev_info);
 125 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 126 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 127                                 struct rte_eth_dev_info *dev_info);
 128 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 129                                 struct rte_eth_fc_conf *fc_conf);
 130 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 131                                 struct rte_eth_fc_conf *fc_conf);
 132 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 133 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 134 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 135 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 136                                     struct rte_intr_handle *handle);
 137 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 138                                                         void *param);
 139 static int  igb_hardware_init(struct e1000_hw *hw);
 140 static void igb_hw_control_acquire(struct e1000_hw *hw);
 141 static void igb_hw_control_release(struct e1000_hw *hw);
 142 static void igb_init_manageability(struct e1000_hw *hw);
 143 static void igb_release_manageability(struct e1000_hw *hw);
 144
 145 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 146
 147 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 148                 uint16_t vlan_id, int on);
 149 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 150                                  enum rte_vlan_type vlan_type,
 151                                  uint16_t tpid_id);
 152 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 153
 154 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 155 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 156 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 157 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 158 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 159 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 160
 161 static int eth_igb_led_on(struct rte_eth_dev *dev);
 162 static int eth_igb_led_off(struct rte_eth_dev *dev);
 163
 164 static void igb_intr_disable(struct e1000_hw *hw);
 165 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 166 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 167                 struct ether_addr *mac_addr,
 168                 uint32_t index, uint32_t pool);
 169 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 170 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 171                 struct ether_addr *addr);
 172
 173 static void igbvf_intr_disable(struct e1000_hw *hw);
 174 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 175 static int igbvf_dev_start(struct rte_eth_dev *dev);
 176 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 177 static void igbvf_dev_close(struct rte_eth_dev *dev);
 178 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 179 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 180 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 181 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 182 static int eth_igbvf_link_update(struct e1000_hw *hw);
 183 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 184                                 struct rte_eth_stats *rte_stats);
 185 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 186                                 struct rte_eth_xstat *xstats, unsigned n);
 187 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 188                                       struct rte_eth_xstat_name *xstats_names,
 189                                       unsigned limit);
 190 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 191 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 192                 uint16_t vlan_id, int on);
 193 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 194 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 195 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 196                 struct ether_addr *addr);
 197 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 198 static int igbvf_get_regs(struct rte_eth_dev *dev,
 199                 struct rte_dev_reg_info *regs);
 200
 201 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 202                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 203                                    uint16_t reta_size);
 204 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 205                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 206                                   uint16_t reta_size);
 207
 208 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 209                         struct rte_eth_syn_filter *filter,
 210                         bool add);
 211 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 212                         struct rte_eth_syn_filter *filter);
 213 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 214                         enum rte_filter_op filter_op,
 215                         void *arg);
 216 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 217                         struct rte_eth_ntuple_filter *ntuple_filter);
 218 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 219                         struct rte_eth_ntuple_filter *ntuple_filter);
 220 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 221                         struct rte_eth_flex_filter *filter,
 222                         bool add);
 223 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 224                         struct rte_eth_flex_filter *filter);
 225 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 226                         enum rte_filter_op filter_op,
 227                         void *arg);
 228 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 229                         struct rte_eth_ntuple_filter *ntuple_filter);
 230 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 231                         struct rte_eth_ntuple_filter *ntuple_filter);
 232 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 233                         struct rte_eth_ntuple_filter *filter,
 234                         bool add);
 235 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 236                         struct rte_eth_ntuple_filter *filter);
 237 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 238                                 enum rte_filter_op filter_op,
 239                                 void *arg);
 240 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 241                         struct rte_eth_ethertype_filter *filter,
 242                         bool add);
 243 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 244                                 enum rte_filter_op filter_op,
 245                                 void *arg);
 246 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 247                         struct rte_eth_ethertype_filter *filter);
 248 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 249                      enum rte_filter_type filter_type,
 250                      enum rte_filter_op filter_op,
 251                      void *arg);
 252 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 253 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 254                 struct rte_dev_reg_info *regs);
 255 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 256 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 257                 struct rte_dev_eeprom_info *eeprom);
 258 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 259                 struct rte_dev_eeprom_info *eeprom);
 260 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 261                                     struct ether_addr *mc_addr_set,
 262                                     uint32_t nb_mc_addr);
 263 static int igb_timesync_enable(struct rte_eth_dev *dev);
 264 static int igb_timesync_disable(struct rte_eth_dev *dev);
 265 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 266                                           struct timespec *timestamp,
 267                                           uint32_t flags);
 268 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 269                                           struct timespec *timestamp);
 270 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 271 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 272                                   struct timespec *timestamp);
 273 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 274                                    const struct timespec *timestamp);
 275 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 276                                         uint16_t queue_id);
 277 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 278                                          uint16_t queue_id);
 279 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 280                                        uint8_t queue, uint8_t msix_vector);
 281 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 282                                uint8_t index, uint8_t offset);
 283 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 284 static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
 285                                         void *param);
 286 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 287
 288 /*
 289  * Define VF Stats MACRO for Non "cleared on read" register
 290  */
 291 #define UPDATE_VF_STAT(reg, last, cur)            \
 292 {                                                 \
 293         u32 latest = E1000_READ_REG(hw, reg);     \
 294         cur += (latest - last) & UINT_MAX;        \
 295         last = latest;                            \
 296 }
 297
 298 #define IGB_FC_PAUSE_TIME 0x0680
 299 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 300 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 301
 302 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 303
 304 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 305
 306 /*
 307  * The set of PCI devices this driver supports
 308  */
 309 static const struct rte_pci_id pci_id_igb_map[] = {
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 318
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 322
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 329
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 347         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 348         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 349         { .vendor_id = 0, /* sentinel */ },
 350 };
 351
 352 /*
 353  * The set of PCI devices this driver supports (for 82576&I350 VF)
 354  */
 355 static const struct rte_pci_id pci_id_igbvf_map[] = {
 356         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 357         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 358         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 359         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 360         { .vendor_id = 0, /* sentinel */ },
 361 };
 362
 363 static const struct rte_eth_desc_lim rx_desc_lim = {
 364         .nb_max = E1000_MAX_RING_DESC,
 365         .nb_min = E1000_MIN_RING_DESC,
 366         .nb_align = IGB_RXD_ALIGN,
 367 };
 368
 369 static const struct rte_eth_desc_lim tx_desc_lim = {
 370         .nb_max = E1000_MAX_RING_DESC,
 371         .nb_min = E1000_MIN_RING_DESC,
 372         .nb_align = IGB_RXD_ALIGN,
 373         .nb_seg_max = IGB_TX_MAX_SEG,
 374         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 375 };
 376
 377 static const struct eth_dev_ops eth_igb_ops = {
 378         .dev_configure        = eth_igb_configure,
 379         .dev_start            = eth_igb_start,
 380         .dev_stop             = eth_igb_stop,
 381         .dev_set_link_up      = eth_igb_dev_set_link_up,
 382         .dev_set_link_down    = eth_igb_dev_set_link_down,
 383         .dev_close            = eth_igb_close,
 384         .promiscuous_enable   = eth_igb_promiscuous_enable,
 385         .promiscuous_disable  = eth_igb_promiscuous_disable,
 386         .allmulticast_enable  = eth_igb_allmulticast_enable,
 387         .allmulticast_disable = eth_igb_allmulticast_disable,
 388         .link_update          = eth_igb_link_update,
 389         .stats_get            = eth_igb_stats_get,
 390         .xstats_get           = eth_igb_xstats_get,
 391         .xstats_get_names     = eth_igb_xstats_get_names,
 392         .stats_reset          = eth_igb_stats_reset,
 393         .xstats_reset         = eth_igb_xstats_reset,
 394         .dev_infos_get        = eth_igb_infos_get,
 395         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 396         .mtu_set              = eth_igb_mtu_set,
 397         .vlan_filter_set      = eth_igb_vlan_filter_set,
 398         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 399         .vlan_offload_set     = eth_igb_vlan_offload_set,
 400         .rx_queue_setup       = eth_igb_rx_queue_setup,
 401         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 402         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 403         .rx_queue_release     = eth_igb_rx_queue_release,
 404         .rx_queue_count       = eth_igb_rx_queue_count,
 405         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 406         .tx_queue_setup       = eth_igb_tx_queue_setup,
 407         .tx_queue_release     = eth_igb_tx_queue_release,
 408         .dev_led_on           = eth_igb_led_on,
 409         .dev_led_off          = eth_igb_led_off,
 410         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 411         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 412         .mac_addr_add         = eth_igb_rar_set,
 413         .mac_addr_remove      = eth_igb_rar_clear,
 414         .mac_addr_set         = eth_igb_default_mac_addr_set,
 415         .reta_update          = eth_igb_rss_reta_update,
 416         .reta_query           = eth_igb_rss_reta_query,
 417         .rss_hash_update      = eth_igb_rss_hash_update,
 418         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 419         .filter_ctrl          = eth_igb_filter_ctrl,
 420         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 421         .rxq_info_get         = igb_rxq_info_get,
 422         .txq_info_get         = igb_txq_info_get,
 423         .timesync_enable      = igb_timesync_enable,
 424         .timesync_disable     = igb_timesync_disable,
 425         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 426         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 427         .get_reg              = eth_igb_get_regs,
 428         .get_eeprom_length    = eth_igb_get_eeprom_length,
 429         .get_eeprom           = eth_igb_get_eeprom,
 430         .set_eeprom           = eth_igb_set_eeprom,
 431         .timesync_adjust_time = igb_timesync_adjust_time,
 432         .timesync_read_time   = igb_timesync_read_time,
 433         .timesync_write_time  = igb_timesync_write_time,
 434 };
 435
 436 /*
 437  * dev_ops for virtual function, bare necessities for basic vf
 438  * operation have been implemented
 439  */
 440 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 441         .dev_configure        = igbvf_dev_configure,
 442         .dev_start            = igbvf_dev_start,
 443         .dev_stop             = igbvf_dev_stop,
 444         .dev_close            = igbvf_dev_close,
 445         .promiscuous_enable   = igbvf_promiscuous_enable,
 446         .promiscuous_disable  = igbvf_promiscuous_disable,
 447         .allmulticast_enable  = igbvf_allmulticast_enable,
 448         .allmulticast_disable = igbvf_allmulticast_disable,
 449         .link_update          = eth_igb_link_update,
 450         .stats_get            = eth_igbvf_stats_get,
 451         .xstats_get           = eth_igbvf_xstats_get,
 452         .xstats_get_names     = eth_igbvf_xstats_get_names,
 453         .stats_reset          = eth_igbvf_stats_reset,
 454         .xstats_reset         = eth_igbvf_stats_reset,
 455         .vlan_filter_set      = igbvf_vlan_filter_set,
 456         .dev_infos_get        = eth_igbvf_infos_get,
 457         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 458         .rx_queue_setup       = eth_igb_rx_queue_setup,
 459         .rx_queue_release     = eth_igb_rx_queue_release,
 460         .tx_queue_setup       = eth_igb_tx_queue_setup,
 461         .tx_queue_release     = eth_igb_tx_queue_release,
 462         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 463         .rxq_info_get         = igb_rxq_info_get,
 464         .txq_info_get         = igb_txq_info_get,
 465         .mac_addr_set         = igbvf_default_mac_addr_set,
 466         .get_reg              = igbvf_get_regs,
 467 };
 468
 469 /* store statistics names and its offset in stats structure */
 470 struct rte_igb_xstats_name_off {
 471         char name[RTE_ETH_XSTATS_NAME_SIZE];
 472         unsigned offset;
 473 };
 474
 475 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 476         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 477         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 478         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 479         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 480         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 481         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 482         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 483                 ecol)},
 484         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 485         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 486         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 487         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 488         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 489         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 490         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 491         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 492         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 493         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 494         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 495                 fcruc)},
 496         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 497         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 498         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 499         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 500         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 501                 prc1023)},
 502         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 503                 prc1522)},
 504         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 505         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 506         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 507         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 508         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 509         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 510         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 511         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 512         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 513         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 514         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 515         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 516         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 517         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 518         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 519         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 520         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 521         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 522                 ptc1023)},
 523         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 524                 ptc1522)},
 525         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 526         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 527         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 528         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 529         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 530         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 531         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 532
 533         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 534 };
 535
 536 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 537                 sizeof(rte_igb_stats_strings[0]))
 538
 539 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 540         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 541         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 542         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 543         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 544         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 545 };
 546
 547 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 548                 sizeof(rte_igbvf_stats_strings[0]))
 549
 550 /**
 551  * Atomically reads the link status information from global
 552  * structure rte_eth_dev.
 553  *
 554  * @param dev
 555  *   - Pointer to the structure rte_eth_dev to read from.
 556  *   - Pointer to the buffer to be saved with the link status.
 557  *
 558  * @return
 559  *   - On success, zero.
 560  *   - On failure, negative value.
 561  */
 562 static inline int
 563 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 564                                 struct rte_eth_link *link)
 565 {
 566         struct rte_eth_link *dst = link;
 567         struct rte_eth_link *src = &(dev->data->dev_link);
 568
 569         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 570                                         *(uint64_t *)src) == 0)
 571                 return -1;
 572
 573         return 0;
 574 }
 575
 576 /**
 577  * Atomically writes the link status information into global
 578  * structure rte_eth_dev.
 579  *
 580  * @param dev
 581  *   - Pointer to the structure rte_eth_dev to read from.
 582  *   - Pointer to the buffer to be saved with the link status.
 583  *
 584  * @return
 585  *   - On success, zero.
 586  *   - On failure, negative value.
 587  */
 588 static inline int
 589 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 590                                 struct rte_eth_link *link)
 591 {
 592         struct rte_eth_link *dst = &(dev->data->dev_link);
 593         struct rte_eth_link *src = link;
 594
 595         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 596                                         *(uint64_t *)src) == 0)
 597                 return -1;
 598
 599         return 0;
 600 }
 601
 602 static inline void
 603 igb_intr_enable(struct rte_eth_dev *dev)
 604 {
 605         struct e1000_interrupt *intr =
 606                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 607         struct e1000_hw *hw =
 608                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 609
 610         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 611         E1000_WRITE_FLUSH(hw);
 612 }
 613
 614 static void
 615 igb_intr_disable(struct e1000_hw *hw)
 616 {
 617         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 618         E1000_WRITE_FLUSH(hw);
 619 }
 620
 621 static inline void
 622 igbvf_intr_enable(struct rte_eth_dev *dev)
 623 {
 624         struct e1000_hw *hw =
 625                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 626
 627         /* only for mailbox */
 628         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 629         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 630         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 631         E1000_WRITE_FLUSH(hw);
 632 }
 633
 634 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 635 static void
 636 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 637 {
 638         uint32_t tmp = 0;
 639
 640         /* mailbox */
 641         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 642         tmp |= E1000_VTIVAR_VALID;
 643         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 644 }
 645
 646 static void
 647 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 648 {
 649         struct e1000_hw *hw =
 650                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 651
 652         /* Configure VF other cause ivar */
 653         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 654 }
 655
 656 static inline int32_t
 657 igb_pf_reset_hw(struct e1000_hw *hw)
 658 {
 659         uint32_t ctrl_ext;
 660         int32_t status;
 661
 662         status = e1000_reset_hw(hw);
 663
 664         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 665         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 666         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 667         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 668         E1000_WRITE_FLUSH(hw);
 669
 670         return status;
 671 }
 672
 673 static void
 674 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 675 {
 676         struct e1000_hw *hw =
 677                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 678
 679
 680         hw->vendor_id = pci_dev->id.vendor_id;
 681         hw->device_id = pci_dev->id.device_id;
 682         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 683         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 684
 685         e1000_set_mac_type(hw);
 686
 687         /* need to check if it is a vf device below */
 688 }
 689
 690 static int
 691 igb_reset_swfw_lock(struct e1000_hw *hw)
 692 {
 693         int ret_val;
 694
 695         /*
 696          * Do mac ops initialization manually here, since we will need
 697          * some function pointers set by this call.
 698          */
 699         ret_val = e1000_init_mac_params(hw);
 700         if (ret_val)
 701                 return ret_val;
 702
 703         /*
 704          * SMBI lock should not fail in this early stage. If this is the case,
 705          * it is due to an improper exit of the application.
 706          * So force the release of the faulty lock.
 707          */
 708         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 709                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 710         }
 711         e1000_put_hw_semaphore_generic(hw);
 712
 713         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 714                 uint16_t mask;
 715
 716                 /*
 717                  * Phy lock should not fail in this early stage. If this is the case,
 718                  * it is due to an improper exit of the application.
 719                  * So force the release of the faulty lock.
 720                  */
 721                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 722                 if (hw->bus.func > E1000_FUNC_1)
 723                         mask <<= 2;
 724                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 725                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 726                                     hw->bus.func);
 727                 }
 728                 hw->mac.ops.release_swfw_sync(hw, mask);
 729
 730                 /*
 731                  * This one is more tricky since it is common to all ports; but
 732                  * swfw_sync retries last long enough (1s) to be almost sure that if
 733                  * lock can not be taken it is due to an improper lock of the
 734                  * semaphore.
 735                  */
 736                 mask = E1000_SWFW_EEP_SM;
 737                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 738                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 739                 }
 740                 hw->mac.ops.release_swfw_sync(hw, mask);
 741         }
 742
 743         return E1000_SUCCESS;
 744 }
 745
 746 static int
 747 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 748 {
 749         int error = 0;
 750         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
 751         struct e1000_hw *hw =
 752                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 753         struct e1000_vfta * shadow_vfta =
 754                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 755         struct e1000_filter_info *filter_info =
 756                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 757         struct e1000_adapter *adapter =
 758                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 759
 760         uint32_t ctrl_ext;
 761
 762         eth_dev->dev_ops = &eth_igb_ops;
 763         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 764         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 765         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 766
 767         /* for secondary processes, we don't initialise any further as primary
 768          * has already done this work. Only check we don't need a different
 769          * RX function */
 770         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 771                 if (eth_dev->data->scattered_rx)
 772                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 773                 return 0;
 774         }
 775
 776         rte_eth_copy_pci_info(eth_dev, pci_dev);
 777
 778         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 779
 780         igb_identify_hardware(eth_dev, pci_dev);
 781         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 782                 error = -EIO;
 783                 goto err_late;
 784         }
 785
 786         e1000_get_bus_info(hw);
 787
 788         /* Reset any pending lock */
 789         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 790                 error = -EIO;
 791                 goto err_late;
 792         }
 793
 794         /* Finish initialization */
 795         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 796                 error = -EIO;
 797                 goto err_late;
 798         }
 799
 800         hw->mac.autoneg = 1;
 801         hw->phy.autoneg_wait_to_complete = 0;
 802         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 803
 804         /* Copper options */
 805         if (hw->phy.media_type == e1000_media_type_copper) {
 806                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 807                 hw->phy.disable_polarity_correction = 0;
 808                 hw->phy.ms_type = e1000_ms_hw_default;
 809         }
 810
 811         /*
 812          * Start from a known state, this is important in reading the nvm
 813          * and mac from that.
 814          */
 815         igb_pf_reset_hw(hw);
 816
 817         /* Make sure we have a good EEPROM before we read from it */
 818         if (e1000_validate_nvm_checksum(hw) < 0) {
 819                 /*
 820                  * Some PCI-E parts fail the first check due to
 821                  * the link being in sleep state, call it again,
 822                  * if it fails a second time its a real issue.
 823                  */
 824                 if (e1000_validate_nvm_checksum(hw) < 0) {
 825                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 826                         error = -EIO;
 827                         goto err_late;
 828                 }
 829         }
 830
 831         /* Read the permanent MAC address out of the EEPROM */
 832         if (e1000_read_mac_addr(hw) != 0) {
 833                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 834                 error = -EIO;
 835                 goto err_late;
 836         }
 837
 838         /* Allocate memory for storing MAC addresses */
 839         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 840                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 841         if (eth_dev->data->mac_addrs == NULL) {
 842                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 843                                                 "store MAC addresses",
 844                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 845                 error = -ENOMEM;
 846                 goto err_late;
 847         }
 848
 849         /* Copy the permanent MAC address */
 850         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 851
 852         /* initialize the vfta */
 853         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 854
 855         /* Now initialize the hardware */
 856         if (igb_hardware_init(hw) != 0) {
 857                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 858                 rte_free(eth_dev->data->mac_addrs);
 859                 eth_dev->data->mac_addrs = NULL;
 860                 error = -ENODEV;
 861                 goto err_late;
 862         }
 863         hw->mac.get_link_status = 1;
 864         adapter->stopped = 0;
 865
 866         /* Indicate SOL/IDER usage */
 867         if (e1000_check_reset_block(hw) < 0) {
 868                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 869                                         "SOL/IDER session");
 870         }
 871
 872         /* initialize PF if max_vfs not zero */
 873         igb_pf_host_init(eth_dev);
 874
 875         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 876         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 877         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 878         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 879         E1000_WRITE_FLUSH(hw);
 880
 881         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 882                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 883                      pci_dev->id.device_id);
 884
 885         rte_intr_callback_register(&pci_dev->intr_handle,
 886                                    eth_igb_interrupt_handler,
 887                                    (void *)eth_dev);
 888
 889         /* enable uio/vfio intr/eventfd mapping */
 890         rte_intr_enable(&pci_dev->intr_handle);
 891
 892         /* enable support intr */
 893         igb_intr_enable(eth_dev);
 894
 895         TAILQ_INIT(&filter_info->flex_list);
 896         filter_info->flex_mask = 0;
 897         TAILQ_INIT(&filter_info->twotuple_list);
 898         filter_info->twotuple_mask = 0;
 899         TAILQ_INIT(&filter_info->fivetuple_list);
 900         filter_info->fivetuple_mask = 0;
 901
 902         return 0;
 903
 904 err_late:
 905         igb_hw_control_release(hw);
 906
 907         return error;
 908 }
 909
 910 static int
 911 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 912 {
 913         struct rte_pci_device *pci_dev;
 914         struct rte_intr_handle *intr_handle;
 915         struct e1000_hw *hw;
 916         struct e1000_adapter *adapter =
 917                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 918
 919         PMD_INIT_FUNC_TRACE();
 920
 921         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 922                 return -EPERM;
 923
 924         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 925         pci_dev = E1000_DEV_TO_PCI(eth_dev);
 926         intr_handle = &pci_dev->intr_handle;
 927
 928         if (adapter->stopped == 0)
 929                 eth_igb_close(eth_dev);
 930
 931         eth_dev->dev_ops = NULL;
 932         eth_dev->rx_pkt_burst = NULL;
 933         eth_dev->tx_pkt_burst = NULL;
 934
 935         /* Reset any pending lock */
 936         igb_reset_swfw_lock(hw);
 937
 938         rte_free(eth_dev->data->mac_addrs);
 939         eth_dev->data->mac_addrs = NULL;
 940
 941         /* uninitialize PF if max_vfs not zero */
 942         igb_pf_host_uninit(eth_dev);
 943
 944         /* disable uio intr before callback unregister */
 945         rte_intr_disable(intr_handle);
 946         rte_intr_callback_unregister(intr_handle,
 947                                      eth_igb_interrupt_handler, eth_dev);
 948
 949         return 0;
 950 }
 951
 952 /*
 953  * Virtual Function device init
 954  */
 955 static int
 956 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 957 {
 958         struct rte_pci_device *pci_dev;
 959         struct rte_intr_handle *intr_handle;
 960         struct e1000_adapter *adapter =
 961                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 962         struct e1000_hw *hw =
 963                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 964         int diag;
 965         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 966
 967         PMD_INIT_FUNC_TRACE();
 968
 969         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 970         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 971         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 972         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 973
 974         /* for secondary processes, we don't initialise any further as primary
 975          * has already done this work. Only check we don't need a different
 976          * RX function */
 977         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 978                 if (eth_dev->data->scattered_rx)
 979                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 980                 return 0;
 981         }
 982
 983         pci_dev = E1000_DEV_TO_PCI(eth_dev);
 984         rte_eth_copy_pci_info(eth_dev, pci_dev);
 985
 986         hw->device_id = pci_dev->id.device_id;
 987         hw->vendor_id = pci_dev->id.vendor_id;
 988         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 989         adapter->stopped = 0;
 990
 991         /* Initialize the shared code (base driver) */
 992         diag = e1000_setup_init_funcs(hw, TRUE);
 993         if (diag != 0) {
 994                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 995                         diag);
 996                 return -EIO;
 997         }
 998
 999         /* init_mailbox_params */
1000         hw->mbx.ops.init_params(hw);
1001
1002         /* Disable the interrupts for VF */
1003         igbvf_intr_disable(hw);
1004
1005         diag = hw->mac.ops.reset_hw(hw);
1006
1007         /* Allocate memory for storing MAC addresses */
1008         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1009                 hw->mac.rar_entry_count, 0);
1010         if (eth_dev->data->mac_addrs == NULL) {
1011                 PMD_INIT_LOG(ERR,
1012                         "Failed to allocate %d bytes needed to store MAC "
1013                         "addresses",
1014                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1015                 return -ENOMEM;
1016         }
1017
1018         /* Generate a random MAC address, if none was assigned by PF. */
1019         if (is_zero_ether_addr(perm_addr)) {
1020                 eth_random_addr(perm_addr->addr_bytes);
1021                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1022                 if (diag) {
1023                         rte_free(eth_dev->data->mac_addrs);
1024                         eth_dev->data->mac_addrs = NULL;
1025                         return diag;
1026                 }
1027                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1028                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1029                              "%02x:%02x:%02x:%02x:%02x:%02x",
1030                              perm_addr->addr_bytes[0],
1031                              perm_addr->addr_bytes[1],
1032                              perm_addr->addr_bytes[2],
1033                              perm_addr->addr_bytes[3],
1034                              perm_addr->addr_bytes[4],
1035                              perm_addr->addr_bytes[5]);
1036         }
1037
1038         /* Copy the permanent MAC address */
1039         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1040                         &eth_dev->data->mac_addrs[0]);
1041
1042         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1043                      "mac.type=%s",
1044                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1045                      pci_dev->id.device_id, "igb_mac_82576_vf");
1046
1047         intr_handle = &pci_dev->intr_handle;
1048         rte_intr_callback_register(intr_handle,
1049                                    eth_igbvf_interrupt_handler, eth_dev);
1050
1051         return 0;
1052 }
1053
1054 static int
1055 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1056 {
1057         struct e1000_adapter *adapter =
1058                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1059         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
1060
1061         PMD_INIT_FUNC_TRACE();
1062
1063         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1064                 return -EPERM;
1065
1066         if (adapter->stopped == 0)
1067                 igbvf_dev_close(eth_dev);
1068
1069         eth_dev->dev_ops = NULL;
1070         eth_dev->rx_pkt_burst = NULL;
1071         eth_dev->tx_pkt_burst = NULL;
1072
1073         rte_free(eth_dev->data->mac_addrs);
1074         eth_dev->data->mac_addrs = NULL;
1075
1076         /* disable uio intr before callback unregister */
1077         rte_intr_disable(&pci_dev->intr_handle);
1078         rte_intr_callback_unregister(&pci_dev->intr_handle,
1079                                      eth_igbvf_interrupt_handler,
1080                                      (void *)eth_dev);
1081
1082         return 0;
1083 }
1084
1085 static struct eth_driver rte_igb_pmd = {
1086         .pci_drv = {
1087                 .id_table = pci_id_igb_map,
1088                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1089                         RTE_PCI_DRV_DETACHABLE,
1090                 .probe = rte_eth_dev_pci_probe,
1091                 .remove = rte_eth_dev_pci_remove,
1092         },
1093         .eth_dev_init = eth_igb_dev_init,
1094         .eth_dev_uninit = eth_igb_dev_uninit,
1095         .dev_private_size = sizeof(struct e1000_adapter),
1096 };
1097
1098 /*
1099  * virtual function driver struct
1100  */
1101 static struct eth_driver rte_igbvf_pmd = {
1102         .pci_drv = {
1103                 .id_table = pci_id_igbvf_map,
1104                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1105                 .probe = rte_eth_dev_pci_probe,
1106                 .remove = rte_eth_dev_pci_remove,
1107         },
1108         .eth_dev_init = eth_igbvf_dev_init,
1109         .eth_dev_uninit = eth_igbvf_dev_uninit,
1110         .dev_private_size = sizeof(struct e1000_adapter),
1111 };
1112
1113 static void
1114 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1115 {
1116         struct e1000_hw *hw =
1117                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1118         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1119         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1120         rctl |= E1000_RCTL_VFE;
1121         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1122 }
1123
1124 static int
1125 igb_check_mq_mode(struct rte_eth_dev *dev)
1126 {
1127         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1128         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1129         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1130         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1131
1132         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1133             tx_mq_mode == ETH_MQ_TX_DCB ||
1134             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1135                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1136                 return -EINVAL;
1137         }
1138         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1139                 /* Check multi-queue mode.
1140                  * To no break software we accept ETH_MQ_RX_NONE as this might
1141                  * be used to turn off VLAN filter.
1142                  */
1143
1144                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1145                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1146                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1147                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1148                 } else {
1149                         /* Only support one queue on VFs.
1150                          * RSS together with SRIOV is not supported.
1151                          */
1152                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1153                                         " wrong mq_mode rx %d.",
1154                                         rx_mq_mode);
1155                         return -EINVAL;
1156                 }
1157                 /* TX mode is not used here, so mode might be ignored.*/
1158                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1159                         /* SRIOV only works in VMDq enable mode */
1160                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1161                                         " TX mode %d is not supported. "
1162                                         " Driver will behave as %d mode.",
1163                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1164                 }
1165
1166                 /* check valid queue number */
1167                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1168                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1169                                         " only support one queue on VFs.");
1170                         return -EINVAL;
1171                 }
1172         } else {
1173                 /* To no break software that set invalid mode, only display
1174                  * warning if invalid mode is used.
1175                  */
1176                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1177                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1178                     rx_mq_mode != ETH_MQ_RX_RSS) {
1179                         /* RSS together with VMDq not supported*/
1180                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1181                                      rx_mq_mode);
1182                         return -EINVAL;
1183                 }
1184
1185                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1186                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1187                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1188                                         " Due to txmode is meaningless in this"
1189                                         " driver, just ignore.",
1190                                         tx_mq_mode);
1191                 }
1192         }
1193         return 0;
1194 }
1195
1196 static int
1197 eth_igb_configure(struct rte_eth_dev *dev)
1198 {
1199         struct e1000_interrupt *intr =
1200                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1201         int ret;
1202
1203         PMD_INIT_FUNC_TRACE();
1204
1205         /* multipe queue mode checking */
1206         ret  = igb_check_mq_mode(dev);
1207         if (ret != 0) {
1208                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1209                             ret);
1210                 return ret;
1211         }
1212
1213         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1214         PMD_INIT_FUNC_TRACE();
1215
1216         return 0;
1217 }
1218
1219 static int
1220 eth_igb_start(struct rte_eth_dev *dev)
1221 {
1222         struct e1000_hw *hw =
1223                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1224         struct e1000_adapter *adapter =
1225                 E1000_DEV_PRIVATE(dev->data->dev_private);
1226         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1227         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1228         int ret, mask;
1229         uint32_t intr_vector = 0;
1230         uint32_t ctrl_ext;
1231         uint32_t *speeds;
1232         int num_speeds;
1233         bool autoneg;
1234
1235         PMD_INIT_FUNC_TRACE();
1236
1237         /* disable uio/vfio intr/eventfd mapping */
1238         rte_intr_disable(intr_handle);
1239
1240         /* Power up the phy. Needed to make the link go Up */
1241         eth_igb_dev_set_link_up(dev);
1242
1243         /*
1244          * Packet Buffer Allocation (PBA)
1245          * Writing PBA sets the receive portion of the buffer
1246          * the remainder is used for the transmit buffer.
1247          */
1248         if (hw->mac.type == e1000_82575) {
1249                 uint32_t pba;
1250
1251                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1252                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1253         }
1254
1255         /* Put the address into the Receive Address Array */
1256         e1000_rar_set(hw, hw->mac.addr, 0);
1257
1258         /* Initialize the hardware */
1259         if (igb_hardware_init(hw)) {
1260                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1261                 return -EIO;
1262         }
1263         adapter->stopped = 0;
1264
1265         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1266
1267         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1268         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1269         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1270         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1271         E1000_WRITE_FLUSH(hw);
1272
1273         /* configure PF module if SRIOV enabled */
1274         igb_pf_host_configure(dev);
1275
1276         /* check and configure queue intr-vector mapping */
1277         if ((rte_intr_cap_multiple(intr_handle) ||
1278              !RTE_ETH_DEV_SRIOV(dev).active) &&
1279             dev->data->dev_conf.intr_conf.rxq != 0) {
1280                 intr_vector = dev->data->nb_rx_queues;
1281                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1282                         return -1;
1283         }
1284
1285         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1286                 intr_handle->intr_vec =
1287                         rte_zmalloc("intr_vec",
1288                                     dev->data->nb_rx_queues * sizeof(int), 0);
1289                 if (intr_handle->intr_vec == NULL) {
1290                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1291                                      " intr_vec\n", dev->data->nb_rx_queues);
1292                         return -ENOMEM;
1293                 }
1294         }
1295
1296         /* confiugre msix for rx interrupt */
1297         eth_igb_configure_msix_intr(dev);
1298
1299         /* Configure for OS presence */
1300         igb_init_manageability(hw);
1301
1302         eth_igb_tx_init(dev);
1303
1304         /* This can fail when allocating mbufs for descriptor rings */
1305         ret = eth_igb_rx_init(dev);
1306         if (ret) {
1307                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1308                 igb_dev_clear_queues(dev);
1309                 return ret;
1310         }
1311
1312         e1000_clear_hw_cntrs_base_generic(hw);
1313
1314         /*
1315          * VLAN Offload Settings
1316          */
1317         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1318                         ETH_VLAN_EXTEND_MASK;
1319         eth_igb_vlan_offload_set(dev, mask);
1320
1321         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1322                 /* Enable VLAN filter since VMDq always use VLAN filter */
1323                 igb_vmdq_vlan_hw_filter_enable(dev);
1324         }
1325
1326         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1327                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1328                 (hw->mac.type == e1000_i211)) {
1329                 /* Configure EITR with the maximum possible value (0xFFFF) */
1330                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1331         }
1332
1333         /* Setup link speed and duplex */
1334         speeds = &dev->data->dev_conf.link_speeds;
1335         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1336                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1337                 hw->mac.autoneg = 1;
1338         } else {
1339                 num_speeds = 0;
1340                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1341
1342                 /* Reset */
1343                 hw->phy.autoneg_advertised = 0;
1344
1345                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1346                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1347                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1348                         num_speeds = -1;
1349                         goto error_invalid_config;
1350                 }
1351                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1352                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1353                         num_speeds++;
1354                 }
1355                 if (*speeds & ETH_LINK_SPEED_10M) {
1356                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1357                         num_speeds++;
1358                 }
1359                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1360                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1361                         num_speeds++;
1362                 }
1363                 if (*speeds & ETH_LINK_SPEED_100M) {
1364                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1365                         num_speeds++;
1366                 }
1367                 if (*speeds & ETH_LINK_SPEED_1G) {
1368                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1369                         num_speeds++;
1370                 }
1371                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1372                         goto error_invalid_config;
1373
1374                 /* Set/reset the mac.autoneg based on the link speed,
1375                  * fixed or not
1376                  */
1377                 if (!autoneg) {
1378                         hw->mac.autoneg = 0;
1379                         hw->mac.forced_speed_duplex =
1380                                         hw->phy.autoneg_advertised;
1381                 } else {
1382                         hw->mac.autoneg = 1;
1383                 }
1384         }
1385
1386         e1000_setup_link(hw);
1387
1388         if (rte_intr_allow_others(intr_handle)) {
1389                 /* check if lsc interrupt is enabled */
1390                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1391                         eth_igb_lsc_interrupt_setup(dev);
1392         } else {
1393                 rte_intr_callback_unregister(intr_handle,
1394                                              eth_igb_interrupt_handler,
1395                                              (void *)dev);
1396                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1397                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1398                                      " no intr multiplex\n");
1399         }
1400
1401         /* check if rxq interrupt is enabled */
1402         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1403             rte_intr_dp_is_en(intr_handle))
1404                 eth_igb_rxq_interrupt_setup(dev);
1405
1406         /* enable uio/vfio intr/eventfd mapping */
1407         rte_intr_enable(intr_handle);
1408
1409         /* resume enabled intr since hw reset */
1410         igb_intr_enable(dev);
1411
1412         PMD_INIT_LOG(DEBUG, "<<");
1413
1414         return 0;
1415
1416 error_invalid_config:
1417         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1418                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1419         igb_dev_clear_queues(dev);
1420         return -EINVAL;
1421 }
1422
1423 /*********************************************************************
1424  *
1425  *  This routine disables all traffic on the adapter by issuing a
1426  *  global reset on the MAC.
1427  *
1428  **********************************************************************/
1429 static void
1430 eth_igb_stop(struct rte_eth_dev *dev)
1431 {
1432         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1433         struct e1000_filter_info *filter_info =
1434                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1435         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1436         struct rte_eth_link link;
1437         struct e1000_flex_filter *p_flex;
1438         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1439         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1440         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1441
1442         igb_intr_disable(hw);
1443
1444         /* disable intr eventfd mapping */
1445         rte_intr_disable(intr_handle);
1446
1447         igb_pf_reset_hw(hw);
1448         E1000_WRITE_REG(hw, E1000_WUC, 0);
1449
1450         /* Set bit for Go Link disconnect */
1451         if (hw->mac.type >= e1000_82580) {
1452                 uint32_t phpm_reg;
1453
1454                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1455                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1456                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1457         }
1458
1459         /* Power down the phy. Needed to make the link go Down */
1460         eth_igb_dev_set_link_down(dev);
1461
1462         igb_dev_clear_queues(dev);
1463
1464         /* clear the recorded link status */
1465         memset(&link, 0, sizeof(link));
1466         rte_igb_dev_atomic_write_link_status(dev, &link);
1467
1468         /* Remove all flex filters of the device */
1469         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1470                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1471                 rte_free(p_flex);
1472         }
1473         filter_info->flex_mask = 0;
1474
1475         /* Remove all ntuple filters of the device */
1476         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1477              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1478                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1479                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1480                              p_5tuple, entries);
1481                 rte_free(p_5tuple);
1482         }
1483         filter_info->fivetuple_mask = 0;
1484         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1485              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1486                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1487                 TAILQ_REMOVE(&filter_info->twotuple_list,
1488                              p_2tuple, entries);
1489                 rte_free(p_2tuple);
1490         }
1491         filter_info->twotuple_mask = 0;
1492
1493         if (!rte_intr_allow_others(intr_handle))
1494                 /* resume to the default handler */
1495                 rte_intr_callback_register(intr_handle,
1496                                            eth_igb_interrupt_handler,
1497                                            (void *)dev);
1498
1499         /* Clean datapath event and queue/vec mapping */
1500         rte_intr_efd_disable(intr_handle);
1501         if (intr_handle->intr_vec != NULL) {
1502                 rte_free(intr_handle->intr_vec);
1503                 intr_handle->intr_vec = NULL;
1504         }
1505 }
1506
1507 static int
1508 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1509 {
1510         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1511
1512         if (hw->phy.media_type == e1000_media_type_copper)
1513                 e1000_power_up_phy(hw);
1514         else
1515                 e1000_power_up_fiber_serdes_link(hw);
1516
1517         return 0;
1518 }
1519
1520 static int
1521 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1522 {
1523         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524
1525         if (hw->phy.media_type == e1000_media_type_copper)
1526                 e1000_power_down_phy(hw);
1527         else
1528                 e1000_shutdown_fiber_serdes_link(hw);
1529
1530         return 0;
1531 }
1532
1533 static void
1534 eth_igb_close(struct rte_eth_dev *dev)
1535 {
1536         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1537         struct e1000_adapter *adapter =
1538                 E1000_DEV_PRIVATE(dev->data->dev_private);
1539         struct rte_eth_link link;
1540         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1541         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1542
1543         eth_igb_stop(dev);
1544         adapter->stopped = 1;
1545
1546         e1000_phy_hw_reset(hw);
1547         igb_release_manageability(hw);
1548         igb_hw_control_release(hw);
1549
1550         /* Clear bit for Go Link disconnect */
1551         if (hw->mac.type >= e1000_82580) {
1552                 uint32_t phpm_reg;
1553
1554                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1555                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1556                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1557         }
1558
1559         igb_dev_free_queues(dev);
1560
1561         if (intr_handle->intr_vec) {
1562                 rte_free(intr_handle->intr_vec);
1563                 intr_handle->intr_vec = NULL;
1564         }
1565
1566         memset(&link, 0, sizeof(link));
1567         rte_igb_dev_atomic_write_link_status(dev, &link);
1568 }
1569
1570 static int
1571 igb_get_rx_buffer_size(struct e1000_hw *hw)
1572 {
1573         uint32_t rx_buf_size;
1574         if (hw->mac.type == e1000_82576) {
1575                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1576         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1577                 /* PBS needs to be translated according to a lookup table */
1578                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1579                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1580                 rx_buf_size = (rx_buf_size << 10);
1581         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1582                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1583         } else {
1584                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1585         }
1586
1587         return rx_buf_size;
1588 }
1589
1590 /*********************************************************************
1591  *
1592  *  Initialize the hardware
1593  *
1594  **********************************************************************/
1595 static int
1596 igb_hardware_init(struct e1000_hw *hw)
1597 {
1598         uint32_t rx_buf_size;
1599         int diag;
1600
1601         /* Let the firmware know the OS is in control */
1602         igb_hw_control_acquire(hw);
1603
1604         /*
1605          * These parameters control the automatic generation (Tx) and
1606          * response (Rx) to Ethernet PAUSE frames.
1607          * - High water mark should allow for at least two standard size (1518)
1608          *   frames to be received after sending an XOFF.
1609          * - Low water mark works best when it is very near the high water mark.
1610          *   This allows the receiver to restart by sending XON when it has
1611          *   drained a bit. Here we use an arbitrary value of 1500 which will
1612          *   restart after one full frame is pulled from the buffer. There
1613          *   could be several smaller frames in the buffer and if so they will
1614          *   not trigger the XON until their total number reduces the buffer
1615          *   by 1500.
1616          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1617          */
1618         rx_buf_size = igb_get_rx_buffer_size(hw);
1619
1620         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1621         hw->fc.low_water = hw->fc.high_water - 1500;
1622         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1623         hw->fc.send_xon = 1;
1624
1625         /* Set Flow control, use the tunable location if sane */
1626         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1627                 hw->fc.requested_mode = igb_fc_setting;
1628         else
1629                 hw->fc.requested_mode = e1000_fc_none;
1630
1631         /* Issue a global reset */
1632         igb_pf_reset_hw(hw);
1633         E1000_WRITE_REG(hw, E1000_WUC, 0);
1634
1635         diag = e1000_init_hw(hw);
1636         if (diag < 0)
1637                 return diag;
1638
1639         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1640         e1000_get_phy_info(hw);
1641         e1000_check_for_link(hw);
1642
1643         return 0;
1644 }
1645
1646 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1647 static void
1648 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1649 {
1650         int pause_frames;
1651
1652         uint64_t old_gprc  = stats->gprc;
1653         uint64_t old_gptc  = stats->gptc;
1654         uint64_t old_tpr   = stats->tpr;
1655         uint64_t old_tpt   = stats->tpt;
1656         uint64_t old_rpthc = stats->rpthc;
1657         uint64_t old_hgptc = stats->hgptc;
1658
1659         if(hw->phy.media_type == e1000_media_type_copper ||
1660             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1661                 stats->symerrs +=
1662                     E1000_READ_REG(hw,E1000_SYMERRS);
1663                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1664         }
1665
1666         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1667         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1668         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1669         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1670
1671         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1672         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1673         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1674         stats->dc += E1000_READ_REG(hw, E1000_DC);
1675         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1676         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1677         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1678         /*
1679         ** For watchdog management we need to know if we have been
1680         ** paused during the last interval, so capture that here.
1681         */
1682         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1683         stats->xoffrxc += pause_frames;
1684         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1685         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1686         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1687         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1688         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1689         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1690         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1691         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1692         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1693         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1694         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1695         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1696
1697         /* For the 64-bit byte counters the low dword must be read first. */
1698         /* Both registers clear on the read of the high dword */
1699
1700         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1701         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1702         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1703         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1704         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1705         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1706         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1707
1708         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1709         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1710         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1711         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1712         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1713
1714         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1715         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1716
1717         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1718         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1719         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1720         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1721         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1722         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1723
1724         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1725         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1726         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1727         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1728         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1729         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1730         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1731         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1732
1733         /* Interrupt Counts */
1734
1735         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1736         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1737         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1738         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1739         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1740         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1741         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1742         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1743         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1744
1745         /* Host to Card Statistics */
1746
1747         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1748         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1749         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1750         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1751         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1752         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1753         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1754         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1755         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1756         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1757         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1758         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1759         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1760         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1761         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1762         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1763
1764         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1765         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1766         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1767         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1768         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1769         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1770 }
1771
1772 static void
1773 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1774 {
1775         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1776         struct e1000_hw_stats *stats =
1777                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1778
1779         igb_read_stats_registers(hw, stats);
1780
1781         if (rte_stats == NULL)
1782                 return;
1783
1784         /* Rx Errors */
1785         rte_stats->imissed = stats->mpc;
1786         rte_stats->ierrors = stats->crcerrs +
1787                              stats->rlec + stats->ruc + stats->roc +
1788                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1789
1790         /* Tx Errors */
1791         rte_stats->oerrors = stats->ecol + stats->latecol;
1792
1793         rte_stats->ipackets = stats->gprc;
1794         rte_stats->opackets = stats->gptc;
1795         rte_stats->ibytes   = stats->gorc;
1796         rte_stats->obytes   = stats->gotc;
1797 }
1798
1799 static void
1800 eth_igb_stats_reset(struct rte_eth_dev *dev)
1801 {
1802         struct e1000_hw_stats *hw_stats =
1803                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1804
1805         /* HW registers are cleared on read */
1806         eth_igb_stats_get(dev, NULL);
1807
1808         /* Reset software totals */
1809         memset(hw_stats, 0, sizeof(*hw_stats));
1810 }
1811
1812 static void
1813 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1814 {
1815         struct e1000_hw_stats *stats =
1816                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1817
1818         /* HW registers are cleared on read */
1819         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1820
1821         /* Reset software totals */
1822         memset(stats, 0, sizeof(*stats));
1823 }
1824
1825 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1826         struct rte_eth_xstat_name *xstats_names,
1827         __rte_unused unsigned limit)
1828 {
1829         unsigned i;
1830
1831         if (xstats_names == NULL)
1832                 return IGB_NB_XSTATS;
1833
1834         /* Note: limit checked in rte_eth_xstats_names() */
1835
1836         for (i = 0; i < IGB_NB_XSTATS; i++) {
1837                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1838                          "%s", rte_igb_stats_strings[i].name);
1839         }
1840
1841         return IGB_NB_XSTATS;
1842 }
1843
1844 static int
1845 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1846                    unsigned n)
1847 {
1848         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1849         struct e1000_hw_stats *hw_stats =
1850                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1851         unsigned i;
1852
1853         if (n < IGB_NB_XSTATS)
1854                 return IGB_NB_XSTATS;
1855
1856         igb_read_stats_registers(hw, hw_stats);
1857
1858         /* If this is a reset xstats is NULL, and we have cleared the
1859          * registers by reading them.
1860          */
1861         if (!xstats)
1862                 return 0;
1863
1864         /* Extended stats */
1865         for (i = 0; i < IGB_NB_XSTATS; i++) {
1866                 xstats[i].id = i;
1867                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1868                         rte_igb_stats_strings[i].offset);
1869         }
1870
1871         return IGB_NB_XSTATS;
1872 }
1873
1874 static void
1875 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1876 {
1877         /* Good Rx packets, include VF loopback */
1878         UPDATE_VF_STAT(E1000_VFGPRC,
1879             hw_stats->last_gprc, hw_stats->gprc);
1880
1881         /* Good Rx octets, include VF loopback */
1882         UPDATE_VF_STAT(E1000_VFGORC,
1883             hw_stats->last_gorc, hw_stats->gorc);
1884
1885         /* Good Tx packets, include VF loopback */
1886         UPDATE_VF_STAT(E1000_VFGPTC,
1887             hw_stats->last_gptc, hw_stats->gptc);
1888
1889         /* Good Tx octets, include VF loopback */
1890         UPDATE_VF_STAT(E1000_VFGOTC,
1891             hw_stats->last_gotc, hw_stats->gotc);
1892
1893         /* Rx Multicst packets */
1894         UPDATE_VF_STAT(E1000_VFMPRC,
1895             hw_stats->last_mprc, hw_stats->mprc);
1896
1897         /* Good Rx loopback packets */
1898         UPDATE_VF_STAT(E1000_VFGPRLBC,
1899             hw_stats->last_gprlbc, hw_stats->gprlbc);
1900
1901         /* Good Rx loopback octets */
1902         UPDATE_VF_STAT(E1000_VFGORLBC,
1903             hw_stats->last_gorlbc, hw_stats->gorlbc);
1904
1905         /* Good Tx loopback packets */
1906         UPDATE_VF_STAT(E1000_VFGPTLBC,
1907             hw_stats->last_gptlbc, hw_stats->gptlbc);
1908
1909         /* Good Tx loopback octets */
1910         UPDATE_VF_STAT(E1000_VFGOTLBC,
1911             hw_stats->last_gotlbc, hw_stats->gotlbc);
1912 }
1913
1914 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1915                                      struct rte_eth_xstat_name *xstats_names,
1916                                      __rte_unused unsigned limit)
1917 {
1918         unsigned i;
1919
1920         if (xstats_names != NULL)
1921                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1922                         snprintf(xstats_names[i].name,
1923                                 sizeof(xstats_names[i].name), "%s",
1924                                 rte_igbvf_stats_strings[i].name);
1925                 }
1926         return IGBVF_NB_XSTATS;
1927 }
1928
1929 static int
1930 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1931                      unsigned n)
1932 {
1933         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1934         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1935                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1936         unsigned i;
1937
1938         if (n < IGBVF_NB_XSTATS)
1939                 return IGBVF_NB_XSTATS;
1940
1941         igbvf_read_stats_registers(hw, hw_stats);
1942
1943         if (!xstats)
1944                 return 0;
1945
1946         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1947                 xstats[i].id = i;
1948                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1949                         rte_igbvf_stats_strings[i].offset);
1950         }
1951
1952         return IGBVF_NB_XSTATS;
1953 }
1954
1955 static void
1956 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1957 {
1958         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1959         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1960                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1961
1962         igbvf_read_stats_registers(hw, hw_stats);
1963
1964         if (rte_stats == NULL)
1965                 return;
1966
1967         rte_stats->ipackets = hw_stats->gprc;
1968         rte_stats->ibytes = hw_stats->gorc;
1969         rte_stats->opackets = hw_stats->gptc;
1970         rte_stats->obytes = hw_stats->gotc;
1971 }
1972
1973 static void
1974 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1975 {
1976         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1977                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1978
1979         /* Sync HW register to the last stats */
1980         eth_igbvf_stats_get(dev, NULL);
1981
1982         /* reset HW current stats*/
1983         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1984                offsetof(struct e1000_vf_stats, gprc));
1985 }
1986
1987 static void
1988 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1989 {
1990         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991
1992         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1993         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1994         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1995         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1996         dev_info->rx_offload_capa =
1997                 DEV_RX_OFFLOAD_VLAN_STRIP |
1998                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1999                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2000                 DEV_RX_OFFLOAD_TCP_CKSUM;
2001         dev_info->tx_offload_capa =
2002                 DEV_TX_OFFLOAD_VLAN_INSERT |
2003                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2004                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2005                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2006                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2007                 DEV_TX_OFFLOAD_TCP_TSO;
2008
2009         switch (hw->mac.type) {
2010         case e1000_82575:
2011                 dev_info->max_rx_queues = 4;
2012                 dev_info->max_tx_queues = 4;
2013                 dev_info->max_vmdq_pools = 0;
2014                 break;
2015
2016         case e1000_82576:
2017                 dev_info->max_rx_queues = 16;
2018                 dev_info->max_tx_queues = 16;
2019                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2020                 dev_info->vmdq_queue_num = 16;
2021                 break;
2022
2023         case e1000_82580:
2024                 dev_info->max_rx_queues = 8;
2025                 dev_info->max_tx_queues = 8;
2026                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2027                 dev_info->vmdq_queue_num = 8;
2028                 break;
2029
2030         case e1000_i350:
2031                 dev_info->max_rx_queues = 8;
2032                 dev_info->max_tx_queues = 8;
2033                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2034                 dev_info->vmdq_queue_num = 8;
2035                 break;
2036
2037         case e1000_i354:
2038                 dev_info->max_rx_queues = 8;
2039                 dev_info->max_tx_queues = 8;
2040                 break;
2041
2042         case e1000_i210:
2043                 dev_info->max_rx_queues = 4;
2044                 dev_info->max_tx_queues = 4;
2045                 dev_info->max_vmdq_pools = 0;
2046                 break;
2047
2048         case e1000_i211:
2049                 dev_info->max_rx_queues = 2;
2050                 dev_info->max_tx_queues = 2;
2051                 dev_info->max_vmdq_pools = 0;
2052                 break;
2053
2054         default:
2055                 /* Should not happen */
2056                 break;
2057         }
2058         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2059         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2060         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2061
2062         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2063                 .rx_thresh = {
2064                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2065                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2066                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2067                 },
2068                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2069                 .rx_drop_en = 0,
2070         };
2071
2072         dev_info->default_txconf = (struct rte_eth_txconf) {
2073                 .tx_thresh = {
2074                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2075                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2076                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2077                 },
2078                 .txq_flags = 0,
2079         };
2080
2081         dev_info->rx_desc_lim = rx_desc_lim;
2082         dev_info->tx_desc_lim = tx_desc_lim;
2083
2084         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2085                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2086                         ETH_LINK_SPEED_1G;
2087 }
2088
2089 static const uint32_t *
2090 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2091 {
2092         static const uint32_t ptypes[] = {
2093                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2094                 RTE_PTYPE_L2_ETHER,
2095                 RTE_PTYPE_L3_IPV4,
2096                 RTE_PTYPE_L3_IPV4_EXT,
2097                 RTE_PTYPE_L3_IPV6,
2098                 RTE_PTYPE_L3_IPV6_EXT,
2099                 RTE_PTYPE_L4_TCP,
2100                 RTE_PTYPE_L4_UDP,
2101                 RTE_PTYPE_L4_SCTP,
2102                 RTE_PTYPE_TUNNEL_IP,
2103                 RTE_PTYPE_INNER_L3_IPV6,
2104                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2105                 RTE_PTYPE_INNER_L4_TCP,
2106                 RTE_PTYPE_INNER_L4_UDP,
2107                 RTE_PTYPE_UNKNOWN
2108         };
2109
2110         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2111             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2112                 return ptypes;
2113         return NULL;
2114 }
2115
2116 static void
2117 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2118 {
2119         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120
2121         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2122         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2123         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2124         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2125         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2126                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2127                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2128                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2129         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2130                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2131                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2132                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2133                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2134                                 DEV_TX_OFFLOAD_TCP_TSO;
2135         switch (hw->mac.type) {
2136         case e1000_vfadapt:
2137                 dev_info->max_rx_queues = 2;
2138                 dev_info->max_tx_queues = 2;
2139                 break;
2140         case e1000_vfadapt_i350:
2141                 dev_info->max_rx_queues = 1;
2142                 dev_info->max_tx_queues = 1;
2143                 break;
2144         default:
2145                 /* Should not happen */
2146                 break;
2147         }
2148
2149         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2150                 .rx_thresh = {
2151                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2152                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2153                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2154                 },
2155                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2156                 .rx_drop_en = 0,
2157         };
2158
2159         dev_info->default_txconf = (struct rte_eth_txconf) {
2160                 .tx_thresh = {
2161                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2162                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2163                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2164                 },
2165                 .txq_flags = 0,
2166         };
2167
2168         dev_info->rx_desc_lim = rx_desc_lim;
2169         dev_info->tx_desc_lim = tx_desc_lim;
2170 }
2171
2172 /* return 0 means link status changed, -1 means not changed */
2173 static int
2174 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2175 {
2176         struct e1000_hw *hw =
2177                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2178         struct rte_eth_link link, old;
2179         int link_check, count;
2180
2181         link_check = 0;
2182         hw->mac.get_link_status = 1;
2183
2184         /* possible wait-to-complete in up to 9 seconds */
2185         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2186                 /* Read the real link status */
2187                 switch (hw->phy.media_type) {
2188                 case e1000_media_type_copper:
2189                         /* Do the work to read phy */
2190                         e1000_check_for_link(hw);
2191                         link_check = !hw->mac.get_link_status;
2192                         break;
2193
2194                 case e1000_media_type_fiber:
2195                         e1000_check_for_link(hw);
2196                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2197                                       E1000_STATUS_LU);
2198                         break;
2199
2200                 case e1000_media_type_internal_serdes:
2201                         e1000_check_for_link(hw);
2202                         link_check = hw->mac.serdes_has_link;
2203                         break;
2204
2205                 /* VF device is type_unknown */
2206                 case e1000_media_type_unknown:
2207                         eth_igbvf_link_update(hw);
2208                         link_check = !hw->mac.get_link_status;
2209                         break;
2210
2211                 default:
2212                         break;
2213                 }
2214                 if (link_check || wait_to_complete == 0)
2215                         break;
2216                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2217         }
2218         memset(&link, 0, sizeof(link));
2219         rte_igb_dev_atomic_read_link_status(dev, &link);
2220         old = link;
2221
2222         /* Now we check if a transition has happened */
2223         if (link_check) {
2224                 uint16_t duplex, speed;
2225                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2226                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2227                                 ETH_LINK_FULL_DUPLEX :
2228                                 ETH_LINK_HALF_DUPLEX;
2229                 link.link_speed = speed;
2230                 link.link_status = ETH_LINK_UP;
2231                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2232                                 ETH_LINK_SPEED_FIXED);
2233         } else if (!link_check) {
2234                 link.link_speed = 0;
2235                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2236                 link.link_status = ETH_LINK_DOWN;
2237                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2238         }
2239         rte_igb_dev_atomic_write_link_status(dev, &link);
2240
2241         /* not changed */
2242         if (old.link_status == link.link_status)
2243                 return -1;
2244
2245         /* changed */
2246         return 0;
2247 }
2248
2249 /*
2250  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2251  * For ASF and Pass Through versions of f/w this means
2252  * that the driver is loaded.
2253  */
2254 static void
2255 igb_hw_control_acquire(struct e1000_hw *hw)
2256 {
2257         uint32_t ctrl_ext;
2258
2259         /* Let firmware know the driver has taken over */
2260         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2261         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2262 }
2263
2264 /*
2265  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2266  * For ASF and Pass Through versions of f/w this means that the
2267  * driver is no longer loaded.
2268  */
2269 static void
2270 igb_hw_control_release(struct e1000_hw *hw)
2271 {
2272         uint32_t ctrl_ext;
2273
2274         /* Let firmware taken over control of h/w */
2275         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2276         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2277                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2278 }
2279
2280 /*
2281  * Bit of a misnomer, what this really means is
2282  * to enable OS management of the system... aka
2283  * to disable special hardware management features.
2284  */
2285 static void
2286 igb_init_manageability(struct e1000_hw *hw)
2287 {
2288         if (e1000_enable_mng_pass_thru(hw)) {
2289                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2290                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2291
2292                 /* disable hardware interception of ARP */
2293                 manc &= ~(E1000_MANC_ARP_EN);
2294
2295                 /* enable receiving management packets to the host */
2296                 manc |= E1000_MANC_EN_MNG2HOST;
2297                 manc2h |= 1 << 5;  /* Mng Port 623 */
2298                 manc2h |= 1 << 6;  /* Mng Port 664 */
2299                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2300                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2301         }
2302 }
2303
2304 static void
2305 igb_release_manageability(struct e1000_hw *hw)
2306 {
2307         if (e1000_enable_mng_pass_thru(hw)) {
2308                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2309
2310                 manc |= E1000_MANC_ARP_EN;
2311                 manc &= ~E1000_MANC_EN_MNG2HOST;
2312
2313                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2314         }
2315 }
2316
2317 static void
2318 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2319 {
2320         struct e1000_hw *hw =
2321                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2322         uint32_t rctl;
2323
2324         rctl = E1000_READ_REG(hw, E1000_RCTL);
2325         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2326         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2327 }
2328
2329 static void
2330 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2331 {
2332         struct e1000_hw *hw =
2333                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2334         uint32_t rctl;
2335
2336         rctl = E1000_READ_REG(hw, E1000_RCTL);
2337         rctl &= (~E1000_RCTL_UPE);
2338         if (dev->data->all_multicast == 1)
2339                 rctl |= E1000_RCTL_MPE;
2340         else
2341                 rctl &= (~E1000_RCTL_MPE);
2342         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2343 }
2344
2345 static void
2346 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2347 {
2348         struct e1000_hw *hw =
2349                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2350         uint32_t rctl;
2351
2352         rctl = E1000_READ_REG(hw, E1000_RCTL);
2353         rctl |= E1000_RCTL_MPE;
2354         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2355 }
2356
2357 static void
2358 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2359 {
2360         struct e1000_hw *hw =
2361                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2362         uint32_t rctl;
2363
2364         if (dev->data->promiscuous == 1)
2365                 return; /* must remain in all_multicast mode */
2366         rctl = E1000_READ_REG(hw, E1000_RCTL);
2367         rctl &= (~E1000_RCTL_MPE);
2368         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2369 }
2370
2371 static int
2372 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2373 {
2374         struct e1000_hw *hw =
2375                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2376         struct e1000_vfta * shadow_vfta =
2377                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2378         uint32_t vfta;
2379         uint32_t vid_idx;
2380         uint32_t vid_bit;
2381
2382         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2383                               E1000_VFTA_ENTRY_MASK);
2384         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2385         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2386         if (on)
2387                 vfta |= vid_bit;
2388         else
2389                 vfta &= ~vid_bit;
2390         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2391
2392         /* update local VFTA copy */
2393         shadow_vfta->vfta[vid_idx] = vfta;
2394
2395         return 0;
2396 }
2397
2398 static int
2399 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2400                       enum rte_vlan_type vlan_type,
2401                       uint16_t tpid)
2402 {
2403         struct e1000_hw *hw =
2404                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2405         uint32_t reg, qinq;
2406
2407         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2408         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2409
2410         /* only outer TPID of double VLAN can be configured*/
2411         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2412                 reg = E1000_READ_REG(hw, E1000_VET);
2413                 reg = (reg & (~E1000_VET_VET_EXT)) |
2414                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2415                 E1000_WRITE_REG(hw, E1000_VET, reg);
2416
2417                 return 0;
2418         }
2419
2420         /* all other TPID values are read-only*/
2421         PMD_DRV_LOG(ERR, "Not supported");
2422
2423         return -ENOTSUP;
2424 }
2425
2426 static void
2427 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2428 {
2429         struct e1000_hw *hw =
2430                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2431         uint32_t reg;
2432
2433         /* Filter Table Disable */
2434         reg = E1000_READ_REG(hw, E1000_RCTL);
2435         reg &= ~E1000_RCTL_CFIEN;
2436         reg &= ~E1000_RCTL_VFE;
2437         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2438 }
2439
2440 static void
2441 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2442 {
2443         struct e1000_hw *hw =
2444                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2445         struct e1000_vfta * shadow_vfta =
2446                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2447         uint32_t reg;
2448         int i;
2449
2450         /* Filter Table Enable, CFI not used for packet acceptance */
2451         reg = E1000_READ_REG(hw, E1000_RCTL);
2452         reg &= ~E1000_RCTL_CFIEN;
2453         reg |= E1000_RCTL_VFE;
2454         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2455
2456         /* restore VFTA table */
2457         for (i = 0; i < IGB_VFTA_SIZE; i++)
2458                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2459 }
2460
2461 static void
2462 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2463 {
2464         struct e1000_hw *hw =
2465                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2466         uint32_t reg;
2467
2468         /* VLAN Mode Disable */
2469         reg = E1000_READ_REG(hw, E1000_CTRL);
2470         reg &= ~E1000_CTRL_VME;
2471         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2472 }
2473
2474 static void
2475 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2476 {
2477         struct e1000_hw *hw =
2478                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2479         uint32_t reg;
2480
2481         /* VLAN Mode Enable */
2482         reg = E1000_READ_REG(hw, E1000_CTRL);
2483         reg |= E1000_CTRL_VME;
2484         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2485 }
2486
2487 static void
2488 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2489 {
2490         struct e1000_hw *hw =
2491                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2492         uint32_t reg;
2493
2494         /* CTRL_EXT: Extended VLAN */
2495         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2496         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2497         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2498
2499         /* Update maximum packet length */
2500         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2501                 E1000_WRITE_REG(hw, E1000_RLPML,
2502                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2503                                                 VLAN_TAG_SIZE);
2504 }
2505
2506 static void
2507 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2508 {
2509         struct e1000_hw *hw =
2510                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2511         uint32_t reg;
2512
2513         /* CTRL_EXT: Extended VLAN */
2514         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2515         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2516         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2517
2518         /* Update maximum packet length */
2519         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2520                 E1000_WRITE_REG(hw, E1000_RLPML,
2521                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2522                                                 2 * VLAN_TAG_SIZE);
2523 }
2524
2525 static void
2526 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2527 {
2528         if(mask & ETH_VLAN_STRIP_MASK){
2529                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2530                         igb_vlan_hw_strip_enable(dev);
2531                 else
2532                         igb_vlan_hw_strip_disable(dev);
2533         }
2534
2535         if(mask & ETH_VLAN_FILTER_MASK){
2536                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2537                         igb_vlan_hw_filter_enable(dev);
2538                 else
2539                         igb_vlan_hw_filter_disable(dev);
2540         }
2541
2542         if(mask & ETH_VLAN_EXTEND_MASK){
2543                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2544                         igb_vlan_hw_extend_enable(dev);
2545                 else
2546                         igb_vlan_hw_extend_disable(dev);
2547         }
2548 }
2549
2550
2551 /**
2552  * It enables the interrupt mask and then enable the interrupt.
2553  *
2554  * @param dev
2555  *  Pointer to struct rte_eth_dev.
2556  *
2557  * @return
2558  *  - On success, zero.
2559  *  - On failure, a negative value.
2560  */
2561 static int
2562 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2563 {
2564         struct e1000_interrupt *intr =
2565                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2566
2567         intr->mask |= E1000_ICR_LSC;
2568
2569         return 0;
2570 }
2571
2572 /* It clears the interrupt causes and enables the interrupt.
2573  * It will be called once only during nic initialized.
2574  *
2575  * @param dev
2576  *  Pointer to struct rte_eth_dev.
2577  *
2578  * @return
2579  *  - On success, zero.
2580  *  - On failure, a negative value.
2581  */
2582 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2583 {
2584         uint32_t mask, regval;
2585         struct e1000_hw *hw =
2586                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2587         struct rte_eth_dev_info dev_info;
2588
2589         memset(&dev_info, 0, sizeof(dev_info));
2590         eth_igb_infos_get(dev, &dev_info);
2591
2592         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2593         regval = E1000_READ_REG(hw, E1000_EIMS);
2594         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2595
2596         return 0;
2597 }
2598
2599 /*
2600  * It reads ICR and gets interrupt causes, check it and set a bit flag
2601  * to update link status.
2602  *
2603  * @param dev
2604  *  Pointer to struct rte_eth_dev.
2605  *
2606  * @return
2607  *  - On success, zero.
2608  *  - On failure, a negative value.
2609  */
2610 static int
2611 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2612 {
2613         uint32_t icr;
2614         struct e1000_hw *hw =
2615                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616         struct e1000_interrupt *intr =
2617                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2618
2619         igb_intr_disable(hw);
2620
2621         /* read-on-clear nic registers here */
2622         icr = E1000_READ_REG(hw, E1000_ICR);
2623
2624         intr->flags = 0;
2625         if (icr & E1000_ICR_LSC) {
2626                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2627         }
2628
2629         if (icr & E1000_ICR_VMMB)
2630                 intr->flags |= E1000_FLAG_MAILBOX;
2631
2632         return 0;
2633 }
2634
2635 /*
2636  * It executes link_update after knowing an interrupt is prsent.
2637  *
2638  * @param dev
2639  *  Pointer to struct rte_eth_dev.
2640  *
2641  * @return
2642  *  - On success, zero.
2643  *  - On failure, a negative value.
2644  */
2645 static int
2646 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2647                          struct rte_intr_handle *intr_handle)
2648 {
2649         struct e1000_hw *hw =
2650                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2651         struct e1000_interrupt *intr =
2652                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2653         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
2654         uint32_t tctl, rctl;
2655         struct rte_eth_link link;
2656         int ret;
2657
2658         if (intr->flags & E1000_FLAG_MAILBOX) {
2659                 igb_pf_mbx_process(dev);
2660                 intr->flags &= ~E1000_FLAG_MAILBOX;
2661         }
2662
2663         igb_intr_enable(dev);
2664         rte_intr_enable(intr_handle);
2665
2666         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2667                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2668
2669                 /* set get_link_status to check register later */
2670                 hw->mac.get_link_status = 1;
2671                 ret = eth_igb_link_update(dev, 0);
2672
2673                 /* check if link has changed */
2674                 if (ret < 0)
2675                         return 0;
2676
2677                 memset(&link, 0, sizeof(link));
2678                 rte_igb_dev_atomic_read_link_status(dev, &link);
2679                 if (link.link_status) {
2680                         PMD_INIT_LOG(INFO,
2681                                      " Port %d: Link Up - speed %u Mbps - %s",
2682                                      dev->data->port_id,
2683                                      (unsigned)link.link_speed,
2684                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2685                                      "full-duplex" : "half-duplex");
2686                 } else {
2687                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2688                                      dev->data->port_id);
2689                 }
2690
2691                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2692                              pci_dev->addr.domain,
2693                              pci_dev->addr.bus,
2694                              pci_dev->addr.devid,
2695                              pci_dev->addr.function);
2696                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2697                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2698                 if (link.link_status) {
2699                         /* enable Tx/Rx */
2700                         tctl |= E1000_TCTL_EN;
2701                         rctl |= E1000_RCTL_EN;
2702                 } else {
2703                         /* disable Tx/Rx */
2704                         tctl &= ~E1000_TCTL_EN;
2705                         rctl &= ~E1000_RCTL_EN;
2706                 }
2707                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2708                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2709                 E1000_WRITE_FLUSH(hw);
2710                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2711         }
2712
2713         return 0;
2714 }
2715
2716 /**
2717  * Interrupt handler which shall be registered at first.
2718  *
2719  * @param handle
2720  *  Pointer to interrupt handle.
2721  * @param param
2722  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2723  *
2724  * @return
2725  *  void
2726  */
2727 static void
2728 eth_igb_interrupt_handler(struct rte_intr_handle *handle, void *param)
2729 {
2730         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2731
2732         eth_igb_interrupt_get_status(dev);
2733         eth_igb_interrupt_action(dev, handle);
2734 }
2735
2736 static int
2737 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2738 {
2739         uint32_t eicr;
2740         struct e1000_hw *hw =
2741                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2742         struct e1000_interrupt *intr =
2743                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2744
2745         igbvf_intr_disable(hw);
2746
2747         /* read-on-clear nic registers here */
2748         eicr = E1000_READ_REG(hw, E1000_EICR);
2749         intr->flags = 0;
2750
2751         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2752                 intr->flags |= E1000_FLAG_MAILBOX;
2753
2754         return 0;
2755 }
2756
2757 void igbvf_mbx_process(struct rte_eth_dev *dev)
2758 {
2759         struct e1000_hw *hw =
2760                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2761         struct e1000_mbx_info *mbx = &hw->mbx;
2762         u32 in_msg = 0;
2763
2764         if (mbx->ops.read(hw, &in_msg, 1, 0))
2765                 return;
2766
2767         /* PF reset VF event */
2768         if (in_msg == E1000_PF_CONTROL_MSG)
2769                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2770 }
2771
2772 static int
2773 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2774 {
2775         struct e1000_interrupt *intr =
2776                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2777
2778         if (intr->flags & E1000_FLAG_MAILBOX) {
2779                 igbvf_mbx_process(dev);
2780                 intr->flags &= ~E1000_FLAG_MAILBOX;
2781         }
2782
2783         igbvf_intr_enable(dev);
2784         rte_intr_enable(intr_handle);
2785
2786         return 0;
2787 }
2788
2789 static void
2790 eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
2791                             void *param)
2792 {
2793         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2794
2795         eth_igbvf_interrupt_get_status(dev);
2796         eth_igbvf_interrupt_action(dev, handle);
2797 }
2798
2799 static int
2800 eth_igb_led_on(struct rte_eth_dev *dev)
2801 {
2802         struct e1000_hw *hw;
2803
2804         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2805         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2806 }
2807
2808 static int
2809 eth_igb_led_off(struct rte_eth_dev *dev)
2810 {
2811         struct e1000_hw *hw;
2812
2813         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2814         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2815 }
2816
2817 static int
2818 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2819 {
2820         struct e1000_hw *hw;
2821         uint32_t ctrl;
2822         int tx_pause;
2823         int rx_pause;
2824
2825         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2826         fc_conf->pause_time = hw->fc.pause_time;
2827         fc_conf->high_water = hw->fc.high_water;
2828         fc_conf->low_water = hw->fc.low_water;
2829         fc_conf->send_xon = hw->fc.send_xon;
2830         fc_conf->autoneg = hw->mac.autoneg;
2831
2832         /*
2833          * Return rx_pause and tx_pause status according to actual setting of
2834          * the TFCE and RFCE bits in the CTRL register.
2835          */
2836         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2837         if (ctrl & E1000_CTRL_TFCE)
2838                 tx_pause = 1;
2839         else
2840                 tx_pause = 0;
2841
2842         if (ctrl & E1000_CTRL_RFCE)
2843                 rx_pause = 1;
2844         else
2845                 rx_pause = 0;
2846
2847         if (rx_pause && tx_pause)
2848                 fc_conf->mode = RTE_FC_FULL;
2849         else if (rx_pause)
2850                 fc_conf->mode = RTE_FC_RX_PAUSE;
2851         else if (tx_pause)
2852                 fc_conf->mode = RTE_FC_TX_PAUSE;
2853         else
2854                 fc_conf->mode = RTE_FC_NONE;
2855
2856         return 0;
2857 }
2858
2859 static int
2860 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2861 {
2862         struct e1000_hw *hw;
2863         int err;
2864         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2865                 e1000_fc_none,
2866                 e1000_fc_rx_pause,
2867                 e1000_fc_tx_pause,
2868                 e1000_fc_full
2869         };
2870         uint32_t rx_buf_size;
2871         uint32_t max_high_water;
2872         uint32_t rctl;
2873
2874         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2875         if (fc_conf->autoneg != hw->mac.autoneg)
2876                 return -ENOTSUP;
2877         rx_buf_size = igb_get_rx_buffer_size(hw);
2878         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2879
2880         /* At least reserve one Ethernet frame for watermark */
2881         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2882         if ((fc_conf->high_water > max_high_water) ||
2883             (fc_conf->high_water < fc_conf->low_water)) {
2884                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2885                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2886                 return -EINVAL;
2887         }
2888
2889         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2890         hw->fc.pause_time     = fc_conf->pause_time;
2891         hw->fc.high_water     = fc_conf->high_water;
2892         hw->fc.low_water      = fc_conf->low_water;
2893         hw->fc.send_xon       = fc_conf->send_xon;
2894
2895         err = e1000_setup_link_generic(hw);
2896         if (err == E1000_SUCCESS) {
2897
2898                 /* check if we want to forward MAC frames - driver doesn't have native
2899                  * capability to do that, so we'll write the registers ourselves */
2900
2901                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2902
2903                 /* set or clear MFLCN.PMCF bit depending on configuration */
2904                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2905                         rctl |= E1000_RCTL_PMCF;
2906                 else
2907                         rctl &= ~E1000_RCTL_PMCF;
2908
2909                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2910                 E1000_WRITE_FLUSH(hw);
2911
2912                 return 0;
2913         }
2914
2915         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2916         return -EIO;
2917 }
2918
2919 #define E1000_RAH_POOLSEL_SHIFT      (18)
2920 static void
2921 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2922                 uint32_t index, __rte_unused uint32_t pool)
2923 {
2924         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2925         uint32_t rah;
2926
2927         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2928         rah = E1000_READ_REG(hw, E1000_RAH(index));
2929         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2930         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2931 }
2932
2933 static void
2934 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2935 {
2936         uint8_t addr[ETHER_ADDR_LEN];
2937         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2938
2939         memset(addr, 0, sizeof(addr));
2940
2941         e1000_rar_set(hw, addr, index);
2942 }
2943
2944 static void
2945 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2946                                 struct ether_addr *addr)
2947 {
2948         eth_igb_rar_clear(dev, 0);
2949
2950         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2951 }
2952 /*
2953  * Virtual Function operations
2954  */
2955 static void
2956 igbvf_intr_disable(struct e1000_hw *hw)
2957 {
2958         PMD_INIT_FUNC_TRACE();
2959
2960         /* Clear interrupt mask to stop from interrupts being generated */
2961         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2962
2963         E1000_WRITE_FLUSH(hw);
2964 }
2965
2966 static void
2967 igbvf_stop_adapter(struct rte_eth_dev *dev)
2968 {
2969         u32 reg_val;
2970         u16 i;
2971         struct rte_eth_dev_info dev_info;
2972         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2973
2974         memset(&dev_info, 0, sizeof(dev_info));
2975         eth_igbvf_infos_get(dev, &dev_info);
2976
2977         /* Clear interrupt mask to stop from interrupts being generated */
2978         igbvf_intr_disable(hw);
2979
2980         /* Clear any pending interrupts, flush previous writes */
2981         E1000_READ_REG(hw, E1000_EICR);
2982
2983         /* Disable the transmit unit.  Each queue must be disabled. */
2984         for (i = 0; i < dev_info.max_tx_queues; i++)
2985                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2986
2987         /* Disable the receive unit by stopping each queue */
2988         for (i = 0; i < dev_info.max_rx_queues; i++) {
2989                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2990                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2991                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2992                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2993                         ;
2994         }
2995
2996         /* flush all queues disables */
2997         E1000_WRITE_FLUSH(hw);
2998         msec_delay(2);
2999 }
3000
3001 static int eth_igbvf_link_update(struct e1000_hw *hw)
3002 {
3003         struct e1000_mbx_info *mbx = &hw->mbx;
3004         struct e1000_mac_info *mac = &hw->mac;
3005         int ret_val = E1000_SUCCESS;
3006
3007         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3008
3009         /*
3010          * We only want to run this if there has been a rst asserted.
3011          * in this case that could mean a link change, device reset,
3012          * or a virtual function reset
3013          */
3014
3015         /* If we were hit with a reset or timeout drop the link */
3016         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3017                 mac->get_link_status = TRUE;
3018
3019         if (!mac->get_link_status)
3020                 goto out;
3021
3022         /* if link status is down no point in checking to see if pf is up */
3023         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3024                 goto out;
3025
3026         /* if we passed all the tests above then the link is up and we no
3027          * longer need to check for link */
3028         mac->get_link_status = FALSE;
3029
3030 out:
3031         return ret_val;
3032 }
3033
3034
3035 static int
3036 igbvf_dev_configure(struct rte_eth_dev *dev)
3037 {
3038         struct rte_eth_conf* conf = &dev->data->dev_conf;
3039
3040         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3041                      dev->data->port_id);
3042
3043         /*
3044          * VF has no ability to enable/disable HW CRC
3045          * Keep the persistent behavior the same as Host PF
3046          */
3047 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3048         if (!conf->rxmode.hw_strip_crc) {
3049                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3050                 conf->rxmode.hw_strip_crc = 1;
3051         }
3052 #else
3053         if (conf->rxmode.hw_strip_crc) {
3054                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3055                 conf->rxmode.hw_strip_crc = 0;
3056         }
3057 #endif
3058
3059         return 0;
3060 }
3061
3062 static int
3063 igbvf_dev_start(struct rte_eth_dev *dev)
3064 {
3065         struct e1000_hw *hw =
3066                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3067         struct e1000_adapter *adapter =
3068                 E1000_DEV_PRIVATE(dev->data->dev_private);
3069         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3070         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3071         int ret;
3072         uint32_t intr_vector = 0;
3073
3074         PMD_INIT_FUNC_TRACE();
3075
3076         hw->mac.ops.reset_hw(hw);
3077         adapter->stopped = 0;
3078
3079         /* Set all vfta */
3080         igbvf_set_vfta_all(dev,1);
3081
3082         eth_igbvf_tx_init(dev);
3083
3084         /* This can fail when allocating mbufs for descriptor rings */
3085         ret = eth_igbvf_rx_init(dev);
3086         if (ret) {
3087                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3088                 igb_dev_clear_queues(dev);
3089                 return ret;
3090         }
3091
3092         /* check and configure queue intr-vector mapping */
3093         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3094                 intr_vector = dev->data->nb_rx_queues;
3095                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3096                 if (ret)
3097                         return ret;
3098         }
3099
3100         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3101                 intr_handle->intr_vec =
3102                         rte_zmalloc("intr_vec",
3103                                     dev->data->nb_rx_queues * sizeof(int), 0);
3104                 if (!intr_handle->intr_vec) {
3105                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3106                                      " intr_vec\n", dev->data->nb_rx_queues);
3107                         return -ENOMEM;
3108                 }
3109         }
3110
3111         eth_igbvf_configure_msix_intr(dev);
3112
3113         /* enable uio/vfio intr/eventfd mapping */
3114         rte_intr_enable(intr_handle);
3115
3116         /* resume enabled intr since hw reset */
3117         igbvf_intr_enable(dev);
3118
3119         return 0;
3120 }
3121
3122 static void
3123 igbvf_dev_stop(struct rte_eth_dev *dev)
3124 {
3125         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3126         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3127
3128         PMD_INIT_FUNC_TRACE();
3129
3130         igbvf_stop_adapter(dev);
3131
3132         /*
3133           * Clear what we set, but we still keep shadow_vfta to
3134           * restore after device starts
3135           */
3136         igbvf_set_vfta_all(dev,0);
3137
3138         igb_dev_clear_queues(dev);
3139
3140         /* disable intr eventfd mapping */
3141         rte_intr_disable(intr_handle);
3142
3143         /* Clean datapath event and queue/vec mapping */
3144         rte_intr_efd_disable(intr_handle);
3145         if (intr_handle->intr_vec) {
3146                 rte_free(intr_handle->intr_vec);
3147                 intr_handle->intr_vec = NULL;
3148         }
3149 }
3150
3151 static void
3152 igbvf_dev_close(struct rte_eth_dev *dev)
3153 {
3154         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3155         struct e1000_adapter *adapter =
3156                 E1000_DEV_PRIVATE(dev->data->dev_private);
3157         struct ether_addr addr;
3158
3159         PMD_INIT_FUNC_TRACE();
3160
3161         e1000_reset_hw(hw);
3162
3163         igbvf_dev_stop(dev);
3164         adapter->stopped = 1;
3165         igb_dev_free_queues(dev);
3166
3167         /**
3168          * reprogram the RAR with a zero mac address,
3169          * to ensure that the VF traffic goes to the PF
3170          * after stop, close and detach of the VF.
3171          **/
3172
3173         memset(&addr, 0, sizeof(addr));
3174         igbvf_default_mac_addr_set(dev, &addr);
3175 }
3176
3177 static void
3178 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3179 {
3180         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3181
3182         /* Set both unicast and multicast promisc */
3183         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3184 }
3185
3186 static void
3187 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3188 {
3189         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3190
3191         /* If in allmulticast mode leave multicast promisc */
3192         if (dev->data->all_multicast == 1)
3193                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3194         else
3195                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3196 }
3197
3198 static void
3199 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3200 {
3201         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3202
3203         /* In promiscuous mode multicast promisc already set */
3204         if (dev->data->promiscuous == 0)
3205                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3206 }
3207
3208 static void
3209 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3210 {
3211         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3212
3213         /* In promiscuous mode leave multicast promisc enabled */
3214         if (dev->data->promiscuous == 0)
3215                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3216 }
3217
3218 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3219 {
3220         struct e1000_mbx_info *mbx = &hw->mbx;
3221         uint32_t msgbuf[2];
3222         s32 err;
3223
3224         /* After set vlan, vlan strip will also be enabled in igb driver*/
3225         msgbuf[0] = E1000_VF_SET_VLAN;
3226         msgbuf[1] = vid;
3227         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3228         if (on)
3229                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3230
3231         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3232         if (err)
3233                 goto mbx_err;
3234
3235         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3236         if (err)
3237                 goto mbx_err;
3238
3239         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3240         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3241                 err = -EINVAL;
3242
3243 mbx_err:
3244         return err;
3245 }
3246
3247 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3248 {
3249         struct e1000_hw *hw =
3250                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3251         struct e1000_vfta * shadow_vfta =
3252                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3253         int i = 0, j = 0, vfta = 0, mask = 1;
3254
3255         for (i = 0; i < IGB_VFTA_SIZE; i++){
3256                 vfta = shadow_vfta->vfta[i];
3257                 if(vfta){
3258                         mask = 1;
3259                         for (j = 0; j < 32; j++){
3260                                 if(vfta & mask)
3261                                         igbvf_set_vfta(hw,
3262                                                 (uint16_t)((i<<5)+j), on);
3263                                 mask<<=1;
3264                         }
3265                 }
3266         }
3267
3268 }
3269
3270 static int
3271 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3272 {
3273         struct e1000_hw *hw =
3274                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3275         struct e1000_vfta * shadow_vfta =
3276                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3277         uint32_t vid_idx = 0;
3278         uint32_t vid_bit = 0;
3279         int ret = 0;
3280
3281         PMD_INIT_FUNC_TRACE();
3282
3283         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3284         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3285         if(ret){
3286                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3287                 return ret;
3288         }
3289         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3290         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3291
3292         /*Save what we set and retore it after device reset*/
3293         if (on)
3294                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3295         else
3296                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3297
3298         return 0;
3299 }
3300
3301 static void
3302 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3303 {
3304         struct e1000_hw *hw =
3305                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3306
3307         /* index is not used by rar_set() */
3308         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3309 }
3310
3311
3312 static int
3313 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3314                         struct rte_eth_rss_reta_entry64 *reta_conf,
3315                         uint16_t reta_size)
3316 {
3317         uint8_t i, j, mask;
3318         uint32_t reta, r;
3319         uint16_t idx, shift;
3320         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3321
3322         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3323                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3324                         "(%d) doesn't match the number hardware can supported "
3325                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3326                 return -EINVAL;
3327         }
3328
3329         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3330                 idx = i / RTE_RETA_GROUP_SIZE;
3331                 shift = i % RTE_RETA_GROUP_SIZE;
3332                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3333                                                 IGB_4_BIT_MASK);
3334                 if (!mask)
3335                         continue;
3336                 if (mask == IGB_4_BIT_MASK)
3337                         r = 0;
3338                 else
3339                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3340                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3341                         if (mask & (0x1 << j))
3342                                 reta |= reta_conf[idx].reta[shift + j] <<
3343                                                         (CHAR_BIT * j);
3344                         else
3345                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3346                 }
3347                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3348         }
3349
3350         return 0;
3351 }
3352
3353 static int
3354 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3355                        struct rte_eth_rss_reta_entry64 *reta_conf,
3356                        uint16_t reta_size)
3357 {
3358         uint8_t i, j, mask;
3359         uint32_t reta;
3360         uint16_t idx, shift;
3361         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3362
3363         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3364                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3365                         "(%d) doesn't match the number hardware can supported "
3366                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3367                 return -EINVAL;
3368         }
3369
3370         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3371                 idx = i / RTE_RETA_GROUP_SIZE;
3372                 shift = i % RTE_RETA_GROUP_SIZE;
3373                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3374                                                 IGB_4_BIT_MASK);
3375                 if (!mask)
3376                         continue;
3377                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3378                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3379                         if (mask & (0x1 << j))
3380                                 reta_conf[idx].reta[shift + j] =
3381                                         ((reta >> (CHAR_BIT * j)) &
3382                                                 IGB_8_BIT_MASK);
3383                 }
3384         }
3385
3386         return 0;
3387 }
3388
3389 #define MAC_TYPE_FILTER_SUP(type)    do {\
3390         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3391                 (type) != e1000_82576)\
3392                 return -ENOTSUP;\
3393 } while (0)
3394
3395 static int
3396 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3397                         struct rte_eth_syn_filter *filter,
3398                         bool add)
3399 {
3400         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3401         uint32_t synqf, rfctl;
3402
3403         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3404                 return -EINVAL;
3405
3406         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3407
3408         if (add) {
3409                 if (synqf & E1000_SYN_FILTER_ENABLE)
3410                         return -EINVAL;
3411
3412                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3413                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3414
3415                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3416                 if (filter->hig_pri)
3417                         rfctl |= E1000_RFCTL_SYNQFP;
3418                 else
3419                         rfctl &= ~E1000_RFCTL_SYNQFP;
3420
3421                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3422         } else {
3423                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3424                         return -ENOENT;
3425                 synqf = 0;
3426         }
3427
3428         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3429         E1000_WRITE_FLUSH(hw);
3430         return 0;
3431 }
3432
3433 static int
3434 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3435                         struct rte_eth_syn_filter *filter)
3436 {
3437         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3438         uint32_t synqf, rfctl;
3439
3440         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3441         if (synqf & E1000_SYN_FILTER_ENABLE) {
3442                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3443                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3444                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3445                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3446                 return 0;
3447         }
3448
3449         return -ENOENT;
3450 }
3451
3452 static int
3453 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3454                         enum rte_filter_op filter_op,
3455                         void *arg)
3456 {
3457         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3458         int ret;
3459
3460         MAC_TYPE_FILTER_SUP(hw->mac.type);
3461
3462         if (filter_op == RTE_ETH_FILTER_NOP)
3463                 return 0;
3464
3465         if (arg == NULL) {
3466                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3467                             filter_op);
3468                 return -EINVAL;
3469         }
3470
3471         switch (filter_op) {
3472         case RTE_ETH_FILTER_ADD:
3473                 ret = eth_igb_syn_filter_set(dev,
3474                                 (struct rte_eth_syn_filter *)arg,
3475                                 TRUE);
3476                 break;
3477         case RTE_ETH_FILTER_DELETE:
3478                 ret = eth_igb_syn_filter_set(dev,
3479                                 (struct rte_eth_syn_filter *)arg,
3480                                 FALSE);
3481                 break;
3482         case RTE_ETH_FILTER_GET:
3483                 ret = eth_igb_syn_filter_get(dev,
3484                                 (struct rte_eth_syn_filter *)arg);
3485                 break;
3486         default:
3487                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3488                 ret = -EINVAL;
3489                 break;
3490         }
3491
3492         return ret;
3493 }
3494
3495 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3496         if ((type) != e1000_82580 && (type) != e1000_i350)\
3497                 return -ENOSYS; \
3498 } while (0)
3499
3500 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3501 static inline int
3502 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3503                         struct e1000_2tuple_filter_info *filter_info)
3504 {
3505         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3506                 return -EINVAL;
3507         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3508                 return -EINVAL;  /* filter index is out of range. */
3509         if (filter->tcp_flags > TCP_FLAG_ALL)
3510                 return -EINVAL;  /* flags is invalid. */
3511
3512         switch (filter->dst_port_mask) {
3513         case UINT16_MAX:
3514                 filter_info->dst_port_mask = 0;
3515                 filter_info->dst_port = filter->dst_port;
3516                 break;
3517         case 0:
3518                 filter_info->dst_port_mask = 1;
3519                 break;
3520         default:
3521                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3522                 return -EINVAL;
3523         }
3524
3525         switch (filter->proto_mask) {
3526         case UINT8_MAX:
3527                 filter_info->proto_mask = 0;
3528                 filter_info->proto = filter->proto;
3529                 break;
3530         case 0:
3531                 filter_info->proto_mask = 1;
3532                 break;
3533         default:
3534                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3535                 return -EINVAL;
3536         }
3537
3538         filter_info->priority = (uint8_t)filter->priority;
3539         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3540                 filter_info->tcp_flags = filter->tcp_flags;
3541         else
3542                 filter_info->tcp_flags = 0;
3543
3544         return 0;
3545 }
3546
3547 static inline struct e1000_2tuple_filter *
3548 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3549                         struct e1000_2tuple_filter_info *key)
3550 {
3551         struct e1000_2tuple_filter *it;
3552
3553         TAILQ_FOREACH(it, filter_list, entries) {
3554                 if (memcmp(key, &it->filter_info,
3555                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3556                         return it;
3557                 }
3558         }
3559         return NULL;
3560 }
3561
3562 /*
3563  * igb_add_2tuple_filter - add a 2tuple filter
3564  *
3565  * @param
3566  * dev: Pointer to struct rte_eth_dev.
3567  * ntuple_filter: ponter to the filter that will be added.
3568  *
3569  * @return
3570  *    - On success, zero.
3571  *    - On failure, a negative value.
3572  */
3573 static int
3574 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3575                         struct rte_eth_ntuple_filter *ntuple_filter)
3576 {
3577         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3578         struct e1000_filter_info *filter_info =
3579                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3580         struct e1000_2tuple_filter *filter;
3581         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3582         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3583         int i, ret;
3584
3585         filter = rte_zmalloc("e1000_2tuple_filter",
3586                         sizeof(struct e1000_2tuple_filter), 0);
3587         if (filter == NULL)
3588                 return -ENOMEM;
3589
3590         ret = ntuple_filter_to_2tuple(ntuple_filter,
3591                                       &filter->filter_info);
3592         if (ret < 0) {
3593                 rte_free(filter);
3594                 return ret;
3595         }
3596         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3597                                          &filter->filter_info) != NULL) {
3598                 PMD_DRV_LOG(ERR, "filter exists.");
3599                 rte_free(filter);
3600                 return -EEXIST;
3601         }
3602         filter->queue = ntuple_filter->queue;
3603
3604         /*
3605          * look for an unused 2tuple filter index,
3606          * and insert the filter to list.
3607          */
3608         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3609                 if (!(filter_info->twotuple_mask & (1 << i))) {
3610                         filter_info->twotuple_mask |= 1 << i;
3611                         filter->index = i;
3612                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3613                                           filter,
3614                                           entries);
3615                         break;
3616                 }
3617         }
3618         if (i >= E1000_MAX_TTQF_FILTERS) {
3619                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3620                 rte_free(filter);
3621                 return -ENOSYS;
3622         }
3623
3624         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3625         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3626                 imir |= E1000_IMIR_PORT_BP;
3627         else
3628                 imir &= ~E1000_IMIR_PORT_BP;
3629
3630         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3631
3632         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3633         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3634         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3635         if (filter->filter_info.proto_mask == 0)
3636                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3637
3638         /* tcp flags bits setting. */
3639         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3640                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3641                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3642                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3643                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3644                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3645                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3646                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3647                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3648                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3649                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3650                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3651                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3652         } else
3653                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3654         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3655         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3656         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3657         return 0;
3658 }
3659
3660 /*
3661  * igb_remove_2tuple_filter - remove a 2tuple filter
3662  *
3663  * @param
3664  * dev: Pointer to struct rte_eth_dev.
3665  * ntuple_filter: ponter to the filter that will be removed.
3666  *
3667  * @return
3668  *    - On success, zero.
3669  *    - On failure, a negative value.
3670  */
3671 static int
3672 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3673                         struct rte_eth_ntuple_filter *ntuple_filter)
3674 {
3675         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3676         struct e1000_filter_info *filter_info =
3677                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3678         struct e1000_2tuple_filter_info filter_2tuple;
3679         struct e1000_2tuple_filter *filter;
3680         int ret;
3681
3682         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3683         ret = ntuple_filter_to_2tuple(ntuple_filter,
3684                                       &filter_2tuple);
3685         if (ret < 0)
3686                 return ret;
3687
3688         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3689                                          &filter_2tuple);
3690         if (filter == NULL) {
3691                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3692                 return -ENOENT;
3693         }
3694
3695         filter_info->twotuple_mask &= ~(1 << filter->index);
3696         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3697         rte_free(filter);
3698
3699         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3700         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3701         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3702         return 0;
3703 }
3704
3705 static inline struct e1000_flex_filter *
3706 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3707                         struct e1000_flex_filter_info *key)
3708 {
3709         struct e1000_flex_filter *it;
3710
3711         TAILQ_FOREACH(it, filter_list, entries) {
3712                 if (memcmp(key, &it->filter_info,
3713                         sizeof(struct e1000_flex_filter_info)) == 0)
3714                         return it;
3715         }
3716
3717         return NULL;
3718 }
3719
3720 static int
3721 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3722                         struct rte_eth_flex_filter *filter,
3723                         bool add)
3724 {
3725         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3726         struct e1000_filter_info *filter_info =
3727                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3728         struct e1000_flex_filter *flex_filter, *it;
3729         uint32_t wufc, queueing, mask;
3730         uint32_t reg_off;
3731         uint8_t shift, i, j = 0;
3732
3733         flex_filter = rte_zmalloc("e1000_flex_filter",
3734                         sizeof(struct e1000_flex_filter), 0);
3735         if (flex_filter == NULL)
3736                 return -ENOMEM;
3737
3738         flex_filter->filter_info.len = filter->len;
3739         flex_filter->filter_info.priority = filter->priority;
3740         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3741         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3742                 mask = 0;
3743                 /* reverse bits in flex filter's mask*/
3744                 for (shift = 0; shift < CHAR_BIT; shift++) {
3745                         if (filter->mask[i] & (0x01 << shift))
3746                                 mask |= (0x80 >> shift);
3747                 }
3748                 flex_filter->filter_info.mask[i] = mask;
3749         }
3750
3751         wufc = E1000_READ_REG(hw, E1000_WUFC);
3752         if (flex_filter->index < E1000_MAX_FHFT)
3753                 reg_off = E1000_FHFT(flex_filter->index);
3754         else
3755                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3756
3757         if (add) {
3758                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3759                                 &flex_filter->filter_info) != NULL) {
3760                         PMD_DRV_LOG(ERR, "filter exists.");
3761                         rte_free(flex_filter);
3762                         return -EEXIST;
3763                 }
3764                 flex_filter->queue = filter->queue;
3765                 /*
3766                  * look for an unused flex filter index
3767                  * and insert the filter into the list.
3768                  */
3769                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3770                         if (!(filter_info->flex_mask & (1 << i))) {
3771                                 filter_info->flex_mask |= 1 << i;
3772                                 flex_filter->index = i;
3773                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3774                                         flex_filter,
3775                                         entries);
3776                                 break;
3777                         }
3778                 }
3779                 if (i >= E1000_MAX_FLEX_FILTERS) {
3780                         PMD_DRV_LOG(ERR, "flex filters are full.");
3781                         rte_free(flex_filter);
3782                         return -ENOSYS;
3783                 }
3784
3785                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3786                                 (E1000_WUFC_FLX0 << flex_filter->index));
3787                 queueing = filter->len |
3788                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3789                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3790                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3791                                 queueing);
3792                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3793                         E1000_WRITE_REG(hw, reg_off,
3794                                         flex_filter->filter_info.dwords[j]);
3795                         reg_off += sizeof(uint32_t);
3796                         E1000_WRITE_REG(hw, reg_off,
3797                                         flex_filter->filter_info.dwords[++j]);
3798                         reg_off += sizeof(uint32_t);
3799                         E1000_WRITE_REG(hw, reg_off,
3800                                 (uint32_t)flex_filter->filter_info.mask[i]);
3801                         reg_off += sizeof(uint32_t) * 2;
3802                         ++j;
3803                 }
3804         } else {
3805                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3806                                 &flex_filter->filter_info);
3807                 if (it == NULL) {
3808                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3809                         rte_free(flex_filter);
3810                         return -ENOENT;
3811                 }
3812
3813                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3814                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3815                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3816                         (~(E1000_WUFC_FLX0 << it->index)));
3817
3818                 filter_info->flex_mask &= ~(1 << it->index);
3819                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3820                 rte_free(it);
3821                 rte_free(flex_filter);
3822         }
3823
3824         return 0;
3825 }
3826
3827 static int
3828 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3829                         struct rte_eth_flex_filter *filter)
3830 {
3831         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3832         struct e1000_filter_info *filter_info =
3833                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3834         struct e1000_flex_filter flex_filter, *it;
3835         uint32_t wufc, queueing, wufc_en = 0;
3836
3837         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3838         flex_filter.filter_info.len = filter->len;
3839         flex_filter.filter_info.priority = filter->priority;
3840         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3841         memcpy(flex_filter.filter_info.mask, filter->mask,
3842                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3843
3844         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3845                                 &flex_filter.filter_info);
3846         if (it == NULL) {
3847                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3848                 return -ENOENT;
3849         }
3850
3851         wufc = E1000_READ_REG(hw, E1000_WUFC);
3852         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3853
3854         if ((wufc & wufc_en) == wufc_en) {
3855                 uint32_t reg_off = 0;
3856                 if (it->index < E1000_MAX_FHFT)
3857                         reg_off = E1000_FHFT(it->index);
3858                 else
3859                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3860
3861                 queueing = E1000_READ_REG(hw,
3862                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3863                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3864                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3865                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3866                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3867                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3868                 return 0;
3869         }
3870         return -ENOENT;
3871 }
3872
3873 static int
3874 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3875                         enum rte_filter_op filter_op,
3876                         void *arg)
3877 {
3878         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3879         struct rte_eth_flex_filter *filter;
3880         int ret = 0;
3881
3882         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3883
3884         if (filter_op == RTE_ETH_FILTER_NOP)
3885                 return ret;
3886
3887         if (arg == NULL) {
3888                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3889                             filter_op);
3890                 return -EINVAL;
3891         }
3892
3893         filter = (struct rte_eth_flex_filter *)arg;
3894         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3895             || filter->len % sizeof(uint64_t) != 0) {
3896                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3897                 return -EINVAL;
3898         }
3899         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3900                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3901                 return -EINVAL;
3902         }
3903
3904         switch (filter_op) {
3905         case RTE_ETH_FILTER_ADD:
3906                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3907                 break;
3908         case RTE_ETH_FILTER_DELETE:
3909                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3910                 break;
3911         case RTE_ETH_FILTER_GET:
3912                 ret = eth_igb_get_flex_filter(dev, filter);
3913                 break;
3914         default:
3915                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3916                 ret = -EINVAL;
3917                 break;
3918         }
3919
3920         return ret;
3921 }
3922
3923 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3924 static inline int
3925 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3926                         struct e1000_5tuple_filter_info *filter_info)
3927 {
3928         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3929                 return -EINVAL;
3930         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3931                 return -EINVAL;  /* filter index is out of range. */
3932         if (filter->tcp_flags > TCP_FLAG_ALL)
3933                 return -EINVAL;  /* flags is invalid. */
3934
3935         switch (filter->dst_ip_mask) {
3936         case UINT32_MAX:
3937                 filter_info->dst_ip_mask = 0;
3938                 filter_info->dst_ip = filter->dst_ip;
3939                 break;
3940         case 0:
3941                 filter_info->dst_ip_mask = 1;
3942                 break;
3943         default:
3944                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3945                 return -EINVAL;
3946         }
3947
3948         switch (filter->src_ip_mask) {
3949         case UINT32_MAX:
3950                 filter_info->src_ip_mask = 0;
3951                 filter_info->src_ip = filter->src_ip;
3952                 break;
3953         case 0:
3954                 filter_info->src_ip_mask = 1;
3955                 break;
3956         default:
3957                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3958                 return -EINVAL;
3959         }
3960
3961         switch (filter->dst_port_mask) {
3962         case UINT16_MAX:
3963                 filter_info->dst_port_mask = 0;
3964                 filter_info->dst_port = filter->dst_port;
3965                 break;
3966         case 0:
3967                 filter_info->dst_port_mask = 1;
3968                 break;
3969         default:
3970                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3971                 return -EINVAL;
3972         }
3973
3974         switch (filter->src_port_mask) {
3975         case UINT16_MAX:
3976                 filter_info->src_port_mask = 0;
3977                 filter_info->src_port = filter->src_port;
3978                 break;
3979         case 0:
3980                 filter_info->src_port_mask = 1;
3981                 break;
3982         default:
3983                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3984                 return -EINVAL;
3985         }
3986
3987         switch (filter->proto_mask) {
3988         case UINT8_MAX:
3989                 filter_info->proto_mask = 0;
3990                 filter_info->proto = filter->proto;
3991                 break;
3992         case 0:
3993                 filter_info->proto_mask = 1;
3994                 break;
3995         default:
3996                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3997                 return -EINVAL;
3998         }
3999
4000         filter_info->priority = (uint8_t)filter->priority;
4001         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4002                 filter_info->tcp_flags = filter->tcp_flags;
4003         else
4004                 filter_info->tcp_flags = 0;
4005
4006         return 0;
4007 }
4008
4009 static inline struct e1000_5tuple_filter *
4010 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4011                         struct e1000_5tuple_filter_info *key)
4012 {
4013         struct e1000_5tuple_filter *it;
4014
4015         TAILQ_FOREACH(it, filter_list, entries) {
4016                 if (memcmp(key, &it->filter_info,
4017                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4018                         return it;
4019                 }
4020         }
4021         return NULL;
4022 }
4023
4024 /*
4025  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4026  *
4027  * @param
4028  * dev: Pointer to struct rte_eth_dev.
4029  * ntuple_filter: ponter to the filter that will be added.
4030  *
4031  * @return
4032  *    - On success, zero.
4033  *    - On failure, a negative value.
4034  */
4035 static int
4036 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4037                         struct rte_eth_ntuple_filter *ntuple_filter)
4038 {
4039         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4040         struct e1000_filter_info *filter_info =
4041                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4042         struct e1000_5tuple_filter *filter;
4043         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4044         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4045         uint8_t i;
4046         int ret;
4047
4048         filter = rte_zmalloc("e1000_5tuple_filter",
4049                         sizeof(struct e1000_5tuple_filter), 0);
4050         if (filter == NULL)
4051                 return -ENOMEM;
4052
4053         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4054                                             &filter->filter_info);
4055         if (ret < 0) {
4056                 rte_free(filter);
4057                 return ret;
4058         }
4059
4060         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4061                                          &filter->filter_info) != NULL) {
4062                 PMD_DRV_LOG(ERR, "filter exists.");
4063                 rte_free(filter);
4064                 return -EEXIST;
4065         }
4066         filter->queue = ntuple_filter->queue;
4067
4068         /*
4069          * look for an unused 5tuple filter index,
4070          * and insert the filter to list.
4071          */
4072         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4073                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4074                         filter_info->fivetuple_mask |= 1 << i;
4075                         filter->index = i;
4076                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4077                                           filter,
4078                                           entries);
4079                         break;
4080                 }
4081         }
4082         if (i >= E1000_MAX_FTQF_FILTERS) {
4083                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4084                 rte_free(filter);
4085                 return -ENOSYS;
4086         }
4087
4088         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4089         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4090                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4091         if (filter->filter_info.dst_ip_mask == 0)
4092                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4093         if (filter->filter_info.src_port_mask == 0)
4094                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4095         if (filter->filter_info.proto_mask == 0)
4096                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4097         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4098                 E1000_FTQF_QUEUE_MASK;
4099         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4100         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4101         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4102         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4103
4104         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4105         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4106
4107         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4108         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4109                 imir |= E1000_IMIR_PORT_BP;
4110         else
4111                 imir &= ~E1000_IMIR_PORT_BP;
4112         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4113
4114         /* tcp flags bits setting. */
4115         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4116                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4117                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4118                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4119                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4120                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4121                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4122                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4123                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4124                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4125                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4126                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4127                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4128         } else
4129                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4130         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4131         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4132         return 0;
4133 }
4134
4135 /*
4136  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4137  *
4138  * @param
4139  * dev: Pointer to struct rte_eth_dev.
4140  * ntuple_filter: ponter to the filter that will be removed.
4141  *
4142  * @return
4143  *    - On success, zero.
4144  *    - On failure, a negative value.
4145  */
4146 static int
4147 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4148                                 struct rte_eth_ntuple_filter *ntuple_filter)
4149 {
4150         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4151         struct e1000_filter_info *filter_info =
4152                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4153         struct e1000_5tuple_filter_info filter_5tuple;
4154         struct e1000_5tuple_filter *filter;
4155         int ret;
4156
4157         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4158         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4159                                             &filter_5tuple);
4160         if (ret < 0)
4161                 return ret;
4162
4163         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4164                                          &filter_5tuple);
4165         if (filter == NULL) {
4166                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4167                 return -ENOENT;
4168         }
4169
4170         filter_info->fivetuple_mask &= ~(1 << filter->index);
4171         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4172         rte_free(filter);
4173
4174         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4175                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4176         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4177         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4178         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4179         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4180         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4181         return 0;
4182 }
4183
4184 static int
4185 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4186 {
4187         uint32_t rctl;
4188         struct e1000_hw *hw;
4189         struct rte_eth_dev_info dev_info;
4190         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4191                                      VLAN_TAG_SIZE);
4192
4193         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4194
4195 #ifdef RTE_LIBRTE_82571_SUPPORT
4196         /* XXX: not bigger than max_rx_pktlen */
4197         if (hw->mac.type == e1000_82571)
4198                 return -ENOTSUP;
4199 #endif
4200         eth_igb_infos_get(dev, &dev_info);
4201
4202         /* check that mtu is within the allowed range */
4203         if ((mtu < ETHER_MIN_MTU) ||
4204             (frame_size > dev_info.max_rx_pktlen))
4205                 return -EINVAL;
4206
4207         /* refuse mtu that requires the support of scattered packets when this
4208          * feature has not been enabled before. */
4209         if (!dev->data->scattered_rx &&
4210             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4211                 return -EINVAL;
4212
4213         rctl = E1000_READ_REG(hw, E1000_RCTL);
4214
4215         /* switch to jumbo mode if needed */
4216         if (frame_size > ETHER_MAX_LEN) {
4217                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4218                 rctl |= E1000_RCTL_LPE;
4219         } else {
4220                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4221                 rctl &= ~E1000_RCTL_LPE;
4222         }
4223         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4224
4225         /* update max frame size */
4226         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4227
4228         E1000_WRITE_REG(hw, E1000_RLPML,
4229                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4230
4231         return 0;
4232 }
4233
4234 /*
4235  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4236  *
4237  * @param
4238  * dev: Pointer to struct rte_eth_dev.
4239  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4240  * add: if true, add filter, if false, remove filter
4241  *
4242  * @return
4243  *    - On success, zero.
4244  *    - On failure, a negative value.
4245  */
4246 static int
4247 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4248                         struct rte_eth_ntuple_filter *ntuple_filter,
4249                         bool add)
4250 {
4251         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4252         int ret;
4253
4254         switch (ntuple_filter->flags) {
4255         case RTE_5TUPLE_FLAGS:
4256         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4257                 if (hw->mac.type != e1000_82576)
4258                         return -ENOTSUP;
4259                 if (add)
4260                         ret = igb_add_5tuple_filter_82576(dev,
4261                                                           ntuple_filter);
4262                 else
4263                         ret = igb_remove_5tuple_filter_82576(dev,
4264                                                              ntuple_filter);
4265                 break;
4266         case RTE_2TUPLE_FLAGS:
4267         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4268                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4269                         return -ENOTSUP;
4270                 if (add)
4271                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4272                 else
4273                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4274                 break;
4275         default:
4276                 ret = -EINVAL;
4277                 break;
4278         }
4279
4280         return ret;
4281 }
4282
4283 /*
4284  * igb_get_ntuple_filter - get a ntuple filter
4285  *
4286  * @param
4287  * dev: Pointer to struct rte_eth_dev.
4288  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4289  *
4290  * @return
4291  *    - On success, zero.
4292  *    - On failure, a negative value.
4293  */
4294 static int
4295 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4296                         struct rte_eth_ntuple_filter *ntuple_filter)
4297 {
4298         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4299         struct e1000_filter_info *filter_info =
4300                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4301         struct e1000_5tuple_filter_info filter_5tuple;
4302         struct e1000_2tuple_filter_info filter_2tuple;
4303         struct e1000_5tuple_filter *p_5tuple_filter;
4304         struct e1000_2tuple_filter *p_2tuple_filter;
4305         int ret;
4306
4307         switch (ntuple_filter->flags) {
4308         case RTE_5TUPLE_FLAGS:
4309         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4310                 if (hw->mac.type != e1000_82576)
4311                         return -ENOTSUP;
4312                 memset(&filter_5tuple,
4313                         0,
4314                         sizeof(struct e1000_5tuple_filter_info));
4315                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4316                                                     &filter_5tuple);
4317                 if (ret < 0)
4318                         return ret;
4319                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4320                                         &filter_info->fivetuple_list,
4321                                         &filter_5tuple);
4322                 if (p_5tuple_filter == NULL) {
4323                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4324                         return -ENOENT;
4325                 }
4326                 ntuple_filter->queue = p_5tuple_filter->queue;
4327                 break;
4328         case RTE_2TUPLE_FLAGS:
4329         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4330                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4331                         return -ENOTSUP;
4332                 memset(&filter_2tuple,
4333                         0,
4334                         sizeof(struct e1000_2tuple_filter_info));
4335                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4336                 if (ret < 0)
4337                         return ret;
4338                 p_2tuple_filter = igb_2tuple_filter_lookup(
4339                                         &filter_info->twotuple_list,
4340                                         &filter_2tuple);
4341                 if (p_2tuple_filter == NULL) {
4342                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4343                         return -ENOENT;
4344                 }
4345                 ntuple_filter->queue = p_2tuple_filter->queue;
4346                 break;
4347         default:
4348                 ret = -EINVAL;
4349                 break;
4350         }
4351
4352         return 0;
4353 }
4354
4355 /*
4356  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4357  * @dev: pointer to rte_eth_dev structure
4358  * @filter_op:operation will be taken.
4359  * @arg: a pointer to specific structure corresponding to the filter_op
4360  */
4361 static int
4362 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4363                                 enum rte_filter_op filter_op,
4364                                 void *arg)
4365 {
4366         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4367         int ret;
4368
4369         MAC_TYPE_FILTER_SUP(hw->mac.type);
4370
4371         if (filter_op == RTE_ETH_FILTER_NOP)
4372                 return 0;
4373
4374         if (arg == NULL) {
4375                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4376                             filter_op);
4377                 return -EINVAL;
4378         }
4379
4380         switch (filter_op) {
4381         case RTE_ETH_FILTER_ADD:
4382                 ret = igb_add_del_ntuple_filter(dev,
4383                         (struct rte_eth_ntuple_filter *)arg,
4384                         TRUE);
4385                 break;
4386         case RTE_ETH_FILTER_DELETE:
4387                 ret = igb_add_del_ntuple_filter(dev,
4388                         (struct rte_eth_ntuple_filter *)arg,
4389                         FALSE);
4390                 break;
4391         case RTE_ETH_FILTER_GET:
4392                 ret = igb_get_ntuple_filter(dev,
4393                         (struct rte_eth_ntuple_filter *)arg);
4394                 break;
4395         default:
4396                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4397                 ret = -EINVAL;
4398                 break;
4399         }
4400         return ret;
4401 }
4402
4403 static inline int
4404 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4405                         uint16_t ethertype)
4406 {
4407         int i;
4408
4409         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4410                 if (filter_info->ethertype_filters[i] == ethertype &&
4411                     (filter_info->ethertype_mask & (1 << i)))
4412                         return i;
4413         }
4414         return -1;
4415 }
4416
4417 static inline int
4418 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4419                         uint16_t ethertype)
4420 {
4421         int i;
4422
4423         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4424                 if (!(filter_info->ethertype_mask & (1 << i))) {
4425                         filter_info->ethertype_mask |= 1 << i;
4426                         filter_info->ethertype_filters[i] = ethertype;
4427                         return i;
4428                 }
4429         }
4430         return -1;
4431 }
4432
4433 static inline int
4434 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4435                         uint8_t idx)
4436 {
4437         if (idx >= E1000_MAX_ETQF_FILTERS)
4438                 return -1;
4439         filter_info->ethertype_mask &= ~(1 << idx);
4440         filter_info->ethertype_filters[idx] = 0;
4441         return idx;
4442 }
4443
4444
4445 static int
4446 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4447                         struct rte_eth_ethertype_filter *filter,
4448                         bool add)
4449 {
4450         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4451         struct e1000_filter_info *filter_info =
4452                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4453         uint32_t etqf = 0;
4454         int ret;
4455
4456         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4457                 filter->ether_type == ETHER_TYPE_IPv6) {
4458                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4459                         " ethertype filter.", filter->ether_type);
4460                 return -EINVAL;
4461         }
4462
4463         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4464                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4465                 return -EINVAL;
4466         }
4467         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4468                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4469                 return -EINVAL;
4470         }
4471
4472         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4473         if (ret >= 0 && add) {
4474                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4475                             filter->ether_type);
4476                 return -EEXIST;
4477         }
4478         if (ret < 0 && !add) {
4479                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4480                             filter->ether_type);
4481                 return -ENOENT;
4482         }
4483
4484         if (add) {
4485                 ret = igb_ethertype_filter_insert(filter_info,
4486                         filter->ether_type);
4487                 if (ret < 0) {
4488                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4489                         return -ENOSYS;
4490                 }
4491
4492                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4493                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4494                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4495         } else {
4496                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4497                 if (ret < 0)
4498                         return -ENOSYS;
4499         }
4500         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4501         E1000_WRITE_FLUSH(hw);
4502
4503         return 0;
4504 }
4505
4506 static int
4507 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4508                         struct rte_eth_ethertype_filter *filter)
4509 {
4510         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4511         struct e1000_filter_info *filter_info =
4512                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4513         uint32_t etqf;
4514         int ret;
4515
4516         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4517         if (ret < 0) {
4518                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4519                             filter->ether_type);
4520                 return -ENOENT;
4521         }
4522
4523         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4524         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4525                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4526                 filter->flags = 0;
4527                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4528                                 E1000_ETQF_QUEUE_SHIFT;
4529                 return 0;
4530         }
4531
4532         return -ENOENT;
4533 }
4534
4535 /*
4536  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4537  * @dev: pointer to rte_eth_dev structure
4538  * @filter_op:operation will be taken.
4539  * @arg: a pointer to specific structure corresponding to the filter_op
4540  */
4541 static int
4542 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4543                                 enum rte_filter_op filter_op,
4544                                 void *arg)
4545 {
4546         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4547         int ret;
4548
4549         MAC_TYPE_FILTER_SUP(hw->mac.type);
4550
4551         if (filter_op == RTE_ETH_FILTER_NOP)
4552                 return 0;
4553
4554         if (arg == NULL) {
4555                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4556                             filter_op);
4557                 return -EINVAL;
4558         }
4559
4560         switch (filter_op) {
4561         case RTE_ETH_FILTER_ADD:
4562                 ret = igb_add_del_ethertype_filter(dev,
4563                         (struct rte_eth_ethertype_filter *)arg,
4564                         TRUE);
4565                 break;
4566         case RTE_ETH_FILTER_DELETE:
4567                 ret = igb_add_del_ethertype_filter(dev,
4568                         (struct rte_eth_ethertype_filter *)arg,
4569                         FALSE);
4570                 break;
4571         case RTE_ETH_FILTER_GET:
4572                 ret = igb_get_ethertype_filter(dev,
4573                         (struct rte_eth_ethertype_filter *)arg);
4574                 break;
4575         default:
4576                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4577                 ret = -EINVAL;
4578                 break;
4579         }
4580         return ret;
4581 }
4582
4583 static int
4584 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4585                      enum rte_filter_type filter_type,
4586                      enum rte_filter_op filter_op,
4587                      void *arg)
4588 {
4589         int ret = -EINVAL;
4590
4591         switch (filter_type) {
4592         case RTE_ETH_FILTER_NTUPLE:
4593                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4594                 break;
4595         case RTE_ETH_FILTER_ETHERTYPE:
4596                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4597                 break;
4598         case RTE_ETH_FILTER_SYN:
4599                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4600                 break;
4601         case RTE_ETH_FILTER_FLEXIBLE:
4602                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4603                 break;
4604         default:
4605                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4606                                                         filter_type);
4607                 break;
4608         }
4609
4610         return ret;
4611 }
4612
4613 static int
4614 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4615                          struct ether_addr *mc_addr_set,
4616                          uint32_t nb_mc_addr)
4617 {
4618         struct e1000_hw *hw;
4619
4620         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4621         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4622         return 0;
4623 }
4624
4625 static uint64_t
4626 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4627 {
4628         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4629         uint64_t systime_cycles;
4630
4631         switch (hw->mac.type) {
4632         case e1000_i210:
4633         case e1000_i211:
4634                 /*
4635                  * Need to read System Time Residue Register to be able
4636                  * to read the other two registers.
4637                  */
4638                 E1000_READ_REG(hw, E1000_SYSTIMR);
4639                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4640                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4641                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4642                                 * NSEC_PER_SEC;
4643                 break;
4644         case e1000_82580:
4645         case e1000_i350:
4646         case e1000_i354:
4647                 /*
4648                  * Need to read System Time Residue Register to be able
4649                  * to read the other two registers.
4650                  */
4651                 E1000_READ_REG(hw, E1000_SYSTIMR);
4652                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4653                 /* Only the 8 LSB are valid. */
4654                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4655                                 & 0xff) << 32;
4656                 break;
4657         default:
4658                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4659                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4660                                 << 32;
4661                 break;
4662         }
4663
4664         return systime_cycles;
4665 }
4666
4667 static uint64_t
4668 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4669 {
4670         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4671         uint64_t rx_tstamp_cycles;
4672
4673         switch (hw->mac.type) {
4674         case e1000_i210:
4675         case e1000_i211:
4676                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4677                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4678                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4679                                 * NSEC_PER_SEC;
4680                 break;
4681         case e1000_82580:
4682         case e1000_i350:
4683         case e1000_i354:
4684                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4685                 /* Only the 8 LSB are valid. */
4686                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4687                                 & 0xff) << 32;
4688                 break;
4689         default:
4690                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4691                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4692                                 << 32;
4693                 break;
4694         }
4695
4696         return rx_tstamp_cycles;
4697 }
4698
4699 static uint64_t
4700 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4701 {
4702         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4703         uint64_t tx_tstamp_cycles;
4704
4705         switch (hw->mac.type) {
4706         case e1000_i210:
4707         case e1000_i211:
4708                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4709                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4710                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4711                                 * NSEC_PER_SEC;
4712                 break;
4713         case e1000_82580:
4714         case e1000_i350:
4715         case e1000_i354:
4716                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4717                 /* Only the 8 LSB are valid. */
4718                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4719                                 & 0xff) << 32;
4720                 break;
4721         default:
4722                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4723                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4724                                 << 32;
4725                 break;
4726         }
4727
4728         return tx_tstamp_cycles;
4729 }
4730
4731 static void
4732 igb_start_timecounters(struct rte_eth_dev *dev)
4733 {
4734         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4735         struct e1000_adapter *adapter =
4736                 (struct e1000_adapter *)dev->data->dev_private;
4737         uint32_t incval = 1;
4738         uint32_t shift = 0;
4739         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4740
4741         switch (hw->mac.type) {
4742         case e1000_82580:
4743         case e1000_i350:
4744         case e1000_i354:
4745                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4746                 mask = (1ULL << 40) - 1;
4747                 /* fall-through */
4748         case e1000_i210:
4749         case e1000_i211:
4750                 /*
4751                  * Start incrementing the register
4752                  * used to timestamp PTP packets.
4753                  */
4754                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4755                 break;
4756         case e1000_82576:
4757                 incval = E1000_INCVALUE_82576;
4758                 shift = IGB_82576_TSYNC_SHIFT;
4759                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4760                                 E1000_INCPERIOD_82576 | incval);
4761                 break;
4762         default:
4763                 /* Not supported */
4764                 return;
4765         }
4766
4767         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4768         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4769         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4770
4771         adapter->systime_tc.cc_mask = mask;
4772         adapter->systime_tc.cc_shift = shift;
4773         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4774
4775         adapter->rx_tstamp_tc.cc_mask = mask;
4776         adapter->rx_tstamp_tc.cc_shift = shift;
4777         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4778
4779         adapter->tx_tstamp_tc.cc_mask = mask;
4780         adapter->tx_tstamp_tc.cc_shift = shift;
4781         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4782 }
4783
4784 static int
4785 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4786 {
4787         struct e1000_adapter *adapter =
4788                         (struct e1000_adapter *)dev->data->dev_private;
4789
4790         adapter->systime_tc.nsec += delta;
4791         adapter->rx_tstamp_tc.nsec += delta;
4792         adapter->tx_tstamp_tc.nsec += delta;
4793
4794         return 0;
4795 }
4796
4797 static int
4798 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4799 {
4800         uint64_t ns;
4801         struct e1000_adapter *adapter =
4802                         (struct e1000_adapter *)dev->data->dev_private;
4803
4804         ns = rte_timespec_to_ns(ts);
4805
4806         /* Set the timecounters to a new value. */
4807         adapter->systime_tc.nsec = ns;
4808         adapter->rx_tstamp_tc.nsec = ns;
4809         adapter->tx_tstamp_tc.nsec = ns;
4810
4811         return 0;
4812 }
4813
4814 static int
4815 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4816 {
4817         uint64_t ns, systime_cycles;
4818         struct e1000_adapter *adapter =
4819                         (struct e1000_adapter *)dev->data->dev_private;
4820
4821         systime_cycles = igb_read_systime_cyclecounter(dev);
4822         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4823         *ts = rte_ns_to_timespec(ns);
4824
4825         return 0;
4826 }
4827
4828 static int
4829 igb_timesync_enable(struct rte_eth_dev *dev)
4830 {
4831         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4832         uint32_t tsync_ctl;
4833         uint32_t tsauxc;
4834
4835         /* Stop the timesync system time. */
4836         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4837         /* Reset the timesync system time value. */
4838         switch (hw->mac.type) {
4839         case e1000_82580:
4840         case e1000_i350:
4841         case e1000_i354:
4842         case e1000_i210:
4843         case e1000_i211:
4844                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4845                 /* fall-through */
4846         case e1000_82576:
4847                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4848                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4849                 break;
4850         default:
4851                 /* Not supported. */
4852                 return -ENOTSUP;
4853         }
4854
4855         /* Enable system time for it isn't on by default. */
4856         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4857         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4858         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4859
4860         igb_start_timecounters(dev);
4861
4862         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4863         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4864                         (ETHER_TYPE_1588 |
4865                          E1000_ETQF_FILTER_ENABLE |
4866                          E1000_ETQF_1588));
4867
4868         /* Enable timestamping of received PTP packets. */
4869         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4870         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4871         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4872
4873         /* Enable Timestamping of transmitted PTP packets. */
4874         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4875         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4876         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4877
4878         return 0;
4879 }
4880
4881 static int
4882 igb_timesync_disable(struct rte_eth_dev *dev)
4883 {
4884         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4885         uint32_t tsync_ctl;
4886
4887         /* Disable timestamping of transmitted PTP packets. */
4888         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4889         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4890         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4891
4892         /* Disable timestamping of received PTP packets. */
4893         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4894         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4895         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4896
4897         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4898         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4899
4900         /* Stop incrementating the System Time registers. */
4901         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4902
4903         return 0;
4904 }
4905
4906 static int
4907 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4908                                struct timespec *timestamp,
4909                                uint32_t flags __rte_unused)
4910 {
4911         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4912         struct e1000_adapter *adapter =
4913                         (struct e1000_adapter *)dev->data->dev_private;
4914         uint32_t tsync_rxctl;
4915         uint64_t rx_tstamp_cycles;
4916         uint64_t ns;
4917
4918         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4919         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4920                 return -EINVAL;
4921
4922         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4923         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4924         *timestamp = rte_ns_to_timespec(ns);
4925
4926         return  0;
4927 }
4928
4929 static int
4930 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4931                                struct timespec *timestamp)
4932 {
4933         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4934         struct e1000_adapter *adapter =
4935                         (struct e1000_adapter *)dev->data->dev_private;
4936         uint32_t tsync_txctl;
4937         uint64_t tx_tstamp_cycles;
4938         uint64_t ns;
4939
4940         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4941         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4942                 return -EINVAL;
4943
4944         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4945         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4946         *timestamp = rte_ns_to_timespec(ns);
4947
4948         return  0;
4949 }
4950
4951 static int
4952 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4953 {
4954         int count = 0;
4955         int g_ind = 0;
4956         const struct reg_info *reg_group;
4957
4958         while ((reg_group = igb_regs[g_ind++]))
4959                 count += igb_reg_group_count(reg_group);
4960
4961         return count;
4962 }
4963
4964 static int
4965 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4966 {
4967         int count = 0;
4968         int g_ind = 0;
4969         const struct reg_info *reg_group;
4970
4971         while ((reg_group = igbvf_regs[g_ind++]))
4972                 count += igb_reg_group_count(reg_group);
4973
4974         return count;
4975 }
4976
4977 static int
4978 eth_igb_get_regs(struct rte_eth_dev *dev,
4979         struct rte_dev_reg_info *regs)
4980 {
4981         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4982         uint32_t *data = regs->data;
4983         int g_ind = 0;
4984         int count = 0;
4985         const struct reg_info *reg_group;
4986
4987         if (data == NULL) {
4988                 regs->length = eth_igb_get_reg_length(dev);
4989                 regs->width = sizeof(uint32_t);
4990                 return 0;
4991         }
4992
4993         /* Support only full register dump */
4994         if ((regs->length == 0) ||
4995             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4996                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4997                         hw->device_id;
4998                 while ((reg_group = igb_regs[g_ind++]))
4999                         count += igb_read_regs_group(dev, &data[count],
5000                                                         reg_group);
5001                 return 0;
5002         }
5003
5004         return -ENOTSUP;
5005 }
5006
5007 static int
5008 igbvf_get_regs(struct rte_eth_dev *dev,
5009         struct rte_dev_reg_info *regs)
5010 {
5011         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5012         uint32_t *data = regs->data;
5013         int g_ind = 0;
5014         int count = 0;
5015         const struct reg_info *reg_group;
5016
5017         if (data == NULL) {
5018                 regs->length = igbvf_get_reg_length(dev);
5019                 regs->width = sizeof(uint32_t);
5020                 return 0;
5021         }
5022
5023         /* Support only full register dump */
5024         if ((regs->length == 0) ||
5025             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5026                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5027                         hw->device_id;
5028                 while ((reg_group = igbvf_regs[g_ind++]))
5029                         count += igb_read_regs_group(dev, &data[count],
5030                                                         reg_group);
5031                 return 0;
5032         }
5033
5034         return -ENOTSUP;
5035 }
5036
5037 static int
5038 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5039 {
5040         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5041
5042         /* Return unit is byte count */
5043         return hw->nvm.word_size * 2;
5044 }
5045
5046 static int
5047 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5048         struct rte_dev_eeprom_info *in_eeprom)
5049 {
5050         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5051         struct e1000_nvm_info *nvm = &hw->nvm;
5052         uint16_t *data = in_eeprom->data;
5053         int first, length;
5054
5055         first = in_eeprom->offset >> 1;
5056         length = in_eeprom->length >> 1;
5057         if ((first >= hw->nvm.word_size) ||
5058             ((first + length) >= hw->nvm.word_size))
5059                 return -EINVAL;
5060
5061         in_eeprom->magic = hw->vendor_id |
5062                 ((uint32_t)hw->device_id << 16);
5063
5064         if ((nvm->ops.read) == NULL)
5065                 return -ENOTSUP;
5066
5067         return nvm->ops.read(hw, first, length, data);
5068 }
5069
5070 static int
5071 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5072         struct rte_dev_eeprom_info *in_eeprom)
5073 {
5074         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5075         struct e1000_nvm_info *nvm = &hw->nvm;
5076         uint16_t *data = in_eeprom->data;
5077         int first, length;
5078
5079         first = in_eeprom->offset >> 1;
5080         length = in_eeprom->length >> 1;
5081         if ((first >= hw->nvm.word_size) ||
5082             ((first + length) >= hw->nvm.word_size))
5083                 return -EINVAL;
5084
5085         in_eeprom->magic = (uint32_t)hw->vendor_id |
5086                 ((uint32_t)hw->device_id << 16);
5087
5088         if ((nvm->ops.write) == NULL)
5089                 return -ENOTSUP;
5090         return nvm->ops.write(hw,  first, length, data);
5091 }
5092
5093 static int
5094 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5095 {
5096         struct e1000_hw *hw =
5097                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5098         uint32_t mask = 1 << queue_id;
5099
5100         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5101         E1000_WRITE_FLUSH(hw);
5102
5103         return 0;
5104 }
5105
5106 static int
5107 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5108 {
5109         struct e1000_hw *hw =
5110                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5111         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5112         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5113         uint32_t mask = 1 << queue_id;
5114         uint32_t regval;
5115
5116         regval = E1000_READ_REG(hw, E1000_EIMS);
5117         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5118         E1000_WRITE_FLUSH(hw);
5119
5120         rte_intr_enable(intr_handle);
5121
5122         return 0;
5123 }
5124
5125 static void
5126 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5127                    uint8_t index, uint8_t offset)
5128 {
5129         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5130
5131         /* clear bits */
5132         val &= ~((uint32_t)0xFF << offset);
5133
5134         /* write vector and valid bit */
5135         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5136
5137         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5138 }
5139
5140 static void
5141 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5142                            uint8_t queue, uint8_t msix_vector)
5143 {
5144         uint32_t tmp = 0;
5145
5146         if (hw->mac.type == e1000_82575) {
5147                 if (direction == 0)
5148                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5149                 else if (direction == 1)
5150                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5151                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5152         } else if (hw->mac.type == e1000_82576) {
5153                 if ((direction == 0) || (direction == 1))
5154                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5155                                            ((queue & 0x8) << 1) +
5156                                            8 * direction);
5157         } else if ((hw->mac.type == e1000_82580) ||
5158                         (hw->mac.type == e1000_i350) ||
5159                         (hw->mac.type == e1000_i354) ||
5160                         (hw->mac.type == e1000_i210) ||
5161                         (hw->mac.type == e1000_i211)) {
5162                 if ((direction == 0) || (direction == 1))
5163                         eth_igb_write_ivar(hw, msix_vector,
5164                                            queue >> 1,
5165                                            ((queue & 0x1) << 4) +
5166                                            8 * direction);
5167         }
5168 }
5169
5170 /* Sets up the hardware to generate MSI-X interrupts properly
5171  * @hw
5172  *  board private structure
5173  */
5174 static void
5175 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5176 {
5177         int queue_id;
5178         uint32_t tmpval, regval, intr_mask;
5179         struct e1000_hw *hw =
5180                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5181         uint32_t vec = E1000_MISC_VEC_ID;
5182         uint32_t base = E1000_MISC_VEC_ID;
5183         uint32_t misc_shift = 0;
5184         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5185         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5186
5187         /* won't configure msix register if no mapping is done
5188          * between intr vector and event fd
5189          */
5190         if (!rte_intr_dp_is_en(intr_handle))
5191                 return;
5192
5193         if (rte_intr_allow_others(intr_handle)) {
5194                 vec = base = E1000_RX_VEC_START;
5195                 misc_shift = 1;
5196         }
5197
5198         /* set interrupt vector for other causes */
5199         if (hw->mac.type == e1000_82575) {
5200                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5201                 /* enable MSI-X PBA support */
5202                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5203
5204                 /* Auto-Mask interrupts upon ICR read */
5205                 tmpval |= E1000_CTRL_EXT_EIAME;
5206                 tmpval |= E1000_CTRL_EXT_IRCA;
5207
5208                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5209
5210                 /* enable msix_other interrupt */
5211                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5212                 regval = E1000_READ_REG(hw, E1000_EIAC);
5213                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5214                 regval = E1000_READ_REG(hw, E1000_EIAM);
5215                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5216         } else if ((hw->mac.type == e1000_82576) ||
5217                         (hw->mac.type == e1000_82580) ||
5218                         (hw->mac.type == e1000_i350) ||
5219                         (hw->mac.type == e1000_i354) ||
5220                         (hw->mac.type == e1000_i210) ||
5221                         (hw->mac.type == e1000_i211)) {
5222                 /* turn on MSI-X capability first */
5223                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5224                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5225                                         E1000_GPIE_NSICR);
5226                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5227                         misc_shift;
5228                 regval = E1000_READ_REG(hw, E1000_EIAC);
5229                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5230
5231                 /* enable msix_other interrupt */
5232                 regval = E1000_READ_REG(hw, E1000_EIMS);
5233                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5234                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5235                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5236         }
5237
5238         /* use EIAM to auto-mask when MSI-X interrupt
5239          * is asserted, this saves a register write for every interrupt
5240          */
5241         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5242                 misc_shift;
5243         regval = E1000_READ_REG(hw, E1000_EIAM);
5244         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5245
5246         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5247                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5248                 intr_handle->intr_vec[queue_id] = vec;
5249                 if (vec < base + intr_handle->nb_efd - 1)
5250                         vec++;
5251         }
5252
5253         E1000_WRITE_FLUSH(hw);
5254 }
5255
5256 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd.pci_drv);
5257 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5258 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio");
5259 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd.pci_drv);
5260 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5261 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio");