drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "base/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59 #include "igb_regs.h"
  60
  61 /*
  62  * Default values for port configuration
  63  */
  64 #define IGB_DEFAULT_RX_FREE_THRESH  32
  65
  66 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  67 #define IGB_DEFAULT_RX_HTHRESH      8
  68 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  69
  70 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  71 #define IGB_DEFAULT_TX_HTHRESH      1
  72 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  73
  74 #define IGB_HKEY_MAX_INDEX 10
  75
  76 /* Bit shift and mask */
  77 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  78 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  79 #define IGB_8_BIT_WIDTH  CHAR_BIT
  80 #define IGB_8_BIT_MASK   UINT8_MAX
  81
  82 /* Additional timesync values. */
  83 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  84 #define E1000_ETQF_FILTER_1588       3
  85 #define IGB_82576_TSYNC_SHIFT        16
  86 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  87 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  89
  90 #define E1000_VTIVAR_MISC                0x01740
  91 #define E1000_VTIVAR_MISC_MASK           0xFF
  92 #define E1000_VTIVAR_VALID               0x80
  93 #define E1000_VTIVAR_MISC_MAILBOX        0
  94 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  95
  96 /* External VLAN Enable bit mask */
  97 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  98
  99 /* External VLAN Ether Type bit mask and shift */
 100 #define E1000_VET_VET_EXT            0xFFFF0000
 101 #define E1000_VET_VET_EXT_SHIFT      16
 102
 103 static int  eth_igb_configure(struct rte_eth_dev *dev);
 104 static int  eth_igb_start(struct rte_eth_dev *dev);
 105 static void eth_igb_stop(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 107 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 108 static void eth_igb_close(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 113 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 114                                 int wait_to_complete);
 115 static int eth_igb_stats_get(struct rte_eth_dev *dev,
 116                                 struct rte_eth_stats *rte_stats);
 117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 118                               struct rte_eth_xstat *xstats, unsigned n);
 119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
 120                 const uint64_t *ids,
 121                 uint64_t *values, unsigned int n);
 122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 123                                     struct rte_eth_xstat_name *xstats_names,
 124                                     unsigned int size);
 125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
 126                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 127                 unsigned int limit);
 128 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 131                                    char *fw_version, size_t fw_size);
 132 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 133                               struct rte_eth_dev_info *dev_info);
 134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 136                                 struct rte_eth_dev_info *dev_info);
 137 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 138                                 struct rte_eth_fc_conf *fc_conf);
 139 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 140                                 struct rte_eth_fc_conf *fc_conf);
 141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 145                                     struct rte_intr_handle *handle);
 146 static void eth_igb_interrupt_handler(void *param);
 147 static int  igb_hardware_init(struct e1000_hw *hw);
 148 static void igb_hw_control_acquire(struct e1000_hw *hw);
 149 static void igb_hw_control_release(struct e1000_hw *hw);
 150 static void igb_init_manageability(struct e1000_hw *hw);
 151 static void igb_release_manageability(struct e1000_hw *hw);
 152
 153 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154
 155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 156                 uint16_t vlan_id, int on);
 157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 158                                  enum rte_vlan_type vlan_type,
 159                                  uint16_t tpid_id);
 160 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 161
 162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 168
 169 static int eth_igb_led_on(struct rte_eth_dev *dev);
 170 static int eth_igb_led_off(struct rte_eth_dev *dev);
 171
 172 static void igb_intr_disable(struct e1000_hw *hw);
 173 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 174 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 175                            struct ether_addr *mac_addr,
 176                            uint32_t index, uint32_t pool);
 177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 179                 struct ether_addr *addr);
 180
 181 static void igbvf_intr_disable(struct e1000_hw *hw);
 182 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 183 static int igbvf_dev_start(struct rte_eth_dev *dev);
 184 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 185 static void igbvf_dev_close(struct rte_eth_dev *dev);
 186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 190 static int eth_igbvf_link_update(struct e1000_hw *hw);
 191 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 192                                 struct rte_eth_stats *rte_stats);
 193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 194                                 struct rte_eth_xstat *xstats, unsigned n);
 195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 196                                       struct rte_eth_xstat_name *xstats_names,
 197                                       unsigned limit);
 198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 200                 uint16_t vlan_id, int on);
 201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 204                 struct ether_addr *addr);
 205 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 206 static int igbvf_get_regs(struct rte_eth_dev *dev,
 207                 struct rte_dev_reg_info *regs);
 208
 209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 210                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 211                                    uint16_t reta_size);
 212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 213                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 214                                   uint16_t reta_size);
 215
 216 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 217                         struct rte_eth_syn_filter *filter);
 218 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 219                         enum rte_filter_op filter_op,
 220                         void *arg);
 221 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 222                         struct rte_eth_ntuple_filter *ntuple_filter);
 223 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 224                         struct rte_eth_ntuple_filter *ntuple_filter);
 225 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 226                         struct rte_eth_flex_filter *filter);
 227 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 228                         enum rte_filter_op filter_op,
 229                         void *arg);
 230 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 231                         struct rte_eth_ntuple_filter *ntuple_filter);
 232 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 233                         struct rte_eth_ntuple_filter *ntuple_filter);
 234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 235                         struct rte_eth_ntuple_filter *filter);
 236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 237                                 enum rte_filter_op filter_op,
 238                                 void *arg);
 239 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 240                                 enum rte_filter_op filter_op,
 241                                 void *arg);
 242 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 243                         struct rte_eth_ethertype_filter *filter);
 244 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 245                      enum rte_filter_type filter_type,
 246                      enum rte_filter_op filter_op,
 247                      void *arg);
 248 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 249 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 250                 struct rte_dev_reg_info *regs);
 251 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 252 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 253                 struct rte_dev_eeprom_info *eeprom);
 254 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 255                 struct rte_dev_eeprom_info *eeprom);
 256 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 257                                     struct ether_addr *mc_addr_set,
 258                                     uint32_t nb_mc_addr);
 259 static int igb_timesync_enable(struct rte_eth_dev *dev);
 260 static int igb_timesync_disable(struct rte_eth_dev *dev);
 261 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 262                                           struct timespec *timestamp,
 263                                           uint32_t flags);
 264 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 265                                           struct timespec *timestamp);
 266 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 267 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 268                                   struct timespec *timestamp);
 269 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 270                                    const struct timespec *timestamp);
 271 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 272                                         uint16_t queue_id);
 273 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 274                                          uint16_t queue_id);
 275 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 276                                        uint8_t queue, uint8_t msix_vector);
 277 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 278                                uint8_t index, uint8_t offset);
 279 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 280 static void eth_igbvf_interrupt_handler(void *param);
 281 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 282 static int igb_filter_restore(struct rte_eth_dev *dev);
 283
 284 /*
 285  * Define VF Stats MACRO for Non "cleared on read" register
 286  */
 287 #define UPDATE_VF_STAT(reg, last, cur)            \
 288 {                                                 \
 289         u32 latest = E1000_READ_REG(hw, reg);     \
 290         cur += (latest - last) & UINT_MAX;        \
 291         last = latest;                            \
 292 }
 293
 294 #define IGB_FC_PAUSE_TIME 0x0680
 295 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 296 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 297
 298 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 299
 300 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 301
 302 /*
 303  * The set of PCI devices this driver supports
 304  */
 305 static const struct rte_pci_id pci_id_igb_map[] = {
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 314
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 318
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 325
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 347         { .vendor_id = 0, /* sentinel */ },
 348 };
 349
 350 /*
 351  * The set of PCI devices this driver supports (for 82576&I350 VF)
 352  */
 353 static const struct rte_pci_id pci_id_igbvf_map[] = {
 354         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 356         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 357         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 358         { .vendor_id = 0, /* sentinel */ },
 359 };
 360
 361 static const struct rte_eth_desc_lim rx_desc_lim = {
 362         .nb_max = E1000_MAX_RING_DESC,
 363         .nb_min = E1000_MIN_RING_DESC,
 364         .nb_align = IGB_RXD_ALIGN,
 365 };
 366
 367 static const struct rte_eth_desc_lim tx_desc_lim = {
 368         .nb_max = E1000_MAX_RING_DESC,
 369         .nb_min = E1000_MIN_RING_DESC,
 370         .nb_align = IGB_RXD_ALIGN,
 371         .nb_seg_max = IGB_TX_MAX_SEG,
 372         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 373 };
 374
 375 static const struct eth_dev_ops eth_igb_ops = {
 376         .dev_configure        = eth_igb_configure,
 377         .dev_start            = eth_igb_start,
 378         .dev_stop             = eth_igb_stop,
 379         .dev_set_link_up      = eth_igb_dev_set_link_up,
 380         .dev_set_link_down    = eth_igb_dev_set_link_down,
 381         .dev_close            = eth_igb_close,
 382         .promiscuous_enable   = eth_igb_promiscuous_enable,
 383         .promiscuous_disable  = eth_igb_promiscuous_disable,
 384         .allmulticast_enable  = eth_igb_allmulticast_enable,
 385         .allmulticast_disable = eth_igb_allmulticast_disable,
 386         .link_update          = eth_igb_link_update,
 387         .stats_get            = eth_igb_stats_get,
 388         .xstats_get           = eth_igb_xstats_get,
 389         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 390         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 391         .xstats_get_names     = eth_igb_xstats_get_names,
 392         .stats_reset          = eth_igb_stats_reset,
 393         .xstats_reset         = eth_igb_xstats_reset,
 394         .fw_version_get       = eth_igb_fw_version_get,
 395         .dev_infos_get        = eth_igb_infos_get,
 396         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 397         .mtu_set              = eth_igb_mtu_set,
 398         .vlan_filter_set      = eth_igb_vlan_filter_set,
 399         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 400         .vlan_offload_set     = eth_igb_vlan_offload_set,
 401         .rx_queue_setup       = eth_igb_rx_queue_setup,
 402         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 403         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 404         .rx_queue_release     = eth_igb_rx_queue_release,
 405         .rx_queue_count       = eth_igb_rx_queue_count,
 406         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 407         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 408         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 409         .tx_queue_setup       = eth_igb_tx_queue_setup,
 410         .tx_queue_release     = eth_igb_tx_queue_release,
 411         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 412         .dev_led_on           = eth_igb_led_on,
 413         .dev_led_off          = eth_igb_led_off,
 414         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 415         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 416         .mac_addr_add         = eth_igb_rar_set,
 417         .mac_addr_remove      = eth_igb_rar_clear,
 418         .mac_addr_set         = eth_igb_default_mac_addr_set,
 419         .reta_update          = eth_igb_rss_reta_update,
 420         .reta_query           = eth_igb_rss_reta_query,
 421         .rss_hash_update      = eth_igb_rss_hash_update,
 422         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 423         .filter_ctrl          = eth_igb_filter_ctrl,
 424         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 425         .rxq_info_get         = igb_rxq_info_get,
 426         .txq_info_get         = igb_txq_info_get,
 427         .timesync_enable      = igb_timesync_enable,
 428         .timesync_disable     = igb_timesync_disable,
 429         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 430         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 431         .get_reg              = eth_igb_get_regs,
 432         .get_eeprom_length    = eth_igb_get_eeprom_length,
 433         .get_eeprom           = eth_igb_get_eeprom,
 434         .set_eeprom           = eth_igb_set_eeprom,
 435         .timesync_adjust_time = igb_timesync_adjust_time,
 436         .timesync_read_time   = igb_timesync_read_time,
 437         .timesync_write_time  = igb_timesync_write_time,
 438 };
 439
 440 /*
 441  * dev_ops for virtual function, bare necessities for basic vf
 442  * operation have been implemented
 443  */
 444 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 445         .dev_configure        = igbvf_dev_configure,
 446         .dev_start            = igbvf_dev_start,
 447         .dev_stop             = igbvf_dev_stop,
 448         .dev_close            = igbvf_dev_close,
 449         .promiscuous_enable   = igbvf_promiscuous_enable,
 450         .promiscuous_disable  = igbvf_promiscuous_disable,
 451         .allmulticast_enable  = igbvf_allmulticast_enable,
 452         .allmulticast_disable = igbvf_allmulticast_disable,
 453         .link_update          = eth_igb_link_update,
 454         .stats_get            = eth_igbvf_stats_get,
 455         .xstats_get           = eth_igbvf_xstats_get,
 456         .xstats_get_names     = eth_igbvf_xstats_get_names,
 457         .stats_reset          = eth_igbvf_stats_reset,
 458         .xstats_reset         = eth_igbvf_stats_reset,
 459         .vlan_filter_set      = igbvf_vlan_filter_set,
 460         .dev_infos_get        = eth_igbvf_infos_get,
 461         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 462         .rx_queue_setup       = eth_igb_rx_queue_setup,
 463         .rx_queue_release     = eth_igb_rx_queue_release,
 464         .tx_queue_setup       = eth_igb_tx_queue_setup,
 465         .tx_queue_release     = eth_igb_tx_queue_release,
 466         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 467         .rxq_info_get         = igb_rxq_info_get,
 468         .txq_info_get         = igb_txq_info_get,
 469         .mac_addr_set         = igbvf_default_mac_addr_set,
 470         .get_reg              = igbvf_get_regs,
 471 };
 472
 473 /* store statistics names and its offset in stats structure */
 474 struct rte_igb_xstats_name_off {
 475         char name[RTE_ETH_XSTATS_NAME_SIZE];
 476         unsigned offset;
 477 };
 478
 479 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 480         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 481         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 482         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 483         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 484         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 485         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 486         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 487                 ecol)},
 488         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 489         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 490         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 491         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 492         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 493         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 494         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 495         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 496         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 497         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 498         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 499                 fcruc)},
 500         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 501         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 502         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 503         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 504         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 505                 prc1023)},
 506         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 507                 prc1522)},
 508         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 509         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 510         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 511         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 512         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 513         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 514         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 515         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 516         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 517         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 518         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 519         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 520         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 521         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 522         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 523         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 524         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 525         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 526                 ptc1023)},
 527         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 528                 ptc1522)},
 529         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 530         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 531         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 532         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 533         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 534         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 535         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 536
 537         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 538 };
 539
 540 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 541                 sizeof(rte_igb_stats_strings[0]))
 542
 543 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 544         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 545         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 546         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 547         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 548         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 549 };
 550
 551 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 552                 sizeof(rte_igbvf_stats_strings[0]))
 553
 554 /**
 555  * Atomically reads the link status information from global
 556  * structure rte_eth_dev.
 557  *
 558  * @param dev
 559  *   - Pointer to the structure rte_eth_dev to read from.
 560  *   - Pointer to the buffer to be saved with the link status.
 561  *
 562  * @return
 563  *   - On success, zero.
 564  *   - On failure, negative value.
 565  */
 566 static inline int
 567 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 568                                 struct rte_eth_link *link)
 569 {
 570         struct rte_eth_link *dst = link;
 571         struct rte_eth_link *src = &(dev->data->dev_link);
 572
 573         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 574                                         *(uint64_t *)src) == 0)
 575                 return -1;
 576
 577         return 0;
 578 }
 579
 580 /**
 581  * Atomically writes the link status information into global
 582  * structure rte_eth_dev.
 583  *
 584  * @param dev
 585  *   - Pointer to the structure rte_eth_dev to read from.
 586  *   - Pointer to the buffer to be saved with the link status.
 587  *
 588  * @return
 589  *   - On success, zero.
 590  *   - On failure, negative value.
 591  */
 592 static inline int
 593 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 594                                 struct rte_eth_link *link)
 595 {
 596         struct rte_eth_link *dst = &(dev->data->dev_link);
 597         struct rte_eth_link *src = link;
 598
 599         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 600                                         *(uint64_t *)src) == 0)
 601                 return -1;
 602
 603         return 0;
 604 }
 605
 606 static inline void
 607 igb_intr_enable(struct rte_eth_dev *dev)
 608 {
 609         struct e1000_interrupt *intr =
 610                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 611         struct e1000_hw *hw =
 612                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 613
 614         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 615         E1000_WRITE_FLUSH(hw);
 616 }
 617
 618 static void
 619 igb_intr_disable(struct e1000_hw *hw)
 620 {
 621         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 622         E1000_WRITE_FLUSH(hw);
 623 }
 624
 625 static inline void
 626 igbvf_intr_enable(struct rte_eth_dev *dev)
 627 {
 628         struct e1000_hw *hw =
 629                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 630
 631         /* only for mailbox */
 632         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 633         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 634         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 635         E1000_WRITE_FLUSH(hw);
 636 }
 637
 638 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 639 static void
 640 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 641 {
 642         uint32_t tmp = 0;
 643
 644         /* mailbox */
 645         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 646         tmp |= E1000_VTIVAR_VALID;
 647         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 648 }
 649
 650 static void
 651 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 652 {
 653         struct e1000_hw *hw =
 654                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 655
 656         /* Configure VF other cause ivar */
 657         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 658 }
 659
 660 static inline int32_t
 661 igb_pf_reset_hw(struct e1000_hw *hw)
 662 {
 663         uint32_t ctrl_ext;
 664         int32_t status;
 665
 666         status = e1000_reset_hw(hw);
 667
 668         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 669         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 670         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 671         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 672         E1000_WRITE_FLUSH(hw);
 673
 674         return status;
 675 }
 676
 677 static void
 678 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 679 {
 680         struct e1000_hw *hw =
 681                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 682
 683
 684         hw->vendor_id = pci_dev->id.vendor_id;
 685         hw->device_id = pci_dev->id.device_id;
 686         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 687         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 688
 689         e1000_set_mac_type(hw);
 690
 691         /* need to check if it is a vf device below */
 692 }
 693
 694 static int
 695 igb_reset_swfw_lock(struct e1000_hw *hw)
 696 {
 697         int ret_val;
 698
 699         /*
 700          * Do mac ops initialization manually here, since we will need
 701          * some function pointers set by this call.
 702          */
 703         ret_val = e1000_init_mac_params(hw);
 704         if (ret_val)
 705                 return ret_val;
 706
 707         /*
 708          * SMBI lock should not fail in this early stage. If this is the case,
 709          * it is due to an improper exit of the application.
 710          * So force the release of the faulty lock.
 711          */
 712         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 713                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 714         }
 715         e1000_put_hw_semaphore_generic(hw);
 716
 717         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 718                 uint16_t mask;
 719
 720                 /*
 721                  * Phy lock should not fail in this early stage. If this is the case,
 722                  * it is due to an improper exit of the application.
 723                  * So force the release of the faulty lock.
 724                  */
 725                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 726                 if (hw->bus.func > E1000_FUNC_1)
 727                         mask <<= 2;
 728                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 729                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 730                                     hw->bus.func);
 731                 }
 732                 hw->mac.ops.release_swfw_sync(hw, mask);
 733
 734                 /*
 735                  * This one is more tricky since it is common to all ports; but
 736                  * swfw_sync retries last long enough (1s) to be almost sure that if
 737                  * lock can not be taken it is due to an improper lock of the
 738                  * semaphore.
 739                  */
 740                 mask = E1000_SWFW_EEP_SM;
 741                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 742                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 743                 }
 744                 hw->mac.ops.release_swfw_sync(hw, mask);
 745         }
 746
 747         return E1000_SUCCESS;
 748 }
 749
 750 /* Remove all ntuple filters of the device */
 751 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 752 {
 753         struct e1000_filter_info *filter_info =
 754                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 755         struct e1000_5tuple_filter *p_5tuple;
 756         struct e1000_2tuple_filter *p_2tuple;
 757
 758         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 759                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 760                         p_5tuple, entries);
 761                         rte_free(p_5tuple);
 762         }
 763         filter_info->fivetuple_mask = 0;
 764         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 765                 TAILQ_REMOVE(&filter_info->twotuple_list,
 766                         p_2tuple, entries);
 767                         rte_free(p_2tuple);
 768         }
 769         filter_info->twotuple_mask = 0;
 770
 771         return 0;
 772 }
 773
 774 /* Remove all flex filters of the device */
 775 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 776 {
 777         struct e1000_filter_info *filter_info =
 778                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 779         struct e1000_flex_filter *p_flex;
 780
 781         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 782                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 783                 rte_free(p_flex);
 784         }
 785         filter_info->flex_mask = 0;
 786
 787         return 0;
 788 }
 789
 790 static int
 791 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 792 {
 793         int error = 0;
 794         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 795         struct e1000_hw *hw =
 796                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 797         struct e1000_vfta * shadow_vfta =
 798                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 799         struct e1000_filter_info *filter_info =
 800                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 801         struct e1000_adapter *adapter =
 802                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 803
 804         uint32_t ctrl_ext;
 805
 806         eth_dev->dev_ops = &eth_igb_ops;
 807         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 808         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 809         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 810
 811         /* for secondary processes, we don't initialise any further as primary
 812          * has already done this work. Only check we don't need a different
 813          * RX function */
 814         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 815                 if (eth_dev->data->scattered_rx)
 816                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 817                 return 0;
 818         }
 819
 820         rte_eth_copy_pci_info(eth_dev, pci_dev);
 821
 822         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 823
 824         igb_identify_hardware(eth_dev, pci_dev);
 825         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 826                 error = -EIO;
 827                 goto err_late;
 828         }
 829
 830         e1000_get_bus_info(hw);
 831
 832         /* Reset any pending lock */
 833         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 834                 error = -EIO;
 835                 goto err_late;
 836         }
 837
 838         /* Finish initialization */
 839         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 840                 error = -EIO;
 841                 goto err_late;
 842         }
 843
 844         hw->mac.autoneg = 1;
 845         hw->phy.autoneg_wait_to_complete = 0;
 846         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 847
 848         /* Copper options */
 849         if (hw->phy.media_type == e1000_media_type_copper) {
 850                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 851                 hw->phy.disable_polarity_correction = 0;
 852                 hw->phy.ms_type = e1000_ms_hw_default;
 853         }
 854
 855         /*
 856          * Start from a known state, this is important in reading the nvm
 857          * and mac from that.
 858          */
 859         igb_pf_reset_hw(hw);
 860
 861         /* Make sure we have a good EEPROM before we read from it */
 862         if (e1000_validate_nvm_checksum(hw) < 0) {
 863                 /*
 864                  * Some PCI-E parts fail the first check due to
 865                  * the link being in sleep state, call it again,
 866                  * if it fails a second time its a real issue.
 867                  */
 868                 if (e1000_validate_nvm_checksum(hw) < 0) {
 869                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 870                         error = -EIO;
 871                         goto err_late;
 872                 }
 873         }
 874
 875         /* Read the permanent MAC address out of the EEPROM */
 876         if (e1000_read_mac_addr(hw) != 0) {
 877                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 878                 error = -EIO;
 879                 goto err_late;
 880         }
 881
 882         /* Allocate memory for storing MAC addresses */
 883         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 884                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 885         if (eth_dev->data->mac_addrs == NULL) {
 886                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 887                                                 "store MAC addresses",
 888                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 889                 error = -ENOMEM;
 890                 goto err_late;
 891         }
 892
 893         /* Copy the permanent MAC address */
 894         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 895
 896         /* initialize the vfta */
 897         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 898
 899         /* Now initialize the hardware */
 900         if (igb_hardware_init(hw) != 0) {
 901                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 902                 rte_free(eth_dev->data->mac_addrs);
 903                 eth_dev->data->mac_addrs = NULL;
 904                 error = -ENODEV;
 905                 goto err_late;
 906         }
 907         hw->mac.get_link_status = 1;
 908         adapter->stopped = 0;
 909
 910         /* Indicate SOL/IDER usage */
 911         if (e1000_check_reset_block(hw) < 0) {
 912                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 913                                         "SOL/IDER session");
 914         }
 915
 916         /* initialize PF if max_vfs not zero */
 917         igb_pf_host_init(eth_dev);
 918
 919         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 920         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 921         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 922         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 923         E1000_WRITE_FLUSH(hw);
 924
 925         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 926                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 927                      pci_dev->id.device_id);
 928
 929         rte_intr_callback_register(&pci_dev->intr_handle,
 930                                    eth_igb_interrupt_handler,
 931                                    (void *)eth_dev);
 932
 933         /* enable uio/vfio intr/eventfd mapping */
 934         rte_intr_enable(&pci_dev->intr_handle);
 935
 936         /* enable support intr */
 937         igb_intr_enable(eth_dev);
 938
 939         /* initialize filter info */
 940         memset(filter_info, 0,
 941                sizeof(struct e1000_filter_info));
 942
 943         TAILQ_INIT(&filter_info->flex_list);
 944         TAILQ_INIT(&filter_info->twotuple_list);
 945         TAILQ_INIT(&filter_info->fivetuple_list);
 946
 947         TAILQ_INIT(&igb_filter_ntuple_list);
 948         TAILQ_INIT(&igb_filter_ethertype_list);
 949         TAILQ_INIT(&igb_filter_syn_list);
 950         TAILQ_INIT(&igb_filter_flex_list);
 951         TAILQ_INIT(&igb_flow_list);
 952
 953         return 0;
 954
 955 err_late:
 956         igb_hw_control_release(hw);
 957
 958         return error;
 959 }
 960
 961 static int
 962 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 963 {
 964         struct rte_pci_device *pci_dev;
 965         struct rte_intr_handle *intr_handle;
 966         struct e1000_hw *hw;
 967         struct e1000_adapter *adapter =
 968                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 969         struct e1000_filter_info *filter_info =
 970                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 971
 972         PMD_INIT_FUNC_TRACE();
 973
 974         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 975                 return -EPERM;
 976
 977         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 978         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 979         intr_handle = &pci_dev->intr_handle;
 980
 981         if (adapter->stopped == 0)
 982                 eth_igb_close(eth_dev);
 983
 984         eth_dev->dev_ops = NULL;
 985         eth_dev->rx_pkt_burst = NULL;
 986         eth_dev->tx_pkt_burst = NULL;
 987
 988         /* Reset any pending lock */
 989         igb_reset_swfw_lock(hw);
 990
 991         rte_free(eth_dev->data->mac_addrs);
 992         eth_dev->data->mac_addrs = NULL;
 993
 994         /* uninitialize PF if max_vfs not zero */
 995         igb_pf_host_uninit(eth_dev);
 996
 997         /* disable uio intr before callback unregister */
 998         rte_intr_disable(intr_handle);
 999         rte_intr_callback_unregister(intr_handle,
1000                                      eth_igb_interrupt_handler, eth_dev);
1001
1002         /* clear the SYN filter info */
1003         filter_info->syn_info = 0;
1004
1005         /* clear the ethertype filters info */
1006         filter_info->ethertype_mask = 0;
1007         memset(filter_info->ethertype_filters, 0,
1008                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1009
1010         /* remove all ntuple filters of the device */
1011         igb_ntuple_filter_uninit(eth_dev);
1012
1013         /* remove all flex filters of the device */
1014         igb_flex_filter_uninit(eth_dev);
1015
1016         /* clear all the filters list */
1017         igb_filterlist_flush(eth_dev);
1018
1019         return 0;
1020 }
1021
1022 /*
1023  * Virtual Function device init
1024  */
1025 static int
1026 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
1027 {
1028         struct rte_pci_device *pci_dev;
1029         struct rte_intr_handle *intr_handle;
1030         struct e1000_adapter *adapter =
1031                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1032         struct e1000_hw *hw =
1033                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1034         int diag;
1035         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
1036
1037         PMD_INIT_FUNC_TRACE();
1038
1039         eth_dev->dev_ops = &igbvf_eth_dev_ops;
1040         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
1041         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
1042         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
1043
1044         /* for secondary processes, we don't initialise any further as primary
1045          * has already done this work. Only check we don't need a different
1046          * RX function */
1047         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1048                 if (eth_dev->data->scattered_rx)
1049                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
1050                 return 0;
1051         }
1052
1053         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1054         rte_eth_copy_pci_info(eth_dev, pci_dev);
1055
1056         hw->device_id = pci_dev->id.device_id;
1057         hw->vendor_id = pci_dev->id.vendor_id;
1058         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1059         adapter->stopped = 0;
1060
1061         /* Initialize the shared code (base driver) */
1062         diag = e1000_setup_init_funcs(hw, TRUE);
1063         if (diag != 0) {
1064                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1065                         diag);
1066                 return -EIO;
1067         }
1068
1069         /* init_mailbox_params */
1070         hw->mbx.ops.init_params(hw);
1071
1072         /* Disable the interrupts for VF */
1073         igbvf_intr_disable(hw);
1074
1075         diag = hw->mac.ops.reset_hw(hw);
1076
1077         /* Allocate memory for storing MAC addresses */
1078         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1079                 hw->mac.rar_entry_count, 0);
1080         if (eth_dev->data->mac_addrs == NULL) {
1081                 PMD_INIT_LOG(ERR,
1082                         "Failed to allocate %d bytes needed to store MAC "
1083                         "addresses",
1084                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1085                 return -ENOMEM;
1086         }
1087
1088         /* Generate a random MAC address, if none was assigned by PF. */
1089         if (is_zero_ether_addr(perm_addr)) {
1090                 eth_random_addr(perm_addr->addr_bytes);
1091                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1092                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1093                              "%02x:%02x:%02x:%02x:%02x:%02x",
1094                              perm_addr->addr_bytes[0],
1095                              perm_addr->addr_bytes[1],
1096                              perm_addr->addr_bytes[2],
1097                              perm_addr->addr_bytes[3],
1098                              perm_addr->addr_bytes[4],
1099                              perm_addr->addr_bytes[5]);
1100         }
1101
1102         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1103         if (diag) {
1104                 rte_free(eth_dev->data->mac_addrs);
1105                 eth_dev->data->mac_addrs = NULL;
1106                 return diag;
1107         }
1108         /* Copy the permanent MAC address */
1109         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1110                         &eth_dev->data->mac_addrs[0]);
1111
1112         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1113                      "mac.type=%s",
1114                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1115                      pci_dev->id.device_id, "igb_mac_82576_vf");
1116
1117         intr_handle = &pci_dev->intr_handle;
1118         rte_intr_callback_register(intr_handle,
1119                                    eth_igbvf_interrupt_handler, eth_dev);
1120
1121         return 0;
1122 }
1123
1124 static int
1125 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1126 {
1127         struct e1000_adapter *adapter =
1128                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1129         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1130
1131         PMD_INIT_FUNC_TRACE();
1132
1133         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1134                 return -EPERM;
1135
1136         if (adapter->stopped == 0)
1137                 igbvf_dev_close(eth_dev);
1138
1139         eth_dev->dev_ops = NULL;
1140         eth_dev->rx_pkt_burst = NULL;
1141         eth_dev->tx_pkt_burst = NULL;
1142
1143         rte_free(eth_dev->data->mac_addrs);
1144         eth_dev->data->mac_addrs = NULL;
1145
1146         /* disable uio intr before callback unregister */
1147         rte_intr_disable(&pci_dev->intr_handle);
1148         rte_intr_callback_unregister(&pci_dev->intr_handle,
1149                                      eth_igbvf_interrupt_handler,
1150                                      (void *)eth_dev);
1151
1152         return 0;
1153 }
1154
1155 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1156         struct rte_pci_device *pci_dev)
1157 {
1158         return rte_eth_dev_pci_generic_probe(pci_dev,
1159                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1160 }
1161
1162 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1163 {
1164         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1165 }
1166
1167 static struct rte_pci_driver rte_igb_pmd = {
1168         .id_table = pci_id_igb_map,
1169         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1170                      RTE_PCI_DRV_IOVA_AS_VA,
1171         .probe = eth_igb_pci_probe,
1172         .remove = eth_igb_pci_remove,
1173 };
1174
1175
1176 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1177         struct rte_pci_device *pci_dev)
1178 {
1179         return rte_eth_dev_pci_generic_probe(pci_dev,
1180                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1181 }
1182
1183 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1184 {
1185         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1186 }
1187
1188 /*
1189  * virtual function driver struct
1190  */
1191 static struct rte_pci_driver rte_igbvf_pmd = {
1192         .id_table = pci_id_igbvf_map,
1193         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1194         .probe = eth_igbvf_pci_probe,
1195         .remove = eth_igbvf_pci_remove,
1196 };
1197
1198 static void
1199 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1200 {
1201         struct e1000_hw *hw =
1202                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1203         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1204         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1205         rctl |= E1000_RCTL_VFE;
1206         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1207 }
1208
1209 static int
1210 igb_check_mq_mode(struct rte_eth_dev *dev)
1211 {
1212         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1213         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1214         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1215         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1216
1217         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1218             tx_mq_mode == ETH_MQ_TX_DCB ||
1219             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1220                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1221                 return -EINVAL;
1222         }
1223         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1224                 /* Check multi-queue mode.
1225                  * To no break software we accept ETH_MQ_RX_NONE as this might
1226                  * be used to turn off VLAN filter.
1227                  */
1228
1229                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1230                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1231                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1232                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1233                 } else {
1234                         /* Only support one queue on VFs.
1235                          * RSS together with SRIOV is not supported.
1236                          */
1237                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1238                                         " wrong mq_mode rx %d.",
1239                                         rx_mq_mode);
1240                         return -EINVAL;
1241                 }
1242                 /* TX mode is not used here, so mode might be ignored.*/
1243                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1244                         /* SRIOV only works in VMDq enable mode */
1245                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1246                                         " TX mode %d is not supported. "
1247                                         " Driver will behave as %d mode.",
1248                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1249                 }
1250
1251                 /* check valid queue number */
1252                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1253                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1254                                         " only support one queue on VFs.");
1255                         return -EINVAL;
1256                 }
1257         } else {
1258                 /* To no break software that set invalid mode, only display
1259                  * warning if invalid mode is used.
1260                  */
1261                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1262                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1263                     rx_mq_mode != ETH_MQ_RX_RSS) {
1264                         /* RSS together with VMDq not supported*/
1265                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1266                                      rx_mq_mode);
1267                         return -EINVAL;
1268                 }
1269
1270                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1271                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1272                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1273                                         " Due to txmode is meaningless in this"
1274                                         " driver, just ignore.",
1275                                         tx_mq_mode);
1276                 }
1277         }
1278         return 0;
1279 }
1280
1281 static int
1282 eth_igb_configure(struct rte_eth_dev *dev)
1283 {
1284         struct e1000_interrupt *intr =
1285                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1286         int ret;
1287
1288         PMD_INIT_FUNC_TRACE();
1289
1290         /* multipe queue mode checking */
1291         ret  = igb_check_mq_mode(dev);
1292         if (ret != 0) {
1293                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1294                             ret);
1295                 return ret;
1296         }
1297
1298         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1299         PMD_INIT_FUNC_TRACE();
1300
1301         return 0;
1302 }
1303
1304 static int
1305 eth_igb_start(struct rte_eth_dev *dev)
1306 {
1307         struct e1000_hw *hw =
1308                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1309         struct e1000_adapter *adapter =
1310                 E1000_DEV_PRIVATE(dev->data->dev_private);
1311         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1312         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1313         int ret, mask;
1314         uint32_t intr_vector = 0;
1315         uint32_t ctrl_ext;
1316         uint32_t *speeds;
1317         int num_speeds;
1318         bool autoneg;
1319
1320         PMD_INIT_FUNC_TRACE();
1321
1322         /* disable uio/vfio intr/eventfd mapping */
1323         rte_intr_disable(intr_handle);
1324
1325         /* Power up the phy. Needed to make the link go Up */
1326         eth_igb_dev_set_link_up(dev);
1327
1328         /*
1329          * Packet Buffer Allocation (PBA)
1330          * Writing PBA sets the receive portion of the buffer
1331          * the remainder is used for the transmit buffer.
1332          */
1333         if (hw->mac.type == e1000_82575) {
1334                 uint32_t pba;
1335
1336                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1337                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1338         }
1339
1340         /* Put the address into the Receive Address Array */
1341         e1000_rar_set(hw, hw->mac.addr, 0);
1342
1343         /* Initialize the hardware */
1344         if (igb_hardware_init(hw)) {
1345                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1346                 return -EIO;
1347         }
1348         adapter->stopped = 0;
1349
1350         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1351
1352         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1353         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1354         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1355         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1356         E1000_WRITE_FLUSH(hw);
1357
1358         /* configure PF module if SRIOV enabled */
1359         igb_pf_host_configure(dev);
1360
1361         /* check and configure queue intr-vector mapping */
1362         if ((rte_intr_cap_multiple(intr_handle) ||
1363              !RTE_ETH_DEV_SRIOV(dev).active) &&
1364             dev->data->dev_conf.intr_conf.rxq != 0) {
1365                 intr_vector = dev->data->nb_rx_queues;
1366                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1367                         return -1;
1368         }
1369
1370         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1371                 intr_handle->intr_vec =
1372                         rte_zmalloc("intr_vec",
1373                                     dev->data->nb_rx_queues * sizeof(int), 0);
1374                 if (intr_handle->intr_vec == NULL) {
1375                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1376                                      " intr_vec", dev->data->nb_rx_queues);
1377                         return -ENOMEM;
1378                 }
1379         }
1380
1381         /* confiugre msix for rx interrupt */
1382         eth_igb_configure_msix_intr(dev);
1383
1384         /* Configure for OS presence */
1385         igb_init_manageability(hw);
1386
1387         eth_igb_tx_init(dev);
1388
1389         /* This can fail when allocating mbufs for descriptor rings */
1390         ret = eth_igb_rx_init(dev);
1391         if (ret) {
1392                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1393                 igb_dev_clear_queues(dev);
1394                 return ret;
1395         }
1396
1397         e1000_clear_hw_cntrs_base_generic(hw);
1398
1399         /*
1400          * VLAN Offload Settings
1401          */
1402         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1403                         ETH_VLAN_EXTEND_MASK;
1404         eth_igb_vlan_offload_set(dev, mask);
1405
1406         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1407                 /* Enable VLAN filter since VMDq always use VLAN filter */
1408                 igb_vmdq_vlan_hw_filter_enable(dev);
1409         }
1410
1411         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1412                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1413                 (hw->mac.type == e1000_i211)) {
1414                 /* Configure EITR with the maximum possible value (0xFFFF) */
1415                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1416         }
1417
1418         /* Setup link speed and duplex */
1419         speeds = &dev->data->dev_conf.link_speeds;
1420         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1421                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1422                 hw->mac.autoneg = 1;
1423         } else {
1424                 num_speeds = 0;
1425                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1426
1427                 /* Reset */
1428                 hw->phy.autoneg_advertised = 0;
1429
1430                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1431                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1432                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1433                         num_speeds = -1;
1434                         goto error_invalid_config;
1435                 }
1436                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1437                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1438                         num_speeds++;
1439                 }
1440                 if (*speeds & ETH_LINK_SPEED_10M) {
1441                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1442                         num_speeds++;
1443                 }
1444                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1445                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1446                         num_speeds++;
1447                 }
1448                 if (*speeds & ETH_LINK_SPEED_100M) {
1449                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1450                         num_speeds++;
1451                 }
1452                 if (*speeds & ETH_LINK_SPEED_1G) {
1453                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1454                         num_speeds++;
1455                 }
1456                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1457                         goto error_invalid_config;
1458
1459                 /* Set/reset the mac.autoneg based on the link speed,
1460                  * fixed or not
1461                  */
1462                 if (!autoneg) {
1463                         hw->mac.autoneg = 0;
1464                         hw->mac.forced_speed_duplex =
1465                                         hw->phy.autoneg_advertised;
1466                 } else {
1467                         hw->mac.autoneg = 1;
1468                 }
1469         }
1470
1471         e1000_setup_link(hw);
1472
1473         if (rte_intr_allow_others(intr_handle)) {
1474                 /* check if lsc interrupt is enabled */
1475                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1476                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1477                 else
1478                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1479         } else {
1480                 rte_intr_callback_unregister(intr_handle,
1481                                              eth_igb_interrupt_handler,
1482                                              (void *)dev);
1483                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1484                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1485                                      " no intr multiplex");
1486         }
1487
1488         /* check if rxq interrupt is enabled */
1489         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1490             rte_intr_dp_is_en(intr_handle))
1491                 eth_igb_rxq_interrupt_setup(dev);
1492
1493         /* enable uio/vfio intr/eventfd mapping */
1494         rte_intr_enable(intr_handle);
1495
1496         /* resume enabled intr since hw reset */
1497         igb_intr_enable(dev);
1498
1499         /* restore all types filter */
1500         igb_filter_restore(dev);
1501
1502         PMD_INIT_LOG(DEBUG, "<<");
1503
1504         return 0;
1505
1506 error_invalid_config:
1507         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1508                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1509         igb_dev_clear_queues(dev);
1510         return -EINVAL;
1511 }
1512
1513 /*********************************************************************
1514  *
1515  *  This routine disables all traffic on the adapter by issuing a
1516  *  global reset on the MAC.
1517  *
1518  **********************************************************************/
1519 static void
1520 eth_igb_stop(struct rte_eth_dev *dev)
1521 {
1522         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1523         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1524         struct rte_eth_link link;
1525         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1526
1527         igb_intr_disable(hw);
1528
1529         /* disable intr eventfd mapping */
1530         rte_intr_disable(intr_handle);
1531
1532         igb_pf_reset_hw(hw);
1533         E1000_WRITE_REG(hw, E1000_WUC, 0);
1534
1535         /* Set bit for Go Link disconnect */
1536         if (hw->mac.type >= e1000_82580) {
1537                 uint32_t phpm_reg;
1538
1539                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1540                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1541                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1542         }
1543
1544         /* Power down the phy. Needed to make the link go Down */
1545         eth_igb_dev_set_link_down(dev);
1546
1547         igb_dev_clear_queues(dev);
1548
1549         /* clear the recorded link status */
1550         memset(&link, 0, sizeof(link));
1551         rte_igb_dev_atomic_write_link_status(dev, &link);
1552
1553         if (!rte_intr_allow_others(intr_handle))
1554                 /* resume to the default handler */
1555                 rte_intr_callback_register(intr_handle,
1556                                            eth_igb_interrupt_handler,
1557                                            (void *)dev);
1558
1559         /* Clean datapath event and queue/vec mapping */
1560         rte_intr_efd_disable(intr_handle);
1561         if (intr_handle->intr_vec != NULL) {
1562                 rte_free(intr_handle->intr_vec);
1563                 intr_handle->intr_vec = NULL;
1564         }
1565 }
1566
1567 static int
1568 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1569 {
1570         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1571
1572         if (hw->phy.media_type == e1000_media_type_copper)
1573                 e1000_power_up_phy(hw);
1574         else
1575                 e1000_power_up_fiber_serdes_link(hw);
1576
1577         return 0;
1578 }
1579
1580 static int
1581 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1582 {
1583         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1584
1585         if (hw->phy.media_type == e1000_media_type_copper)
1586                 e1000_power_down_phy(hw);
1587         else
1588                 e1000_shutdown_fiber_serdes_link(hw);
1589
1590         return 0;
1591 }
1592
1593 static void
1594 eth_igb_close(struct rte_eth_dev *dev)
1595 {
1596         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1597         struct e1000_adapter *adapter =
1598                 E1000_DEV_PRIVATE(dev->data->dev_private);
1599         struct rte_eth_link link;
1600         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1601         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1602
1603         eth_igb_stop(dev);
1604         adapter->stopped = 1;
1605
1606         e1000_phy_hw_reset(hw);
1607         igb_release_manageability(hw);
1608         igb_hw_control_release(hw);
1609
1610         /* Clear bit for Go Link disconnect */
1611         if (hw->mac.type >= e1000_82580) {
1612                 uint32_t phpm_reg;
1613
1614                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1615                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1616                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1617         }
1618
1619         igb_dev_free_queues(dev);
1620
1621         if (intr_handle->intr_vec) {
1622                 rte_free(intr_handle->intr_vec);
1623                 intr_handle->intr_vec = NULL;
1624         }
1625
1626         memset(&link, 0, sizeof(link));
1627         rte_igb_dev_atomic_write_link_status(dev, &link);
1628 }
1629
1630 static int
1631 igb_get_rx_buffer_size(struct e1000_hw *hw)
1632 {
1633         uint32_t rx_buf_size;
1634         if (hw->mac.type == e1000_82576) {
1635                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1636         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1637                 /* PBS needs to be translated according to a lookup table */
1638                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1639                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1640                 rx_buf_size = (rx_buf_size << 10);
1641         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1642                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1643         } else {
1644                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1645         }
1646
1647         return rx_buf_size;
1648 }
1649
1650 /*********************************************************************
1651  *
1652  *  Initialize the hardware
1653  *
1654  **********************************************************************/
1655 static int
1656 igb_hardware_init(struct e1000_hw *hw)
1657 {
1658         uint32_t rx_buf_size;
1659         int diag;
1660
1661         /* Let the firmware know the OS is in control */
1662         igb_hw_control_acquire(hw);
1663
1664         /*
1665          * These parameters control the automatic generation (Tx) and
1666          * response (Rx) to Ethernet PAUSE frames.
1667          * - High water mark should allow for at least two standard size (1518)
1668          *   frames to be received after sending an XOFF.
1669          * - Low water mark works best when it is very near the high water mark.
1670          *   This allows the receiver to restart by sending XON when it has
1671          *   drained a bit. Here we use an arbitrary value of 1500 which will
1672          *   restart after one full frame is pulled from the buffer. There
1673          *   could be several smaller frames in the buffer and if so they will
1674          *   not trigger the XON until their total number reduces the buffer
1675          *   by 1500.
1676          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1677          */
1678         rx_buf_size = igb_get_rx_buffer_size(hw);
1679
1680         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1681         hw->fc.low_water = hw->fc.high_water - 1500;
1682         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1683         hw->fc.send_xon = 1;
1684
1685         /* Set Flow control, use the tunable location if sane */
1686         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1687                 hw->fc.requested_mode = igb_fc_setting;
1688         else
1689                 hw->fc.requested_mode = e1000_fc_none;
1690
1691         /* Issue a global reset */
1692         igb_pf_reset_hw(hw);
1693         E1000_WRITE_REG(hw, E1000_WUC, 0);
1694
1695         diag = e1000_init_hw(hw);
1696         if (diag < 0)
1697                 return diag;
1698
1699         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1700         e1000_get_phy_info(hw);
1701         e1000_check_for_link(hw);
1702
1703         return 0;
1704 }
1705
1706 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1707 static void
1708 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1709 {
1710         int pause_frames;
1711
1712         uint64_t old_gprc  = stats->gprc;
1713         uint64_t old_gptc  = stats->gptc;
1714         uint64_t old_tpr   = stats->tpr;
1715         uint64_t old_tpt   = stats->tpt;
1716         uint64_t old_rpthc = stats->rpthc;
1717         uint64_t old_hgptc = stats->hgptc;
1718
1719         if(hw->phy.media_type == e1000_media_type_copper ||
1720             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1721                 stats->symerrs +=
1722                     E1000_READ_REG(hw,E1000_SYMERRS);
1723                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1724         }
1725
1726         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1727         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1728         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1729         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1730
1731         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1732         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1733         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1734         stats->dc += E1000_READ_REG(hw, E1000_DC);
1735         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1736         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1737         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1738         /*
1739         ** For watchdog management we need to know if we have been
1740         ** paused during the last interval, so capture that here.
1741         */
1742         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1743         stats->xoffrxc += pause_frames;
1744         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1745         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1746         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1747         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1748         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1749         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1750         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1751         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1752         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1753         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1754         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1755         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1756
1757         /* For the 64-bit byte counters the low dword must be read first. */
1758         /* Both registers clear on the read of the high dword */
1759
1760         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1761         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1762         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1763         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1764         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1765         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1766         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1767
1768         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1769         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1770         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1771         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1772         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1773
1774         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1775         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1776
1777         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1778         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1779         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1780         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1781         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1782         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1783
1784         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1785         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1786         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1787         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1788         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1789         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1790         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1791         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1792
1793         /* Interrupt Counts */
1794
1795         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1796         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1797         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1798         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1799         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1800         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1801         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1802         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1803         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1804
1805         /* Host to Card Statistics */
1806
1807         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1808         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1809         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1810         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1811         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1812         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1813         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1814         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1815         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1816         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1817         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1818         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1819         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1820         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1821         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1822         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1823
1824         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1825         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1826         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1827         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1828         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1829         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1830 }
1831
1832 static int
1833 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1834 {
1835         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1836         struct e1000_hw_stats *stats =
1837                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1838
1839         igb_read_stats_registers(hw, stats);
1840
1841         if (rte_stats == NULL)
1842                 return -EINVAL;
1843
1844         /* Rx Errors */
1845         rte_stats->imissed = stats->mpc;
1846         rte_stats->ierrors = stats->crcerrs +
1847                              stats->rlec + stats->ruc + stats->roc +
1848                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1849
1850         /* Tx Errors */
1851         rte_stats->oerrors = stats->ecol + stats->latecol;
1852
1853         rte_stats->ipackets = stats->gprc;
1854         rte_stats->opackets = stats->gptc;
1855         rte_stats->ibytes   = stats->gorc;
1856         rte_stats->obytes   = stats->gotc;
1857         return 0;
1858 }
1859
1860 static void
1861 eth_igb_stats_reset(struct rte_eth_dev *dev)
1862 {
1863         struct e1000_hw_stats *hw_stats =
1864                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1865
1866         /* HW registers are cleared on read */
1867         eth_igb_stats_get(dev, NULL);
1868
1869         /* Reset software totals */
1870         memset(hw_stats, 0, sizeof(*hw_stats));
1871 }
1872
1873 static void
1874 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1875 {
1876         struct e1000_hw_stats *stats =
1877                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1878
1879         /* HW registers are cleared on read */
1880         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1881
1882         /* Reset software totals */
1883         memset(stats, 0, sizeof(*stats));
1884 }
1885
1886 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1887         struct rte_eth_xstat_name *xstats_names,
1888         __rte_unused unsigned int size)
1889 {
1890         unsigned i;
1891
1892         if (xstats_names == NULL)
1893                 return IGB_NB_XSTATS;
1894
1895         /* Note: limit checked in rte_eth_xstats_names() */
1896
1897         for (i = 0; i < IGB_NB_XSTATS; i++) {
1898                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1899                          "%s", rte_igb_stats_strings[i].name);
1900         }
1901
1902         return IGB_NB_XSTATS;
1903 }
1904
1905 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1906                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1907                 unsigned int limit)
1908 {
1909         unsigned int i;
1910
1911         if (!ids) {
1912                 if (xstats_names == NULL)
1913                         return IGB_NB_XSTATS;
1914
1915                 for (i = 0; i < IGB_NB_XSTATS; i++)
1916                         snprintf(xstats_names[i].name,
1917                                         sizeof(xstats_names[i].name),
1918                                         "%s", rte_igb_stats_strings[i].name);
1919
1920                 return IGB_NB_XSTATS;
1921
1922         } else {
1923                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1924
1925                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1926                                 IGB_NB_XSTATS);
1927
1928                 for (i = 0; i < limit; i++) {
1929                         if (ids[i] >= IGB_NB_XSTATS) {
1930                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1931                                 return -1;
1932                         }
1933                         strcpy(xstats_names[i].name,
1934                                         xstats_names_copy[ids[i]].name);
1935                 }
1936                 return limit;
1937         }
1938 }
1939
1940 static int
1941 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1942                    unsigned n)
1943 {
1944         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1945         struct e1000_hw_stats *hw_stats =
1946                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1947         unsigned i;
1948
1949         if (n < IGB_NB_XSTATS)
1950                 return IGB_NB_XSTATS;
1951
1952         igb_read_stats_registers(hw, hw_stats);
1953
1954         /* If this is a reset xstats is NULL, and we have cleared the
1955          * registers by reading them.
1956          */
1957         if (!xstats)
1958                 return 0;
1959
1960         /* Extended stats */
1961         for (i = 0; i < IGB_NB_XSTATS; i++) {
1962                 xstats[i].id = i;
1963                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1964                         rte_igb_stats_strings[i].offset);
1965         }
1966
1967         return IGB_NB_XSTATS;
1968 }
1969
1970 static int
1971 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1972                 uint64_t *values, unsigned int n)
1973 {
1974         unsigned int i;
1975
1976         if (!ids) {
1977                 struct e1000_hw *hw =
1978                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1979                 struct e1000_hw_stats *hw_stats =
1980                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1981
1982                 if (n < IGB_NB_XSTATS)
1983                         return IGB_NB_XSTATS;
1984
1985                 igb_read_stats_registers(hw, hw_stats);
1986
1987                 /* If this is a reset xstats is NULL, and we have cleared the
1988                  * registers by reading them.
1989                  */
1990                 if (!values)
1991                         return 0;
1992
1993                 /* Extended stats */
1994                 for (i = 0; i < IGB_NB_XSTATS; i++)
1995                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1996                                         rte_igb_stats_strings[i].offset);
1997
1998                 return IGB_NB_XSTATS;
1999
2000         } else {
2001                 uint64_t values_copy[IGB_NB_XSTATS];
2002
2003                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2004                                 IGB_NB_XSTATS);
2005
2006                 for (i = 0; i < n; i++) {
2007                         if (ids[i] >= IGB_NB_XSTATS) {
2008                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2009                                 return -1;
2010                         }
2011                         values[i] = values_copy[ids[i]];
2012                 }
2013                 return n;
2014         }
2015 }
2016
2017 static void
2018 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2019 {
2020         /* Good Rx packets, include VF loopback */
2021         UPDATE_VF_STAT(E1000_VFGPRC,
2022             hw_stats->last_gprc, hw_stats->gprc);
2023
2024         /* Good Rx octets, include VF loopback */
2025         UPDATE_VF_STAT(E1000_VFGORC,
2026             hw_stats->last_gorc, hw_stats->gorc);
2027
2028         /* Good Tx packets, include VF loopback */
2029         UPDATE_VF_STAT(E1000_VFGPTC,
2030             hw_stats->last_gptc, hw_stats->gptc);
2031
2032         /* Good Tx octets, include VF loopback */
2033         UPDATE_VF_STAT(E1000_VFGOTC,
2034             hw_stats->last_gotc, hw_stats->gotc);
2035
2036         /* Rx Multicst packets */
2037         UPDATE_VF_STAT(E1000_VFMPRC,
2038             hw_stats->last_mprc, hw_stats->mprc);
2039
2040         /* Good Rx loopback packets */
2041         UPDATE_VF_STAT(E1000_VFGPRLBC,
2042             hw_stats->last_gprlbc, hw_stats->gprlbc);
2043
2044         /* Good Rx loopback octets */
2045         UPDATE_VF_STAT(E1000_VFGORLBC,
2046             hw_stats->last_gorlbc, hw_stats->gorlbc);
2047
2048         /* Good Tx loopback packets */
2049         UPDATE_VF_STAT(E1000_VFGPTLBC,
2050             hw_stats->last_gptlbc, hw_stats->gptlbc);
2051
2052         /* Good Tx loopback octets */
2053         UPDATE_VF_STAT(E1000_VFGOTLBC,
2054             hw_stats->last_gotlbc, hw_stats->gotlbc);
2055 }
2056
2057 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2058                                      struct rte_eth_xstat_name *xstats_names,
2059                                      __rte_unused unsigned limit)
2060 {
2061         unsigned i;
2062
2063         if (xstats_names != NULL)
2064                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2065                         snprintf(xstats_names[i].name,
2066                                 sizeof(xstats_names[i].name), "%s",
2067                                 rte_igbvf_stats_strings[i].name);
2068                 }
2069         return IGBVF_NB_XSTATS;
2070 }
2071
2072 static int
2073 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2074                      unsigned n)
2075 {
2076         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2078                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2079         unsigned i;
2080
2081         if (n < IGBVF_NB_XSTATS)
2082                 return IGBVF_NB_XSTATS;
2083
2084         igbvf_read_stats_registers(hw, hw_stats);
2085
2086         if (!xstats)
2087                 return 0;
2088
2089         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2090                 xstats[i].id = i;
2091                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2092                         rte_igbvf_stats_strings[i].offset);
2093         }
2094
2095         return IGBVF_NB_XSTATS;
2096 }
2097
2098 static int
2099 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2100 {
2101         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2102         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2103                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2104
2105         igbvf_read_stats_registers(hw, hw_stats);
2106
2107         if (rte_stats == NULL)
2108                 return -EINVAL;
2109
2110         rte_stats->ipackets = hw_stats->gprc;
2111         rte_stats->ibytes = hw_stats->gorc;
2112         rte_stats->opackets = hw_stats->gptc;
2113         rte_stats->obytes = hw_stats->gotc;
2114         return 0;
2115 }
2116
2117 static void
2118 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2119 {
2120         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2121                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2122
2123         /* Sync HW register to the last stats */
2124         eth_igbvf_stats_get(dev, NULL);
2125
2126         /* reset HW current stats*/
2127         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2128                offsetof(struct e1000_vf_stats, gprc));
2129 }
2130
2131 static int
2132 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2133                        size_t fw_size)
2134 {
2135         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2136         struct e1000_fw_version fw;
2137         int ret;
2138
2139         e1000_get_fw_version(hw, &fw);
2140
2141         switch (hw->mac.type) {
2142         case e1000_i210:
2143         case e1000_i211:
2144                 if (!(e1000_get_flash_presence_i210(hw))) {
2145                         ret = snprintf(fw_version, fw_size,
2146                                  "%2d.%2d-%d",
2147                                  fw.invm_major, fw.invm_minor,
2148                                  fw.invm_img_type);
2149                         break;
2150                 }
2151                 /* fall through */
2152         default:
2153                 /* if option rom is valid, display its version too */
2154                 if (fw.or_valid) {
2155                         ret = snprintf(fw_version, fw_size,
2156                                  "%d.%d, 0x%08x, %d.%d.%d",
2157                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2158                                  fw.or_major, fw.or_build, fw.or_patch);
2159                 /* no option rom */
2160                 } else {
2161                         if (fw.etrack_id != 0X0000) {
2162                                 ret = snprintf(fw_version, fw_size,
2163                                          "%d.%d, 0x%08x",
2164                                          fw.eep_major, fw.eep_minor,
2165                                          fw.etrack_id);
2166                         } else {
2167                                 ret = snprintf(fw_version, fw_size,
2168                                          "%d.%d.%d",
2169                                          fw.eep_major, fw.eep_minor,
2170                                          fw.eep_build);
2171                         }
2172                 }
2173                 break;
2174         }
2175
2176         ret += 1; /* add the size of '\0' */
2177         if (fw_size < (u32)ret)
2178                 return ret;
2179         else
2180                 return 0;
2181 }
2182
2183 static void
2184 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2185 {
2186         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2187
2188         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2189         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2190         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2191         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2192         dev_info->rx_offload_capa =
2193                 DEV_RX_OFFLOAD_VLAN_STRIP |
2194                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2195                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2196                 DEV_RX_OFFLOAD_TCP_CKSUM;
2197         dev_info->tx_offload_capa =
2198                 DEV_TX_OFFLOAD_VLAN_INSERT |
2199                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2200                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2201                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2202                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2203                 DEV_TX_OFFLOAD_TCP_TSO;
2204
2205         switch (hw->mac.type) {
2206         case e1000_82575:
2207                 dev_info->max_rx_queues = 4;
2208                 dev_info->max_tx_queues = 4;
2209                 dev_info->max_vmdq_pools = 0;
2210                 break;
2211
2212         case e1000_82576:
2213                 dev_info->max_rx_queues = 16;
2214                 dev_info->max_tx_queues = 16;
2215                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2216                 dev_info->vmdq_queue_num = 16;
2217                 break;
2218
2219         case e1000_82580:
2220                 dev_info->max_rx_queues = 8;
2221                 dev_info->max_tx_queues = 8;
2222                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2223                 dev_info->vmdq_queue_num = 8;
2224                 break;
2225
2226         case e1000_i350:
2227                 dev_info->max_rx_queues = 8;
2228                 dev_info->max_tx_queues = 8;
2229                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2230                 dev_info->vmdq_queue_num = 8;
2231                 break;
2232
2233         case e1000_i354:
2234                 dev_info->max_rx_queues = 8;
2235                 dev_info->max_tx_queues = 8;
2236                 break;
2237
2238         case e1000_i210:
2239                 dev_info->max_rx_queues = 4;
2240                 dev_info->max_tx_queues = 4;
2241                 dev_info->max_vmdq_pools = 0;
2242                 break;
2243
2244         case e1000_i211:
2245                 dev_info->max_rx_queues = 2;
2246                 dev_info->max_tx_queues = 2;
2247                 dev_info->max_vmdq_pools = 0;
2248                 break;
2249
2250         default:
2251                 /* Should not happen */
2252                 break;
2253         }
2254         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2255         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2256         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2257
2258         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2259                 .rx_thresh = {
2260                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2261                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2262                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2263                 },
2264                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2265                 .rx_drop_en = 0,
2266         };
2267
2268         dev_info->default_txconf = (struct rte_eth_txconf) {
2269                 .tx_thresh = {
2270                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2271                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2272                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2273                 },
2274                 .txq_flags = 0,
2275         };
2276
2277         dev_info->rx_desc_lim = rx_desc_lim;
2278         dev_info->tx_desc_lim = tx_desc_lim;
2279
2280         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2281                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2282                         ETH_LINK_SPEED_1G;
2283 }
2284
2285 static const uint32_t *
2286 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2287 {
2288         static const uint32_t ptypes[] = {
2289                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2290                 RTE_PTYPE_L2_ETHER,
2291                 RTE_PTYPE_L3_IPV4,
2292                 RTE_PTYPE_L3_IPV4_EXT,
2293                 RTE_PTYPE_L3_IPV6,
2294                 RTE_PTYPE_L3_IPV6_EXT,
2295                 RTE_PTYPE_L4_TCP,
2296                 RTE_PTYPE_L4_UDP,
2297                 RTE_PTYPE_L4_SCTP,
2298                 RTE_PTYPE_TUNNEL_IP,
2299                 RTE_PTYPE_INNER_L3_IPV6,
2300                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2301                 RTE_PTYPE_INNER_L4_TCP,
2302                 RTE_PTYPE_INNER_L4_UDP,
2303                 RTE_PTYPE_UNKNOWN
2304         };
2305
2306         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2307             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2308                 return ptypes;
2309         return NULL;
2310 }
2311
2312 static void
2313 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2314 {
2315         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2316
2317         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2318         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2319         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2320         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2321         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2322                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2323                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2324                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2325         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2326                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2327                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2328                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2329                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2330                                 DEV_TX_OFFLOAD_TCP_TSO;
2331         switch (hw->mac.type) {
2332         case e1000_vfadapt:
2333                 dev_info->max_rx_queues = 2;
2334                 dev_info->max_tx_queues = 2;
2335                 break;
2336         case e1000_vfadapt_i350:
2337                 dev_info->max_rx_queues = 1;
2338                 dev_info->max_tx_queues = 1;
2339                 break;
2340         default:
2341                 /* Should not happen */
2342                 break;
2343         }
2344
2345         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2346                 .rx_thresh = {
2347                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2348                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2349                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2350                 },
2351                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2352                 .rx_drop_en = 0,
2353         };
2354
2355         dev_info->default_txconf = (struct rte_eth_txconf) {
2356                 .tx_thresh = {
2357                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2358                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2359                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2360                 },
2361                 .txq_flags = 0,
2362         };
2363
2364         dev_info->rx_desc_lim = rx_desc_lim;
2365         dev_info->tx_desc_lim = tx_desc_lim;
2366 }
2367
2368 /* return 0 means link status changed, -1 means not changed */
2369 static int
2370 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2371 {
2372         struct e1000_hw *hw =
2373                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2374         struct rte_eth_link link, old;
2375         int link_check, count;
2376
2377         link_check = 0;
2378         hw->mac.get_link_status = 1;
2379
2380         /* possible wait-to-complete in up to 9 seconds */
2381         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2382                 /* Read the real link status */
2383                 switch (hw->phy.media_type) {
2384                 case e1000_media_type_copper:
2385                         /* Do the work to read phy */
2386                         e1000_check_for_link(hw);
2387                         link_check = !hw->mac.get_link_status;
2388                         break;
2389
2390                 case e1000_media_type_fiber:
2391                         e1000_check_for_link(hw);
2392                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2393                                       E1000_STATUS_LU);
2394                         break;
2395
2396                 case e1000_media_type_internal_serdes:
2397                         e1000_check_for_link(hw);
2398                         link_check = hw->mac.serdes_has_link;
2399                         break;
2400
2401                 /* VF device is type_unknown */
2402                 case e1000_media_type_unknown:
2403                         eth_igbvf_link_update(hw);
2404                         link_check = !hw->mac.get_link_status;
2405                         break;
2406
2407                 default:
2408                         break;
2409                 }
2410                 if (link_check || wait_to_complete == 0)
2411                         break;
2412                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2413         }
2414         memset(&link, 0, sizeof(link));
2415         rte_igb_dev_atomic_read_link_status(dev, &link);
2416         old = link;
2417
2418         /* Now we check if a transition has happened */
2419         if (link_check) {
2420                 uint16_t duplex, speed;
2421                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2422                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2423                                 ETH_LINK_FULL_DUPLEX :
2424                                 ETH_LINK_HALF_DUPLEX;
2425                 link.link_speed = speed;
2426                 link.link_status = ETH_LINK_UP;
2427                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2428                                 ETH_LINK_SPEED_FIXED);
2429         } else if (!link_check) {
2430                 link.link_speed = 0;
2431                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2432                 link.link_status = ETH_LINK_DOWN;
2433                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2434         }
2435         rte_igb_dev_atomic_write_link_status(dev, &link);
2436
2437         /* not changed */
2438         if (old.link_status == link.link_status)
2439                 return -1;
2440
2441         /* changed */
2442         return 0;
2443 }
2444
2445 /*
2446  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2447  * For ASF and Pass Through versions of f/w this means
2448  * that the driver is loaded.
2449  */
2450 static void
2451 igb_hw_control_acquire(struct e1000_hw *hw)
2452 {
2453         uint32_t ctrl_ext;
2454
2455         /* Let firmware know the driver has taken over */
2456         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2457         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2458 }
2459
2460 /*
2461  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2462  * For ASF and Pass Through versions of f/w this means that the
2463  * driver is no longer loaded.
2464  */
2465 static void
2466 igb_hw_control_release(struct e1000_hw *hw)
2467 {
2468         uint32_t ctrl_ext;
2469
2470         /* Let firmware taken over control of h/w */
2471         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2472         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2473                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2474 }
2475
2476 /*
2477  * Bit of a misnomer, what this really means is
2478  * to enable OS management of the system... aka
2479  * to disable special hardware management features.
2480  */
2481 static void
2482 igb_init_manageability(struct e1000_hw *hw)
2483 {
2484         if (e1000_enable_mng_pass_thru(hw)) {
2485                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2486                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2487
2488                 /* disable hardware interception of ARP */
2489                 manc &= ~(E1000_MANC_ARP_EN);
2490
2491                 /* enable receiving management packets to the host */
2492                 manc |= E1000_MANC_EN_MNG2HOST;
2493                 manc2h |= 1 << 5;  /* Mng Port 623 */
2494                 manc2h |= 1 << 6;  /* Mng Port 664 */
2495                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2496                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2497         }
2498 }
2499
2500 static void
2501 igb_release_manageability(struct e1000_hw *hw)
2502 {
2503         if (e1000_enable_mng_pass_thru(hw)) {
2504                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2505
2506                 manc |= E1000_MANC_ARP_EN;
2507                 manc &= ~E1000_MANC_EN_MNG2HOST;
2508
2509                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2510         }
2511 }
2512
2513 static void
2514 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2515 {
2516         struct e1000_hw *hw =
2517                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2518         uint32_t rctl;
2519
2520         rctl = E1000_READ_REG(hw, E1000_RCTL);
2521         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2522         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2523 }
2524
2525 static void
2526 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2527 {
2528         struct e1000_hw *hw =
2529                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2530         uint32_t rctl;
2531
2532         rctl = E1000_READ_REG(hw, E1000_RCTL);
2533         rctl &= (~E1000_RCTL_UPE);
2534         if (dev->data->all_multicast == 1)
2535                 rctl |= E1000_RCTL_MPE;
2536         else
2537                 rctl &= (~E1000_RCTL_MPE);
2538         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2539 }
2540
2541 static void
2542 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2543 {
2544         struct e1000_hw *hw =
2545                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2546         uint32_t rctl;
2547
2548         rctl = E1000_READ_REG(hw, E1000_RCTL);
2549         rctl |= E1000_RCTL_MPE;
2550         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2551 }
2552
2553 static void
2554 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2555 {
2556         struct e1000_hw *hw =
2557                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2558         uint32_t rctl;
2559
2560         if (dev->data->promiscuous == 1)
2561                 return; /* must remain in all_multicast mode */
2562         rctl = E1000_READ_REG(hw, E1000_RCTL);
2563         rctl &= (~E1000_RCTL_MPE);
2564         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2565 }
2566
2567 static int
2568 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2569 {
2570         struct e1000_hw *hw =
2571                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2572         struct e1000_vfta * shadow_vfta =
2573                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2574         uint32_t vfta;
2575         uint32_t vid_idx;
2576         uint32_t vid_bit;
2577
2578         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2579                               E1000_VFTA_ENTRY_MASK);
2580         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2581         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2582         if (on)
2583                 vfta |= vid_bit;
2584         else
2585                 vfta &= ~vid_bit;
2586         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2587
2588         /* update local VFTA copy */
2589         shadow_vfta->vfta[vid_idx] = vfta;
2590
2591         return 0;
2592 }
2593
2594 static int
2595 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2596                       enum rte_vlan_type vlan_type,
2597                       uint16_t tpid)
2598 {
2599         struct e1000_hw *hw =
2600                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2601         uint32_t reg, qinq;
2602
2603         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2604         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2605
2606         /* only outer TPID of double VLAN can be configured*/
2607         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2608                 reg = E1000_READ_REG(hw, E1000_VET);
2609                 reg = (reg & (~E1000_VET_VET_EXT)) |
2610                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2611                 E1000_WRITE_REG(hw, E1000_VET, reg);
2612
2613                 return 0;
2614         }
2615
2616         /* all other TPID values are read-only*/
2617         PMD_DRV_LOG(ERR, "Not supported");
2618
2619         return -ENOTSUP;
2620 }
2621
2622 static void
2623 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2624 {
2625         struct e1000_hw *hw =
2626                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2627         uint32_t reg;
2628
2629         /* Filter Table Disable */
2630         reg = E1000_READ_REG(hw, E1000_RCTL);
2631         reg &= ~E1000_RCTL_CFIEN;
2632         reg &= ~E1000_RCTL_VFE;
2633         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2634 }
2635
2636 static void
2637 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2638 {
2639         struct e1000_hw *hw =
2640                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2641         struct e1000_vfta * shadow_vfta =
2642                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2643         uint32_t reg;
2644         int i;
2645
2646         /* Filter Table Enable, CFI not used for packet acceptance */
2647         reg = E1000_READ_REG(hw, E1000_RCTL);
2648         reg &= ~E1000_RCTL_CFIEN;
2649         reg |= E1000_RCTL_VFE;
2650         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2651
2652         /* restore VFTA table */
2653         for (i = 0; i < IGB_VFTA_SIZE; i++)
2654                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2655 }
2656
2657 static void
2658 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2659 {
2660         struct e1000_hw *hw =
2661                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2662         uint32_t reg;
2663
2664         /* VLAN Mode Disable */
2665         reg = E1000_READ_REG(hw, E1000_CTRL);
2666         reg &= ~E1000_CTRL_VME;
2667         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2668 }
2669
2670 static void
2671 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2672 {
2673         struct e1000_hw *hw =
2674                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2675         uint32_t reg;
2676
2677         /* VLAN Mode Enable */
2678         reg = E1000_READ_REG(hw, E1000_CTRL);
2679         reg |= E1000_CTRL_VME;
2680         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2681 }
2682
2683 static void
2684 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2685 {
2686         struct e1000_hw *hw =
2687                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2688         uint32_t reg;
2689
2690         /* CTRL_EXT: Extended VLAN */
2691         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2692         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2693         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2694
2695         /* Update maximum packet length */
2696         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2697                 E1000_WRITE_REG(hw, E1000_RLPML,
2698                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2699                                                 VLAN_TAG_SIZE);
2700 }
2701
2702 static void
2703 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2704 {
2705         struct e1000_hw *hw =
2706                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2707         uint32_t reg;
2708
2709         /* CTRL_EXT: Extended VLAN */
2710         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2711         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2712         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2713
2714         /* Update maximum packet length */
2715         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2716                 E1000_WRITE_REG(hw, E1000_RLPML,
2717                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2718                                                 2 * VLAN_TAG_SIZE);
2719 }
2720
2721 static void
2722 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2723 {
2724         if(mask & ETH_VLAN_STRIP_MASK){
2725                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2726                         igb_vlan_hw_strip_enable(dev);
2727                 else
2728                         igb_vlan_hw_strip_disable(dev);
2729         }
2730
2731         if(mask & ETH_VLAN_FILTER_MASK){
2732                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2733                         igb_vlan_hw_filter_enable(dev);
2734                 else
2735                         igb_vlan_hw_filter_disable(dev);
2736         }
2737
2738         if(mask & ETH_VLAN_EXTEND_MASK){
2739                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2740                         igb_vlan_hw_extend_enable(dev);
2741                 else
2742                         igb_vlan_hw_extend_disable(dev);
2743         }
2744 }
2745
2746
2747 /**
2748  * It enables the interrupt mask and then enable the interrupt.
2749  *
2750  * @param dev
2751  *  Pointer to struct rte_eth_dev.
2752  * @param on
2753  *  Enable or Disable
2754  *
2755  * @return
2756  *  - On success, zero.
2757  *  - On failure, a negative value.
2758  */
2759 static int
2760 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2761 {
2762         struct e1000_interrupt *intr =
2763                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2764
2765         if (on)
2766                 intr->mask |= E1000_ICR_LSC;
2767         else
2768                 intr->mask &= ~E1000_ICR_LSC;
2769
2770         return 0;
2771 }
2772
2773 /* It clears the interrupt causes and enables the interrupt.
2774  * It will be called once only during nic initialized.
2775  *
2776  * @param dev
2777  *  Pointer to struct rte_eth_dev.
2778  *
2779  * @return
2780  *  - On success, zero.
2781  *  - On failure, a negative value.
2782  */
2783 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2784 {
2785         uint32_t mask, regval;
2786         struct e1000_hw *hw =
2787                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2788         struct rte_eth_dev_info dev_info;
2789
2790         memset(&dev_info, 0, sizeof(dev_info));
2791         eth_igb_infos_get(dev, &dev_info);
2792
2793         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2794         regval = E1000_READ_REG(hw, E1000_EIMS);
2795         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2796
2797         return 0;
2798 }
2799
2800 /*
2801  * It reads ICR and gets interrupt causes, check it and set a bit flag
2802  * to update link status.
2803  *
2804  * @param dev
2805  *  Pointer to struct rte_eth_dev.
2806  *
2807  * @return
2808  *  - On success, zero.
2809  *  - On failure, a negative value.
2810  */
2811 static int
2812 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2813 {
2814         uint32_t icr;
2815         struct e1000_hw *hw =
2816                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2817         struct e1000_interrupt *intr =
2818                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2819
2820         igb_intr_disable(hw);
2821
2822         /* read-on-clear nic registers here */
2823         icr = E1000_READ_REG(hw, E1000_ICR);
2824
2825         intr->flags = 0;
2826         if (icr & E1000_ICR_LSC) {
2827                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2828         }
2829
2830         if (icr & E1000_ICR_VMMB)
2831                 intr->flags |= E1000_FLAG_MAILBOX;
2832
2833         return 0;
2834 }
2835
2836 /*
2837  * It executes link_update after knowing an interrupt is prsent.
2838  *
2839  * @param dev
2840  *  Pointer to struct rte_eth_dev.
2841  *
2842  * @return
2843  *  - On success, zero.
2844  *  - On failure, a negative value.
2845  */
2846 static int
2847 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2848                          struct rte_intr_handle *intr_handle)
2849 {
2850         struct e1000_hw *hw =
2851                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2852         struct e1000_interrupt *intr =
2853                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2854         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2855         uint32_t tctl, rctl;
2856         struct rte_eth_link link;
2857         int ret;
2858
2859         if (intr->flags & E1000_FLAG_MAILBOX) {
2860                 igb_pf_mbx_process(dev);
2861                 intr->flags &= ~E1000_FLAG_MAILBOX;
2862         }
2863
2864         igb_intr_enable(dev);
2865         rte_intr_enable(intr_handle);
2866
2867         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2868                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2869
2870                 /* set get_link_status to check register later */
2871                 hw->mac.get_link_status = 1;
2872                 ret = eth_igb_link_update(dev, 0);
2873
2874                 /* check if link has changed */
2875                 if (ret < 0)
2876                         return 0;
2877
2878                 memset(&link, 0, sizeof(link));
2879                 rte_igb_dev_atomic_read_link_status(dev, &link);
2880                 if (link.link_status) {
2881                         PMD_INIT_LOG(INFO,
2882                                      " Port %d: Link Up - speed %u Mbps - %s",
2883                                      dev->data->port_id,
2884                                      (unsigned)link.link_speed,
2885                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2886                                      "full-duplex" : "half-duplex");
2887                 } else {
2888                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2889                                      dev->data->port_id);
2890                 }
2891
2892                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2893                              pci_dev->addr.domain,
2894                              pci_dev->addr.bus,
2895                              pci_dev->addr.devid,
2896                              pci_dev->addr.function);
2897                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2898                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2899                 if (link.link_status) {
2900                         /* enable Tx/Rx */
2901                         tctl |= E1000_TCTL_EN;
2902                         rctl |= E1000_RCTL_EN;
2903                 } else {
2904                         /* disable Tx/Rx */
2905                         tctl &= ~E1000_TCTL_EN;
2906                         rctl &= ~E1000_RCTL_EN;
2907                 }
2908                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2909                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2910                 E1000_WRITE_FLUSH(hw);
2911                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2912                                               NULL, NULL);
2913         }
2914
2915         return 0;
2916 }
2917
2918 /**
2919  * Interrupt handler which shall be registered at first.
2920  *
2921  * @param handle
2922  *  Pointer to interrupt handle.
2923  * @param param
2924  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2925  *
2926  * @return
2927  *  void
2928  */
2929 static void
2930 eth_igb_interrupt_handler(void *param)
2931 {
2932         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2933
2934         eth_igb_interrupt_get_status(dev);
2935         eth_igb_interrupt_action(dev, dev->intr_handle);
2936 }
2937
2938 static int
2939 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2940 {
2941         uint32_t eicr;
2942         struct e1000_hw *hw =
2943                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2944         struct e1000_interrupt *intr =
2945                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2946
2947         igbvf_intr_disable(hw);
2948
2949         /* read-on-clear nic registers here */
2950         eicr = E1000_READ_REG(hw, E1000_EICR);
2951         intr->flags = 0;
2952
2953         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2954                 intr->flags |= E1000_FLAG_MAILBOX;
2955
2956         return 0;
2957 }
2958
2959 void igbvf_mbx_process(struct rte_eth_dev *dev)
2960 {
2961         struct e1000_hw *hw =
2962                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2963         struct e1000_mbx_info *mbx = &hw->mbx;
2964         u32 in_msg = 0;
2965
2966         if (mbx->ops.read(hw, &in_msg, 1, 0))
2967                 return;
2968
2969         /* PF reset VF event */
2970         if (in_msg == E1000_PF_CONTROL_MSG)
2971                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2972                                               NULL, NULL);
2973 }
2974
2975 static int
2976 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2977 {
2978         struct e1000_interrupt *intr =
2979                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2980
2981         if (intr->flags & E1000_FLAG_MAILBOX) {
2982                 igbvf_mbx_process(dev);
2983                 intr->flags &= ~E1000_FLAG_MAILBOX;
2984         }
2985
2986         igbvf_intr_enable(dev);
2987         rte_intr_enable(intr_handle);
2988
2989         return 0;
2990 }
2991
2992 static void
2993 eth_igbvf_interrupt_handler(void *param)
2994 {
2995         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2996
2997         eth_igbvf_interrupt_get_status(dev);
2998         eth_igbvf_interrupt_action(dev, dev->intr_handle);
2999 }
3000
3001 static int
3002 eth_igb_led_on(struct rte_eth_dev *dev)
3003 {
3004         struct e1000_hw *hw;
3005
3006         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3007         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3008 }
3009
3010 static int
3011 eth_igb_led_off(struct rte_eth_dev *dev)
3012 {
3013         struct e1000_hw *hw;
3014
3015         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3016         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3017 }
3018
3019 static int
3020 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3021 {
3022         struct e1000_hw *hw;
3023         uint32_t ctrl;
3024         int tx_pause;
3025         int rx_pause;
3026
3027         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3028         fc_conf->pause_time = hw->fc.pause_time;
3029         fc_conf->high_water = hw->fc.high_water;
3030         fc_conf->low_water = hw->fc.low_water;
3031         fc_conf->send_xon = hw->fc.send_xon;
3032         fc_conf->autoneg = hw->mac.autoneg;
3033
3034         /*
3035          * Return rx_pause and tx_pause status according to actual setting of
3036          * the TFCE and RFCE bits in the CTRL register.
3037          */
3038         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3039         if (ctrl & E1000_CTRL_TFCE)
3040                 tx_pause = 1;
3041         else
3042                 tx_pause = 0;
3043
3044         if (ctrl & E1000_CTRL_RFCE)
3045                 rx_pause = 1;
3046         else
3047                 rx_pause = 0;
3048
3049         if (rx_pause && tx_pause)
3050                 fc_conf->mode = RTE_FC_FULL;
3051         else if (rx_pause)
3052                 fc_conf->mode = RTE_FC_RX_PAUSE;
3053         else if (tx_pause)
3054                 fc_conf->mode = RTE_FC_TX_PAUSE;
3055         else
3056                 fc_conf->mode = RTE_FC_NONE;
3057
3058         return 0;
3059 }
3060
3061 static int
3062 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3063 {
3064         struct e1000_hw *hw;
3065         int err;
3066         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3067                 e1000_fc_none,
3068                 e1000_fc_rx_pause,
3069                 e1000_fc_tx_pause,
3070                 e1000_fc_full
3071         };
3072         uint32_t rx_buf_size;
3073         uint32_t max_high_water;
3074         uint32_t rctl;
3075
3076         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3077         if (fc_conf->autoneg != hw->mac.autoneg)
3078                 return -ENOTSUP;
3079         rx_buf_size = igb_get_rx_buffer_size(hw);
3080         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3081
3082         /* At least reserve one Ethernet frame for watermark */
3083         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3084         if ((fc_conf->high_water > max_high_water) ||
3085             (fc_conf->high_water < fc_conf->low_water)) {
3086                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3087                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3088                 return -EINVAL;
3089         }
3090
3091         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3092         hw->fc.pause_time     = fc_conf->pause_time;
3093         hw->fc.high_water     = fc_conf->high_water;
3094         hw->fc.low_water      = fc_conf->low_water;
3095         hw->fc.send_xon       = fc_conf->send_xon;
3096
3097         err = e1000_setup_link_generic(hw);
3098         if (err == E1000_SUCCESS) {
3099
3100                 /* check if we want to forward MAC frames - driver doesn't have native
3101                  * capability to do that, so we'll write the registers ourselves */
3102
3103                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3104
3105                 /* set or clear MFLCN.PMCF bit depending on configuration */
3106                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3107                         rctl |= E1000_RCTL_PMCF;
3108                 else
3109                         rctl &= ~E1000_RCTL_PMCF;
3110
3111                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3112                 E1000_WRITE_FLUSH(hw);
3113
3114                 return 0;
3115         }
3116
3117         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3118         return -EIO;
3119 }
3120
3121 #define E1000_RAH_POOLSEL_SHIFT      (18)
3122 static int
3123 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3124                 uint32_t index, uint32_t pool)
3125 {
3126         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3127         uint32_t rah;
3128
3129         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3130         rah = E1000_READ_REG(hw, E1000_RAH(index));
3131         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3132         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3133         return 0;
3134 }
3135
3136 static void
3137 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3138 {
3139         uint8_t addr[ETHER_ADDR_LEN];
3140         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3141
3142         memset(addr, 0, sizeof(addr));
3143
3144         e1000_rar_set(hw, addr, index);
3145 }
3146
3147 static void
3148 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3149                                 struct ether_addr *addr)
3150 {
3151         eth_igb_rar_clear(dev, 0);
3152
3153         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3154 }
3155 /*
3156  * Virtual Function operations
3157  */
3158 static void
3159 igbvf_intr_disable(struct e1000_hw *hw)
3160 {
3161         PMD_INIT_FUNC_TRACE();
3162
3163         /* Clear interrupt mask to stop from interrupts being generated */
3164         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3165
3166         E1000_WRITE_FLUSH(hw);
3167 }
3168
3169 static void
3170 igbvf_stop_adapter(struct rte_eth_dev *dev)
3171 {
3172         u32 reg_val;
3173         u16 i;
3174         struct rte_eth_dev_info dev_info;
3175         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3176
3177         memset(&dev_info, 0, sizeof(dev_info));
3178         eth_igbvf_infos_get(dev, &dev_info);
3179
3180         /* Clear interrupt mask to stop from interrupts being generated */
3181         igbvf_intr_disable(hw);
3182
3183         /* Clear any pending interrupts, flush previous writes */
3184         E1000_READ_REG(hw, E1000_EICR);
3185
3186         /* Disable the transmit unit.  Each queue must be disabled. */
3187         for (i = 0; i < dev_info.max_tx_queues; i++)
3188                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3189
3190         /* Disable the receive unit by stopping each queue */
3191         for (i = 0; i < dev_info.max_rx_queues; i++) {
3192                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3193                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3194                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3195                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3196                         ;
3197         }
3198
3199         /* flush all queues disables */
3200         E1000_WRITE_FLUSH(hw);
3201         msec_delay(2);
3202 }
3203
3204 static int eth_igbvf_link_update(struct e1000_hw *hw)
3205 {
3206         struct e1000_mbx_info *mbx = &hw->mbx;
3207         struct e1000_mac_info *mac = &hw->mac;
3208         int ret_val = E1000_SUCCESS;
3209
3210         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3211
3212         /*
3213          * We only want to run this if there has been a rst asserted.
3214          * in this case that could mean a link change, device reset,
3215          * or a virtual function reset
3216          */
3217
3218         /* If we were hit with a reset or timeout drop the link */
3219         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3220                 mac->get_link_status = TRUE;
3221
3222         if (!mac->get_link_status)
3223                 goto out;
3224
3225         /* if link status is down no point in checking to see if pf is up */
3226         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3227                 goto out;
3228
3229         /* if we passed all the tests above then the link is up and we no
3230          * longer need to check for link */
3231         mac->get_link_status = FALSE;
3232
3233 out:
3234         return ret_val;
3235 }
3236
3237
3238 static int
3239 igbvf_dev_configure(struct rte_eth_dev *dev)
3240 {
3241         struct rte_eth_conf* conf = &dev->data->dev_conf;
3242
3243         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3244                      dev->data->port_id);
3245
3246         /*
3247          * VF has no ability to enable/disable HW CRC
3248          * Keep the persistent behavior the same as Host PF
3249          */
3250 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3251         if (!conf->rxmode.hw_strip_crc) {
3252                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3253                 conf->rxmode.hw_strip_crc = 1;
3254         }
3255 #else
3256         if (conf->rxmode.hw_strip_crc) {
3257                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3258                 conf->rxmode.hw_strip_crc = 0;
3259         }
3260 #endif
3261
3262         return 0;
3263 }
3264
3265 static int
3266 igbvf_dev_start(struct rte_eth_dev *dev)
3267 {
3268         struct e1000_hw *hw =
3269                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3270         struct e1000_adapter *adapter =
3271                 E1000_DEV_PRIVATE(dev->data->dev_private);
3272         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3273         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3274         int ret;
3275         uint32_t intr_vector = 0;
3276
3277         PMD_INIT_FUNC_TRACE();
3278
3279         hw->mac.ops.reset_hw(hw);
3280         adapter->stopped = 0;
3281
3282         /* Set all vfta */
3283         igbvf_set_vfta_all(dev,1);
3284
3285         eth_igbvf_tx_init(dev);
3286
3287         /* This can fail when allocating mbufs for descriptor rings */
3288         ret = eth_igbvf_rx_init(dev);
3289         if (ret) {
3290                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3291                 igb_dev_clear_queues(dev);
3292                 return ret;
3293         }
3294
3295         /* check and configure queue intr-vector mapping */
3296         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3297                 intr_vector = dev->data->nb_rx_queues;
3298                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3299                 if (ret)
3300                         return ret;
3301         }
3302
3303         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3304                 intr_handle->intr_vec =
3305                         rte_zmalloc("intr_vec",
3306                                     dev->data->nb_rx_queues * sizeof(int), 0);
3307                 if (!intr_handle->intr_vec) {
3308                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3309                                      " intr_vec", dev->data->nb_rx_queues);
3310                         return -ENOMEM;
3311                 }
3312         }
3313
3314         eth_igbvf_configure_msix_intr(dev);
3315
3316         /* enable uio/vfio intr/eventfd mapping */
3317         rte_intr_enable(intr_handle);
3318
3319         /* resume enabled intr since hw reset */
3320         igbvf_intr_enable(dev);
3321
3322         return 0;
3323 }
3324
3325 static void
3326 igbvf_dev_stop(struct rte_eth_dev *dev)
3327 {
3328         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3329         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3330
3331         PMD_INIT_FUNC_TRACE();
3332
3333         igbvf_stop_adapter(dev);
3334
3335         /*
3336           * Clear what we set, but we still keep shadow_vfta to
3337           * restore after device starts
3338           */
3339         igbvf_set_vfta_all(dev,0);
3340
3341         igb_dev_clear_queues(dev);
3342
3343         /* disable intr eventfd mapping */
3344         rte_intr_disable(intr_handle);
3345
3346         /* Clean datapath event and queue/vec mapping */
3347         rte_intr_efd_disable(intr_handle);
3348         if (intr_handle->intr_vec) {
3349                 rte_free(intr_handle->intr_vec);
3350                 intr_handle->intr_vec = NULL;
3351         }
3352 }
3353
3354 static void
3355 igbvf_dev_close(struct rte_eth_dev *dev)
3356 {
3357         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3358         struct e1000_adapter *adapter =
3359                 E1000_DEV_PRIVATE(dev->data->dev_private);
3360         struct ether_addr addr;
3361
3362         PMD_INIT_FUNC_TRACE();
3363
3364         e1000_reset_hw(hw);
3365
3366         igbvf_dev_stop(dev);
3367         adapter->stopped = 1;
3368         igb_dev_free_queues(dev);
3369
3370         /**
3371          * reprogram the RAR with a zero mac address,
3372          * to ensure that the VF traffic goes to the PF
3373          * after stop, close and detach of the VF.
3374          **/
3375
3376         memset(&addr, 0, sizeof(addr));
3377         igbvf_default_mac_addr_set(dev, &addr);
3378 }
3379
3380 static void
3381 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3382 {
3383         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3384
3385         /* Set both unicast and multicast promisc */
3386         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3387 }
3388
3389 static void
3390 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3391 {
3392         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3393
3394         /* If in allmulticast mode leave multicast promisc */
3395         if (dev->data->all_multicast == 1)
3396                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3397         else
3398                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3399 }
3400
3401 static void
3402 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3403 {
3404         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3405
3406         /* In promiscuous mode multicast promisc already set */
3407         if (dev->data->promiscuous == 0)
3408                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3409 }
3410
3411 static void
3412 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3413 {
3414         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3415
3416         /* In promiscuous mode leave multicast promisc enabled */
3417         if (dev->data->promiscuous == 0)
3418                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3419 }
3420
3421 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3422 {
3423         struct e1000_mbx_info *mbx = &hw->mbx;
3424         uint32_t msgbuf[2];
3425         s32 err;
3426
3427         /* After set vlan, vlan strip will also be enabled in igb driver*/
3428         msgbuf[0] = E1000_VF_SET_VLAN;
3429         msgbuf[1] = vid;
3430         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3431         if (on)
3432                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3433
3434         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3435         if (err)
3436                 goto mbx_err;
3437
3438         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3439         if (err)
3440                 goto mbx_err;
3441
3442         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3443         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3444                 err = -EINVAL;
3445
3446 mbx_err:
3447         return err;
3448 }
3449
3450 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3451 {
3452         struct e1000_hw *hw =
3453                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3454         struct e1000_vfta * shadow_vfta =
3455                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3456         int i = 0, j = 0, vfta = 0, mask = 1;
3457
3458         for (i = 0; i < IGB_VFTA_SIZE; i++){
3459                 vfta = shadow_vfta->vfta[i];
3460                 if(vfta){
3461                         mask = 1;
3462                         for (j = 0; j < 32; j++){
3463                                 if(vfta & mask)
3464                                         igbvf_set_vfta(hw,
3465                                                 (uint16_t)((i<<5)+j), on);
3466                                 mask<<=1;
3467                         }
3468                 }
3469         }
3470
3471 }
3472
3473 static int
3474 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3475 {
3476         struct e1000_hw *hw =
3477                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3478         struct e1000_vfta * shadow_vfta =
3479                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3480         uint32_t vid_idx = 0;
3481         uint32_t vid_bit = 0;
3482         int ret = 0;
3483
3484         PMD_INIT_FUNC_TRACE();
3485
3486         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3487         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3488         if(ret){
3489                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3490                 return ret;
3491         }
3492         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3493         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3494
3495         /*Save what we set and retore it after device reset*/
3496         if (on)
3497                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3498         else
3499                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3500
3501         return 0;
3502 }
3503
3504 static void
3505 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3506 {
3507         struct e1000_hw *hw =
3508                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3509
3510         /* index is not used by rar_set() */
3511         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3512 }
3513
3514
3515 static int
3516 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3517                         struct rte_eth_rss_reta_entry64 *reta_conf,
3518                         uint16_t reta_size)
3519 {
3520         uint8_t i, j, mask;
3521         uint32_t reta, r;
3522         uint16_t idx, shift;
3523         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3524
3525         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3526                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3527                         "(%d) doesn't match the number hardware can supported "
3528                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3529                 return -EINVAL;
3530         }
3531
3532         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3533                 idx = i / RTE_RETA_GROUP_SIZE;
3534                 shift = i % RTE_RETA_GROUP_SIZE;
3535                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3536                                                 IGB_4_BIT_MASK);
3537                 if (!mask)
3538                         continue;
3539                 if (mask == IGB_4_BIT_MASK)
3540                         r = 0;
3541                 else
3542                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3543                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3544                         if (mask & (0x1 << j))
3545                                 reta |= reta_conf[idx].reta[shift + j] <<
3546                                                         (CHAR_BIT * j);
3547                         else
3548                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3549                 }
3550                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3551         }
3552
3553         return 0;
3554 }
3555
3556 static int
3557 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3558                        struct rte_eth_rss_reta_entry64 *reta_conf,
3559                        uint16_t reta_size)
3560 {
3561         uint8_t i, j, mask;
3562         uint32_t reta;
3563         uint16_t idx, shift;
3564         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3565
3566         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3567                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3568                         "(%d) doesn't match the number hardware can supported "
3569                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3570                 return -EINVAL;
3571         }
3572
3573         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3574                 idx = i / RTE_RETA_GROUP_SIZE;
3575                 shift = i % RTE_RETA_GROUP_SIZE;
3576                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3577                                                 IGB_4_BIT_MASK);
3578                 if (!mask)
3579                         continue;
3580                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3581                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3582                         if (mask & (0x1 << j))
3583                                 reta_conf[idx].reta[shift + j] =
3584                                         ((reta >> (CHAR_BIT * j)) &
3585                                                 IGB_8_BIT_MASK);
3586                 }
3587         }
3588
3589         return 0;
3590 }
3591
3592 int
3593 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3594                         struct rte_eth_syn_filter *filter,
3595                         bool add)
3596 {
3597         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3598         struct e1000_filter_info *filter_info =
3599                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3600         uint32_t synqf, rfctl;
3601
3602         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3603                 return -EINVAL;
3604
3605         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3606
3607         if (add) {
3608                 if (synqf & E1000_SYN_FILTER_ENABLE)
3609                         return -EINVAL;
3610
3611                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3612                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3613
3614                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3615                 if (filter->hig_pri)
3616                         rfctl |= E1000_RFCTL_SYNQFP;
3617                 else
3618                         rfctl &= ~E1000_RFCTL_SYNQFP;
3619
3620                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3621         } else {
3622                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3623                         return -ENOENT;
3624                 synqf = 0;
3625         }
3626
3627         filter_info->syn_info = synqf;
3628         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3629         E1000_WRITE_FLUSH(hw);
3630         return 0;
3631 }
3632
3633 static int
3634 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3635                         struct rte_eth_syn_filter *filter)
3636 {
3637         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3638         uint32_t synqf, rfctl;
3639
3640         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3641         if (synqf & E1000_SYN_FILTER_ENABLE) {
3642                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3643                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3644                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3645                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3646                 return 0;
3647         }
3648
3649         return -ENOENT;
3650 }
3651
3652 static int
3653 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3654                         enum rte_filter_op filter_op,
3655                         void *arg)
3656 {
3657         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3658         int ret;
3659
3660         MAC_TYPE_FILTER_SUP(hw->mac.type);
3661
3662         if (filter_op == RTE_ETH_FILTER_NOP)
3663                 return 0;
3664
3665         if (arg == NULL) {
3666                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3667                             filter_op);
3668                 return -EINVAL;
3669         }
3670
3671         switch (filter_op) {
3672         case RTE_ETH_FILTER_ADD:
3673                 ret = eth_igb_syn_filter_set(dev,
3674                                 (struct rte_eth_syn_filter *)arg,
3675                                 TRUE);
3676                 break;
3677         case RTE_ETH_FILTER_DELETE:
3678                 ret = eth_igb_syn_filter_set(dev,
3679                                 (struct rte_eth_syn_filter *)arg,
3680                                 FALSE);
3681                 break;
3682         case RTE_ETH_FILTER_GET:
3683                 ret = eth_igb_syn_filter_get(dev,
3684                                 (struct rte_eth_syn_filter *)arg);
3685                 break;
3686         default:
3687                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3688                 ret = -EINVAL;
3689                 break;
3690         }
3691
3692         return ret;
3693 }
3694
3695 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3696 static inline int
3697 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3698                         struct e1000_2tuple_filter_info *filter_info)
3699 {
3700         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3701                 return -EINVAL;
3702         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3703                 return -EINVAL;  /* filter index is out of range. */
3704         if (filter->tcp_flags > TCP_FLAG_ALL)
3705                 return -EINVAL;  /* flags is invalid. */
3706
3707         switch (filter->dst_port_mask) {
3708         case UINT16_MAX:
3709                 filter_info->dst_port_mask = 0;
3710                 filter_info->dst_port = filter->dst_port;
3711                 break;
3712         case 0:
3713                 filter_info->dst_port_mask = 1;
3714                 break;
3715         default:
3716                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3717                 return -EINVAL;
3718         }
3719
3720         switch (filter->proto_mask) {
3721         case UINT8_MAX:
3722                 filter_info->proto_mask = 0;
3723                 filter_info->proto = filter->proto;
3724                 break;
3725         case 0:
3726                 filter_info->proto_mask = 1;
3727                 break;
3728         default:
3729                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3730                 return -EINVAL;
3731         }
3732
3733         filter_info->priority = (uint8_t)filter->priority;
3734         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3735                 filter_info->tcp_flags = filter->tcp_flags;
3736         else
3737                 filter_info->tcp_flags = 0;
3738
3739         return 0;
3740 }
3741
3742 static inline struct e1000_2tuple_filter *
3743 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3744                         struct e1000_2tuple_filter_info *key)
3745 {
3746         struct e1000_2tuple_filter *it;
3747
3748         TAILQ_FOREACH(it, filter_list, entries) {
3749                 if (memcmp(key, &it->filter_info,
3750                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3751                         return it;
3752                 }
3753         }
3754         return NULL;
3755 }
3756
3757 /* inject a igb 2tuple filter to HW */
3758 static inline void
3759 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3760                            struct e1000_2tuple_filter *filter)
3761 {
3762         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3763         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3764         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3765         int i;
3766
3767         i = filter->index;
3768         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3769         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3770                 imir |= E1000_IMIR_PORT_BP;
3771         else
3772                 imir &= ~E1000_IMIR_PORT_BP;
3773
3774         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3775
3776         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3777         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3778         ttqf |= (uint32_t)(filter->filter_info.proto &
3779                                                 E1000_TTQF_PROTOCOL_MASK);
3780         if (filter->filter_info.proto_mask == 0)
3781                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3782
3783         /* tcp flags bits setting. */
3784         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3785                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3786                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3787                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3788                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3789                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3790                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3791                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3792                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3793                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3794                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3795                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3796                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3797         } else {
3798                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3799         }
3800         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3801         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3802         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3803 }
3804
3805 /*
3806  * igb_add_2tuple_filter - add a 2tuple filter
3807  *
3808  * @param
3809  * dev: Pointer to struct rte_eth_dev.
3810  * ntuple_filter: ponter to the filter that will be added.
3811  *
3812  * @return
3813  *    - On success, zero.
3814  *    - On failure, a negative value.
3815  */
3816 static int
3817 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3818                         struct rte_eth_ntuple_filter *ntuple_filter)
3819 {
3820         struct e1000_filter_info *filter_info =
3821                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3822         struct e1000_2tuple_filter *filter;
3823         int i, ret;
3824
3825         filter = rte_zmalloc("e1000_2tuple_filter",
3826                         sizeof(struct e1000_2tuple_filter), 0);
3827         if (filter == NULL)
3828                 return -ENOMEM;
3829
3830         ret = ntuple_filter_to_2tuple(ntuple_filter,
3831                                       &filter->filter_info);
3832         if (ret < 0) {
3833                 rte_free(filter);
3834                 return ret;
3835         }
3836         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3837                                          &filter->filter_info) != NULL) {
3838                 PMD_DRV_LOG(ERR, "filter exists.");
3839                 rte_free(filter);
3840                 return -EEXIST;
3841         }
3842         filter->queue = ntuple_filter->queue;
3843
3844         /*
3845          * look for an unused 2tuple filter index,
3846          * and insert the filter to list.
3847          */
3848         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3849                 if (!(filter_info->twotuple_mask & (1 << i))) {
3850                         filter_info->twotuple_mask |= 1 << i;
3851                         filter->index = i;
3852                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3853                                           filter,
3854                                           entries);
3855                         break;
3856                 }
3857         }
3858         if (i >= E1000_MAX_TTQF_FILTERS) {
3859                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3860                 rte_free(filter);
3861                 return -ENOSYS;
3862         }
3863
3864         igb_inject_2uple_filter(dev, filter);
3865         return 0;
3866 }
3867
3868 int
3869 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3870                         struct e1000_2tuple_filter *filter)
3871 {
3872         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3873         struct e1000_filter_info *filter_info =
3874                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3875
3876         filter_info->twotuple_mask &= ~(1 << filter->index);
3877         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3878         rte_free(filter);
3879
3880         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3881         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3882         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3883         return 0;
3884 }
3885
3886 /*
3887  * igb_remove_2tuple_filter - remove a 2tuple filter
3888  *
3889  * @param
3890  * dev: Pointer to struct rte_eth_dev.
3891  * ntuple_filter: ponter to the filter that will be removed.
3892  *
3893  * @return
3894  *    - On success, zero.
3895  *    - On failure, a negative value.
3896  */
3897 static int
3898 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3899                         struct rte_eth_ntuple_filter *ntuple_filter)
3900 {
3901         struct e1000_filter_info *filter_info =
3902                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3903         struct e1000_2tuple_filter_info filter_2tuple;
3904         struct e1000_2tuple_filter *filter;
3905         int ret;
3906
3907         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3908         ret = ntuple_filter_to_2tuple(ntuple_filter,
3909                                       &filter_2tuple);
3910         if (ret < 0)
3911                 return ret;
3912
3913         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3914                                          &filter_2tuple);
3915         if (filter == NULL) {
3916                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3917                 return -ENOENT;
3918         }
3919
3920         igb_delete_2tuple_filter(dev, filter);
3921
3922         return 0;
3923 }
3924
3925 /* inject a igb flex filter to HW */
3926 static inline void
3927 igb_inject_flex_filter(struct rte_eth_dev *dev,
3928                            struct e1000_flex_filter *filter)
3929 {
3930         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3931         uint32_t wufc, queueing;
3932         uint32_t reg_off;
3933         uint8_t i, j = 0;
3934
3935         wufc = E1000_READ_REG(hw, E1000_WUFC);
3936         if (filter->index < E1000_MAX_FHFT)
3937                 reg_off = E1000_FHFT(filter->index);
3938         else
3939                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3940
3941         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3942                         (E1000_WUFC_FLX0 << filter->index));
3943         queueing = filter->filter_info.len |
3944                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3945                 (filter->filter_info.priority <<
3946                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3947         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3948                         queueing);
3949
3950         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3951                 E1000_WRITE_REG(hw, reg_off,
3952                                 filter->filter_info.dwords[j]);
3953                 reg_off += sizeof(uint32_t);
3954                 E1000_WRITE_REG(hw, reg_off,
3955                                 filter->filter_info.dwords[++j]);
3956                 reg_off += sizeof(uint32_t);
3957                 E1000_WRITE_REG(hw, reg_off,
3958                         (uint32_t)filter->filter_info.mask[i]);
3959                 reg_off += sizeof(uint32_t) * 2;
3960                 ++j;
3961         }
3962 }
3963
3964 static inline struct e1000_flex_filter *
3965 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3966                         struct e1000_flex_filter_info *key)
3967 {
3968         struct e1000_flex_filter *it;
3969
3970         TAILQ_FOREACH(it, filter_list, entries) {
3971                 if (memcmp(key, &it->filter_info,
3972                         sizeof(struct e1000_flex_filter_info)) == 0)
3973                         return it;
3974         }
3975
3976         return NULL;
3977 }
3978
3979 /* remove a flex byte filter
3980  * @param
3981  * dev: Pointer to struct rte_eth_dev.
3982  * filter: the pointer of the filter will be removed.
3983  */
3984 void
3985 igb_remove_flex_filter(struct rte_eth_dev *dev,
3986                         struct e1000_flex_filter *filter)
3987 {
3988         struct e1000_filter_info *filter_info =
3989                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3990         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3991         uint32_t wufc, i;
3992         uint32_t reg_off;
3993
3994         wufc = E1000_READ_REG(hw, E1000_WUFC);
3995         if (filter->index < E1000_MAX_FHFT)
3996                 reg_off = E1000_FHFT(filter->index);
3997         else
3998                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3999
4000         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4001                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4002
4003         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4004                 (~(E1000_WUFC_FLX0 << filter->index)));
4005
4006         filter_info->flex_mask &= ~(1 << filter->index);
4007         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4008         rte_free(filter);
4009 }
4010
4011 int
4012 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4013                         struct rte_eth_flex_filter *filter,
4014                         bool add)
4015 {
4016         struct e1000_filter_info *filter_info =
4017                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4018         struct e1000_flex_filter *flex_filter, *it;
4019         uint32_t mask;
4020         uint8_t shift, i;
4021
4022         flex_filter = rte_zmalloc("e1000_flex_filter",
4023                         sizeof(struct e1000_flex_filter), 0);
4024         if (flex_filter == NULL)
4025                 return -ENOMEM;
4026
4027         flex_filter->filter_info.len = filter->len;
4028         flex_filter->filter_info.priority = filter->priority;
4029         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4030         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4031                 mask = 0;
4032                 /* reverse bits in flex filter's mask*/
4033                 for (shift = 0; shift < CHAR_BIT; shift++) {
4034                         if (filter->mask[i] & (0x01 << shift))
4035                                 mask |= (0x80 >> shift);
4036                 }
4037                 flex_filter->filter_info.mask[i] = mask;
4038         }
4039
4040         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4041                                 &flex_filter->filter_info);
4042         if (it == NULL && !add) {
4043                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4044                 rte_free(flex_filter);
4045                 return -ENOENT;
4046         }
4047         if (it != NULL && add) {
4048                 PMD_DRV_LOG(ERR, "filter exists.");
4049                 rte_free(flex_filter);
4050                 return -EEXIST;
4051         }
4052
4053         if (add) {
4054                 flex_filter->queue = filter->queue;
4055                 /*
4056                  * look for an unused flex filter index
4057                  * and insert the filter into the list.
4058                  */
4059                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4060                         if (!(filter_info->flex_mask & (1 << i))) {
4061                                 filter_info->flex_mask |= 1 << i;
4062                                 flex_filter->index = i;
4063                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4064                                         flex_filter,
4065                                         entries);
4066                                 break;
4067                         }
4068                 }
4069                 if (i >= E1000_MAX_FLEX_FILTERS) {
4070                         PMD_DRV_LOG(ERR, "flex filters are full.");
4071                         rte_free(flex_filter);
4072                         return -ENOSYS;
4073                 }
4074
4075                 igb_inject_flex_filter(dev, flex_filter);
4076
4077         } else {
4078                 igb_remove_flex_filter(dev, it);
4079                 rte_free(flex_filter);
4080         }
4081
4082         return 0;
4083 }
4084
4085 static int
4086 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4087                         struct rte_eth_flex_filter *filter)
4088 {
4089         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4090         struct e1000_filter_info *filter_info =
4091                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4092         struct e1000_flex_filter flex_filter, *it;
4093         uint32_t wufc, queueing, wufc_en = 0;
4094
4095         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4096         flex_filter.filter_info.len = filter->len;
4097         flex_filter.filter_info.priority = filter->priority;
4098         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4099         memcpy(flex_filter.filter_info.mask, filter->mask,
4100                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4101
4102         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4103                                 &flex_filter.filter_info);
4104         if (it == NULL) {
4105                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4106                 return -ENOENT;
4107         }
4108
4109         wufc = E1000_READ_REG(hw, E1000_WUFC);
4110         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4111
4112         if ((wufc & wufc_en) == wufc_en) {
4113                 uint32_t reg_off = 0;
4114                 if (it->index < E1000_MAX_FHFT)
4115                         reg_off = E1000_FHFT(it->index);
4116                 else
4117                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4118
4119                 queueing = E1000_READ_REG(hw,
4120                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4121                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4122                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4123                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4124                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4125                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4126                 return 0;
4127         }
4128         return -ENOENT;
4129 }
4130
4131 static int
4132 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4133                         enum rte_filter_op filter_op,
4134                         void *arg)
4135 {
4136         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4137         struct rte_eth_flex_filter *filter;
4138         int ret = 0;
4139
4140         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4141
4142         if (filter_op == RTE_ETH_FILTER_NOP)
4143                 return ret;
4144
4145         if (arg == NULL) {
4146                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4147                             filter_op);
4148                 return -EINVAL;
4149         }
4150
4151         filter = (struct rte_eth_flex_filter *)arg;
4152         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4153             || filter->len % sizeof(uint64_t) != 0) {
4154                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4155                 return -EINVAL;
4156         }
4157         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4158                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4159                 return -EINVAL;
4160         }
4161
4162         switch (filter_op) {
4163         case RTE_ETH_FILTER_ADD:
4164                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4165                 break;
4166         case RTE_ETH_FILTER_DELETE:
4167                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4168                 break;
4169         case RTE_ETH_FILTER_GET:
4170                 ret = eth_igb_get_flex_filter(dev, filter);
4171                 break;
4172         default:
4173                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4174                 ret = -EINVAL;
4175                 break;
4176         }
4177
4178         return ret;
4179 }
4180
4181 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4182 static inline int
4183 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4184                         struct e1000_5tuple_filter_info *filter_info)
4185 {
4186         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4187                 return -EINVAL;
4188         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4189                 return -EINVAL;  /* filter index is out of range. */
4190         if (filter->tcp_flags > TCP_FLAG_ALL)
4191                 return -EINVAL;  /* flags is invalid. */
4192
4193         switch (filter->dst_ip_mask) {
4194         case UINT32_MAX:
4195                 filter_info->dst_ip_mask = 0;
4196                 filter_info->dst_ip = filter->dst_ip;
4197                 break;
4198         case 0:
4199                 filter_info->dst_ip_mask = 1;
4200                 break;
4201         default:
4202                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4203                 return -EINVAL;
4204         }
4205
4206         switch (filter->src_ip_mask) {
4207         case UINT32_MAX:
4208                 filter_info->src_ip_mask = 0;
4209                 filter_info->src_ip = filter->src_ip;
4210                 break;
4211         case 0:
4212                 filter_info->src_ip_mask = 1;
4213                 break;
4214         default:
4215                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4216                 return -EINVAL;
4217         }
4218
4219         switch (filter->dst_port_mask) {
4220         case UINT16_MAX:
4221                 filter_info->dst_port_mask = 0;
4222                 filter_info->dst_port = filter->dst_port;
4223                 break;
4224         case 0:
4225                 filter_info->dst_port_mask = 1;
4226                 break;
4227         default:
4228                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4229                 return -EINVAL;
4230         }
4231
4232         switch (filter->src_port_mask) {
4233         case UINT16_MAX:
4234                 filter_info->src_port_mask = 0;
4235                 filter_info->src_port = filter->src_port;
4236                 break;
4237         case 0:
4238                 filter_info->src_port_mask = 1;
4239                 break;
4240         default:
4241                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4242                 return -EINVAL;
4243         }
4244
4245         switch (filter->proto_mask) {
4246         case UINT8_MAX:
4247                 filter_info->proto_mask = 0;
4248                 filter_info->proto = filter->proto;
4249                 break;
4250         case 0:
4251                 filter_info->proto_mask = 1;
4252                 break;
4253         default:
4254                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4255                 return -EINVAL;
4256         }
4257
4258         filter_info->priority = (uint8_t)filter->priority;
4259         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4260                 filter_info->tcp_flags = filter->tcp_flags;
4261         else
4262                 filter_info->tcp_flags = 0;
4263
4264         return 0;
4265 }
4266
4267 static inline struct e1000_5tuple_filter *
4268 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4269                         struct e1000_5tuple_filter_info *key)
4270 {
4271         struct e1000_5tuple_filter *it;
4272
4273         TAILQ_FOREACH(it, filter_list, entries) {
4274                 if (memcmp(key, &it->filter_info,
4275                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4276                         return it;
4277                 }
4278         }
4279         return NULL;
4280 }
4281
4282 /* inject a igb 5-tuple filter to HW */
4283 static inline void
4284 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4285                            struct e1000_5tuple_filter *filter)
4286 {
4287         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4288         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4289         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4290         uint8_t i;
4291
4292         i = filter->index;
4293         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4294         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4295                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4296         if (filter->filter_info.dst_ip_mask == 0)
4297                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4298         if (filter->filter_info.src_port_mask == 0)
4299                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4300         if (filter->filter_info.proto_mask == 0)
4301                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4302         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4303                 E1000_FTQF_QUEUE_MASK;
4304         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4305         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4306         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4307         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4308
4309         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4310         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4311
4312         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4313         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4314                 imir |= E1000_IMIR_PORT_BP;
4315         else
4316                 imir &= ~E1000_IMIR_PORT_BP;
4317         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4318
4319         /* tcp flags bits setting. */
4320         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4321                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4322                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4323                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4324                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4325                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4326                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4327                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4328                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4329                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4330                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4331                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4332                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4333         } else {
4334                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4335         }
4336         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4337         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4338 }
4339
4340 /*
4341  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4342  *
4343  * @param
4344  * dev: Pointer to struct rte_eth_dev.
4345  * ntuple_filter: ponter to the filter that will be added.
4346  *
4347  * @return
4348  *    - On success, zero.
4349  *    - On failure, a negative value.
4350  */
4351 static int
4352 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4353                         struct rte_eth_ntuple_filter *ntuple_filter)
4354 {
4355         struct e1000_filter_info *filter_info =
4356                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4357         struct e1000_5tuple_filter *filter;
4358         uint8_t i;
4359         int ret;
4360
4361         filter = rte_zmalloc("e1000_5tuple_filter",
4362                         sizeof(struct e1000_5tuple_filter), 0);
4363         if (filter == NULL)
4364                 return -ENOMEM;
4365
4366         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4367                                             &filter->filter_info);
4368         if (ret < 0) {
4369                 rte_free(filter);
4370                 return ret;
4371         }
4372
4373         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4374                                          &filter->filter_info) != NULL) {
4375                 PMD_DRV_LOG(ERR, "filter exists.");
4376                 rte_free(filter);
4377                 return -EEXIST;
4378         }
4379         filter->queue = ntuple_filter->queue;
4380
4381         /*
4382          * look for an unused 5tuple filter index,
4383          * and insert the filter to list.
4384          */
4385         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4386                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4387                         filter_info->fivetuple_mask |= 1 << i;
4388                         filter->index = i;
4389                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4390                                           filter,
4391                                           entries);
4392                         break;
4393                 }
4394         }
4395         if (i >= E1000_MAX_FTQF_FILTERS) {
4396                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4397                 rte_free(filter);
4398                 return -ENOSYS;
4399         }
4400
4401         igb_inject_5tuple_filter_82576(dev, filter);
4402         return 0;
4403 }
4404
4405 int
4406 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4407                                 struct e1000_5tuple_filter *filter)
4408 {
4409         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4410         struct e1000_filter_info *filter_info =
4411                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4412
4413         filter_info->fivetuple_mask &= ~(1 << filter->index);
4414         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4415         rte_free(filter);
4416
4417         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4418                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4419         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4420         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4421         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4422         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4423         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4424         return 0;
4425 }
4426
4427 /*
4428  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4429  *
4430  * @param
4431  * dev: Pointer to struct rte_eth_dev.
4432  * ntuple_filter: ponter to the filter that will be removed.
4433  *
4434  * @return
4435  *    - On success, zero.
4436  *    - On failure, a negative value.
4437  */
4438 static int
4439 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4440                                 struct rte_eth_ntuple_filter *ntuple_filter)
4441 {
4442         struct e1000_filter_info *filter_info =
4443                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4444         struct e1000_5tuple_filter_info filter_5tuple;
4445         struct e1000_5tuple_filter *filter;
4446         int ret;
4447
4448         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4449         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4450                                             &filter_5tuple);
4451         if (ret < 0)
4452                 return ret;
4453
4454         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4455                                          &filter_5tuple);
4456         if (filter == NULL) {
4457                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4458                 return -ENOENT;
4459         }
4460
4461         igb_delete_5tuple_filter_82576(dev, filter);
4462
4463         return 0;
4464 }
4465
4466 static int
4467 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4468 {
4469         uint32_t rctl;
4470         struct e1000_hw *hw;
4471         struct rte_eth_dev_info dev_info;
4472         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4473                                      VLAN_TAG_SIZE);
4474
4475         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4476
4477 #ifdef RTE_LIBRTE_82571_SUPPORT
4478         /* XXX: not bigger than max_rx_pktlen */
4479         if (hw->mac.type == e1000_82571)
4480                 return -ENOTSUP;
4481 #endif
4482         eth_igb_infos_get(dev, &dev_info);
4483
4484         /* check that mtu is within the allowed range */
4485         if ((mtu < ETHER_MIN_MTU) ||
4486             (frame_size > dev_info.max_rx_pktlen))
4487                 return -EINVAL;
4488
4489         /* refuse mtu that requires the support of scattered packets when this
4490          * feature has not been enabled before. */
4491         if (!dev->data->scattered_rx &&
4492             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4493                 return -EINVAL;
4494
4495         rctl = E1000_READ_REG(hw, E1000_RCTL);
4496
4497         /* switch to jumbo mode if needed */
4498         if (frame_size > ETHER_MAX_LEN) {
4499                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4500                 rctl |= E1000_RCTL_LPE;
4501         } else {
4502                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4503                 rctl &= ~E1000_RCTL_LPE;
4504         }
4505         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4506
4507         /* update max frame size */
4508         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4509
4510         E1000_WRITE_REG(hw, E1000_RLPML,
4511                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4512
4513         return 0;
4514 }
4515
4516 /*
4517  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4518  *
4519  * @param
4520  * dev: Pointer to struct rte_eth_dev.
4521  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4522  * add: if true, add filter, if false, remove filter
4523  *
4524  * @return
4525  *    - On success, zero.
4526  *    - On failure, a negative value.
4527  */
4528 int
4529 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4530                         struct rte_eth_ntuple_filter *ntuple_filter,
4531                         bool add)
4532 {
4533         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4534         int ret;
4535
4536         switch (ntuple_filter->flags) {
4537         case RTE_5TUPLE_FLAGS:
4538         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4539                 if (hw->mac.type != e1000_82576)
4540                         return -ENOTSUP;
4541                 if (add)
4542                         ret = igb_add_5tuple_filter_82576(dev,
4543                                                           ntuple_filter);
4544                 else
4545                         ret = igb_remove_5tuple_filter_82576(dev,
4546                                                              ntuple_filter);
4547                 break;
4548         case RTE_2TUPLE_FLAGS:
4549         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4550                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4551                         hw->mac.type != e1000_i210 &&
4552                         hw->mac.type != e1000_i211)
4553                         return -ENOTSUP;
4554                 if (add)
4555                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4556                 else
4557                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4558                 break;
4559         default:
4560                 ret = -EINVAL;
4561                 break;
4562         }
4563
4564         return ret;
4565 }
4566
4567 /*
4568  * igb_get_ntuple_filter - get a ntuple filter
4569  *
4570  * @param
4571  * dev: Pointer to struct rte_eth_dev.
4572  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4573  *
4574  * @return
4575  *    - On success, zero.
4576  *    - On failure, a negative value.
4577  */
4578 static int
4579 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4580                         struct rte_eth_ntuple_filter *ntuple_filter)
4581 {
4582         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4583         struct e1000_filter_info *filter_info =
4584                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4585         struct e1000_5tuple_filter_info filter_5tuple;
4586         struct e1000_2tuple_filter_info filter_2tuple;
4587         struct e1000_5tuple_filter *p_5tuple_filter;
4588         struct e1000_2tuple_filter *p_2tuple_filter;
4589         int ret;
4590
4591         switch (ntuple_filter->flags) {
4592         case RTE_5TUPLE_FLAGS:
4593         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4594                 if (hw->mac.type != e1000_82576)
4595                         return -ENOTSUP;
4596                 memset(&filter_5tuple,
4597                         0,
4598                         sizeof(struct e1000_5tuple_filter_info));
4599                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4600                                                     &filter_5tuple);
4601                 if (ret < 0)
4602                         return ret;
4603                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4604                                         &filter_info->fivetuple_list,
4605                                         &filter_5tuple);
4606                 if (p_5tuple_filter == NULL) {
4607                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4608                         return -ENOENT;
4609                 }
4610                 ntuple_filter->queue = p_5tuple_filter->queue;
4611                 break;
4612         case RTE_2TUPLE_FLAGS:
4613         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4614                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4615                         return -ENOTSUP;
4616                 memset(&filter_2tuple,
4617                         0,
4618                         sizeof(struct e1000_2tuple_filter_info));
4619                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4620                 if (ret < 0)
4621                         return ret;
4622                 p_2tuple_filter = igb_2tuple_filter_lookup(
4623                                         &filter_info->twotuple_list,
4624                                         &filter_2tuple);
4625                 if (p_2tuple_filter == NULL) {
4626                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4627                         return -ENOENT;
4628                 }
4629                 ntuple_filter->queue = p_2tuple_filter->queue;
4630                 break;
4631         default:
4632                 ret = -EINVAL;
4633                 break;
4634         }
4635
4636         return 0;
4637 }
4638
4639 /*
4640  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4641  * @dev: pointer to rte_eth_dev structure
4642  * @filter_op:operation will be taken.
4643  * @arg: a pointer to specific structure corresponding to the filter_op
4644  */
4645 static int
4646 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4647                                 enum rte_filter_op filter_op,
4648                                 void *arg)
4649 {
4650         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4651         int ret;
4652
4653         MAC_TYPE_FILTER_SUP(hw->mac.type);
4654
4655         if (filter_op == RTE_ETH_FILTER_NOP)
4656                 return 0;
4657
4658         if (arg == NULL) {
4659                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4660                             filter_op);
4661                 return -EINVAL;
4662         }
4663
4664         switch (filter_op) {
4665         case RTE_ETH_FILTER_ADD:
4666                 ret = igb_add_del_ntuple_filter(dev,
4667                         (struct rte_eth_ntuple_filter *)arg,
4668                         TRUE);
4669                 break;
4670         case RTE_ETH_FILTER_DELETE:
4671                 ret = igb_add_del_ntuple_filter(dev,
4672                         (struct rte_eth_ntuple_filter *)arg,
4673                         FALSE);
4674                 break;
4675         case RTE_ETH_FILTER_GET:
4676                 ret = igb_get_ntuple_filter(dev,
4677                         (struct rte_eth_ntuple_filter *)arg);
4678                 break;
4679         default:
4680                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4681                 ret = -EINVAL;
4682                 break;
4683         }
4684         return ret;
4685 }
4686
4687 static inline int
4688 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4689                         uint16_t ethertype)
4690 {
4691         int i;
4692
4693         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4694                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4695                     (filter_info->ethertype_mask & (1 << i)))
4696                         return i;
4697         }
4698         return -1;
4699 }
4700
4701 static inline int
4702 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4703                         uint16_t ethertype, uint32_t etqf)
4704 {
4705         int i;
4706
4707         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4708                 if (!(filter_info->ethertype_mask & (1 << i))) {
4709                         filter_info->ethertype_mask |= 1 << i;
4710                         filter_info->ethertype_filters[i].ethertype = ethertype;
4711                         filter_info->ethertype_filters[i].etqf = etqf;
4712                         return i;
4713                 }
4714         }
4715         return -1;
4716 }
4717
4718 int
4719 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4720                         uint8_t idx)
4721 {
4722         if (idx >= E1000_MAX_ETQF_FILTERS)
4723                 return -1;
4724         filter_info->ethertype_mask &= ~(1 << idx);
4725         filter_info->ethertype_filters[idx].ethertype = 0;
4726         filter_info->ethertype_filters[idx].etqf = 0;
4727         return idx;
4728 }
4729
4730
4731 int
4732 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4733                         struct rte_eth_ethertype_filter *filter,
4734                         bool add)
4735 {
4736         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4737         struct e1000_filter_info *filter_info =
4738                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4739         uint32_t etqf = 0;
4740         int ret;
4741
4742         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4743                 filter->ether_type == ETHER_TYPE_IPv6) {
4744                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4745                         " ethertype filter.", filter->ether_type);
4746                 return -EINVAL;
4747         }
4748
4749         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4750                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4751                 return -EINVAL;
4752         }
4753         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4754                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4755                 return -EINVAL;
4756         }
4757
4758         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4759         if (ret >= 0 && add) {
4760                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4761                             filter->ether_type);
4762                 return -EEXIST;
4763         }
4764         if (ret < 0 && !add) {
4765                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4766                             filter->ether_type);
4767                 return -ENOENT;
4768         }
4769
4770         if (add) {
4771                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4772                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4773                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4774                 ret = igb_ethertype_filter_insert(filter_info,
4775                                 filter->ether_type, etqf);
4776                 if (ret < 0) {
4777                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4778                         return -ENOSYS;
4779                 }
4780         } else {
4781                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4782                 if (ret < 0)
4783                         return -ENOSYS;
4784         }
4785         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4786         E1000_WRITE_FLUSH(hw);
4787
4788         return 0;
4789 }
4790
4791 static int
4792 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4793                         struct rte_eth_ethertype_filter *filter)
4794 {
4795         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4796         struct e1000_filter_info *filter_info =
4797                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4798         uint32_t etqf;
4799         int ret;
4800
4801         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4802         if (ret < 0) {
4803                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4804                             filter->ether_type);
4805                 return -ENOENT;
4806         }
4807
4808         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4809         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4810                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4811                 filter->flags = 0;
4812                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4813                                 E1000_ETQF_QUEUE_SHIFT;
4814                 return 0;
4815         }
4816
4817         return -ENOENT;
4818 }
4819
4820 /*
4821  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4822  * @dev: pointer to rte_eth_dev structure
4823  * @filter_op:operation will be taken.
4824  * @arg: a pointer to specific structure corresponding to the filter_op
4825  */
4826 static int
4827 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4828                                 enum rte_filter_op filter_op,
4829                                 void *arg)
4830 {
4831         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4832         int ret;
4833
4834         MAC_TYPE_FILTER_SUP(hw->mac.type);
4835
4836         if (filter_op == RTE_ETH_FILTER_NOP)
4837                 return 0;
4838
4839         if (arg == NULL) {
4840                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4841                             filter_op);
4842                 return -EINVAL;
4843         }
4844
4845         switch (filter_op) {
4846         case RTE_ETH_FILTER_ADD:
4847                 ret = igb_add_del_ethertype_filter(dev,
4848                         (struct rte_eth_ethertype_filter *)arg,
4849                         TRUE);
4850                 break;
4851         case RTE_ETH_FILTER_DELETE:
4852                 ret = igb_add_del_ethertype_filter(dev,
4853                         (struct rte_eth_ethertype_filter *)arg,
4854                         FALSE);
4855                 break;
4856         case RTE_ETH_FILTER_GET:
4857                 ret = igb_get_ethertype_filter(dev,
4858                         (struct rte_eth_ethertype_filter *)arg);
4859                 break;
4860         default:
4861                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4862                 ret = -EINVAL;
4863                 break;
4864         }
4865         return ret;
4866 }
4867
4868 static int
4869 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4870                      enum rte_filter_type filter_type,
4871                      enum rte_filter_op filter_op,
4872                      void *arg)
4873 {
4874         int ret = 0;
4875
4876         switch (filter_type) {
4877         case RTE_ETH_FILTER_NTUPLE:
4878                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4879                 break;
4880         case RTE_ETH_FILTER_ETHERTYPE:
4881                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4882                 break;
4883         case RTE_ETH_FILTER_SYN:
4884                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4885                 break;
4886         case RTE_ETH_FILTER_FLEXIBLE:
4887                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4888                 break;
4889         case RTE_ETH_FILTER_GENERIC:
4890                 if (filter_op != RTE_ETH_FILTER_GET)
4891                         return -EINVAL;
4892                 *(const void **)arg = &igb_flow_ops;
4893                 break;
4894         default:
4895                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4896                                                         filter_type);
4897                 break;
4898         }
4899
4900         return ret;
4901 }
4902
4903 static int
4904 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4905                          struct ether_addr *mc_addr_set,
4906                          uint32_t nb_mc_addr)
4907 {
4908         struct e1000_hw *hw;
4909
4910         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4911         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4912         return 0;
4913 }
4914
4915 static uint64_t
4916 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4917 {
4918         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4919         uint64_t systime_cycles;
4920
4921         switch (hw->mac.type) {
4922         case e1000_i210:
4923         case e1000_i211:
4924                 /*
4925                  * Need to read System Time Residue Register to be able
4926                  * to read the other two registers.
4927                  */
4928                 E1000_READ_REG(hw, E1000_SYSTIMR);
4929                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4930                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4931                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4932                                 * NSEC_PER_SEC;
4933                 break;
4934         case e1000_82580:
4935         case e1000_i350:
4936         case e1000_i354:
4937                 /*
4938                  * Need to read System Time Residue Register to be able
4939                  * to read the other two registers.
4940                  */
4941                 E1000_READ_REG(hw, E1000_SYSTIMR);
4942                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4943                 /* Only the 8 LSB are valid. */
4944                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4945                                 & 0xff) << 32;
4946                 break;
4947         default:
4948                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4949                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4950                                 << 32;
4951                 break;
4952         }
4953
4954         return systime_cycles;
4955 }
4956
4957 static uint64_t
4958 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4959 {
4960         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4961         uint64_t rx_tstamp_cycles;
4962
4963         switch (hw->mac.type) {
4964         case e1000_i210:
4965         case e1000_i211:
4966                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4967                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4968                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4969                                 * NSEC_PER_SEC;
4970                 break;
4971         case e1000_82580:
4972         case e1000_i350:
4973         case e1000_i354:
4974                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4975                 /* Only the 8 LSB are valid. */
4976                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4977                                 & 0xff) << 32;
4978                 break;
4979         default:
4980                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4981                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4982                                 << 32;
4983                 break;
4984         }
4985
4986         return rx_tstamp_cycles;
4987 }
4988
4989 static uint64_t
4990 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4991 {
4992         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4993         uint64_t tx_tstamp_cycles;
4994
4995         switch (hw->mac.type) {
4996         case e1000_i210:
4997         case e1000_i211:
4998                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4999                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5000                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5001                                 * NSEC_PER_SEC;
5002                 break;
5003         case e1000_82580:
5004         case e1000_i350:
5005         case e1000_i354:
5006                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5007                 /* Only the 8 LSB are valid. */
5008                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5009                                 & 0xff) << 32;
5010                 break;
5011         default:
5012                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5013                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5014                                 << 32;
5015                 break;
5016         }
5017
5018         return tx_tstamp_cycles;
5019 }
5020
5021 static void
5022 igb_start_timecounters(struct rte_eth_dev *dev)
5023 {
5024         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5025         struct e1000_adapter *adapter =
5026                 (struct e1000_adapter *)dev->data->dev_private;
5027         uint32_t incval = 1;
5028         uint32_t shift = 0;
5029         uint64_t mask = E1000_CYCLECOUNTER_MASK;
5030
5031         switch (hw->mac.type) {
5032         case e1000_82580:
5033         case e1000_i350:
5034         case e1000_i354:
5035                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5036                 mask = (1ULL << 40) - 1;
5037                 /* fall-through */
5038         case e1000_i210:
5039         case e1000_i211:
5040                 /*
5041                  * Start incrementing the register
5042                  * used to timestamp PTP packets.
5043                  */
5044                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5045                 break;
5046         case e1000_82576:
5047                 incval = E1000_INCVALUE_82576;
5048                 shift = IGB_82576_TSYNC_SHIFT;
5049                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5050                                 E1000_INCPERIOD_82576 | incval);
5051                 break;
5052         default:
5053                 /* Not supported */
5054                 return;
5055         }
5056
5057         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5058         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5059         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5060
5061         adapter->systime_tc.cc_mask = mask;
5062         adapter->systime_tc.cc_shift = shift;
5063         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5064
5065         adapter->rx_tstamp_tc.cc_mask = mask;
5066         adapter->rx_tstamp_tc.cc_shift = shift;
5067         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5068
5069         adapter->tx_tstamp_tc.cc_mask = mask;
5070         adapter->tx_tstamp_tc.cc_shift = shift;
5071         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5072 }
5073
5074 static int
5075 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5076 {
5077         struct e1000_adapter *adapter =
5078                         (struct e1000_adapter *)dev->data->dev_private;
5079
5080         adapter->systime_tc.nsec += delta;
5081         adapter->rx_tstamp_tc.nsec += delta;
5082         adapter->tx_tstamp_tc.nsec += delta;
5083
5084         return 0;
5085 }
5086
5087 static int
5088 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5089 {
5090         uint64_t ns;
5091         struct e1000_adapter *adapter =
5092                         (struct e1000_adapter *)dev->data->dev_private;
5093
5094         ns = rte_timespec_to_ns(ts);
5095
5096         /* Set the timecounters to a new value. */
5097         adapter->systime_tc.nsec = ns;
5098         adapter->rx_tstamp_tc.nsec = ns;
5099         adapter->tx_tstamp_tc.nsec = ns;
5100
5101         return 0;
5102 }
5103
5104 static int
5105 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5106 {
5107         uint64_t ns, systime_cycles;
5108         struct e1000_adapter *adapter =
5109                         (struct e1000_adapter *)dev->data->dev_private;
5110
5111         systime_cycles = igb_read_systime_cyclecounter(dev);
5112         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5113         *ts = rte_ns_to_timespec(ns);
5114
5115         return 0;
5116 }
5117
5118 static int
5119 igb_timesync_enable(struct rte_eth_dev *dev)
5120 {
5121         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5122         uint32_t tsync_ctl;
5123         uint32_t tsauxc;
5124
5125         /* Stop the timesync system time. */
5126         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5127         /* Reset the timesync system time value. */
5128         switch (hw->mac.type) {
5129         case e1000_82580:
5130         case e1000_i350:
5131         case e1000_i354:
5132         case e1000_i210:
5133         case e1000_i211:
5134                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5135                 /* fall-through */
5136         case e1000_82576:
5137                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5138                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5139                 break;
5140         default:
5141                 /* Not supported. */
5142                 return -ENOTSUP;
5143         }
5144
5145         /* Enable system time for it isn't on by default. */
5146         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5147         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5148         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5149
5150         igb_start_timecounters(dev);
5151
5152         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5153         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5154                         (ETHER_TYPE_1588 |
5155                          E1000_ETQF_FILTER_ENABLE |
5156                          E1000_ETQF_1588));
5157
5158         /* Enable timestamping of received PTP packets. */
5159         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5160         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5161         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5162
5163         /* Enable Timestamping of transmitted PTP packets. */
5164         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5165         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5166         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5167
5168         return 0;
5169 }
5170
5171 static int
5172 igb_timesync_disable(struct rte_eth_dev *dev)
5173 {
5174         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5175         uint32_t tsync_ctl;
5176
5177         /* Disable timestamping of transmitted PTP packets. */
5178         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5179         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5180         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5181
5182         /* Disable timestamping of received PTP packets. */
5183         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5184         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5185         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5186
5187         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5188         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5189
5190         /* Stop incrementating the System Time registers. */
5191         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5192
5193         return 0;
5194 }
5195
5196 static int
5197 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5198                                struct timespec *timestamp,
5199                                uint32_t flags __rte_unused)
5200 {
5201         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5202         struct e1000_adapter *adapter =
5203                         (struct e1000_adapter *)dev->data->dev_private;
5204         uint32_t tsync_rxctl;
5205         uint64_t rx_tstamp_cycles;
5206         uint64_t ns;
5207
5208         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5209         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5210                 return -EINVAL;
5211
5212         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5213         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5214         *timestamp = rte_ns_to_timespec(ns);
5215
5216         return  0;
5217 }
5218
5219 static int
5220 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5221                                struct timespec *timestamp)
5222 {
5223         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5224         struct e1000_adapter *adapter =
5225                         (struct e1000_adapter *)dev->data->dev_private;
5226         uint32_t tsync_txctl;
5227         uint64_t tx_tstamp_cycles;
5228         uint64_t ns;
5229
5230         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5231         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5232                 return -EINVAL;
5233
5234         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5235         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5236         *timestamp = rte_ns_to_timespec(ns);
5237
5238         return  0;
5239 }
5240
5241 static int
5242 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5243 {
5244         int count = 0;
5245         int g_ind = 0;
5246         const struct reg_info *reg_group;
5247
5248         while ((reg_group = igb_regs[g_ind++]))
5249                 count += igb_reg_group_count(reg_group);
5250
5251         return count;
5252 }
5253
5254 static int
5255 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5256 {
5257         int count = 0;
5258         int g_ind = 0;
5259         const struct reg_info *reg_group;
5260
5261         while ((reg_group = igbvf_regs[g_ind++]))
5262                 count += igb_reg_group_count(reg_group);
5263
5264         return count;
5265 }
5266
5267 static int
5268 eth_igb_get_regs(struct rte_eth_dev *dev,
5269         struct rte_dev_reg_info *regs)
5270 {
5271         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5272         uint32_t *data = regs->data;
5273         int g_ind = 0;
5274         int count = 0;
5275         const struct reg_info *reg_group;
5276
5277         if (data == NULL) {
5278                 regs->length = eth_igb_get_reg_length(dev);
5279                 regs->width = sizeof(uint32_t);
5280                 return 0;
5281         }
5282
5283         /* Support only full register dump */
5284         if ((regs->length == 0) ||
5285             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5286                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5287                         hw->device_id;
5288                 while ((reg_group = igb_regs[g_ind++]))
5289                         count += igb_read_regs_group(dev, &data[count],
5290                                                         reg_group);
5291                 return 0;
5292         }
5293
5294         return -ENOTSUP;
5295 }
5296
5297 static int
5298 igbvf_get_regs(struct rte_eth_dev *dev,
5299         struct rte_dev_reg_info *regs)
5300 {
5301         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5302         uint32_t *data = regs->data;
5303         int g_ind = 0;
5304         int count = 0;
5305         const struct reg_info *reg_group;
5306
5307         if (data == NULL) {
5308                 regs->length = igbvf_get_reg_length(dev);
5309                 regs->width = sizeof(uint32_t);
5310                 return 0;
5311         }
5312
5313         /* Support only full register dump */
5314         if ((regs->length == 0) ||
5315             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5316                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5317                         hw->device_id;
5318                 while ((reg_group = igbvf_regs[g_ind++]))
5319                         count += igb_read_regs_group(dev, &data[count],
5320                                                         reg_group);
5321                 return 0;
5322         }
5323
5324         return -ENOTSUP;
5325 }
5326
5327 static int
5328 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5329 {
5330         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5331
5332         /* Return unit is byte count */
5333         return hw->nvm.word_size * 2;
5334 }
5335
5336 static int
5337 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5338         struct rte_dev_eeprom_info *in_eeprom)
5339 {
5340         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5341         struct e1000_nvm_info *nvm = &hw->nvm;
5342         uint16_t *data = in_eeprom->data;
5343         int first, length;
5344
5345         first = in_eeprom->offset >> 1;
5346         length = in_eeprom->length >> 1;
5347         if ((first >= hw->nvm.word_size) ||
5348             ((first + length) >= hw->nvm.word_size))
5349                 return -EINVAL;
5350
5351         in_eeprom->magic = hw->vendor_id |
5352                 ((uint32_t)hw->device_id << 16);
5353
5354         if ((nvm->ops.read) == NULL)
5355                 return -ENOTSUP;
5356
5357         return nvm->ops.read(hw, first, length, data);
5358 }
5359
5360 static int
5361 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5362         struct rte_dev_eeprom_info *in_eeprom)
5363 {
5364         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5365         struct e1000_nvm_info *nvm = &hw->nvm;
5366         uint16_t *data = in_eeprom->data;
5367         int first, length;
5368
5369         first = in_eeprom->offset >> 1;
5370         length = in_eeprom->length >> 1;
5371         if ((first >= hw->nvm.word_size) ||
5372             ((first + length) >= hw->nvm.word_size))
5373                 return -EINVAL;
5374
5375         in_eeprom->magic = (uint32_t)hw->vendor_id |
5376                 ((uint32_t)hw->device_id << 16);
5377
5378         if ((nvm->ops.write) == NULL)
5379                 return -ENOTSUP;
5380         return nvm->ops.write(hw,  first, length, data);
5381 }
5382
5383 static int
5384 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5385 {
5386         struct e1000_hw *hw =
5387                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5388         uint32_t mask = 1 << queue_id;
5389
5390         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5391         E1000_WRITE_FLUSH(hw);
5392
5393         return 0;
5394 }
5395
5396 static int
5397 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5398 {
5399         struct e1000_hw *hw =
5400                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5401         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5402         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5403         uint32_t mask = 1 << queue_id;
5404         uint32_t regval;
5405
5406         regval = E1000_READ_REG(hw, E1000_EIMS);
5407         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5408         E1000_WRITE_FLUSH(hw);
5409
5410         rte_intr_enable(intr_handle);
5411
5412         return 0;
5413 }
5414
5415 static void
5416 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5417                    uint8_t index, uint8_t offset)
5418 {
5419         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5420
5421         /* clear bits */
5422         val &= ~((uint32_t)0xFF << offset);
5423
5424         /* write vector and valid bit */
5425         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5426
5427         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5428 }
5429
5430 static void
5431 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5432                            uint8_t queue, uint8_t msix_vector)
5433 {
5434         uint32_t tmp = 0;
5435
5436         if (hw->mac.type == e1000_82575) {
5437                 if (direction == 0)
5438                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5439                 else if (direction == 1)
5440                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5441                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5442         } else if (hw->mac.type == e1000_82576) {
5443                 if ((direction == 0) || (direction == 1))
5444                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5445                                            ((queue & 0x8) << 1) +
5446                                            8 * direction);
5447         } else if ((hw->mac.type == e1000_82580) ||
5448                         (hw->mac.type == e1000_i350) ||
5449                         (hw->mac.type == e1000_i354) ||
5450                         (hw->mac.type == e1000_i210) ||
5451                         (hw->mac.type == e1000_i211)) {
5452                 if ((direction == 0) || (direction == 1))
5453                         eth_igb_write_ivar(hw, msix_vector,
5454                                            queue >> 1,
5455                                            ((queue & 0x1) << 4) +
5456                                            8 * direction);
5457         }
5458 }
5459
5460 /* Sets up the hardware to generate MSI-X interrupts properly
5461  * @hw
5462  *  board private structure
5463  */
5464 static void
5465 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5466 {
5467         int queue_id;
5468         uint32_t tmpval, regval, intr_mask;
5469         struct e1000_hw *hw =
5470                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5471         uint32_t vec = E1000_MISC_VEC_ID;
5472         uint32_t base = E1000_MISC_VEC_ID;
5473         uint32_t misc_shift = 0;
5474         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5475         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5476
5477         /* won't configure msix register if no mapping is done
5478          * between intr vector and event fd
5479          */
5480         if (!rte_intr_dp_is_en(intr_handle))
5481                 return;
5482
5483         if (rte_intr_allow_others(intr_handle)) {
5484                 vec = base = E1000_RX_VEC_START;
5485                 misc_shift = 1;
5486         }
5487
5488         /* set interrupt vector for other causes */
5489         if (hw->mac.type == e1000_82575) {
5490                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5491                 /* enable MSI-X PBA support */
5492                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5493
5494                 /* Auto-Mask interrupts upon ICR read */
5495                 tmpval |= E1000_CTRL_EXT_EIAME;
5496                 tmpval |= E1000_CTRL_EXT_IRCA;
5497
5498                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5499
5500                 /* enable msix_other interrupt */
5501                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5502                 regval = E1000_READ_REG(hw, E1000_EIAC);
5503                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5504                 regval = E1000_READ_REG(hw, E1000_EIAM);
5505                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5506         } else if ((hw->mac.type == e1000_82576) ||
5507                         (hw->mac.type == e1000_82580) ||
5508                         (hw->mac.type == e1000_i350) ||
5509                         (hw->mac.type == e1000_i354) ||
5510                         (hw->mac.type == e1000_i210) ||
5511                         (hw->mac.type == e1000_i211)) {
5512                 /* turn on MSI-X capability first */
5513                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5514                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5515                                         E1000_GPIE_NSICR);
5516                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5517                         misc_shift;
5518                 regval = E1000_READ_REG(hw, E1000_EIAC);
5519                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5520
5521                 /* enable msix_other interrupt */
5522                 regval = E1000_READ_REG(hw, E1000_EIMS);
5523                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5524                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5525                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5526         }
5527
5528         /* use EIAM to auto-mask when MSI-X interrupt
5529          * is asserted, this saves a register write for every interrupt
5530          */
5531         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5532                 misc_shift;
5533         regval = E1000_READ_REG(hw, E1000_EIAM);
5534         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5535
5536         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5537                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5538                 intr_handle->intr_vec[queue_id] = vec;
5539                 if (vec < base + intr_handle->nb_efd - 1)
5540                         vec++;
5541         }
5542
5543         E1000_WRITE_FLUSH(hw);
5544 }
5545
5546 /* restore n-tuple filter */
5547 static inline void
5548 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5549 {
5550         struct e1000_filter_info *filter_info =
5551                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5552         struct e1000_5tuple_filter *p_5tuple;
5553         struct e1000_2tuple_filter *p_2tuple;
5554
5555         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5556                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5557         }
5558
5559         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5560                 igb_inject_2uple_filter(dev, p_2tuple);
5561         }
5562 }
5563
5564 /* restore SYN filter */
5565 static inline void
5566 igb_syn_filter_restore(struct rte_eth_dev *dev)
5567 {
5568         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5569         struct e1000_filter_info *filter_info =
5570                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5571         uint32_t synqf;
5572
5573         synqf = filter_info->syn_info;
5574
5575         if (synqf & E1000_SYN_FILTER_ENABLE) {
5576                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5577                 E1000_WRITE_FLUSH(hw);
5578         }
5579 }
5580
5581 /* restore ethernet type filter */
5582 static inline void
5583 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5584 {
5585         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5586         struct e1000_filter_info *filter_info =
5587                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5588         int i;
5589
5590         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5591                 if (filter_info->ethertype_mask & (1 << i)) {
5592                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5593                                 filter_info->ethertype_filters[i].etqf);
5594                         E1000_WRITE_FLUSH(hw);
5595                 }
5596         }
5597 }
5598
5599 /* restore flex byte filter */
5600 static inline void
5601 igb_flex_filter_restore(struct rte_eth_dev *dev)
5602 {
5603         struct e1000_filter_info *filter_info =
5604                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5605         struct e1000_flex_filter *flex_filter;
5606
5607         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5608                 igb_inject_flex_filter(dev, flex_filter);
5609         }
5610 }
5611
5612 /* restore all types filter */
5613 static int
5614 igb_filter_restore(struct rte_eth_dev *dev)
5615 {
5616         igb_ntuple_filter_restore(dev);
5617         igb_ethertype_filter_restore(dev);
5618         igb_syn_filter_restore(dev);
5619         igb_flex_filter_restore(dev);
5620
5621         return 0;
5622 }
5623
5624 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5625 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5626 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5627 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5628 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5629 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");