drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64
  65 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  66 #define IGB_DEFAULT_RX_HTHRESH      8
  67 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  68
  69 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  70 #define IGB_DEFAULT_TX_HTHRESH      1
  71 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  72
  73 #define IGB_HKEY_MAX_INDEX 10
  74
  75 /* Bit shift and mask */
  76 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  77 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  78 #define IGB_8_BIT_WIDTH  CHAR_BIT
  79 #define IGB_8_BIT_MASK   UINT8_MAX
  80
  81 /* Additional timesync values. */
  82 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  83 #define E1000_ETQF_FILTER_1588       3
  84 #define IGB_82576_TSYNC_SHIFT        16
  85 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  86 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  88
  89 #define E1000_VTIVAR_MISC                0x01740
  90 #define E1000_VTIVAR_MISC_MASK           0xFF
  91 #define E1000_VTIVAR_VALID               0x80
  92 #define E1000_VTIVAR_MISC_MAILBOX        0
  93 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  94
  95 /* External VLAN Enable bit mask */
  96 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  97
  98 /* External VLAN Ether Type bit mask and shift */
  99 #define E1000_VET_VET_EXT            0xFFFF0000
 100 #define E1000_VET_VET_EXT_SHIFT      16
 101
 102 static int  eth_igb_configure(struct rte_eth_dev *dev);
 103 static int  eth_igb_start(struct rte_eth_dev *dev);
 104 static void eth_igb_stop(struct rte_eth_dev *dev);
 105 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 107 static void eth_igb_close(struct rte_eth_dev *dev);
 108 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 110 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 112 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 113                                 int wait_to_complete);
 114 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 115                                 struct rte_eth_stats *rte_stats);
 116 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 117                               struct rte_eth_xstat *xstats, unsigned n);
 118 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 119                                     struct rte_eth_xstat_name *xstats_names,
 120                                     unsigned limit);
 121 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 122 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 123 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 124                               struct rte_eth_dev_info *dev_info);
 125 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 126 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 127                                 struct rte_eth_dev_info *dev_info);
 128 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 129                                 struct rte_eth_fc_conf *fc_conf);
 130 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 131                                 struct rte_eth_fc_conf *fc_conf);
 132 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 133 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 134 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 135 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 136                                     struct rte_intr_handle *handle);
 137 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 138                                                         void *param);
 139 static int  igb_hardware_init(struct e1000_hw *hw);
 140 static void igb_hw_control_acquire(struct e1000_hw *hw);
 141 static void igb_hw_control_release(struct e1000_hw *hw);
 142 static void igb_init_manageability(struct e1000_hw *hw);
 143 static void igb_release_manageability(struct e1000_hw *hw);
 144
 145 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 146
 147 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 148                 uint16_t vlan_id, int on);
 149 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 150                                  enum rte_vlan_type vlan_type,
 151                                  uint16_t tpid_id);
 152 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 153
 154 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 155 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 156 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 157 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 158 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 159 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 160
 161 static int eth_igb_led_on(struct rte_eth_dev *dev);
 162 static int eth_igb_led_off(struct rte_eth_dev *dev);
 163
 164 static void igb_intr_disable(struct e1000_hw *hw);
 165 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 166 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 167                 struct ether_addr *mac_addr,
 168                 uint32_t index, uint32_t pool);
 169 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 170 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 171                 struct ether_addr *addr);
 172
 173 static void igbvf_intr_disable(struct e1000_hw *hw);
 174 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 175 static int igbvf_dev_start(struct rte_eth_dev *dev);
 176 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 177 static void igbvf_dev_close(struct rte_eth_dev *dev);
 178 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 179 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 180 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 181 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 182 static int eth_igbvf_link_update(struct e1000_hw *hw);
 183 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 184                                 struct rte_eth_stats *rte_stats);
 185 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 186                                 struct rte_eth_xstat *xstats, unsigned n);
 187 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 188                                       struct rte_eth_xstat_name *xstats_names,
 189                                       unsigned limit);
 190 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 191 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 192                 uint16_t vlan_id, int on);
 193 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 194 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 195 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 196                 struct ether_addr *addr);
 197 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 198 static int igbvf_get_regs(struct rte_eth_dev *dev,
 199                 struct rte_dev_reg_info *regs);
 200
 201 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 202                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 203                                    uint16_t reta_size);
 204 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 205                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 206                                   uint16_t reta_size);
 207
 208 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 209                         struct rte_eth_syn_filter *filter,
 210                         bool add);
 211 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 212                         struct rte_eth_syn_filter *filter);
 213 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 214                         enum rte_filter_op filter_op,
 215                         void *arg);
 216 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 217                         struct rte_eth_ntuple_filter *ntuple_filter);
 218 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 219                         struct rte_eth_ntuple_filter *ntuple_filter);
 220 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 221                         struct rte_eth_flex_filter *filter,
 222                         bool add);
 223 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 224                         struct rte_eth_flex_filter *filter);
 225 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 226                         enum rte_filter_op filter_op,
 227                         void *arg);
 228 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 229                         struct rte_eth_ntuple_filter *ntuple_filter);
 230 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 231                         struct rte_eth_ntuple_filter *ntuple_filter);
 232 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 233                         struct rte_eth_ntuple_filter *filter,
 234                         bool add);
 235 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 236                         struct rte_eth_ntuple_filter *filter);
 237 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 238                                 enum rte_filter_op filter_op,
 239                                 void *arg);
 240 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 241                         struct rte_eth_ethertype_filter *filter,
 242                         bool add);
 243 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 244                                 enum rte_filter_op filter_op,
 245                                 void *arg);
 246 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 247                         struct rte_eth_ethertype_filter *filter);
 248 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 249                      enum rte_filter_type filter_type,
 250                      enum rte_filter_op filter_op,
 251                      void *arg);
 252 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 253 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 254                 struct rte_dev_reg_info *regs);
 255 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 256 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 257                 struct rte_dev_eeprom_info *eeprom);
 258 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 259                 struct rte_dev_eeprom_info *eeprom);
 260 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 261                                     struct ether_addr *mc_addr_set,
 262                                     uint32_t nb_mc_addr);
 263 static int igb_timesync_enable(struct rte_eth_dev *dev);
 264 static int igb_timesync_disable(struct rte_eth_dev *dev);
 265 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 266                                           struct timespec *timestamp,
 267                                           uint32_t flags);
 268 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 269                                           struct timespec *timestamp);
 270 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 271 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 272                                   struct timespec *timestamp);
 273 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 274                                    const struct timespec *timestamp);
 275 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 276                                         uint16_t queue_id);
 277 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 278                                          uint16_t queue_id);
 279 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 280                                        uint8_t queue, uint8_t msix_vector);
 281 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 282                                uint8_t index, uint8_t offset);
 283 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 284 static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
 285                                         void *param);
 286 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 287
 288 /*
 289  * Define VF Stats MACRO for Non "cleared on read" register
 290  */
 291 #define UPDATE_VF_STAT(reg, last, cur)            \
 292 {                                                 \
 293         u32 latest = E1000_READ_REG(hw, reg);     \
 294         cur += (latest - last) & UINT_MAX;        \
 295         last = latest;                            \
 296 }
 297
 298 #define IGB_FC_PAUSE_TIME 0x0680
 299 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 300 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 301
 302 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 303
 304 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 305
 306 /*
 307  * The set of PCI devices this driver supports
 308  */
 309 static const struct rte_pci_id pci_id_igb_map[] = {
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 318
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 322
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 329
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 347         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 348         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 349         { .vendor_id = 0, /* sentinel */ },
 350 };
 351
 352 /*
 353  * The set of PCI devices this driver supports (for 82576&I350 VF)
 354  */
 355 static const struct rte_pci_id pci_id_igbvf_map[] = {
 356         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 357         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 358         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 359         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 360         { .vendor_id = 0, /* sentinel */ },
 361 };
 362
 363 static const struct rte_eth_desc_lim rx_desc_lim = {
 364         .nb_max = E1000_MAX_RING_DESC,
 365         .nb_min = E1000_MIN_RING_DESC,
 366         .nb_align = IGB_RXD_ALIGN,
 367 };
 368
 369 static const struct rte_eth_desc_lim tx_desc_lim = {
 370         .nb_max = E1000_MAX_RING_DESC,
 371         .nb_min = E1000_MIN_RING_DESC,
 372         .nb_align = IGB_RXD_ALIGN,
 373 };
 374
 375 static const struct eth_dev_ops eth_igb_ops = {
 376         .dev_configure        = eth_igb_configure,
 377         .dev_start            = eth_igb_start,
 378         .dev_stop             = eth_igb_stop,
 379         .dev_set_link_up      = eth_igb_dev_set_link_up,
 380         .dev_set_link_down    = eth_igb_dev_set_link_down,
 381         .dev_close            = eth_igb_close,
 382         .promiscuous_enable   = eth_igb_promiscuous_enable,
 383         .promiscuous_disable  = eth_igb_promiscuous_disable,
 384         .allmulticast_enable  = eth_igb_allmulticast_enable,
 385         .allmulticast_disable = eth_igb_allmulticast_disable,
 386         .link_update          = eth_igb_link_update,
 387         .stats_get            = eth_igb_stats_get,
 388         .xstats_get           = eth_igb_xstats_get,
 389         .xstats_get_names     = eth_igb_xstats_get_names,
 390         .stats_reset          = eth_igb_stats_reset,
 391         .xstats_reset         = eth_igb_xstats_reset,
 392         .dev_infos_get        = eth_igb_infos_get,
 393         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 394         .mtu_set              = eth_igb_mtu_set,
 395         .vlan_filter_set      = eth_igb_vlan_filter_set,
 396         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 397         .vlan_offload_set     = eth_igb_vlan_offload_set,
 398         .rx_queue_setup       = eth_igb_rx_queue_setup,
 399         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 400         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 401         .rx_queue_release     = eth_igb_rx_queue_release,
 402         .rx_queue_count       = eth_igb_rx_queue_count,
 403         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 404         .tx_queue_setup       = eth_igb_tx_queue_setup,
 405         .tx_queue_release     = eth_igb_tx_queue_release,
 406         .dev_led_on           = eth_igb_led_on,
 407         .dev_led_off          = eth_igb_led_off,
 408         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 409         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 410         .mac_addr_add         = eth_igb_rar_set,
 411         .mac_addr_remove      = eth_igb_rar_clear,
 412         .mac_addr_set         = eth_igb_default_mac_addr_set,
 413         .reta_update          = eth_igb_rss_reta_update,
 414         .reta_query           = eth_igb_rss_reta_query,
 415         .rss_hash_update      = eth_igb_rss_hash_update,
 416         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 417         .filter_ctrl          = eth_igb_filter_ctrl,
 418         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 419         .rxq_info_get         = igb_rxq_info_get,
 420         .txq_info_get         = igb_txq_info_get,
 421         .timesync_enable      = igb_timesync_enable,
 422         .timesync_disable     = igb_timesync_disable,
 423         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 424         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 425         .get_reg              = eth_igb_get_regs,
 426         .get_eeprom_length    = eth_igb_get_eeprom_length,
 427         .get_eeprom           = eth_igb_get_eeprom,
 428         .set_eeprom           = eth_igb_set_eeprom,
 429         .timesync_adjust_time = igb_timesync_adjust_time,
 430         .timesync_read_time   = igb_timesync_read_time,
 431         .timesync_write_time  = igb_timesync_write_time,
 432 };
 433
 434 /*
 435  * dev_ops for virtual function, bare necessities for basic vf
 436  * operation have been implemented
 437  */
 438 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 439         .dev_configure        = igbvf_dev_configure,
 440         .dev_start            = igbvf_dev_start,
 441         .dev_stop             = igbvf_dev_stop,
 442         .dev_close            = igbvf_dev_close,
 443         .promiscuous_enable   = igbvf_promiscuous_enable,
 444         .promiscuous_disable  = igbvf_promiscuous_disable,
 445         .allmulticast_enable  = igbvf_allmulticast_enable,
 446         .allmulticast_disable = igbvf_allmulticast_disable,
 447         .link_update          = eth_igb_link_update,
 448         .stats_get            = eth_igbvf_stats_get,
 449         .xstats_get           = eth_igbvf_xstats_get,
 450         .xstats_get_names     = eth_igbvf_xstats_get_names,
 451         .stats_reset          = eth_igbvf_stats_reset,
 452         .xstats_reset         = eth_igbvf_stats_reset,
 453         .vlan_filter_set      = igbvf_vlan_filter_set,
 454         .dev_infos_get        = eth_igbvf_infos_get,
 455         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 456         .rx_queue_setup       = eth_igb_rx_queue_setup,
 457         .rx_queue_release     = eth_igb_rx_queue_release,
 458         .tx_queue_setup       = eth_igb_tx_queue_setup,
 459         .tx_queue_release     = eth_igb_tx_queue_release,
 460         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 461         .rxq_info_get         = igb_rxq_info_get,
 462         .txq_info_get         = igb_txq_info_get,
 463         .mac_addr_set         = igbvf_default_mac_addr_set,
 464         .get_reg              = igbvf_get_regs,
 465 };
 466
 467 /* store statistics names and its offset in stats structure */
 468 struct rte_igb_xstats_name_off {
 469         char name[RTE_ETH_XSTATS_NAME_SIZE];
 470         unsigned offset;
 471 };
 472
 473 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 474         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 475         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 476         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 477         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 478         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 479         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 480         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 481                 ecol)},
 482         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 483         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 484         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 485         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 486         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 487         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 488         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 489         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 490         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 491         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 492         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 493                 fcruc)},
 494         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 495         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 496         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 497         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 498         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 499                 prc1023)},
 500         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 501                 prc1522)},
 502         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 503         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 504         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 505         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 506         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 507         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 508         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 509         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 510         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 511         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 512         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 513         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 514         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 515         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 516         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 517         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 518         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 519         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 520                 ptc1023)},
 521         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 522                 ptc1522)},
 523         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 524         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 525         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 526         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 527         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 528         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 529         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 530
 531         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 532 };
 533
 534 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 535                 sizeof(rte_igb_stats_strings[0]))
 536
 537 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 538         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 539         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 540         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 541         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 542         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 543 };
 544
 545 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 546                 sizeof(rte_igbvf_stats_strings[0]))
 547
 548 /**
 549  * Atomically reads the link status information from global
 550  * structure rte_eth_dev.
 551  *
 552  * @param dev
 553  *   - Pointer to the structure rte_eth_dev to read from.
 554  *   - Pointer to the buffer to be saved with the link status.
 555  *
 556  * @return
 557  *   - On success, zero.
 558  *   - On failure, negative value.
 559  */
 560 static inline int
 561 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 562                                 struct rte_eth_link *link)
 563 {
 564         struct rte_eth_link *dst = link;
 565         struct rte_eth_link *src = &(dev->data->dev_link);
 566
 567         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 568                                         *(uint64_t *)src) == 0)
 569                 return -1;
 570
 571         return 0;
 572 }
 573
 574 /**
 575  * Atomically writes the link status information into global
 576  * structure rte_eth_dev.
 577  *
 578  * @param dev
 579  *   - Pointer to the structure rte_eth_dev to read from.
 580  *   - Pointer to the buffer to be saved with the link status.
 581  *
 582  * @return
 583  *   - On success, zero.
 584  *   - On failure, negative value.
 585  */
 586 static inline int
 587 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 588                                 struct rte_eth_link *link)
 589 {
 590         struct rte_eth_link *dst = &(dev->data->dev_link);
 591         struct rte_eth_link *src = link;
 592
 593         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 594                                         *(uint64_t *)src) == 0)
 595                 return -1;
 596
 597         return 0;
 598 }
 599
 600 static inline void
 601 igb_intr_enable(struct rte_eth_dev *dev)
 602 {
 603         struct e1000_interrupt *intr =
 604                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 605         struct e1000_hw *hw =
 606                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 607
 608         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 609         E1000_WRITE_FLUSH(hw);
 610 }
 611
 612 static void
 613 igb_intr_disable(struct e1000_hw *hw)
 614 {
 615         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 616         E1000_WRITE_FLUSH(hw);
 617 }
 618
 619 static inline void
 620 igbvf_intr_enable(struct rte_eth_dev *dev)
 621 {
 622         struct e1000_hw *hw =
 623                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 624
 625         /* only for mailbox */
 626         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 627         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 628         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 629         E1000_WRITE_FLUSH(hw);
 630 }
 631
 632 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 633 static void
 634 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 635 {
 636         uint32_t tmp = 0;
 637
 638         /* mailbox */
 639         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 640         tmp |= E1000_VTIVAR_VALID;
 641         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 642 }
 643
 644 static void
 645 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 646 {
 647         struct e1000_hw *hw =
 648                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 649
 650         /* Configure VF other cause ivar */
 651         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 652 }
 653
 654 static inline int32_t
 655 igb_pf_reset_hw(struct e1000_hw *hw)
 656 {
 657         uint32_t ctrl_ext;
 658         int32_t status;
 659
 660         status = e1000_reset_hw(hw);
 661
 662         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 663         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 664         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 665         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 666         E1000_WRITE_FLUSH(hw);
 667
 668         return status;
 669 }
 670
 671 static void
 672 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 673 {
 674         struct e1000_hw *hw =
 675                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 676
 677
 678         hw->vendor_id = pci_dev->id.vendor_id;
 679         hw->device_id = pci_dev->id.device_id;
 680         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 681         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 682
 683         e1000_set_mac_type(hw);
 684
 685         /* need to check if it is a vf device below */
 686 }
 687
 688 static int
 689 igb_reset_swfw_lock(struct e1000_hw *hw)
 690 {
 691         int ret_val;
 692
 693         /*
 694          * Do mac ops initialization manually here, since we will need
 695          * some function pointers set by this call.
 696          */
 697         ret_val = e1000_init_mac_params(hw);
 698         if (ret_val)
 699                 return ret_val;
 700
 701         /*
 702          * SMBI lock should not fail in this early stage. If this is the case,
 703          * it is due to an improper exit of the application.
 704          * So force the release of the faulty lock.
 705          */
 706         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 707                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 708         }
 709         e1000_put_hw_semaphore_generic(hw);
 710
 711         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 712                 uint16_t mask;
 713
 714                 /*
 715                  * Phy lock should not fail in this early stage. If this is the case,
 716                  * it is due to an improper exit of the application.
 717                  * So force the release of the faulty lock.
 718                  */
 719                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 720                 if (hw->bus.func > E1000_FUNC_1)
 721                         mask <<= 2;
 722                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 723                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 724                                     hw->bus.func);
 725                 }
 726                 hw->mac.ops.release_swfw_sync(hw, mask);
 727
 728                 /*
 729                  * This one is more tricky since it is common to all ports; but
 730                  * swfw_sync retries last long enough (1s) to be almost sure that if
 731                  * lock can not be taken it is due to an improper lock of the
 732                  * semaphore.
 733                  */
 734                 mask = E1000_SWFW_EEP_SM;
 735                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 736                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 737                 }
 738                 hw->mac.ops.release_swfw_sync(hw, mask);
 739         }
 740
 741         return E1000_SUCCESS;
 742 }
 743
 744 static int
 745 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 746 {
 747         int error = 0;
 748         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
 749         struct e1000_hw *hw =
 750                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 751         struct e1000_vfta * shadow_vfta =
 752                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 753         struct e1000_filter_info *filter_info =
 754                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 755         struct e1000_adapter *adapter =
 756                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 757
 758         uint32_t ctrl_ext;
 759
 760         eth_dev->dev_ops = &eth_igb_ops;
 761         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 762         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 763
 764         /* for secondary processes, we don't initialise any further as primary
 765          * has already done this work. Only check we don't need a different
 766          * RX function */
 767         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 768                 if (eth_dev->data->scattered_rx)
 769                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 770                 return 0;
 771         }
 772
 773         rte_eth_copy_pci_info(eth_dev, pci_dev);
 774
 775         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 776
 777         igb_identify_hardware(eth_dev, pci_dev);
 778         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 779                 error = -EIO;
 780                 goto err_late;
 781         }
 782
 783         e1000_get_bus_info(hw);
 784
 785         /* Reset any pending lock */
 786         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 787                 error = -EIO;
 788                 goto err_late;
 789         }
 790
 791         /* Finish initialization */
 792         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 793                 error = -EIO;
 794                 goto err_late;
 795         }
 796
 797         hw->mac.autoneg = 1;
 798         hw->phy.autoneg_wait_to_complete = 0;
 799         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 800
 801         /* Copper options */
 802         if (hw->phy.media_type == e1000_media_type_copper) {
 803                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 804                 hw->phy.disable_polarity_correction = 0;
 805                 hw->phy.ms_type = e1000_ms_hw_default;
 806         }
 807
 808         /*
 809          * Start from a known state, this is important in reading the nvm
 810          * and mac from that.
 811          */
 812         igb_pf_reset_hw(hw);
 813
 814         /* Make sure we have a good EEPROM before we read from it */
 815         if (e1000_validate_nvm_checksum(hw) < 0) {
 816                 /*
 817                  * Some PCI-E parts fail the first check due to
 818                  * the link being in sleep state, call it again,
 819                  * if it fails a second time its a real issue.
 820                  */
 821                 if (e1000_validate_nvm_checksum(hw) < 0) {
 822                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 823                         error = -EIO;
 824                         goto err_late;
 825                 }
 826         }
 827
 828         /* Read the permanent MAC address out of the EEPROM */
 829         if (e1000_read_mac_addr(hw) != 0) {
 830                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 831                 error = -EIO;
 832                 goto err_late;
 833         }
 834
 835         /* Allocate memory for storing MAC addresses */
 836         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 837                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 838         if (eth_dev->data->mac_addrs == NULL) {
 839                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 840                                                 "store MAC addresses",
 841                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 842                 error = -ENOMEM;
 843                 goto err_late;
 844         }
 845
 846         /* Copy the permanent MAC address */
 847         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 848
 849         /* initialize the vfta */
 850         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 851
 852         /* Now initialize the hardware */
 853         if (igb_hardware_init(hw) != 0) {
 854                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 855                 rte_free(eth_dev->data->mac_addrs);
 856                 eth_dev->data->mac_addrs = NULL;
 857                 error = -ENODEV;
 858                 goto err_late;
 859         }
 860         hw->mac.get_link_status = 1;
 861         adapter->stopped = 0;
 862
 863         /* Indicate SOL/IDER usage */
 864         if (e1000_check_reset_block(hw) < 0) {
 865                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 866                                         "SOL/IDER session");
 867         }
 868
 869         /* initialize PF if max_vfs not zero */
 870         igb_pf_host_init(eth_dev);
 871
 872         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 873         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 874         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 875         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 876         E1000_WRITE_FLUSH(hw);
 877
 878         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 879                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 880                      pci_dev->id.device_id);
 881
 882         rte_intr_callback_register(&pci_dev->intr_handle,
 883                                    eth_igb_interrupt_handler,
 884                                    (void *)eth_dev);
 885
 886         /* enable uio/vfio intr/eventfd mapping */
 887         rte_intr_enable(&pci_dev->intr_handle);
 888
 889         /* enable support intr */
 890         igb_intr_enable(eth_dev);
 891
 892         TAILQ_INIT(&filter_info->flex_list);
 893         filter_info->flex_mask = 0;
 894         TAILQ_INIT(&filter_info->twotuple_list);
 895         filter_info->twotuple_mask = 0;
 896         TAILQ_INIT(&filter_info->fivetuple_list);
 897         filter_info->fivetuple_mask = 0;
 898
 899         return 0;
 900
 901 err_late:
 902         igb_hw_control_release(hw);
 903
 904         return error;
 905 }
 906
 907 static int
 908 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 909 {
 910         struct rte_pci_device *pci_dev;
 911         struct rte_intr_handle *intr_handle;
 912         struct e1000_hw *hw;
 913         struct e1000_adapter *adapter =
 914                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 915
 916         PMD_INIT_FUNC_TRACE();
 917
 918         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 919                 return -EPERM;
 920
 921         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 922         pci_dev = E1000_DEV_TO_PCI(eth_dev);
 923         intr_handle = &pci_dev->intr_handle;
 924
 925         if (adapter->stopped == 0)
 926                 eth_igb_close(eth_dev);
 927
 928         eth_dev->dev_ops = NULL;
 929         eth_dev->rx_pkt_burst = NULL;
 930         eth_dev->tx_pkt_burst = NULL;
 931
 932         /* Reset any pending lock */
 933         igb_reset_swfw_lock(hw);
 934
 935         rte_free(eth_dev->data->mac_addrs);
 936         eth_dev->data->mac_addrs = NULL;
 937
 938         /* uninitialize PF if max_vfs not zero */
 939         igb_pf_host_uninit(eth_dev);
 940
 941         /* disable uio intr before callback unregister */
 942         rte_intr_disable(intr_handle);
 943         rte_intr_callback_unregister(intr_handle,
 944                                      eth_igb_interrupt_handler, eth_dev);
 945
 946         return 0;
 947 }
 948
 949 /*
 950  * Virtual Function device init
 951  */
 952 static int
 953 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 954 {
 955         struct rte_pci_device *pci_dev;
 956         struct rte_intr_handle *intr_handle;
 957         struct e1000_adapter *adapter =
 958                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 959         struct e1000_hw *hw =
 960                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 961         int diag;
 962         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 963
 964         PMD_INIT_FUNC_TRACE();
 965
 966         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 967         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 968         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 969
 970         /* for secondary processes, we don't initialise any further as primary
 971          * has already done this work. Only check we don't need a different
 972          * RX function */
 973         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 974                 if (eth_dev->data->scattered_rx)
 975                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 976                 return 0;
 977         }
 978
 979         pci_dev = E1000_DEV_TO_PCI(eth_dev);
 980         rte_eth_copy_pci_info(eth_dev, pci_dev);
 981
 982         hw->device_id = pci_dev->id.device_id;
 983         hw->vendor_id = pci_dev->id.vendor_id;
 984         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 985         adapter->stopped = 0;
 986
 987         /* Initialize the shared code (base driver) */
 988         diag = e1000_setup_init_funcs(hw, TRUE);
 989         if (diag != 0) {
 990                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 991                         diag);
 992                 return -EIO;
 993         }
 994
 995         /* init_mailbox_params */
 996         hw->mbx.ops.init_params(hw);
 997
 998         /* Disable the interrupts for VF */
 999         igbvf_intr_disable(hw);
1000
1001         diag = hw->mac.ops.reset_hw(hw);
1002
1003         /* Allocate memory for storing MAC addresses */
1004         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1005                 hw->mac.rar_entry_count, 0);
1006         if (eth_dev->data->mac_addrs == NULL) {
1007                 PMD_INIT_LOG(ERR,
1008                         "Failed to allocate %d bytes needed to store MAC "
1009                         "addresses",
1010                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1011                 return -ENOMEM;
1012         }
1013
1014         /* Generate a random MAC address, if none was assigned by PF. */
1015         if (is_zero_ether_addr(perm_addr)) {
1016                 eth_random_addr(perm_addr->addr_bytes);
1017                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1018                 if (diag) {
1019                         rte_free(eth_dev->data->mac_addrs);
1020                         eth_dev->data->mac_addrs = NULL;
1021                         return diag;
1022                 }
1023                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1024                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1025                              "%02x:%02x:%02x:%02x:%02x:%02x",
1026                              perm_addr->addr_bytes[0],
1027                              perm_addr->addr_bytes[1],
1028                              perm_addr->addr_bytes[2],
1029                              perm_addr->addr_bytes[3],
1030                              perm_addr->addr_bytes[4],
1031                              perm_addr->addr_bytes[5]);
1032         }
1033
1034         /* Copy the permanent MAC address */
1035         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1036                         &eth_dev->data->mac_addrs[0]);
1037
1038         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1039                      "mac.type=%s",
1040                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1041                      pci_dev->id.device_id, "igb_mac_82576_vf");
1042
1043         intr_handle = &pci_dev->intr_handle;
1044         rte_intr_callback_register(intr_handle,
1045                                    eth_igbvf_interrupt_handler, eth_dev);
1046
1047         return 0;
1048 }
1049
1050 static int
1051 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1052 {
1053         struct e1000_adapter *adapter =
1054                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1055         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
1056
1057         PMD_INIT_FUNC_TRACE();
1058
1059         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1060                 return -EPERM;
1061
1062         if (adapter->stopped == 0)
1063                 igbvf_dev_close(eth_dev);
1064
1065         eth_dev->dev_ops = NULL;
1066         eth_dev->rx_pkt_burst = NULL;
1067         eth_dev->tx_pkt_burst = NULL;
1068
1069         rte_free(eth_dev->data->mac_addrs);
1070         eth_dev->data->mac_addrs = NULL;
1071
1072         /* disable uio intr before callback unregister */
1073         rte_intr_disable(&pci_dev->intr_handle);
1074         rte_intr_callback_unregister(&pci_dev->intr_handle,
1075                                      eth_igbvf_interrupt_handler,
1076                                      (void *)eth_dev);
1077
1078         return 0;
1079 }
1080
1081 static struct eth_driver rte_igb_pmd = {
1082         .pci_drv = {
1083                 .id_table = pci_id_igb_map,
1084                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1085                         RTE_PCI_DRV_DETACHABLE,
1086                 .probe = rte_eth_dev_pci_probe,
1087                 .remove = rte_eth_dev_pci_remove,
1088         },
1089         .eth_dev_init = eth_igb_dev_init,
1090         .eth_dev_uninit = eth_igb_dev_uninit,
1091         .dev_private_size = sizeof(struct e1000_adapter),
1092 };
1093
1094 /*
1095  * virtual function driver struct
1096  */
1097 static struct eth_driver rte_igbvf_pmd = {
1098         .pci_drv = {
1099                 .id_table = pci_id_igbvf_map,
1100                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1101                 .probe = rte_eth_dev_pci_probe,
1102                 .remove = rte_eth_dev_pci_remove,
1103         },
1104         .eth_dev_init = eth_igbvf_dev_init,
1105         .eth_dev_uninit = eth_igbvf_dev_uninit,
1106         .dev_private_size = sizeof(struct e1000_adapter),
1107 };
1108
1109 static void
1110 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1111 {
1112         struct e1000_hw *hw =
1113                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1114         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1115         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1116         rctl |= E1000_RCTL_VFE;
1117         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1118 }
1119
1120 static int
1121 igb_check_mq_mode(struct rte_eth_dev *dev)
1122 {
1123         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1124         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1125         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1126         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1127
1128         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1129             tx_mq_mode == ETH_MQ_TX_DCB ||
1130             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1131                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1132                 return -EINVAL;
1133         }
1134         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1135                 /* Check multi-queue mode.
1136                  * To no break software we accept ETH_MQ_RX_NONE as this might
1137                  * be used to turn off VLAN filter.
1138                  */
1139
1140                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1141                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1142                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1143                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1144                 } else {
1145                         /* Only support one queue on VFs.
1146                          * RSS together with SRIOV is not supported.
1147                          */
1148                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1149                                         " wrong mq_mode rx %d.",
1150                                         rx_mq_mode);
1151                         return -EINVAL;
1152                 }
1153                 /* TX mode is not used here, so mode might be ignored.*/
1154                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1155                         /* SRIOV only works in VMDq enable mode */
1156                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1157                                         " TX mode %d is not supported. "
1158                                         " Driver will behave as %d mode.",
1159                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1160                 }
1161
1162                 /* check valid queue number */
1163                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1164                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1165                                         " only support one queue on VFs.");
1166                         return -EINVAL;
1167                 }
1168         } else {
1169                 /* To no break software that set invalid mode, only display
1170                  * warning if invalid mode is used.
1171                  */
1172                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1173                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1174                     rx_mq_mode != ETH_MQ_RX_RSS) {
1175                         /* RSS together with VMDq not supported*/
1176                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1177                                      rx_mq_mode);
1178                         return -EINVAL;
1179                 }
1180
1181                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1182                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1183                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1184                                         " Due to txmode is meaningless in this"
1185                                         " driver, just ignore.",
1186                                         tx_mq_mode);
1187                 }
1188         }
1189         return 0;
1190 }
1191
1192 static int
1193 eth_igb_configure(struct rte_eth_dev *dev)
1194 {
1195         struct e1000_interrupt *intr =
1196                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1197         int ret;
1198
1199         PMD_INIT_FUNC_TRACE();
1200
1201         /* multipe queue mode checking */
1202         ret  = igb_check_mq_mode(dev);
1203         if (ret != 0) {
1204                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1205                             ret);
1206                 return ret;
1207         }
1208
1209         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1210         PMD_INIT_FUNC_TRACE();
1211
1212         return 0;
1213 }
1214
1215 static int
1216 eth_igb_start(struct rte_eth_dev *dev)
1217 {
1218         struct e1000_hw *hw =
1219                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1220         struct e1000_adapter *adapter =
1221                 E1000_DEV_PRIVATE(dev->data->dev_private);
1222         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1223         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1224         int ret, mask;
1225         uint32_t intr_vector = 0;
1226         uint32_t ctrl_ext;
1227         uint32_t *speeds;
1228         int num_speeds;
1229         bool autoneg;
1230
1231         PMD_INIT_FUNC_TRACE();
1232
1233         /* disable uio/vfio intr/eventfd mapping */
1234         rte_intr_disable(intr_handle);
1235
1236         /* Power up the phy. Needed to make the link go Up */
1237         eth_igb_dev_set_link_up(dev);
1238
1239         /*
1240          * Packet Buffer Allocation (PBA)
1241          * Writing PBA sets the receive portion of the buffer
1242          * the remainder is used for the transmit buffer.
1243          */
1244         if (hw->mac.type == e1000_82575) {
1245                 uint32_t pba;
1246
1247                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1248                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1249         }
1250
1251         /* Put the address into the Receive Address Array */
1252         e1000_rar_set(hw, hw->mac.addr, 0);
1253
1254         /* Initialize the hardware */
1255         if (igb_hardware_init(hw)) {
1256                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1257                 return -EIO;
1258         }
1259         adapter->stopped = 0;
1260
1261         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1262
1263         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1264         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1265         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1266         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1267         E1000_WRITE_FLUSH(hw);
1268
1269         /* configure PF module if SRIOV enabled */
1270         igb_pf_host_configure(dev);
1271
1272         /* check and configure queue intr-vector mapping */
1273         if ((rte_intr_cap_multiple(intr_handle) ||
1274              !RTE_ETH_DEV_SRIOV(dev).active) &&
1275             dev->data->dev_conf.intr_conf.rxq != 0) {
1276                 intr_vector = dev->data->nb_rx_queues;
1277                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1278                         return -1;
1279         }
1280
1281         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1282                 intr_handle->intr_vec =
1283                         rte_zmalloc("intr_vec",
1284                                     dev->data->nb_rx_queues * sizeof(int), 0);
1285                 if (intr_handle->intr_vec == NULL) {
1286                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1287                                      " intr_vec\n", dev->data->nb_rx_queues);
1288                         return -ENOMEM;
1289                 }
1290         }
1291
1292         /* confiugre msix for rx interrupt */
1293         eth_igb_configure_msix_intr(dev);
1294
1295         /* Configure for OS presence */
1296         igb_init_manageability(hw);
1297
1298         eth_igb_tx_init(dev);
1299
1300         /* This can fail when allocating mbufs for descriptor rings */
1301         ret = eth_igb_rx_init(dev);
1302         if (ret) {
1303                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1304                 igb_dev_clear_queues(dev);
1305                 return ret;
1306         }
1307
1308         e1000_clear_hw_cntrs_base_generic(hw);
1309
1310         /*
1311          * VLAN Offload Settings
1312          */
1313         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1314                         ETH_VLAN_EXTEND_MASK;
1315         eth_igb_vlan_offload_set(dev, mask);
1316
1317         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1318                 /* Enable VLAN filter since VMDq always use VLAN filter */
1319                 igb_vmdq_vlan_hw_filter_enable(dev);
1320         }
1321
1322         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1323                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1324                 (hw->mac.type == e1000_i211)) {
1325                 /* Configure EITR with the maximum possible value (0xFFFF) */
1326                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1327         }
1328
1329         /* Setup link speed and duplex */
1330         speeds = &dev->data->dev_conf.link_speeds;
1331         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1332                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1333                 hw->mac.autoneg = 1;
1334         } else {
1335                 num_speeds = 0;
1336                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1337
1338                 /* Reset */
1339                 hw->phy.autoneg_advertised = 0;
1340
1341                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1342                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1343                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1344                         num_speeds = -1;
1345                         goto error_invalid_config;
1346                 }
1347                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1348                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1349                         num_speeds++;
1350                 }
1351                 if (*speeds & ETH_LINK_SPEED_10M) {
1352                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1353                         num_speeds++;
1354                 }
1355                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1356                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1357                         num_speeds++;
1358                 }
1359                 if (*speeds & ETH_LINK_SPEED_100M) {
1360                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1361                         num_speeds++;
1362                 }
1363                 if (*speeds & ETH_LINK_SPEED_1G) {
1364                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1365                         num_speeds++;
1366                 }
1367                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1368                         goto error_invalid_config;
1369
1370                 /* Set/reset the mac.autoneg based on the link speed,
1371                  * fixed or not
1372                  */
1373                 if (!autoneg) {
1374                         hw->mac.autoneg = 0;
1375                         hw->mac.forced_speed_duplex =
1376                                         hw->phy.autoneg_advertised;
1377                 } else {
1378                         hw->mac.autoneg = 1;
1379                 }
1380         }
1381
1382         e1000_setup_link(hw);
1383
1384         if (rte_intr_allow_others(intr_handle)) {
1385                 /* check if lsc interrupt is enabled */
1386                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1387                         eth_igb_lsc_interrupt_setup(dev);
1388         } else {
1389                 rte_intr_callback_unregister(intr_handle,
1390                                              eth_igb_interrupt_handler,
1391                                              (void *)dev);
1392                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1393                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1394                                      " no intr multiplex\n");
1395         }
1396
1397         /* check if rxq interrupt is enabled */
1398         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1399             rte_intr_dp_is_en(intr_handle))
1400                 eth_igb_rxq_interrupt_setup(dev);
1401
1402         /* enable uio/vfio intr/eventfd mapping */
1403         rte_intr_enable(intr_handle);
1404
1405         /* resume enabled intr since hw reset */
1406         igb_intr_enable(dev);
1407
1408         PMD_INIT_LOG(DEBUG, "<<");
1409
1410         return 0;
1411
1412 error_invalid_config:
1413         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1414                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1415         igb_dev_clear_queues(dev);
1416         return -EINVAL;
1417 }
1418
1419 /*********************************************************************
1420  *
1421  *  This routine disables all traffic on the adapter by issuing a
1422  *  global reset on the MAC.
1423  *
1424  **********************************************************************/
1425 static void
1426 eth_igb_stop(struct rte_eth_dev *dev)
1427 {
1428         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1429         struct e1000_filter_info *filter_info =
1430                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1431         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1432         struct rte_eth_link link;
1433         struct e1000_flex_filter *p_flex;
1434         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1435         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1436         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1437
1438         igb_intr_disable(hw);
1439
1440         /* disable intr eventfd mapping */
1441         rte_intr_disable(intr_handle);
1442
1443         igb_pf_reset_hw(hw);
1444         E1000_WRITE_REG(hw, E1000_WUC, 0);
1445
1446         /* Set bit for Go Link disconnect */
1447         if (hw->mac.type >= e1000_82580) {
1448                 uint32_t phpm_reg;
1449
1450                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1451                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1452                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1453         }
1454
1455         /* Power down the phy. Needed to make the link go Down */
1456         eth_igb_dev_set_link_down(dev);
1457
1458         igb_dev_clear_queues(dev);
1459
1460         /* clear the recorded link status */
1461         memset(&link, 0, sizeof(link));
1462         rte_igb_dev_atomic_write_link_status(dev, &link);
1463
1464         /* Remove all flex filters of the device */
1465         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1466                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1467                 rte_free(p_flex);
1468         }
1469         filter_info->flex_mask = 0;
1470
1471         /* Remove all ntuple filters of the device */
1472         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1473              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1474                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1475                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1476                              p_5tuple, entries);
1477                 rte_free(p_5tuple);
1478         }
1479         filter_info->fivetuple_mask = 0;
1480         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1481              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1482                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1483                 TAILQ_REMOVE(&filter_info->twotuple_list,
1484                              p_2tuple, entries);
1485                 rte_free(p_2tuple);
1486         }
1487         filter_info->twotuple_mask = 0;
1488
1489         if (!rte_intr_allow_others(intr_handle))
1490                 /* resume to the default handler */
1491                 rte_intr_callback_register(intr_handle,
1492                                            eth_igb_interrupt_handler,
1493                                            (void *)dev);
1494
1495         /* Clean datapath event and queue/vec mapping */
1496         rte_intr_efd_disable(intr_handle);
1497         if (intr_handle->intr_vec != NULL) {
1498                 rte_free(intr_handle->intr_vec);
1499                 intr_handle->intr_vec = NULL;
1500         }
1501 }
1502
1503 static int
1504 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1505 {
1506         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1507
1508         if (hw->phy.media_type == e1000_media_type_copper)
1509                 e1000_power_up_phy(hw);
1510         else
1511                 e1000_power_up_fiber_serdes_link(hw);
1512
1513         return 0;
1514 }
1515
1516 static int
1517 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1518 {
1519         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1520
1521         if (hw->phy.media_type == e1000_media_type_copper)
1522                 e1000_power_down_phy(hw);
1523         else
1524                 e1000_shutdown_fiber_serdes_link(hw);
1525
1526         return 0;
1527 }
1528
1529 static void
1530 eth_igb_close(struct rte_eth_dev *dev)
1531 {
1532         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1533         struct e1000_adapter *adapter =
1534                 E1000_DEV_PRIVATE(dev->data->dev_private);
1535         struct rte_eth_link link;
1536         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1537         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1538
1539         eth_igb_stop(dev);
1540         adapter->stopped = 1;
1541
1542         e1000_phy_hw_reset(hw);
1543         igb_release_manageability(hw);
1544         igb_hw_control_release(hw);
1545
1546         /* Clear bit for Go Link disconnect */
1547         if (hw->mac.type >= e1000_82580) {
1548                 uint32_t phpm_reg;
1549
1550                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1551                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1552                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1553         }
1554
1555         igb_dev_free_queues(dev);
1556
1557         if (intr_handle->intr_vec) {
1558                 rte_free(intr_handle->intr_vec);
1559                 intr_handle->intr_vec = NULL;
1560         }
1561
1562         memset(&link, 0, sizeof(link));
1563         rte_igb_dev_atomic_write_link_status(dev, &link);
1564 }
1565
1566 static int
1567 igb_get_rx_buffer_size(struct e1000_hw *hw)
1568 {
1569         uint32_t rx_buf_size;
1570         if (hw->mac.type == e1000_82576) {
1571                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1572         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1573                 /* PBS needs to be translated according to a lookup table */
1574                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1575                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1576                 rx_buf_size = (rx_buf_size << 10);
1577         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1578                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1579         } else {
1580                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1581         }
1582
1583         return rx_buf_size;
1584 }
1585
1586 /*********************************************************************
1587  *
1588  *  Initialize the hardware
1589  *
1590  **********************************************************************/
1591 static int
1592 igb_hardware_init(struct e1000_hw *hw)
1593 {
1594         uint32_t rx_buf_size;
1595         int diag;
1596
1597         /* Let the firmware know the OS is in control */
1598         igb_hw_control_acquire(hw);
1599
1600         /*
1601          * These parameters control the automatic generation (Tx) and
1602          * response (Rx) to Ethernet PAUSE frames.
1603          * - High water mark should allow for at least two standard size (1518)
1604          *   frames to be received after sending an XOFF.
1605          * - Low water mark works best when it is very near the high water mark.
1606          *   This allows the receiver to restart by sending XON when it has
1607          *   drained a bit. Here we use an arbitrary value of 1500 which will
1608          *   restart after one full frame is pulled from the buffer. There
1609          *   could be several smaller frames in the buffer and if so they will
1610          *   not trigger the XON until their total number reduces the buffer
1611          *   by 1500.
1612          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1613          */
1614         rx_buf_size = igb_get_rx_buffer_size(hw);
1615
1616         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1617         hw->fc.low_water = hw->fc.high_water - 1500;
1618         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1619         hw->fc.send_xon = 1;
1620
1621         /* Set Flow control, use the tunable location if sane */
1622         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1623                 hw->fc.requested_mode = igb_fc_setting;
1624         else
1625                 hw->fc.requested_mode = e1000_fc_none;
1626
1627         /* Issue a global reset */
1628         igb_pf_reset_hw(hw);
1629         E1000_WRITE_REG(hw, E1000_WUC, 0);
1630
1631         diag = e1000_init_hw(hw);
1632         if (diag < 0)
1633                 return diag;
1634
1635         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1636         e1000_get_phy_info(hw);
1637         e1000_check_for_link(hw);
1638
1639         return 0;
1640 }
1641
1642 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1643 static void
1644 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1645 {
1646         int pause_frames;
1647
1648         uint64_t old_gprc  = stats->gprc;
1649         uint64_t old_gptc  = stats->gptc;
1650         uint64_t old_tpr   = stats->tpr;
1651         uint64_t old_tpt   = stats->tpt;
1652         uint64_t old_rpthc = stats->rpthc;
1653         uint64_t old_hgptc = stats->hgptc;
1654
1655         if(hw->phy.media_type == e1000_media_type_copper ||
1656             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1657                 stats->symerrs +=
1658                     E1000_READ_REG(hw,E1000_SYMERRS);
1659                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1660         }
1661
1662         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1663         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1664         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1665         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1666
1667         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1668         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1669         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1670         stats->dc += E1000_READ_REG(hw, E1000_DC);
1671         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1672         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1673         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1674         /*
1675         ** For watchdog management we need to know if we have been
1676         ** paused during the last interval, so capture that here.
1677         */
1678         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1679         stats->xoffrxc += pause_frames;
1680         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1681         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1682         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1683         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1684         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1685         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1686         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1687         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1688         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1689         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1690         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1691         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1692
1693         /* For the 64-bit byte counters the low dword must be read first. */
1694         /* Both registers clear on the read of the high dword */
1695
1696         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1697         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1698         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1699         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1700         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1701         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1702         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1703
1704         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1705         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1706         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1707         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1708         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1709
1710         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1711         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1712
1713         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1714         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1715         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1716         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1717         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1718         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1719
1720         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1721         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1722         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1723         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1724         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1725         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1726         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1727         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1728
1729         /* Interrupt Counts */
1730
1731         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1732         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1733         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1734         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1735         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1736         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1737         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1738         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1739         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1740
1741         /* Host to Card Statistics */
1742
1743         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1744         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1745         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1746         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1747         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1748         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1749         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1750         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1751         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1752         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1753         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1754         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1755         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1756         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1757         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1758         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1759
1760         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1761         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1762         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1763         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1764         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1765         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1766 }
1767
1768 static void
1769 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1770 {
1771         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1772         struct e1000_hw_stats *stats =
1773                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1774
1775         igb_read_stats_registers(hw, stats);
1776
1777         if (rte_stats == NULL)
1778                 return;
1779
1780         /* Rx Errors */
1781         rte_stats->imissed = stats->mpc;
1782         rte_stats->ierrors = stats->crcerrs +
1783                              stats->rlec + stats->ruc + stats->roc +
1784                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1785
1786         /* Tx Errors */
1787         rte_stats->oerrors = stats->ecol + stats->latecol;
1788
1789         rte_stats->ipackets = stats->gprc;
1790         rte_stats->opackets = stats->gptc;
1791         rte_stats->ibytes   = stats->gorc;
1792         rte_stats->obytes   = stats->gotc;
1793 }
1794
1795 static void
1796 eth_igb_stats_reset(struct rte_eth_dev *dev)
1797 {
1798         struct e1000_hw_stats *hw_stats =
1799                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1800
1801         /* HW registers are cleared on read */
1802         eth_igb_stats_get(dev, NULL);
1803
1804         /* Reset software totals */
1805         memset(hw_stats, 0, sizeof(*hw_stats));
1806 }
1807
1808 static void
1809 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1810 {
1811         struct e1000_hw_stats *stats =
1812                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1813
1814         /* HW registers are cleared on read */
1815         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1816
1817         /* Reset software totals */
1818         memset(stats, 0, sizeof(*stats));
1819 }
1820
1821 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1822         struct rte_eth_xstat_name *xstats_names,
1823         __rte_unused unsigned limit)
1824 {
1825         unsigned i;
1826
1827         if (xstats_names == NULL)
1828                 return IGB_NB_XSTATS;
1829
1830         /* Note: limit checked in rte_eth_xstats_names() */
1831
1832         for (i = 0; i < IGB_NB_XSTATS; i++) {
1833                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1834                          "%s", rte_igb_stats_strings[i].name);
1835         }
1836
1837         return IGB_NB_XSTATS;
1838 }
1839
1840 static int
1841 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1842                    unsigned n)
1843 {
1844         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         struct e1000_hw_stats *hw_stats =
1846                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1847         unsigned i;
1848
1849         if (n < IGB_NB_XSTATS)
1850                 return IGB_NB_XSTATS;
1851
1852         igb_read_stats_registers(hw, hw_stats);
1853
1854         /* If this is a reset xstats is NULL, and we have cleared the
1855          * registers by reading them.
1856          */
1857         if (!xstats)
1858                 return 0;
1859
1860         /* Extended stats */
1861         for (i = 0; i < IGB_NB_XSTATS; i++) {
1862                 xstats[i].id = i;
1863                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1864                         rte_igb_stats_strings[i].offset);
1865         }
1866
1867         return IGB_NB_XSTATS;
1868 }
1869
1870 static void
1871 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1872 {
1873         /* Good Rx packets, include VF loopback */
1874         UPDATE_VF_STAT(E1000_VFGPRC,
1875             hw_stats->last_gprc, hw_stats->gprc);
1876
1877         /* Good Rx octets, include VF loopback */
1878         UPDATE_VF_STAT(E1000_VFGORC,
1879             hw_stats->last_gorc, hw_stats->gorc);
1880
1881         /* Good Tx packets, include VF loopback */
1882         UPDATE_VF_STAT(E1000_VFGPTC,
1883             hw_stats->last_gptc, hw_stats->gptc);
1884
1885         /* Good Tx octets, include VF loopback */
1886         UPDATE_VF_STAT(E1000_VFGOTC,
1887             hw_stats->last_gotc, hw_stats->gotc);
1888
1889         /* Rx Multicst packets */
1890         UPDATE_VF_STAT(E1000_VFMPRC,
1891             hw_stats->last_mprc, hw_stats->mprc);
1892
1893         /* Good Rx loopback packets */
1894         UPDATE_VF_STAT(E1000_VFGPRLBC,
1895             hw_stats->last_gprlbc, hw_stats->gprlbc);
1896
1897         /* Good Rx loopback octets */
1898         UPDATE_VF_STAT(E1000_VFGORLBC,
1899             hw_stats->last_gorlbc, hw_stats->gorlbc);
1900
1901         /* Good Tx loopback packets */
1902         UPDATE_VF_STAT(E1000_VFGPTLBC,
1903             hw_stats->last_gptlbc, hw_stats->gptlbc);
1904
1905         /* Good Tx loopback octets */
1906         UPDATE_VF_STAT(E1000_VFGOTLBC,
1907             hw_stats->last_gotlbc, hw_stats->gotlbc);
1908 }
1909
1910 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1911                                      struct rte_eth_xstat_name *xstats_names,
1912                                      __rte_unused unsigned limit)
1913 {
1914         unsigned i;
1915
1916         if (xstats_names != NULL)
1917                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1918                         snprintf(xstats_names[i].name,
1919                                 sizeof(xstats_names[i].name), "%s",
1920                                 rte_igbvf_stats_strings[i].name);
1921                 }
1922         return IGBVF_NB_XSTATS;
1923 }
1924
1925 static int
1926 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1927                      unsigned n)
1928 {
1929         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1931                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1932         unsigned i;
1933
1934         if (n < IGBVF_NB_XSTATS)
1935                 return IGBVF_NB_XSTATS;
1936
1937         igbvf_read_stats_registers(hw, hw_stats);
1938
1939         if (!xstats)
1940                 return 0;
1941
1942         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1943                 xstats[i].id = i;
1944                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1945                         rte_igbvf_stats_strings[i].offset);
1946         }
1947
1948         return IGBVF_NB_XSTATS;
1949 }
1950
1951 static void
1952 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1953 {
1954         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1955         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1956                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1957
1958         igbvf_read_stats_registers(hw, hw_stats);
1959
1960         if (rte_stats == NULL)
1961                 return;
1962
1963         rte_stats->ipackets = hw_stats->gprc;
1964         rte_stats->ibytes = hw_stats->gorc;
1965         rte_stats->opackets = hw_stats->gptc;
1966         rte_stats->obytes = hw_stats->gotc;
1967 }
1968
1969 static void
1970 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1971 {
1972         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1973                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1974
1975         /* Sync HW register to the last stats */
1976         eth_igbvf_stats_get(dev, NULL);
1977
1978         /* reset HW current stats*/
1979         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1980                offsetof(struct e1000_vf_stats, gprc));
1981 }
1982
1983 static void
1984 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1985 {
1986         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1987
1988         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1989         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1990         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1991         dev_info->rx_offload_capa =
1992                 DEV_RX_OFFLOAD_VLAN_STRIP |
1993                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1994                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1995                 DEV_RX_OFFLOAD_TCP_CKSUM;
1996         dev_info->tx_offload_capa =
1997                 DEV_TX_OFFLOAD_VLAN_INSERT |
1998                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1999                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2000                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2001                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2002                 DEV_TX_OFFLOAD_TCP_TSO;
2003
2004         switch (hw->mac.type) {
2005         case e1000_82575:
2006                 dev_info->max_rx_queues = 4;
2007                 dev_info->max_tx_queues = 4;
2008                 dev_info->max_vmdq_pools = 0;
2009                 break;
2010
2011         case e1000_82576:
2012                 dev_info->max_rx_queues = 16;
2013                 dev_info->max_tx_queues = 16;
2014                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2015                 dev_info->vmdq_queue_num = 16;
2016                 break;
2017
2018         case e1000_82580:
2019                 dev_info->max_rx_queues = 8;
2020                 dev_info->max_tx_queues = 8;
2021                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2022                 dev_info->vmdq_queue_num = 8;
2023                 break;
2024
2025         case e1000_i350:
2026                 dev_info->max_rx_queues = 8;
2027                 dev_info->max_tx_queues = 8;
2028                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2029                 dev_info->vmdq_queue_num = 8;
2030                 break;
2031
2032         case e1000_i354:
2033                 dev_info->max_rx_queues = 8;
2034                 dev_info->max_tx_queues = 8;
2035                 break;
2036
2037         case e1000_i210:
2038                 dev_info->max_rx_queues = 4;
2039                 dev_info->max_tx_queues = 4;
2040                 dev_info->max_vmdq_pools = 0;
2041                 break;
2042
2043         case e1000_i211:
2044                 dev_info->max_rx_queues = 2;
2045                 dev_info->max_tx_queues = 2;
2046                 dev_info->max_vmdq_pools = 0;
2047                 break;
2048
2049         default:
2050                 /* Should not happen */
2051                 break;
2052         }
2053         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2054         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2055         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2056
2057         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2058                 .rx_thresh = {
2059                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2060                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2061                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2062                 },
2063                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2064                 .rx_drop_en = 0,
2065         };
2066
2067         dev_info->default_txconf = (struct rte_eth_txconf) {
2068                 .tx_thresh = {
2069                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2070                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2071                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2072                 },
2073                 .txq_flags = 0,
2074         };
2075
2076         dev_info->rx_desc_lim = rx_desc_lim;
2077         dev_info->tx_desc_lim = tx_desc_lim;
2078
2079         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2080                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2081                         ETH_LINK_SPEED_1G;
2082 }
2083
2084 static const uint32_t *
2085 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2086 {
2087         static const uint32_t ptypes[] = {
2088                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2089                 RTE_PTYPE_L2_ETHER,
2090                 RTE_PTYPE_L3_IPV4,
2091                 RTE_PTYPE_L3_IPV4_EXT,
2092                 RTE_PTYPE_L3_IPV6,
2093                 RTE_PTYPE_L3_IPV6_EXT,
2094                 RTE_PTYPE_L4_TCP,
2095                 RTE_PTYPE_L4_UDP,
2096                 RTE_PTYPE_L4_SCTP,
2097                 RTE_PTYPE_TUNNEL_IP,
2098                 RTE_PTYPE_INNER_L3_IPV6,
2099                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2100                 RTE_PTYPE_INNER_L4_TCP,
2101                 RTE_PTYPE_INNER_L4_UDP,
2102                 RTE_PTYPE_UNKNOWN
2103         };
2104
2105         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2106             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2107                 return ptypes;
2108         return NULL;
2109 }
2110
2111 static void
2112 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2113 {
2114         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2115
2116         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2117         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2118         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2119         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2120                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2121                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2122                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2123         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2124                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2125                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2126                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2127                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2128                                 DEV_TX_OFFLOAD_TCP_TSO;
2129         switch (hw->mac.type) {
2130         case e1000_vfadapt:
2131                 dev_info->max_rx_queues = 2;
2132                 dev_info->max_tx_queues = 2;
2133                 break;
2134         case e1000_vfadapt_i350:
2135                 dev_info->max_rx_queues = 1;
2136                 dev_info->max_tx_queues = 1;
2137                 break;
2138         default:
2139                 /* Should not happen */
2140                 break;
2141         }
2142
2143         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2144                 .rx_thresh = {
2145                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2146                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2147                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2148                 },
2149                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2150                 .rx_drop_en = 0,
2151         };
2152
2153         dev_info->default_txconf = (struct rte_eth_txconf) {
2154                 .tx_thresh = {
2155                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2156                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2157                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2158                 },
2159                 .txq_flags = 0,
2160         };
2161
2162         dev_info->rx_desc_lim = rx_desc_lim;
2163         dev_info->tx_desc_lim = tx_desc_lim;
2164 }
2165
2166 /* return 0 means link status changed, -1 means not changed */
2167 static int
2168 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2169 {
2170         struct e1000_hw *hw =
2171                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2172         struct rte_eth_link link, old;
2173         int link_check, count;
2174
2175         link_check = 0;
2176         hw->mac.get_link_status = 1;
2177
2178         /* possible wait-to-complete in up to 9 seconds */
2179         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2180                 /* Read the real link status */
2181                 switch (hw->phy.media_type) {
2182                 case e1000_media_type_copper:
2183                         /* Do the work to read phy */
2184                         e1000_check_for_link(hw);
2185                         link_check = !hw->mac.get_link_status;
2186                         break;
2187
2188                 case e1000_media_type_fiber:
2189                         e1000_check_for_link(hw);
2190                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2191                                       E1000_STATUS_LU);
2192                         break;
2193
2194                 case e1000_media_type_internal_serdes:
2195                         e1000_check_for_link(hw);
2196                         link_check = hw->mac.serdes_has_link;
2197                         break;
2198
2199                 /* VF device is type_unknown */
2200                 case e1000_media_type_unknown:
2201                         eth_igbvf_link_update(hw);
2202                         link_check = !hw->mac.get_link_status;
2203                         break;
2204
2205                 default:
2206                         break;
2207                 }
2208                 if (link_check || wait_to_complete == 0)
2209                         break;
2210                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2211         }
2212         memset(&link, 0, sizeof(link));
2213         rte_igb_dev_atomic_read_link_status(dev, &link);
2214         old = link;
2215
2216         /* Now we check if a transition has happened */
2217         if (link_check) {
2218                 uint16_t duplex, speed;
2219                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2220                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2221                                 ETH_LINK_FULL_DUPLEX :
2222                                 ETH_LINK_HALF_DUPLEX;
2223                 link.link_speed = speed;
2224                 link.link_status = ETH_LINK_UP;
2225                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2226                                 ETH_LINK_SPEED_FIXED);
2227         } else if (!link_check) {
2228                 link.link_speed = 0;
2229                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2230                 link.link_status = ETH_LINK_DOWN;
2231                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2232         }
2233         rte_igb_dev_atomic_write_link_status(dev, &link);
2234
2235         /* not changed */
2236         if (old.link_status == link.link_status)
2237                 return -1;
2238
2239         /* changed */
2240         return 0;
2241 }
2242
2243 /*
2244  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2245  * For ASF and Pass Through versions of f/w this means
2246  * that the driver is loaded.
2247  */
2248 static void
2249 igb_hw_control_acquire(struct e1000_hw *hw)
2250 {
2251         uint32_t ctrl_ext;
2252
2253         /* Let firmware know the driver has taken over */
2254         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2255         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2256 }
2257
2258 /*
2259  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2260  * For ASF and Pass Through versions of f/w this means that the
2261  * driver is no longer loaded.
2262  */
2263 static void
2264 igb_hw_control_release(struct e1000_hw *hw)
2265 {
2266         uint32_t ctrl_ext;
2267
2268         /* Let firmware taken over control of h/w */
2269         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2270         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2271                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2272 }
2273
2274 /*
2275  * Bit of a misnomer, what this really means is
2276  * to enable OS management of the system... aka
2277  * to disable special hardware management features.
2278  */
2279 static void
2280 igb_init_manageability(struct e1000_hw *hw)
2281 {
2282         if (e1000_enable_mng_pass_thru(hw)) {
2283                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2284                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2285
2286                 /* disable hardware interception of ARP */
2287                 manc &= ~(E1000_MANC_ARP_EN);
2288
2289                 /* enable receiving management packets to the host */
2290                 manc |= E1000_MANC_EN_MNG2HOST;
2291                 manc2h |= 1 << 5;  /* Mng Port 623 */
2292                 manc2h |= 1 << 6;  /* Mng Port 664 */
2293                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2294                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2295         }
2296 }
2297
2298 static void
2299 igb_release_manageability(struct e1000_hw *hw)
2300 {
2301         if (e1000_enable_mng_pass_thru(hw)) {
2302                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2303
2304                 manc |= E1000_MANC_ARP_EN;
2305                 manc &= ~E1000_MANC_EN_MNG2HOST;
2306
2307                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2308         }
2309 }
2310
2311 static void
2312 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2313 {
2314         struct e1000_hw *hw =
2315                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2316         uint32_t rctl;
2317
2318         rctl = E1000_READ_REG(hw, E1000_RCTL);
2319         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2320         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2321 }
2322
2323 static void
2324 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2325 {
2326         struct e1000_hw *hw =
2327                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2328         uint32_t rctl;
2329
2330         rctl = E1000_READ_REG(hw, E1000_RCTL);
2331         rctl &= (~E1000_RCTL_UPE);
2332         if (dev->data->all_multicast == 1)
2333                 rctl |= E1000_RCTL_MPE;
2334         else
2335                 rctl &= (~E1000_RCTL_MPE);
2336         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2337 }
2338
2339 static void
2340 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2341 {
2342         struct e1000_hw *hw =
2343                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2344         uint32_t rctl;
2345
2346         rctl = E1000_READ_REG(hw, E1000_RCTL);
2347         rctl |= E1000_RCTL_MPE;
2348         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2349 }
2350
2351 static void
2352 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2353 {
2354         struct e1000_hw *hw =
2355                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2356         uint32_t rctl;
2357
2358         if (dev->data->promiscuous == 1)
2359                 return; /* must remain in all_multicast mode */
2360         rctl = E1000_READ_REG(hw, E1000_RCTL);
2361         rctl &= (~E1000_RCTL_MPE);
2362         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2363 }
2364
2365 static int
2366 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2367 {
2368         struct e1000_hw *hw =
2369                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2370         struct e1000_vfta * shadow_vfta =
2371                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2372         uint32_t vfta;
2373         uint32_t vid_idx;
2374         uint32_t vid_bit;
2375
2376         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2377                               E1000_VFTA_ENTRY_MASK);
2378         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2379         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2380         if (on)
2381                 vfta |= vid_bit;
2382         else
2383                 vfta &= ~vid_bit;
2384         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2385
2386         /* update local VFTA copy */
2387         shadow_vfta->vfta[vid_idx] = vfta;
2388
2389         return 0;
2390 }
2391
2392 static int
2393 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2394                       enum rte_vlan_type vlan_type,
2395                       uint16_t tpid)
2396 {
2397         struct e1000_hw *hw =
2398                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2399         uint32_t reg, qinq;
2400
2401         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2402         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2403
2404         /* only outer TPID of double VLAN can be configured*/
2405         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2406                 reg = E1000_READ_REG(hw, E1000_VET);
2407                 reg = (reg & (~E1000_VET_VET_EXT)) |
2408                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2409                 E1000_WRITE_REG(hw, E1000_VET, reg);
2410
2411                 return 0;
2412         }
2413
2414         /* all other TPID values are read-only*/
2415         PMD_DRV_LOG(ERR, "Not supported");
2416
2417         return -ENOTSUP;
2418 }
2419
2420 static void
2421 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2422 {
2423         struct e1000_hw *hw =
2424                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2425         uint32_t reg;
2426
2427         /* Filter Table Disable */
2428         reg = E1000_READ_REG(hw, E1000_RCTL);
2429         reg &= ~E1000_RCTL_CFIEN;
2430         reg &= ~E1000_RCTL_VFE;
2431         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2432 }
2433
2434 static void
2435 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2436 {
2437         struct e1000_hw *hw =
2438                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2439         struct e1000_vfta * shadow_vfta =
2440                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2441         uint32_t reg;
2442         int i;
2443
2444         /* Filter Table Enable, CFI not used for packet acceptance */
2445         reg = E1000_READ_REG(hw, E1000_RCTL);
2446         reg &= ~E1000_RCTL_CFIEN;
2447         reg |= E1000_RCTL_VFE;
2448         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2449
2450         /* restore VFTA table */
2451         for (i = 0; i < IGB_VFTA_SIZE; i++)
2452                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2453 }
2454
2455 static void
2456 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2457 {
2458         struct e1000_hw *hw =
2459                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2460         uint32_t reg;
2461
2462         /* VLAN Mode Disable */
2463         reg = E1000_READ_REG(hw, E1000_CTRL);
2464         reg &= ~E1000_CTRL_VME;
2465         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2466 }
2467
2468 static void
2469 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2470 {
2471         struct e1000_hw *hw =
2472                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2473         uint32_t reg;
2474
2475         /* VLAN Mode Enable */
2476         reg = E1000_READ_REG(hw, E1000_CTRL);
2477         reg |= E1000_CTRL_VME;
2478         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2479 }
2480
2481 static void
2482 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2483 {
2484         struct e1000_hw *hw =
2485                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486         uint32_t reg;
2487
2488         /* CTRL_EXT: Extended VLAN */
2489         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2490         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2491         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2492
2493         /* Update maximum packet length */
2494         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2495                 E1000_WRITE_REG(hw, E1000_RLPML,
2496                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2497                                                 VLAN_TAG_SIZE);
2498 }
2499
2500 static void
2501 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2502 {
2503         struct e1000_hw *hw =
2504                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2505         uint32_t reg;
2506
2507         /* CTRL_EXT: Extended VLAN */
2508         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2509         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2510         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2511
2512         /* Update maximum packet length */
2513         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2514                 E1000_WRITE_REG(hw, E1000_RLPML,
2515                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2516                                                 2 * VLAN_TAG_SIZE);
2517 }
2518
2519 static void
2520 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2521 {
2522         if(mask & ETH_VLAN_STRIP_MASK){
2523                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2524                         igb_vlan_hw_strip_enable(dev);
2525                 else
2526                         igb_vlan_hw_strip_disable(dev);
2527         }
2528
2529         if(mask & ETH_VLAN_FILTER_MASK){
2530                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2531                         igb_vlan_hw_filter_enable(dev);
2532                 else
2533                         igb_vlan_hw_filter_disable(dev);
2534         }
2535
2536         if(mask & ETH_VLAN_EXTEND_MASK){
2537                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2538                         igb_vlan_hw_extend_enable(dev);
2539                 else
2540                         igb_vlan_hw_extend_disable(dev);
2541         }
2542 }
2543
2544
2545 /**
2546  * It enables the interrupt mask and then enable the interrupt.
2547  *
2548  * @param dev
2549  *  Pointer to struct rte_eth_dev.
2550  *
2551  * @return
2552  *  - On success, zero.
2553  *  - On failure, a negative value.
2554  */
2555 static int
2556 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2557 {
2558         struct e1000_interrupt *intr =
2559                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2560
2561         intr->mask |= E1000_ICR_LSC;
2562
2563         return 0;
2564 }
2565
2566 /* It clears the interrupt causes and enables the interrupt.
2567  * It will be called once only during nic initialized.
2568  *
2569  * @param dev
2570  *  Pointer to struct rte_eth_dev.
2571  *
2572  * @return
2573  *  - On success, zero.
2574  *  - On failure, a negative value.
2575  */
2576 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2577 {
2578         uint32_t mask, regval;
2579         struct e1000_hw *hw =
2580                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2581         struct rte_eth_dev_info dev_info;
2582
2583         memset(&dev_info, 0, sizeof(dev_info));
2584         eth_igb_infos_get(dev, &dev_info);
2585
2586         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2587         regval = E1000_READ_REG(hw, E1000_EIMS);
2588         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2589
2590         return 0;
2591 }
2592
2593 /*
2594  * It reads ICR and gets interrupt causes, check it and set a bit flag
2595  * to update link status.
2596  *
2597  * @param dev
2598  *  Pointer to struct rte_eth_dev.
2599  *
2600  * @return
2601  *  - On success, zero.
2602  *  - On failure, a negative value.
2603  */
2604 static int
2605 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2606 {
2607         uint32_t icr;
2608         struct e1000_hw *hw =
2609                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2610         struct e1000_interrupt *intr =
2611                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2612
2613         igb_intr_disable(hw);
2614
2615         /* read-on-clear nic registers here */
2616         icr = E1000_READ_REG(hw, E1000_ICR);
2617
2618         intr->flags = 0;
2619         if (icr & E1000_ICR_LSC) {
2620                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2621         }
2622
2623         if (icr & E1000_ICR_VMMB)
2624                 intr->flags |= E1000_FLAG_MAILBOX;
2625
2626         return 0;
2627 }
2628
2629 /*
2630  * It executes link_update after knowing an interrupt is prsent.
2631  *
2632  * @param dev
2633  *  Pointer to struct rte_eth_dev.
2634  *
2635  * @return
2636  *  - On success, zero.
2637  *  - On failure, a negative value.
2638  */
2639 static int
2640 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2641                          struct rte_intr_handle *intr_handle)
2642 {
2643         struct e1000_hw *hw =
2644                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2645         struct e1000_interrupt *intr =
2646                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2647         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
2648         uint32_t tctl, rctl;
2649         struct rte_eth_link link;
2650         int ret;
2651
2652         if (intr->flags & E1000_FLAG_MAILBOX) {
2653                 igb_pf_mbx_process(dev);
2654                 intr->flags &= ~E1000_FLAG_MAILBOX;
2655         }
2656
2657         igb_intr_enable(dev);
2658         rte_intr_enable(intr_handle);
2659
2660         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2661                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2662
2663                 /* set get_link_status to check register later */
2664                 hw->mac.get_link_status = 1;
2665                 ret = eth_igb_link_update(dev, 0);
2666
2667                 /* check if link has changed */
2668                 if (ret < 0)
2669                         return 0;
2670
2671                 memset(&link, 0, sizeof(link));
2672                 rte_igb_dev_atomic_read_link_status(dev, &link);
2673                 if (link.link_status) {
2674                         PMD_INIT_LOG(INFO,
2675                                      " Port %d: Link Up - speed %u Mbps - %s",
2676                                      dev->data->port_id,
2677                                      (unsigned)link.link_speed,
2678                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2679                                      "full-duplex" : "half-duplex");
2680                 } else {
2681                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2682                                      dev->data->port_id);
2683                 }
2684
2685                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2686                              pci_dev->addr.domain,
2687                              pci_dev->addr.bus,
2688                              pci_dev->addr.devid,
2689                              pci_dev->addr.function);
2690                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2691                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2692                 if (link.link_status) {
2693                         /* enable Tx/Rx */
2694                         tctl |= E1000_TCTL_EN;
2695                         rctl |= E1000_RCTL_EN;
2696                 } else {
2697                         /* disable Tx/Rx */
2698                         tctl &= ~E1000_TCTL_EN;
2699                         rctl &= ~E1000_RCTL_EN;
2700                 }
2701                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2702                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2703                 E1000_WRITE_FLUSH(hw);
2704                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2705         }
2706
2707         return 0;
2708 }
2709
2710 /**
2711  * Interrupt handler which shall be registered at first.
2712  *
2713  * @param handle
2714  *  Pointer to interrupt handle.
2715  * @param param
2716  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2717  *
2718  * @return
2719  *  void
2720  */
2721 static void
2722 eth_igb_interrupt_handler(struct rte_intr_handle *handle, void *param)
2723 {
2724         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2725
2726         eth_igb_interrupt_get_status(dev);
2727         eth_igb_interrupt_action(dev, handle);
2728 }
2729
2730 static int
2731 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2732 {
2733         uint32_t eicr;
2734         struct e1000_hw *hw =
2735                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2736         struct e1000_interrupt *intr =
2737                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2738
2739         igbvf_intr_disable(hw);
2740
2741         /* read-on-clear nic registers here */
2742         eicr = E1000_READ_REG(hw, E1000_EICR);
2743         intr->flags = 0;
2744
2745         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2746                 intr->flags |= E1000_FLAG_MAILBOX;
2747
2748         return 0;
2749 }
2750
2751 void igbvf_mbx_process(struct rte_eth_dev *dev)
2752 {
2753         struct e1000_hw *hw =
2754                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2755         struct e1000_mbx_info *mbx = &hw->mbx;
2756         u32 in_msg = 0;
2757
2758         if (mbx->ops.read(hw, &in_msg, 1, 0))
2759                 return;
2760
2761         /* PF reset VF event */
2762         if (in_msg == E1000_PF_CONTROL_MSG)
2763                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2764 }
2765
2766 static int
2767 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2768 {
2769         struct e1000_interrupt *intr =
2770                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2771
2772         if (intr->flags & E1000_FLAG_MAILBOX) {
2773                 igbvf_mbx_process(dev);
2774                 intr->flags &= ~E1000_FLAG_MAILBOX;
2775         }
2776
2777         igbvf_intr_enable(dev);
2778         rte_intr_enable(intr_handle);
2779
2780         return 0;
2781 }
2782
2783 static void
2784 eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
2785                             void *param)
2786 {
2787         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2788
2789         eth_igbvf_interrupt_get_status(dev);
2790         eth_igbvf_interrupt_action(dev, handle);
2791 }
2792
2793 static int
2794 eth_igb_led_on(struct rte_eth_dev *dev)
2795 {
2796         struct e1000_hw *hw;
2797
2798         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2799         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2800 }
2801
2802 static int
2803 eth_igb_led_off(struct rte_eth_dev *dev)
2804 {
2805         struct e1000_hw *hw;
2806
2807         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2808         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2809 }
2810
2811 static int
2812 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2813 {
2814         struct e1000_hw *hw;
2815         uint32_t ctrl;
2816         int tx_pause;
2817         int rx_pause;
2818
2819         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820         fc_conf->pause_time = hw->fc.pause_time;
2821         fc_conf->high_water = hw->fc.high_water;
2822         fc_conf->low_water = hw->fc.low_water;
2823         fc_conf->send_xon = hw->fc.send_xon;
2824         fc_conf->autoneg = hw->mac.autoneg;
2825
2826         /*
2827          * Return rx_pause and tx_pause status according to actual setting of
2828          * the TFCE and RFCE bits in the CTRL register.
2829          */
2830         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2831         if (ctrl & E1000_CTRL_TFCE)
2832                 tx_pause = 1;
2833         else
2834                 tx_pause = 0;
2835
2836         if (ctrl & E1000_CTRL_RFCE)
2837                 rx_pause = 1;
2838         else
2839                 rx_pause = 0;
2840
2841         if (rx_pause && tx_pause)
2842                 fc_conf->mode = RTE_FC_FULL;
2843         else if (rx_pause)
2844                 fc_conf->mode = RTE_FC_RX_PAUSE;
2845         else if (tx_pause)
2846                 fc_conf->mode = RTE_FC_TX_PAUSE;
2847         else
2848                 fc_conf->mode = RTE_FC_NONE;
2849
2850         return 0;
2851 }
2852
2853 static int
2854 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2855 {
2856         struct e1000_hw *hw;
2857         int err;
2858         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2859                 e1000_fc_none,
2860                 e1000_fc_rx_pause,
2861                 e1000_fc_tx_pause,
2862                 e1000_fc_full
2863         };
2864         uint32_t rx_buf_size;
2865         uint32_t max_high_water;
2866         uint32_t rctl;
2867
2868         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2869         if (fc_conf->autoneg != hw->mac.autoneg)
2870                 return -ENOTSUP;
2871         rx_buf_size = igb_get_rx_buffer_size(hw);
2872         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2873
2874         /* At least reserve one Ethernet frame for watermark */
2875         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2876         if ((fc_conf->high_water > max_high_water) ||
2877             (fc_conf->high_water < fc_conf->low_water)) {
2878                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2879                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2880                 return -EINVAL;
2881         }
2882
2883         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2884         hw->fc.pause_time     = fc_conf->pause_time;
2885         hw->fc.high_water     = fc_conf->high_water;
2886         hw->fc.low_water      = fc_conf->low_water;
2887         hw->fc.send_xon       = fc_conf->send_xon;
2888
2889         err = e1000_setup_link_generic(hw);
2890         if (err == E1000_SUCCESS) {
2891
2892                 /* check if we want to forward MAC frames - driver doesn't have native
2893                  * capability to do that, so we'll write the registers ourselves */
2894
2895                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2896
2897                 /* set or clear MFLCN.PMCF bit depending on configuration */
2898                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2899                         rctl |= E1000_RCTL_PMCF;
2900                 else
2901                         rctl &= ~E1000_RCTL_PMCF;
2902
2903                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2904                 E1000_WRITE_FLUSH(hw);
2905
2906                 return 0;
2907         }
2908
2909         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2910         return -EIO;
2911 }
2912
2913 #define E1000_RAH_POOLSEL_SHIFT      (18)
2914 static void
2915 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2916                 uint32_t index, __rte_unused uint32_t pool)
2917 {
2918         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2919         uint32_t rah;
2920
2921         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2922         rah = E1000_READ_REG(hw, E1000_RAH(index));
2923         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2924         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2925 }
2926
2927 static void
2928 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2929 {
2930         uint8_t addr[ETHER_ADDR_LEN];
2931         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2932
2933         memset(addr, 0, sizeof(addr));
2934
2935         e1000_rar_set(hw, addr, index);
2936 }
2937
2938 static void
2939 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2940                                 struct ether_addr *addr)
2941 {
2942         eth_igb_rar_clear(dev, 0);
2943
2944         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2945 }
2946 /*
2947  * Virtual Function operations
2948  */
2949 static void
2950 igbvf_intr_disable(struct e1000_hw *hw)
2951 {
2952         PMD_INIT_FUNC_TRACE();
2953
2954         /* Clear interrupt mask to stop from interrupts being generated */
2955         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2956
2957         E1000_WRITE_FLUSH(hw);
2958 }
2959
2960 static void
2961 igbvf_stop_adapter(struct rte_eth_dev *dev)
2962 {
2963         u32 reg_val;
2964         u16 i;
2965         struct rte_eth_dev_info dev_info;
2966         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2967
2968         memset(&dev_info, 0, sizeof(dev_info));
2969         eth_igbvf_infos_get(dev, &dev_info);
2970
2971         /* Clear interrupt mask to stop from interrupts being generated */
2972         igbvf_intr_disable(hw);
2973
2974         /* Clear any pending interrupts, flush previous writes */
2975         E1000_READ_REG(hw, E1000_EICR);
2976
2977         /* Disable the transmit unit.  Each queue must be disabled. */
2978         for (i = 0; i < dev_info.max_tx_queues; i++)
2979                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2980
2981         /* Disable the receive unit by stopping each queue */
2982         for (i = 0; i < dev_info.max_rx_queues; i++) {
2983                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2984                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2985                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2986                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2987                         ;
2988         }
2989
2990         /* flush all queues disables */
2991         E1000_WRITE_FLUSH(hw);
2992         msec_delay(2);
2993 }
2994
2995 static int eth_igbvf_link_update(struct e1000_hw *hw)
2996 {
2997         struct e1000_mbx_info *mbx = &hw->mbx;
2998         struct e1000_mac_info *mac = &hw->mac;
2999         int ret_val = E1000_SUCCESS;
3000
3001         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3002
3003         /*
3004          * We only want to run this if there has been a rst asserted.
3005          * in this case that could mean a link change, device reset,
3006          * or a virtual function reset
3007          */
3008
3009         /* If we were hit with a reset or timeout drop the link */
3010         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3011                 mac->get_link_status = TRUE;
3012
3013         if (!mac->get_link_status)
3014                 goto out;
3015
3016         /* if link status is down no point in checking to see if pf is up */
3017         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3018                 goto out;
3019
3020         /* if we passed all the tests above then the link is up and we no
3021          * longer need to check for link */
3022         mac->get_link_status = FALSE;
3023
3024 out:
3025         return ret_val;
3026 }
3027
3028
3029 static int
3030 igbvf_dev_configure(struct rte_eth_dev *dev)
3031 {
3032         struct rte_eth_conf* conf = &dev->data->dev_conf;
3033
3034         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3035                      dev->data->port_id);
3036
3037         /*
3038          * VF has no ability to enable/disable HW CRC
3039          * Keep the persistent behavior the same as Host PF
3040          */
3041 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3042         if (!conf->rxmode.hw_strip_crc) {
3043                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3044                 conf->rxmode.hw_strip_crc = 1;
3045         }
3046 #else
3047         if (conf->rxmode.hw_strip_crc) {
3048                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3049                 conf->rxmode.hw_strip_crc = 0;
3050         }
3051 #endif
3052
3053         return 0;
3054 }
3055
3056 static int
3057 igbvf_dev_start(struct rte_eth_dev *dev)
3058 {
3059         struct e1000_hw *hw =
3060                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3061         struct e1000_adapter *adapter =
3062                 E1000_DEV_PRIVATE(dev->data->dev_private);
3063         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3064         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3065         int ret;
3066         uint32_t intr_vector = 0;
3067
3068         PMD_INIT_FUNC_TRACE();
3069
3070         hw->mac.ops.reset_hw(hw);
3071         adapter->stopped = 0;
3072
3073         /* Set all vfta */
3074         igbvf_set_vfta_all(dev,1);
3075
3076         eth_igbvf_tx_init(dev);
3077
3078         /* This can fail when allocating mbufs for descriptor rings */
3079         ret = eth_igbvf_rx_init(dev);
3080         if (ret) {
3081                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3082                 igb_dev_clear_queues(dev);
3083                 return ret;
3084         }
3085
3086         /* check and configure queue intr-vector mapping */
3087         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3088                 intr_vector = dev->data->nb_rx_queues;
3089                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3090                 if (ret)
3091                         return ret;
3092         }
3093
3094         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3095                 intr_handle->intr_vec =
3096                         rte_zmalloc("intr_vec",
3097                                     dev->data->nb_rx_queues * sizeof(int), 0);
3098                 if (!intr_handle->intr_vec) {
3099                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3100                                      " intr_vec\n", dev->data->nb_rx_queues);
3101                         return -ENOMEM;
3102                 }
3103         }
3104
3105         eth_igbvf_configure_msix_intr(dev);
3106
3107         /* enable uio/vfio intr/eventfd mapping */
3108         rte_intr_enable(intr_handle);
3109
3110         /* resume enabled intr since hw reset */
3111         igbvf_intr_enable(dev);
3112
3113         return 0;
3114 }
3115
3116 static void
3117 igbvf_dev_stop(struct rte_eth_dev *dev)
3118 {
3119         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3120         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3121
3122         PMD_INIT_FUNC_TRACE();
3123
3124         igbvf_stop_adapter(dev);
3125
3126         /*
3127           * Clear what we set, but we still keep shadow_vfta to
3128           * restore after device starts
3129           */
3130         igbvf_set_vfta_all(dev,0);
3131
3132         igb_dev_clear_queues(dev);
3133
3134         /* disable intr eventfd mapping */
3135         rte_intr_disable(intr_handle);
3136
3137         /* Clean datapath event and queue/vec mapping */
3138         rte_intr_efd_disable(intr_handle);
3139         if (intr_handle->intr_vec) {
3140                 rte_free(intr_handle->intr_vec);
3141                 intr_handle->intr_vec = NULL;
3142         }
3143 }
3144
3145 static void
3146 igbvf_dev_close(struct rte_eth_dev *dev)
3147 {
3148         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3149         struct e1000_adapter *adapter =
3150                 E1000_DEV_PRIVATE(dev->data->dev_private);
3151         struct ether_addr addr;
3152
3153         PMD_INIT_FUNC_TRACE();
3154
3155         e1000_reset_hw(hw);
3156
3157         igbvf_dev_stop(dev);
3158         adapter->stopped = 1;
3159         igb_dev_free_queues(dev);
3160
3161         /**
3162          * reprogram the RAR with a zero mac address,
3163          * to ensure that the VF traffic goes to the PF
3164          * after stop, close and detach of the VF.
3165          **/
3166
3167         memset(&addr, 0, sizeof(addr));
3168         igbvf_default_mac_addr_set(dev, &addr);
3169 }
3170
3171 static void
3172 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3173 {
3174         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3175
3176         /* Set both unicast and multicast promisc */
3177         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3178 }
3179
3180 static void
3181 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3182 {
3183         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3184
3185         /* If in allmulticast mode leave multicast promisc */
3186         if (dev->data->all_multicast == 1)
3187                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3188         else
3189                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3190 }
3191
3192 static void
3193 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3194 {
3195         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3196
3197         /* In promiscuous mode multicast promisc already set */
3198         if (dev->data->promiscuous == 0)
3199                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3200 }
3201
3202 static void
3203 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3204 {
3205         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3206
3207         /* In promiscuous mode leave multicast promisc enabled */
3208         if (dev->data->promiscuous == 0)
3209                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3210 }
3211
3212 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3213 {
3214         struct e1000_mbx_info *mbx = &hw->mbx;
3215         uint32_t msgbuf[2];
3216         s32 err;
3217
3218         /* After set vlan, vlan strip will also be enabled in igb driver*/
3219         msgbuf[0] = E1000_VF_SET_VLAN;
3220         msgbuf[1] = vid;
3221         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3222         if (on)
3223                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3224
3225         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3226         if (err)
3227                 goto mbx_err;
3228
3229         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3230         if (err)
3231                 goto mbx_err;
3232
3233         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3234         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3235                 err = -EINVAL;
3236
3237 mbx_err:
3238         return err;
3239 }
3240
3241 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3242 {
3243         struct e1000_hw *hw =
3244                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3245         struct e1000_vfta * shadow_vfta =
3246                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3247         int i = 0, j = 0, vfta = 0, mask = 1;
3248
3249         for (i = 0; i < IGB_VFTA_SIZE; i++){
3250                 vfta = shadow_vfta->vfta[i];
3251                 if(vfta){
3252                         mask = 1;
3253                         for (j = 0; j < 32; j++){
3254                                 if(vfta & mask)
3255                                         igbvf_set_vfta(hw,
3256                                                 (uint16_t)((i<<5)+j), on);
3257                                 mask<<=1;
3258                         }
3259                 }
3260         }
3261
3262 }
3263
3264 static int
3265 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3266 {
3267         struct e1000_hw *hw =
3268                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3269         struct e1000_vfta * shadow_vfta =
3270                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3271         uint32_t vid_idx = 0;
3272         uint32_t vid_bit = 0;
3273         int ret = 0;
3274
3275         PMD_INIT_FUNC_TRACE();
3276
3277         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3278         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3279         if(ret){
3280                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3281                 return ret;
3282         }
3283         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3284         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3285
3286         /*Save what we set and retore it after device reset*/
3287         if (on)
3288                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3289         else
3290                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3291
3292         return 0;
3293 }
3294
3295 static void
3296 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3297 {
3298         struct e1000_hw *hw =
3299                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300
3301         /* index is not used by rar_set() */
3302         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3303 }
3304
3305
3306 static int
3307 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3308                         struct rte_eth_rss_reta_entry64 *reta_conf,
3309                         uint16_t reta_size)
3310 {
3311         uint8_t i, j, mask;
3312         uint32_t reta, r;
3313         uint16_t idx, shift;
3314         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3315
3316         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3317                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3318                         "(%d) doesn't match the number hardware can supported "
3319                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3320                 return -EINVAL;
3321         }
3322
3323         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3324                 idx = i / RTE_RETA_GROUP_SIZE;
3325                 shift = i % RTE_RETA_GROUP_SIZE;
3326                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3327                                                 IGB_4_BIT_MASK);
3328                 if (!mask)
3329                         continue;
3330                 if (mask == IGB_4_BIT_MASK)
3331                         r = 0;
3332                 else
3333                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3334                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3335                         if (mask & (0x1 << j))
3336                                 reta |= reta_conf[idx].reta[shift + j] <<
3337                                                         (CHAR_BIT * j);
3338                         else
3339                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3340                 }
3341                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3342         }
3343
3344         return 0;
3345 }
3346
3347 static int
3348 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3349                        struct rte_eth_rss_reta_entry64 *reta_conf,
3350                        uint16_t reta_size)
3351 {
3352         uint8_t i, j, mask;
3353         uint32_t reta;
3354         uint16_t idx, shift;
3355         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3356
3357         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3358                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3359                         "(%d) doesn't match the number hardware can supported "
3360                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3361                 return -EINVAL;
3362         }
3363
3364         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3365                 idx = i / RTE_RETA_GROUP_SIZE;
3366                 shift = i % RTE_RETA_GROUP_SIZE;
3367                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3368                                                 IGB_4_BIT_MASK);
3369                 if (!mask)
3370                         continue;
3371                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3372                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3373                         if (mask & (0x1 << j))
3374                                 reta_conf[idx].reta[shift + j] =
3375                                         ((reta >> (CHAR_BIT * j)) &
3376                                                 IGB_8_BIT_MASK);
3377                 }
3378         }
3379
3380         return 0;
3381 }
3382
3383 #define MAC_TYPE_FILTER_SUP(type)    do {\
3384         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3385                 (type) != e1000_82576)\
3386                 return -ENOTSUP;\
3387 } while (0)
3388
3389 static int
3390 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3391                         struct rte_eth_syn_filter *filter,
3392                         bool add)
3393 {
3394         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3395         uint32_t synqf, rfctl;
3396
3397         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3398                 return -EINVAL;
3399
3400         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3401
3402         if (add) {
3403                 if (synqf & E1000_SYN_FILTER_ENABLE)
3404                         return -EINVAL;
3405
3406                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3407                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3408
3409                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3410                 if (filter->hig_pri)
3411                         rfctl |= E1000_RFCTL_SYNQFP;
3412                 else
3413                         rfctl &= ~E1000_RFCTL_SYNQFP;
3414
3415                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3416         } else {
3417                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3418                         return -ENOENT;
3419                 synqf = 0;
3420         }
3421
3422         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3423         E1000_WRITE_FLUSH(hw);
3424         return 0;
3425 }
3426
3427 static int
3428 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3429                         struct rte_eth_syn_filter *filter)
3430 {
3431         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3432         uint32_t synqf, rfctl;
3433
3434         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3435         if (synqf & E1000_SYN_FILTER_ENABLE) {
3436                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3437                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3438                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3439                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3440                 return 0;
3441         }
3442
3443         return -ENOENT;
3444 }
3445
3446 static int
3447 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3448                         enum rte_filter_op filter_op,
3449                         void *arg)
3450 {
3451         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3452         int ret;
3453
3454         MAC_TYPE_FILTER_SUP(hw->mac.type);
3455
3456         if (filter_op == RTE_ETH_FILTER_NOP)
3457                 return 0;
3458
3459         if (arg == NULL) {
3460                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3461                             filter_op);
3462                 return -EINVAL;
3463         }
3464
3465         switch (filter_op) {
3466         case RTE_ETH_FILTER_ADD:
3467                 ret = eth_igb_syn_filter_set(dev,
3468                                 (struct rte_eth_syn_filter *)arg,
3469                                 TRUE);
3470                 break;
3471         case RTE_ETH_FILTER_DELETE:
3472                 ret = eth_igb_syn_filter_set(dev,
3473                                 (struct rte_eth_syn_filter *)arg,
3474                                 FALSE);
3475                 break;
3476         case RTE_ETH_FILTER_GET:
3477                 ret = eth_igb_syn_filter_get(dev,
3478                                 (struct rte_eth_syn_filter *)arg);
3479                 break;
3480         default:
3481                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3482                 ret = -EINVAL;
3483                 break;
3484         }
3485
3486         return ret;
3487 }
3488
3489 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3490         if ((type) != e1000_82580 && (type) != e1000_i350)\
3491                 return -ENOSYS; \
3492 } while (0)
3493
3494 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3495 static inline int
3496 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3497                         struct e1000_2tuple_filter_info *filter_info)
3498 {
3499         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3500                 return -EINVAL;
3501         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3502                 return -EINVAL;  /* filter index is out of range. */
3503         if (filter->tcp_flags > TCP_FLAG_ALL)
3504                 return -EINVAL;  /* flags is invalid. */
3505
3506         switch (filter->dst_port_mask) {
3507         case UINT16_MAX:
3508                 filter_info->dst_port_mask = 0;
3509                 filter_info->dst_port = filter->dst_port;
3510                 break;
3511         case 0:
3512                 filter_info->dst_port_mask = 1;
3513                 break;
3514         default:
3515                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3516                 return -EINVAL;
3517         }
3518
3519         switch (filter->proto_mask) {
3520         case UINT8_MAX:
3521                 filter_info->proto_mask = 0;
3522                 filter_info->proto = filter->proto;
3523                 break;
3524         case 0:
3525                 filter_info->proto_mask = 1;
3526                 break;
3527         default:
3528                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3529                 return -EINVAL;
3530         }
3531
3532         filter_info->priority = (uint8_t)filter->priority;
3533         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3534                 filter_info->tcp_flags = filter->tcp_flags;
3535         else
3536                 filter_info->tcp_flags = 0;
3537
3538         return 0;
3539 }
3540
3541 static inline struct e1000_2tuple_filter *
3542 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3543                         struct e1000_2tuple_filter_info *key)
3544 {
3545         struct e1000_2tuple_filter *it;
3546
3547         TAILQ_FOREACH(it, filter_list, entries) {
3548                 if (memcmp(key, &it->filter_info,
3549                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3550                         return it;
3551                 }
3552         }
3553         return NULL;
3554 }
3555
3556 /*
3557  * igb_add_2tuple_filter - add a 2tuple filter
3558  *
3559  * @param
3560  * dev: Pointer to struct rte_eth_dev.
3561  * ntuple_filter: ponter to the filter that will be added.
3562  *
3563  * @return
3564  *    - On success, zero.
3565  *    - On failure, a negative value.
3566  */
3567 static int
3568 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3569                         struct rte_eth_ntuple_filter *ntuple_filter)
3570 {
3571         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3572         struct e1000_filter_info *filter_info =
3573                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3574         struct e1000_2tuple_filter *filter;
3575         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3576         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3577         int i, ret;
3578
3579         filter = rte_zmalloc("e1000_2tuple_filter",
3580                         sizeof(struct e1000_2tuple_filter), 0);
3581         if (filter == NULL)
3582                 return -ENOMEM;
3583
3584         ret = ntuple_filter_to_2tuple(ntuple_filter,
3585                                       &filter->filter_info);
3586         if (ret < 0) {
3587                 rte_free(filter);
3588                 return ret;
3589         }
3590         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3591                                          &filter->filter_info) != NULL) {
3592                 PMD_DRV_LOG(ERR, "filter exists.");
3593                 rte_free(filter);
3594                 return -EEXIST;
3595         }
3596         filter->queue = ntuple_filter->queue;
3597
3598         /*
3599          * look for an unused 2tuple filter index,
3600          * and insert the filter to list.
3601          */
3602         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3603                 if (!(filter_info->twotuple_mask & (1 << i))) {
3604                         filter_info->twotuple_mask |= 1 << i;
3605                         filter->index = i;
3606                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3607                                           filter,
3608                                           entries);
3609                         break;
3610                 }
3611         }
3612         if (i >= E1000_MAX_TTQF_FILTERS) {
3613                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3614                 rte_free(filter);
3615                 return -ENOSYS;
3616         }
3617
3618         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3619         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3620                 imir |= E1000_IMIR_PORT_BP;
3621         else
3622                 imir &= ~E1000_IMIR_PORT_BP;
3623
3624         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3625
3626         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3627         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3628         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3629         if (filter->filter_info.proto_mask == 0)
3630                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3631
3632         /* tcp flags bits setting. */
3633         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3634                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3635                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3636                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3637                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3638                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3639                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3640                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3641                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3642                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3643                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3644                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3645                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3646         } else
3647                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3648         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3649         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3650         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3651         return 0;
3652 }
3653
3654 /*
3655  * igb_remove_2tuple_filter - remove a 2tuple filter
3656  *
3657  * @param
3658  * dev: Pointer to struct rte_eth_dev.
3659  * ntuple_filter: ponter to the filter that will be removed.
3660  *
3661  * @return
3662  *    - On success, zero.
3663  *    - On failure, a negative value.
3664  */
3665 static int
3666 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3667                         struct rte_eth_ntuple_filter *ntuple_filter)
3668 {
3669         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3670         struct e1000_filter_info *filter_info =
3671                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3672         struct e1000_2tuple_filter_info filter_2tuple;
3673         struct e1000_2tuple_filter *filter;
3674         int ret;
3675
3676         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3677         ret = ntuple_filter_to_2tuple(ntuple_filter,
3678                                       &filter_2tuple);
3679         if (ret < 0)
3680                 return ret;
3681
3682         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3683                                          &filter_2tuple);
3684         if (filter == NULL) {
3685                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3686                 return -ENOENT;
3687         }
3688
3689         filter_info->twotuple_mask &= ~(1 << filter->index);
3690         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3691         rte_free(filter);
3692
3693         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3694         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3695         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3696         return 0;
3697 }
3698
3699 static inline struct e1000_flex_filter *
3700 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3701                         struct e1000_flex_filter_info *key)
3702 {
3703         struct e1000_flex_filter *it;
3704
3705         TAILQ_FOREACH(it, filter_list, entries) {
3706                 if (memcmp(key, &it->filter_info,
3707                         sizeof(struct e1000_flex_filter_info)) == 0)
3708                         return it;
3709         }
3710
3711         return NULL;
3712 }
3713
3714 static int
3715 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3716                         struct rte_eth_flex_filter *filter,
3717                         bool add)
3718 {
3719         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3720         struct e1000_filter_info *filter_info =
3721                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3722         struct e1000_flex_filter *flex_filter, *it;
3723         uint32_t wufc, queueing, mask;
3724         uint32_t reg_off;
3725         uint8_t shift, i, j = 0;
3726
3727         flex_filter = rte_zmalloc("e1000_flex_filter",
3728                         sizeof(struct e1000_flex_filter), 0);
3729         if (flex_filter == NULL)
3730                 return -ENOMEM;
3731
3732         flex_filter->filter_info.len = filter->len;
3733         flex_filter->filter_info.priority = filter->priority;
3734         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3735         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3736                 mask = 0;
3737                 /* reverse bits in flex filter's mask*/
3738                 for (shift = 0; shift < CHAR_BIT; shift++) {
3739                         if (filter->mask[i] & (0x01 << shift))
3740                                 mask |= (0x80 >> shift);
3741                 }
3742                 flex_filter->filter_info.mask[i] = mask;
3743         }
3744
3745         wufc = E1000_READ_REG(hw, E1000_WUFC);
3746         if (flex_filter->index < E1000_MAX_FHFT)
3747                 reg_off = E1000_FHFT(flex_filter->index);
3748         else
3749                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3750
3751         if (add) {
3752                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3753                                 &flex_filter->filter_info) != NULL) {
3754                         PMD_DRV_LOG(ERR, "filter exists.");
3755                         rte_free(flex_filter);
3756                         return -EEXIST;
3757                 }
3758                 flex_filter->queue = filter->queue;
3759                 /*
3760                  * look for an unused flex filter index
3761                  * and insert the filter into the list.
3762                  */
3763                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3764                         if (!(filter_info->flex_mask & (1 << i))) {
3765                                 filter_info->flex_mask |= 1 << i;
3766                                 flex_filter->index = i;
3767                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3768                                         flex_filter,
3769                                         entries);
3770                                 break;
3771                         }
3772                 }
3773                 if (i >= E1000_MAX_FLEX_FILTERS) {
3774                         PMD_DRV_LOG(ERR, "flex filters are full.");
3775                         rte_free(flex_filter);
3776                         return -ENOSYS;
3777                 }
3778
3779                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3780                                 (E1000_WUFC_FLX0 << flex_filter->index));
3781                 queueing = filter->len |
3782                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3783                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3784                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3785                                 queueing);
3786                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3787                         E1000_WRITE_REG(hw, reg_off,
3788                                         flex_filter->filter_info.dwords[j]);
3789                         reg_off += sizeof(uint32_t);
3790                         E1000_WRITE_REG(hw, reg_off,
3791                                         flex_filter->filter_info.dwords[++j]);
3792                         reg_off += sizeof(uint32_t);
3793                         E1000_WRITE_REG(hw, reg_off,
3794                                 (uint32_t)flex_filter->filter_info.mask[i]);
3795                         reg_off += sizeof(uint32_t) * 2;
3796                         ++j;
3797                 }
3798         } else {
3799                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3800                                 &flex_filter->filter_info);
3801                 if (it == NULL) {
3802                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3803                         rte_free(flex_filter);
3804                         return -ENOENT;
3805                 }
3806
3807                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3808                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3809                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3810                         (~(E1000_WUFC_FLX0 << it->index)));
3811
3812                 filter_info->flex_mask &= ~(1 << it->index);
3813                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3814                 rte_free(it);
3815                 rte_free(flex_filter);
3816         }
3817
3818         return 0;
3819 }
3820
3821 static int
3822 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3823                         struct rte_eth_flex_filter *filter)
3824 {
3825         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3826         struct e1000_filter_info *filter_info =
3827                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3828         struct e1000_flex_filter flex_filter, *it;
3829         uint32_t wufc, queueing, wufc_en = 0;
3830
3831         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3832         flex_filter.filter_info.len = filter->len;
3833         flex_filter.filter_info.priority = filter->priority;
3834         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3835         memcpy(flex_filter.filter_info.mask, filter->mask,
3836                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3837
3838         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3839                                 &flex_filter.filter_info);
3840         if (it == NULL) {
3841                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3842                 return -ENOENT;
3843         }
3844
3845         wufc = E1000_READ_REG(hw, E1000_WUFC);
3846         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3847
3848         if ((wufc & wufc_en) == wufc_en) {
3849                 uint32_t reg_off = 0;
3850                 if (it->index < E1000_MAX_FHFT)
3851                         reg_off = E1000_FHFT(it->index);
3852                 else
3853                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3854
3855                 queueing = E1000_READ_REG(hw,
3856                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3857                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3858                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3859                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3860                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3861                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3862                 return 0;
3863         }
3864         return -ENOENT;
3865 }
3866
3867 static int
3868 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3869                         enum rte_filter_op filter_op,
3870                         void *arg)
3871 {
3872         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3873         struct rte_eth_flex_filter *filter;
3874         int ret = 0;
3875
3876         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3877
3878         if (filter_op == RTE_ETH_FILTER_NOP)
3879                 return ret;
3880
3881         if (arg == NULL) {
3882                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3883                             filter_op);
3884                 return -EINVAL;
3885         }
3886
3887         filter = (struct rte_eth_flex_filter *)arg;
3888         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3889             || filter->len % sizeof(uint64_t) != 0) {
3890                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3891                 return -EINVAL;
3892         }
3893         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3894                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3895                 return -EINVAL;
3896         }
3897
3898         switch (filter_op) {
3899         case RTE_ETH_FILTER_ADD:
3900                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3901                 break;
3902         case RTE_ETH_FILTER_DELETE:
3903                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3904                 break;
3905         case RTE_ETH_FILTER_GET:
3906                 ret = eth_igb_get_flex_filter(dev, filter);
3907                 break;
3908         default:
3909                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3910                 ret = -EINVAL;
3911                 break;
3912         }
3913
3914         return ret;
3915 }
3916
3917 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3918 static inline int
3919 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3920                         struct e1000_5tuple_filter_info *filter_info)
3921 {
3922         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3923                 return -EINVAL;
3924         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3925                 return -EINVAL;  /* filter index is out of range. */
3926         if (filter->tcp_flags > TCP_FLAG_ALL)
3927                 return -EINVAL;  /* flags is invalid. */
3928
3929         switch (filter->dst_ip_mask) {
3930         case UINT32_MAX:
3931                 filter_info->dst_ip_mask = 0;
3932                 filter_info->dst_ip = filter->dst_ip;
3933                 break;
3934         case 0:
3935                 filter_info->dst_ip_mask = 1;
3936                 break;
3937         default:
3938                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3939                 return -EINVAL;
3940         }
3941
3942         switch (filter->src_ip_mask) {
3943         case UINT32_MAX:
3944                 filter_info->src_ip_mask = 0;
3945                 filter_info->src_ip = filter->src_ip;
3946                 break;
3947         case 0:
3948                 filter_info->src_ip_mask = 1;
3949                 break;
3950         default:
3951                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3952                 return -EINVAL;
3953         }
3954
3955         switch (filter->dst_port_mask) {
3956         case UINT16_MAX:
3957                 filter_info->dst_port_mask = 0;
3958                 filter_info->dst_port = filter->dst_port;
3959                 break;
3960         case 0:
3961                 filter_info->dst_port_mask = 1;
3962                 break;
3963         default:
3964                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3965                 return -EINVAL;
3966         }
3967
3968         switch (filter->src_port_mask) {
3969         case UINT16_MAX:
3970                 filter_info->src_port_mask = 0;
3971                 filter_info->src_port = filter->src_port;
3972                 break;
3973         case 0:
3974                 filter_info->src_port_mask = 1;
3975                 break;
3976         default:
3977                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3978                 return -EINVAL;
3979         }
3980
3981         switch (filter->proto_mask) {
3982         case UINT8_MAX:
3983                 filter_info->proto_mask = 0;
3984                 filter_info->proto = filter->proto;
3985                 break;
3986         case 0:
3987                 filter_info->proto_mask = 1;
3988                 break;
3989         default:
3990                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3991                 return -EINVAL;
3992         }
3993
3994         filter_info->priority = (uint8_t)filter->priority;
3995         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3996                 filter_info->tcp_flags = filter->tcp_flags;
3997         else
3998                 filter_info->tcp_flags = 0;
3999
4000         return 0;
4001 }
4002
4003 static inline struct e1000_5tuple_filter *
4004 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4005                         struct e1000_5tuple_filter_info *key)
4006 {
4007         struct e1000_5tuple_filter *it;
4008
4009         TAILQ_FOREACH(it, filter_list, entries) {
4010                 if (memcmp(key, &it->filter_info,
4011                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4012                         return it;
4013                 }
4014         }
4015         return NULL;
4016 }
4017
4018 /*
4019  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4020  *
4021  * @param
4022  * dev: Pointer to struct rte_eth_dev.
4023  * ntuple_filter: ponter to the filter that will be added.
4024  *
4025  * @return
4026  *    - On success, zero.
4027  *    - On failure, a negative value.
4028  */
4029 static int
4030 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4031                         struct rte_eth_ntuple_filter *ntuple_filter)
4032 {
4033         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4034         struct e1000_filter_info *filter_info =
4035                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4036         struct e1000_5tuple_filter *filter;
4037         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4038         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4039         uint8_t i;
4040         int ret;
4041
4042         filter = rte_zmalloc("e1000_5tuple_filter",
4043                         sizeof(struct e1000_5tuple_filter), 0);
4044         if (filter == NULL)
4045                 return -ENOMEM;
4046
4047         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4048                                             &filter->filter_info);
4049         if (ret < 0) {
4050                 rte_free(filter);
4051                 return ret;
4052         }
4053
4054         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4055                                          &filter->filter_info) != NULL) {
4056                 PMD_DRV_LOG(ERR, "filter exists.");
4057                 rte_free(filter);
4058                 return -EEXIST;
4059         }
4060         filter->queue = ntuple_filter->queue;
4061
4062         /*
4063          * look for an unused 5tuple filter index,
4064          * and insert the filter to list.
4065          */
4066         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4067                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4068                         filter_info->fivetuple_mask |= 1 << i;
4069                         filter->index = i;
4070                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4071                                           filter,
4072                                           entries);
4073                         break;
4074                 }
4075         }
4076         if (i >= E1000_MAX_FTQF_FILTERS) {
4077                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4078                 rte_free(filter);
4079                 return -ENOSYS;
4080         }
4081
4082         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4083         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4084                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4085         if (filter->filter_info.dst_ip_mask == 0)
4086                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4087         if (filter->filter_info.src_port_mask == 0)
4088                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4089         if (filter->filter_info.proto_mask == 0)
4090                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4091         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4092                 E1000_FTQF_QUEUE_MASK;
4093         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4094         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4095         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4096         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4097
4098         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4099         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4100
4101         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4102         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4103                 imir |= E1000_IMIR_PORT_BP;
4104         else
4105                 imir &= ~E1000_IMIR_PORT_BP;
4106         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4107
4108         /* tcp flags bits setting. */
4109         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4110                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4111                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4112                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4113                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4114                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4115                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4116                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4117                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4118                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4119                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4120                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4121                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4122         } else
4123                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4124         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4125         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4126         return 0;
4127 }
4128
4129 /*
4130  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4131  *
4132  * @param
4133  * dev: Pointer to struct rte_eth_dev.
4134  * ntuple_filter: ponter to the filter that will be removed.
4135  *
4136  * @return
4137  *    - On success, zero.
4138  *    - On failure, a negative value.
4139  */
4140 static int
4141 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4142                                 struct rte_eth_ntuple_filter *ntuple_filter)
4143 {
4144         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4145         struct e1000_filter_info *filter_info =
4146                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4147         struct e1000_5tuple_filter_info filter_5tuple;
4148         struct e1000_5tuple_filter *filter;
4149         int ret;
4150
4151         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4152         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4153                                             &filter_5tuple);
4154         if (ret < 0)
4155                 return ret;
4156
4157         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4158                                          &filter_5tuple);
4159         if (filter == NULL) {
4160                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4161                 return -ENOENT;
4162         }
4163
4164         filter_info->fivetuple_mask &= ~(1 << filter->index);
4165         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4166         rte_free(filter);
4167
4168         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4169                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4170         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4171         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4172         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4173         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4174         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4175         return 0;
4176 }
4177
4178 static int
4179 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4180 {
4181         uint32_t rctl;
4182         struct e1000_hw *hw;
4183         struct rte_eth_dev_info dev_info;
4184         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4185                                      VLAN_TAG_SIZE);
4186
4187         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4188
4189 #ifdef RTE_LIBRTE_82571_SUPPORT
4190         /* XXX: not bigger than max_rx_pktlen */
4191         if (hw->mac.type == e1000_82571)
4192                 return -ENOTSUP;
4193 #endif
4194         eth_igb_infos_get(dev, &dev_info);
4195
4196         /* check that mtu is within the allowed range */
4197         if ((mtu < ETHER_MIN_MTU) ||
4198             (frame_size > dev_info.max_rx_pktlen))
4199                 return -EINVAL;
4200
4201         /* refuse mtu that requires the support of scattered packets when this
4202          * feature has not been enabled before. */
4203         if (!dev->data->scattered_rx &&
4204             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4205                 return -EINVAL;
4206
4207         rctl = E1000_READ_REG(hw, E1000_RCTL);
4208
4209         /* switch to jumbo mode if needed */
4210         if (frame_size > ETHER_MAX_LEN) {
4211                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4212                 rctl |= E1000_RCTL_LPE;
4213         } else {
4214                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4215                 rctl &= ~E1000_RCTL_LPE;
4216         }
4217         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4218
4219         /* update max frame size */
4220         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4221
4222         E1000_WRITE_REG(hw, E1000_RLPML,
4223                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4224
4225         return 0;
4226 }
4227
4228 /*
4229  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4230  *
4231  * @param
4232  * dev: Pointer to struct rte_eth_dev.
4233  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4234  * add: if true, add filter, if false, remove filter
4235  *
4236  * @return
4237  *    - On success, zero.
4238  *    - On failure, a negative value.
4239  */
4240 static int
4241 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4242                         struct rte_eth_ntuple_filter *ntuple_filter,
4243                         bool add)
4244 {
4245         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4246         int ret;
4247
4248         switch (ntuple_filter->flags) {
4249         case RTE_5TUPLE_FLAGS:
4250         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4251                 if (hw->mac.type != e1000_82576)
4252                         return -ENOTSUP;
4253                 if (add)
4254                         ret = igb_add_5tuple_filter_82576(dev,
4255                                                           ntuple_filter);
4256                 else
4257                         ret = igb_remove_5tuple_filter_82576(dev,
4258                                                              ntuple_filter);
4259                 break;
4260         case RTE_2TUPLE_FLAGS:
4261         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4262                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4263                         return -ENOTSUP;
4264                 if (add)
4265                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4266                 else
4267                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4268                 break;
4269         default:
4270                 ret = -EINVAL;
4271                 break;
4272         }
4273
4274         return ret;
4275 }
4276
4277 /*
4278  * igb_get_ntuple_filter - get a ntuple filter
4279  *
4280  * @param
4281  * dev: Pointer to struct rte_eth_dev.
4282  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4283  *
4284  * @return
4285  *    - On success, zero.
4286  *    - On failure, a negative value.
4287  */
4288 static int
4289 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4290                         struct rte_eth_ntuple_filter *ntuple_filter)
4291 {
4292         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4293         struct e1000_filter_info *filter_info =
4294                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4295         struct e1000_5tuple_filter_info filter_5tuple;
4296         struct e1000_2tuple_filter_info filter_2tuple;
4297         struct e1000_5tuple_filter *p_5tuple_filter;
4298         struct e1000_2tuple_filter *p_2tuple_filter;
4299         int ret;
4300
4301         switch (ntuple_filter->flags) {
4302         case RTE_5TUPLE_FLAGS:
4303         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4304                 if (hw->mac.type != e1000_82576)
4305                         return -ENOTSUP;
4306                 memset(&filter_5tuple,
4307                         0,
4308                         sizeof(struct e1000_5tuple_filter_info));
4309                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4310                                                     &filter_5tuple);
4311                 if (ret < 0)
4312                         return ret;
4313                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4314                                         &filter_info->fivetuple_list,
4315                                         &filter_5tuple);
4316                 if (p_5tuple_filter == NULL) {
4317                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4318                         return -ENOENT;
4319                 }
4320                 ntuple_filter->queue = p_5tuple_filter->queue;
4321                 break;
4322         case RTE_2TUPLE_FLAGS:
4323         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4324                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4325                         return -ENOTSUP;
4326                 memset(&filter_2tuple,
4327                         0,
4328                         sizeof(struct e1000_2tuple_filter_info));
4329                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4330                 if (ret < 0)
4331                         return ret;
4332                 p_2tuple_filter = igb_2tuple_filter_lookup(
4333                                         &filter_info->twotuple_list,
4334                                         &filter_2tuple);
4335                 if (p_2tuple_filter == NULL) {
4336                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4337                         return -ENOENT;
4338                 }
4339                 ntuple_filter->queue = p_2tuple_filter->queue;
4340                 break;
4341         default:
4342                 ret = -EINVAL;
4343                 break;
4344         }
4345
4346         return 0;
4347 }
4348
4349 /*
4350  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4351  * @dev: pointer to rte_eth_dev structure
4352  * @filter_op:operation will be taken.
4353  * @arg: a pointer to specific structure corresponding to the filter_op
4354  */
4355 static int
4356 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4357                                 enum rte_filter_op filter_op,
4358                                 void *arg)
4359 {
4360         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4361         int ret;
4362
4363         MAC_TYPE_FILTER_SUP(hw->mac.type);
4364
4365         if (filter_op == RTE_ETH_FILTER_NOP)
4366                 return 0;
4367
4368         if (arg == NULL) {
4369                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4370                             filter_op);
4371                 return -EINVAL;
4372         }
4373
4374         switch (filter_op) {
4375         case RTE_ETH_FILTER_ADD:
4376                 ret = igb_add_del_ntuple_filter(dev,
4377                         (struct rte_eth_ntuple_filter *)arg,
4378                         TRUE);
4379                 break;
4380         case RTE_ETH_FILTER_DELETE:
4381                 ret = igb_add_del_ntuple_filter(dev,
4382                         (struct rte_eth_ntuple_filter *)arg,
4383                         FALSE);
4384                 break;
4385         case RTE_ETH_FILTER_GET:
4386                 ret = igb_get_ntuple_filter(dev,
4387                         (struct rte_eth_ntuple_filter *)arg);
4388                 break;
4389         default:
4390                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4391                 ret = -EINVAL;
4392                 break;
4393         }
4394         return ret;
4395 }
4396
4397 static inline int
4398 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4399                         uint16_t ethertype)
4400 {
4401         int i;
4402
4403         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4404                 if (filter_info->ethertype_filters[i] == ethertype &&
4405                     (filter_info->ethertype_mask & (1 << i)))
4406                         return i;
4407         }
4408         return -1;
4409 }
4410
4411 static inline int
4412 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4413                         uint16_t ethertype)
4414 {
4415         int i;
4416
4417         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4418                 if (!(filter_info->ethertype_mask & (1 << i))) {
4419                         filter_info->ethertype_mask |= 1 << i;
4420                         filter_info->ethertype_filters[i] = ethertype;
4421                         return i;
4422                 }
4423         }
4424         return -1;
4425 }
4426
4427 static inline int
4428 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4429                         uint8_t idx)
4430 {
4431         if (idx >= E1000_MAX_ETQF_FILTERS)
4432                 return -1;
4433         filter_info->ethertype_mask &= ~(1 << idx);
4434         filter_info->ethertype_filters[idx] = 0;
4435         return idx;
4436 }
4437
4438
4439 static int
4440 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4441                         struct rte_eth_ethertype_filter *filter,
4442                         bool add)
4443 {
4444         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4445         struct e1000_filter_info *filter_info =
4446                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4447         uint32_t etqf = 0;
4448         int ret;
4449
4450         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4451                 filter->ether_type == ETHER_TYPE_IPv6) {
4452                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4453                         " ethertype filter.", filter->ether_type);
4454                 return -EINVAL;
4455         }
4456
4457         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4458                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4459                 return -EINVAL;
4460         }
4461         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4462                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4463                 return -EINVAL;
4464         }
4465
4466         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4467         if (ret >= 0 && add) {
4468                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4469                             filter->ether_type);
4470                 return -EEXIST;
4471         }
4472         if (ret < 0 && !add) {
4473                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4474                             filter->ether_type);
4475                 return -ENOENT;
4476         }
4477
4478         if (add) {
4479                 ret = igb_ethertype_filter_insert(filter_info,
4480                         filter->ether_type);
4481                 if (ret < 0) {
4482                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4483                         return -ENOSYS;
4484                 }
4485
4486                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4487                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4488                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4489         } else {
4490                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4491                 if (ret < 0)
4492                         return -ENOSYS;
4493         }
4494         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4495         E1000_WRITE_FLUSH(hw);
4496
4497         return 0;
4498 }
4499
4500 static int
4501 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4502                         struct rte_eth_ethertype_filter *filter)
4503 {
4504         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4505         struct e1000_filter_info *filter_info =
4506                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4507         uint32_t etqf;
4508         int ret;
4509
4510         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4511         if (ret < 0) {
4512                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4513                             filter->ether_type);
4514                 return -ENOENT;
4515         }
4516
4517         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4518         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4519                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4520                 filter->flags = 0;
4521                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4522                                 E1000_ETQF_QUEUE_SHIFT;
4523                 return 0;
4524         }
4525
4526         return -ENOENT;
4527 }
4528
4529 /*
4530  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4531  * @dev: pointer to rte_eth_dev structure
4532  * @filter_op:operation will be taken.
4533  * @arg: a pointer to specific structure corresponding to the filter_op
4534  */
4535 static int
4536 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4537                                 enum rte_filter_op filter_op,
4538                                 void *arg)
4539 {
4540         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4541         int ret;
4542
4543         MAC_TYPE_FILTER_SUP(hw->mac.type);
4544
4545         if (filter_op == RTE_ETH_FILTER_NOP)
4546                 return 0;
4547
4548         if (arg == NULL) {
4549                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4550                             filter_op);
4551                 return -EINVAL;
4552         }
4553
4554         switch (filter_op) {
4555         case RTE_ETH_FILTER_ADD:
4556                 ret = igb_add_del_ethertype_filter(dev,
4557                         (struct rte_eth_ethertype_filter *)arg,
4558                         TRUE);
4559                 break;
4560         case RTE_ETH_FILTER_DELETE:
4561                 ret = igb_add_del_ethertype_filter(dev,
4562                         (struct rte_eth_ethertype_filter *)arg,
4563                         FALSE);
4564                 break;
4565         case RTE_ETH_FILTER_GET:
4566                 ret = igb_get_ethertype_filter(dev,
4567                         (struct rte_eth_ethertype_filter *)arg);
4568                 break;
4569         default:
4570                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4571                 ret = -EINVAL;
4572                 break;
4573         }
4574         return ret;
4575 }
4576
4577 static int
4578 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4579                      enum rte_filter_type filter_type,
4580                      enum rte_filter_op filter_op,
4581                      void *arg)
4582 {
4583         int ret = -EINVAL;
4584
4585         switch (filter_type) {
4586         case RTE_ETH_FILTER_NTUPLE:
4587                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4588                 break;
4589         case RTE_ETH_FILTER_ETHERTYPE:
4590                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4591                 break;
4592         case RTE_ETH_FILTER_SYN:
4593                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4594                 break;
4595         case RTE_ETH_FILTER_FLEXIBLE:
4596                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4597                 break;
4598         default:
4599                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4600                                                         filter_type);
4601                 break;
4602         }
4603
4604         return ret;
4605 }
4606
4607 static int
4608 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4609                          struct ether_addr *mc_addr_set,
4610                          uint32_t nb_mc_addr)
4611 {
4612         struct e1000_hw *hw;
4613
4614         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4615         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4616         return 0;
4617 }
4618
4619 static uint64_t
4620 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4621 {
4622         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4623         uint64_t systime_cycles;
4624
4625         switch (hw->mac.type) {
4626         case e1000_i210:
4627         case e1000_i211:
4628                 /*
4629                  * Need to read System Time Residue Register to be able
4630                  * to read the other two registers.
4631                  */
4632                 E1000_READ_REG(hw, E1000_SYSTIMR);
4633                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4634                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4635                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4636                                 * NSEC_PER_SEC;
4637                 break;
4638         case e1000_82580:
4639         case e1000_i350:
4640         case e1000_i354:
4641                 /*
4642                  * Need to read System Time Residue Register to be able
4643                  * to read the other two registers.
4644                  */
4645                 E1000_READ_REG(hw, E1000_SYSTIMR);
4646                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4647                 /* Only the 8 LSB are valid. */
4648                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4649                                 & 0xff) << 32;
4650                 break;
4651         default:
4652                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4653                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4654                                 << 32;
4655                 break;
4656         }
4657
4658         return systime_cycles;
4659 }
4660
4661 static uint64_t
4662 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4663 {
4664         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4665         uint64_t rx_tstamp_cycles;
4666
4667         switch (hw->mac.type) {
4668         case e1000_i210:
4669         case e1000_i211:
4670                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4671                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4672                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4673                                 * NSEC_PER_SEC;
4674                 break;
4675         case e1000_82580:
4676         case e1000_i350:
4677         case e1000_i354:
4678                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4679                 /* Only the 8 LSB are valid. */
4680                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4681                                 & 0xff) << 32;
4682                 break;
4683         default:
4684                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4685                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4686                                 << 32;
4687                 break;
4688         }
4689
4690         return rx_tstamp_cycles;
4691 }
4692
4693 static uint64_t
4694 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4695 {
4696         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4697         uint64_t tx_tstamp_cycles;
4698
4699         switch (hw->mac.type) {
4700         case e1000_i210:
4701         case e1000_i211:
4702                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4703                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4704                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4705                                 * NSEC_PER_SEC;
4706                 break;
4707         case e1000_82580:
4708         case e1000_i350:
4709         case e1000_i354:
4710                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4711                 /* Only the 8 LSB are valid. */
4712                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4713                                 & 0xff) << 32;
4714                 break;
4715         default:
4716                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4717                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4718                                 << 32;
4719                 break;
4720         }
4721
4722         return tx_tstamp_cycles;
4723 }
4724
4725 static void
4726 igb_start_timecounters(struct rte_eth_dev *dev)
4727 {
4728         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4729         struct e1000_adapter *adapter =
4730                 (struct e1000_adapter *)dev->data->dev_private;
4731         uint32_t incval = 1;
4732         uint32_t shift = 0;
4733         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4734
4735         switch (hw->mac.type) {
4736         case e1000_82580:
4737         case e1000_i350:
4738         case e1000_i354:
4739                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4740                 mask = (1ULL << 40) - 1;
4741                 /* fall-through */
4742         case e1000_i210:
4743         case e1000_i211:
4744                 /*
4745                  * Start incrementing the register
4746                  * used to timestamp PTP packets.
4747                  */
4748                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4749                 break;
4750         case e1000_82576:
4751                 incval = E1000_INCVALUE_82576;
4752                 shift = IGB_82576_TSYNC_SHIFT;
4753                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4754                                 E1000_INCPERIOD_82576 | incval);
4755                 break;
4756         default:
4757                 /* Not supported */
4758                 return;
4759         }
4760
4761         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4762         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4763         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4764
4765         adapter->systime_tc.cc_mask = mask;
4766         adapter->systime_tc.cc_shift = shift;
4767         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4768
4769         adapter->rx_tstamp_tc.cc_mask = mask;
4770         adapter->rx_tstamp_tc.cc_shift = shift;
4771         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4772
4773         adapter->tx_tstamp_tc.cc_mask = mask;
4774         adapter->tx_tstamp_tc.cc_shift = shift;
4775         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4776 }
4777
4778 static int
4779 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4780 {
4781         struct e1000_adapter *adapter =
4782                         (struct e1000_adapter *)dev->data->dev_private;
4783
4784         adapter->systime_tc.nsec += delta;
4785         adapter->rx_tstamp_tc.nsec += delta;
4786         adapter->tx_tstamp_tc.nsec += delta;
4787
4788         return 0;
4789 }
4790
4791 static int
4792 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4793 {
4794         uint64_t ns;
4795         struct e1000_adapter *adapter =
4796                         (struct e1000_adapter *)dev->data->dev_private;
4797
4798         ns = rte_timespec_to_ns(ts);
4799
4800         /* Set the timecounters to a new value. */
4801         adapter->systime_tc.nsec = ns;
4802         adapter->rx_tstamp_tc.nsec = ns;
4803         adapter->tx_tstamp_tc.nsec = ns;
4804
4805         return 0;
4806 }
4807
4808 static int
4809 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4810 {
4811         uint64_t ns, systime_cycles;
4812         struct e1000_adapter *adapter =
4813                         (struct e1000_adapter *)dev->data->dev_private;
4814
4815         systime_cycles = igb_read_systime_cyclecounter(dev);
4816         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4817         *ts = rte_ns_to_timespec(ns);
4818
4819         return 0;
4820 }
4821
4822 static int
4823 igb_timesync_enable(struct rte_eth_dev *dev)
4824 {
4825         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4826         uint32_t tsync_ctl;
4827         uint32_t tsauxc;
4828
4829         /* Stop the timesync system time. */
4830         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4831         /* Reset the timesync system time value. */
4832         switch (hw->mac.type) {
4833         case e1000_82580:
4834         case e1000_i350:
4835         case e1000_i354:
4836         case e1000_i210:
4837         case e1000_i211:
4838                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4839                 /* fall-through */
4840         case e1000_82576:
4841                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4842                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4843                 break;
4844         default:
4845                 /* Not supported. */
4846                 return -ENOTSUP;
4847         }
4848
4849         /* Enable system time for it isn't on by default. */
4850         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4851         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4852         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4853
4854         igb_start_timecounters(dev);
4855
4856         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4857         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4858                         (ETHER_TYPE_1588 |
4859                          E1000_ETQF_FILTER_ENABLE |
4860                          E1000_ETQF_1588));
4861
4862         /* Enable timestamping of received PTP packets. */
4863         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4864         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4865         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4866
4867         /* Enable Timestamping of transmitted PTP packets. */
4868         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4869         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4870         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4871
4872         return 0;
4873 }
4874
4875 static int
4876 igb_timesync_disable(struct rte_eth_dev *dev)
4877 {
4878         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4879         uint32_t tsync_ctl;
4880
4881         /* Disable timestamping of transmitted PTP packets. */
4882         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4883         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4884         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4885
4886         /* Disable timestamping of received PTP packets. */
4887         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4888         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4889         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4890
4891         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4892         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4893
4894         /* Stop incrementating the System Time registers. */
4895         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4896
4897         return 0;
4898 }
4899
4900 static int
4901 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4902                                struct timespec *timestamp,
4903                                uint32_t flags __rte_unused)
4904 {
4905         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4906         struct e1000_adapter *adapter =
4907                         (struct e1000_adapter *)dev->data->dev_private;
4908         uint32_t tsync_rxctl;
4909         uint64_t rx_tstamp_cycles;
4910         uint64_t ns;
4911
4912         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4913         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4914                 return -EINVAL;
4915
4916         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4917         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4918         *timestamp = rte_ns_to_timespec(ns);
4919
4920         return  0;
4921 }
4922
4923 static int
4924 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4925                                struct timespec *timestamp)
4926 {
4927         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4928         struct e1000_adapter *adapter =
4929                         (struct e1000_adapter *)dev->data->dev_private;
4930         uint32_t tsync_txctl;
4931         uint64_t tx_tstamp_cycles;
4932         uint64_t ns;
4933
4934         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4935         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4936                 return -EINVAL;
4937
4938         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4939         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4940         *timestamp = rte_ns_to_timespec(ns);
4941
4942         return  0;
4943 }
4944
4945 static int
4946 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4947 {
4948         int count = 0;
4949         int g_ind = 0;
4950         const struct reg_info *reg_group;
4951
4952         while ((reg_group = igb_regs[g_ind++]))
4953                 count += igb_reg_group_count(reg_group);
4954
4955         return count;
4956 }
4957
4958 static int
4959 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4960 {
4961         int count = 0;
4962         int g_ind = 0;
4963         const struct reg_info *reg_group;
4964
4965         while ((reg_group = igbvf_regs[g_ind++]))
4966                 count += igb_reg_group_count(reg_group);
4967
4968         return count;
4969 }
4970
4971 static int
4972 eth_igb_get_regs(struct rte_eth_dev *dev,
4973         struct rte_dev_reg_info *regs)
4974 {
4975         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4976         uint32_t *data = regs->data;
4977         int g_ind = 0;
4978         int count = 0;
4979         const struct reg_info *reg_group;
4980
4981         if (data == NULL) {
4982                 regs->length = eth_igb_get_reg_length(dev);
4983                 regs->width = sizeof(uint32_t);
4984                 return 0;
4985         }
4986
4987         /* Support only full register dump */
4988         if ((regs->length == 0) ||
4989             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4990                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4991                         hw->device_id;
4992                 while ((reg_group = igb_regs[g_ind++]))
4993                         count += igb_read_regs_group(dev, &data[count],
4994                                                         reg_group);
4995                 return 0;
4996         }
4997
4998         return -ENOTSUP;
4999 }
5000
5001 static int
5002 igbvf_get_regs(struct rte_eth_dev *dev,
5003         struct rte_dev_reg_info *regs)
5004 {
5005         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5006         uint32_t *data = regs->data;
5007         int g_ind = 0;
5008         int count = 0;
5009         const struct reg_info *reg_group;
5010
5011         if (data == NULL) {
5012                 regs->length = igbvf_get_reg_length(dev);
5013                 regs->width = sizeof(uint32_t);
5014                 return 0;
5015         }
5016
5017         /* Support only full register dump */
5018         if ((regs->length == 0) ||
5019             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5020                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5021                         hw->device_id;
5022                 while ((reg_group = igbvf_regs[g_ind++]))
5023                         count += igb_read_regs_group(dev, &data[count],
5024                                                         reg_group);
5025                 return 0;
5026         }
5027
5028         return -ENOTSUP;
5029 }
5030
5031 static int
5032 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5033 {
5034         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5035
5036         /* Return unit is byte count */
5037         return hw->nvm.word_size * 2;
5038 }
5039
5040 static int
5041 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5042         struct rte_dev_eeprom_info *in_eeprom)
5043 {
5044         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5045         struct e1000_nvm_info *nvm = &hw->nvm;
5046         uint16_t *data = in_eeprom->data;
5047         int first, length;
5048
5049         first = in_eeprom->offset >> 1;
5050         length = in_eeprom->length >> 1;
5051         if ((first >= hw->nvm.word_size) ||
5052             ((first + length) >= hw->nvm.word_size))
5053                 return -EINVAL;
5054
5055         in_eeprom->magic = hw->vendor_id |
5056                 ((uint32_t)hw->device_id << 16);
5057
5058         if ((nvm->ops.read) == NULL)
5059                 return -ENOTSUP;
5060
5061         return nvm->ops.read(hw, first, length, data);
5062 }
5063
5064 static int
5065 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5066         struct rte_dev_eeprom_info *in_eeprom)
5067 {
5068         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5069         struct e1000_nvm_info *nvm = &hw->nvm;
5070         uint16_t *data = in_eeprom->data;
5071         int first, length;
5072
5073         first = in_eeprom->offset >> 1;
5074         length = in_eeprom->length >> 1;
5075         if ((first >= hw->nvm.word_size) ||
5076             ((first + length) >= hw->nvm.word_size))
5077                 return -EINVAL;
5078
5079         in_eeprom->magic = (uint32_t)hw->vendor_id |
5080                 ((uint32_t)hw->device_id << 16);
5081
5082         if ((nvm->ops.write) == NULL)
5083                 return -ENOTSUP;
5084         return nvm->ops.write(hw,  first, length, data);
5085 }
5086
5087 static int
5088 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5089 {
5090         struct e1000_hw *hw =
5091                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5092         uint32_t mask = 1 << queue_id;
5093
5094         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5095         E1000_WRITE_FLUSH(hw);
5096
5097         return 0;
5098 }
5099
5100 static int
5101 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5102 {
5103         struct e1000_hw *hw =
5104                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5105         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5106         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5107         uint32_t mask = 1 << queue_id;
5108         uint32_t regval;
5109
5110         regval = E1000_READ_REG(hw, E1000_EIMS);
5111         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5112         E1000_WRITE_FLUSH(hw);
5113
5114         rte_intr_enable(intr_handle);
5115
5116         return 0;
5117 }
5118
5119 static void
5120 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5121                    uint8_t index, uint8_t offset)
5122 {
5123         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5124
5125         /* clear bits */
5126         val &= ~((uint32_t)0xFF << offset);
5127
5128         /* write vector and valid bit */
5129         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5130
5131         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5132 }
5133
5134 static void
5135 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5136                            uint8_t queue, uint8_t msix_vector)
5137 {
5138         uint32_t tmp = 0;
5139
5140         if (hw->mac.type == e1000_82575) {
5141                 if (direction == 0)
5142                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5143                 else if (direction == 1)
5144                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5145                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5146         } else if (hw->mac.type == e1000_82576) {
5147                 if ((direction == 0) || (direction == 1))
5148                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5149                                            ((queue & 0x8) << 1) +
5150                                            8 * direction);
5151         } else if ((hw->mac.type == e1000_82580) ||
5152                         (hw->mac.type == e1000_i350) ||
5153                         (hw->mac.type == e1000_i354) ||
5154                         (hw->mac.type == e1000_i210) ||
5155                         (hw->mac.type == e1000_i211)) {
5156                 if ((direction == 0) || (direction == 1))
5157                         eth_igb_write_ivar(hw, msix_vector,
5158                                            queue >> 1,
5159                                            ((queue & 0x1) << 4) +
5160                                            8 * direction);
5161         }
5162 }
5163
5164 /* Sets up the hardware to generate MSI-X interrupts properly
5165  * @hw
5166  *  board private structure
5167  */
5168 static void
5169 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5170 {
5171         int queue_id;
5172         uint32_t tmpval, regval, intr_mask;
5173         struct e1000_hw *hw =
5174                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5175         uint32_t vec = E1000_MISC_VEC_ID;
5176         uint32_t base = E1000_MISC_VEC_ID;
5177         uint32_t misc_shift = 0;
5178         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5179         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5180
5181         /* won't configure msix register if no mapping is done
5182          * between intr vector and event fd
5183          */
5184         if (!rte_intr_dp_is_en(intr_handle))
5185                 return;
5186
5187         if (rte_intr_allow_others(intr_handle)) {
5188                 vec = base = E1000_RX_VEC_START;
5189                 misc_shift = 1;
5190         }
5191
5192         /* set interrupt vector for other causes */
5193         if (hw->mac.type == e1000_82575) {
5194                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5195                 /* enable MSI-X PBA support */
5196                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5197
5198                 /* Auto-Mask interrupts upon ICR read */
5199                 tmpval |= E1000_CTRL_EXT_EIAME;
5200                 tmpval |= E1000_CTRL_EXT_IRCA;
5201
5202                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5203
5204                 /* enable msix_other interrupt */
5205                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5206                 regval = E1000_READ_REG(hw, E1000_EIAC);
5207                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5208                 regval = E1000_READ_REG(hw, E1000_EIAM);
5209                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5210         } else if ((hw->mac.type == e1000_82576) ||
5211                         (hw->mac.type == e1000_82580) ||
5212                         (hw->mac.type == e1000_i350) ||
5213                         (hw->mac.type == e1000_i354) ||
5214                         (hw->mac.type == e1000_i210) ||
5215                         (hw->mac.type == e1000_i211)) {
5216                 /* turn on MSI-X capability first */
5217                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5218                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5219                                         E1000_GPIE_NSICR);
5220                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5221                         misc_shift;
5222                 regval = E1000_READ_REG(hw, E1000_EIAC);
5223                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5224
5225                 /* enable msix_other interrupt */
5226                 regval = E1000_READ_REG(hw, E1000_EIMS);
5227                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5228                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5229                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5230         }
5231
5232         /* use EIAM to auto-mask when MSI-X interrupt
5233          * is asserted, this saves a register write for every interrupt
5234          */
5235         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5236                 misc_shift;
5237         regval = E1000_READ_REG(hw, E1000_EIAM);
5238         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5239
5240         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5241                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5242                 intr_handle->intr_vec[queue_id] = vec;
5243                 if (vec < base + intr_handle->nb_efd - 1)
5244                         vec++;
5245         }
5246
5247         E1000_WRITE_FLUSH(hw);
5248 }
5249
5250 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd.pci_drv);
5251 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5252 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio");
5253 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd.pci_drv);
5254 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5255 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio");