drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64
  65 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  66 #define IGB_DEFAULT_RX_HTHRESH      8
  67 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  68
  69 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  70 #define IGB_DEFAULT_TX_HTHRESH      1
  71 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  72
  73 #define IGB_HKEY_MAX_INDEX 10
  74
  75 /* Bit shift and mask */
  76 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  77 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  78 #define IGB_8_BIT_WIDTH  CHAR_BIT
  79 #define IGB_8_BIT_MASK   UINT8_MAX
  80
  81 /* Additional timesync values. */
  82 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  83 #define E1000_ETQF_FILTER_1588       3
  84 #define IGB_82576_TSYNC_SHIFT        16
  85 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  86 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  88
  89 #define E1000_VTIVAR_MISC                0x01740
  90 #define E1000_VTIVAR_MISC_MASK           0xFF
  91 #define E1000_VTIVAR_VALID               0x80
  92 #define E1000_VTIVAR_MISC_MAILBOX        0
  93 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  94
  95 /* External VLAN Enable bit mask */
  96 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  97
  98 /* External VLAN Ether Type bit mask and shift */
  99 #define E1000_VET_VET_EXT            0xFFFF0000
 100 #define E1000_VET_VET_EXT_SHIFT      16
 101
 102 static int  eth_igb_configure(struct rte_eth_dev *dev);
 103 static int  eth_igb_start(struct rte_eth_dev *dev);
 104 static void eth_igb_stop(struct rte_eth_dev *dev);
 105 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 107 static void eth_igb_close(struct rte_eth_dev *dev);
 108 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 110 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 112 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 113                                 int wait_to_complete);
 114 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 115                                 struct rte_eth_stats *rte_stats);
 116 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 117                               struct rte_eth_xstat *xstats, unsigned n);
 118 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 119                                     struct rte_eth_xstat_name *xstats_names,
 120                                     unsigned limit);
 121 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 122 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 123 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 124                               struct rte_eth_dev_info *dev_info);
 125 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 126 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 127                                 struct rte_eth_dev_info *dev_info);
 128 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 129                                 struct rte_eth_fc_conf *fc_conf);
 130 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 131                                 struct rte_eth_fc_conf *fc_conf);
 132 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 133 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 134 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 135 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 136                                     struct rte_intr_handle *handle);
 137 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 138                                                         void *param);
 139 static int  igb_hardware_init(struct e1000_hw *hw);
 140 static void igb_hw_control_acquire(struct e1000_hw *hw);
 141 static void igb_hw_control_release(struct e1000_hw *hw);
 142 static void igb_init_manageability(struct e1000_hw *hw);
 143 static void igb_release_manageability(struct e1000_hw *hw);
 144
 145 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 146
 147 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 148                 uint16_t vlan_id, int on);
 149 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 150                                  enum rte_vlan_type vlan_type,
 151                                  uint16_t tpid_id);
 152 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 153
 154 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 155 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 156 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 157 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 158 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 159 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 160
 161 static int eth_igb_led_on(struct rte_eth_dev *dev);
 162 static int eth_igb_led_off(struct rte_eth_dev *dev);
 163
 164 static void igb_intr_disable(struct e1000_hw *hw);
 165 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 166 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 167                 struct ether_addr *mac_addr,
 168                 uint32_t index, uint32_t pool);
 169 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 170 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 171                 struct ether_addr *addr);
 172
 173 static void igbvf_intr_disable(struct e1000_hw *hw);
 174 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 175 static int igbvf_dev_start(struct rte_eth_dev *dev);
 176 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 177 static void igbvf_dev_close(struct rte_eth_dev *dev);
 178 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 179 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 180 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 181 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 182 static int eth_igbvf_link_update(struct e1000_hw *hw);
 183 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 184                                 struct rte_eth_stats *rte_stats);
 185 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 186                                 struct rte_eth_xstat *xstats, unsigned n);
 187 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 188                                       struct rte_eth_xstat_name *xstats_names,
 189                                       unsigned limit);
 190 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 191 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 192                 uint16_t vlan_id, int on);
 193 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 194 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 195 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 196                 struct ether_addr *addr);
 197 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 198 static int igbvf_get_regs(struct rte_eth_dev *dev,
 199                 struct rte_dev_reg_info *regs);
 200
 201 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 202                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 203                                    uint16_t reta_size);
 204 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 205                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 206                                   uint16_t reta_size);
 207
 208 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 209                         struct rte_eth_syn_filter *filter,
 210                         bool add);
 211 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 212                         struct rte_eth_syn_filter *filter);
 213 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 214                         enum rte_filter_op filter_op,
 215                         void *arg);
 216 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 217                         struct rte_eth_ntuple_filter *ntuple_filter);
 218 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 219                         struct rte_eth_ntuple_filter *ntuple_filter);
 220 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 221                         struct rte_eth_flex_filter *filter,
 222                         bool add);
 223 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 224                         struct rte_eth_flex_filter *filter);
 225 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 226                         enum rte_filter_op filter_op,
 227                         void *arg);
 228 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 229                         struct rte_eth_ntuple_filter *ntuple_filter);
 230 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 231                         struct rte_eth_ntuple_filter *ntuple_filter);
 232 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 233                         struct rte_eth_ntuple_filter *filter,
 234                         bool add);
 235 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 236                         struct rte_eth_ntuple_filter *filter);
 237 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 238                                 enum rte_filter_op filter_op,
 239                                 void *arg);
 240 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 241                         struct rte_eth_ethertype_filter *filter,
 242                         bool add);
 243 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 244                                 enum rte_filter_op filter_op,
 245                                 void *arg);
 246 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 247                         struct rte_eth_ethertype_filter *filter);
 248 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 249                      enum rte_filter_type filter_type,
 250                      enum rte_filter_op filter_op,
 251                      void *arg);
 252 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 253 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 254                 struct rte_dev_reg_info *regs);
 255 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 256 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 257                 struct rte_dev_eeprom_info *eeprom);
 258 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 259                 struct rte_dev_eeprom_info *eeprom);
 260 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 261                                     struct ether_addr *mc_addr_set,
 262                                     uint32_t nb_mc_addr);
 263 static int igb_timesync_enable(struct rte_eth_dev *dev);
 264 static int igb_timesync_disable(struct rte_eth_dev *dev);
 265 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 266                                           struct timespec *timestamp,
 267                                           uint32_t flags);
 268 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 269                                           struct timespec *timestamp);
 270 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 271 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 272                                   struct timespec *timestamp);
 273 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 274                                    const struct timespec *timestamp);
 275 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 276                                         uint16_t queue_id);
 277 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 278                                          uint16_t queue_id);
 279 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 280                                        uint8_t queue, uint8_t msix_vector);
 281 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 282                                uint8_t index, uint8_t offset);
 283 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 284 static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
 285                                         void *param);
 286 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 287
 288 /*
 289  * Define VF Stats MACRO for Non "cleared on read" register
 290  */
 291 #define UPDATE_VF_STAT(reg, last, cur)            \
 292 {                                                 \
 293         u32 latest = E1000_READ_REG(hw, reg);     \
 294         cur += (latest - last) & UINT_MAX;        \
 295         last = latest;                            \
 296 }
 297
 298 #define IGB_FC_PAUSE_TIME 0x0680
 299 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 300 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 301
 302 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 303
 304 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 305
 306 /*
 307  * The set of PCI devices this driver supports
 308  */
 309 static const struct rte_pci_id pci_id_igb_map[] = {
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 318
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 322
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 329
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 347         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 348         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 349         { .vendor_id = 0, /* sentinel */ },
 350 };
 351
 352 /*
 353  * The set of PCI devices this driver supports (for 82576&I350 VF)
 354  */
 355 static const struct rte_pci_id pci_id_igbvf_map[] = {
 356         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 357         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 358         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 359         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 360         { .vendor_id = 0, /* sentinel */ },
 361 };
 362
 363 static const struct rte_eth_desc_lim rx_desc_lim = {
 364         .nb_max = E1000_MAX_RING_DESC,
 365         .nb_min = E1000_MIN_RING_DESC,
 366         .nb_align = IGB_RXD_ALIGN,
 367 };
 368
 369 static const struct rte_eth_desc_lim tx_desc_lim = {
 370         .nb_max = E1000_MAX_RING_DESC,
 371         .nb_min = E1000_MIN_RING_DESC,
 372         .nb_align = IGB_RXD_ALIGN,
 373 };
 374
 375 static const struct eth_dev_ops eth_igb_ops = {
 376         .dev_configure        = eth_igb_configure,
 377         .dev_start            = eth_igb_start,
 378         .dev_stop             = eth_igb_stop,
 379         .dev_set_link_up      = eth_igb_dev_set_link_up,
 380         .dev_set_link_down    = eth_igb_dev_set_link_down,
 381         .dev_close            = eth_igb_close,
 382         .promiscuous_enable   = eth_igb_promiscuous_enable,
 383         .promiscuous_disable  = eth_igb_promiscuous_disable,
 384         .allmulticast_enable  = eth_igb_allmulticast_enable,
 385         .allmulticast_disable = eth_igb_allmulticast_disable,
 386         .link_update          = eth_igb_link_update,
 387         .stats_get            = eth_igb_stats_get,
 388         .xstats_get           = eth_igb_xstats_get,
 389         .xstats_get_names     = eth_igb_xstats_get_names,
 390         .stats_reset          = eth_igb_stats_reset,
 391         .xstats_reset         = eth_igb_xstats_reset,
 392         .dev_infos_get        = eth_igb_infos_get,
 393         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 394         .mtu_set              = eth_igb_mtu_set,
 395         .vlan_filter_set      = eth_igb_vlan_filter_set,
 396         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 397         .vlan_offload_set     = eth_igb_vlan_offload_set,
 398         .rx_queue_setup       = eth_igb_rx_queue_setup,
 399         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 400         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 401         .rx_queue_release     = eth_igb_rx_queue_release,
 402         .rx_queue_count       = eth_igb_rx_queue_count,
 403         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 404         .tx_queue_setup       = eth_igb_tx_queue_setup,
 405         .tx_queue_release     = eth_igb_tx_queue_release,
 406         .dev_led_on           = eth_igb_led_on,
 407         .dev_led_off          = eth_igb_led_off,
 408         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 409         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 410         .mac_addr_add         = eth_igb_rar_set,
 411         .mac_addr_remove      = eth_igb_rar_clear,
 412         .mac_addr_set         = eth_igb_default_mac_addr_set,
 413         .reta_update          = eth_igb_rss_reta_update,
 414         .reta_query           = eth_igb_rss_reta_query,
 415         .rss_hash_update      = eth_igb_rss_hash_update,
 416         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 417         .filter_ctrl          = eth_igb_filter_ctrl,
 418         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 419         .rxq_info_get         = igb_rxq_info_get,
 420         .txq_info_get         = igb_txq_info_get,
 421         .timesync_enable      = igb_timesync_enable,
 422         .timesync_disable     = igb_timesync_disable,
 423         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 424         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 425         .get_reg              = eth_igb_get_regs,
 426         .get_eeprom_length    = eth_igb_get_eeprom_length,
 427         .get_eeprom           = eth_igb_get_eeprom,
 428         .set_eeprom           = eth_igb_set_eeprom,
 429         .timesync_adjust_time = igb_timesync_adjust_time,
 430         .timesync_read_time   = igb_timesync_read_time,
 431         .timesync_write_time  = igb_timesync_write_time,
 432 };
 433
 434 /*
 435  * dev_ops for virtual function, bare necessities for basic vf
 436  * operation have been implemented
 437  */
 438 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 439         .dev_configure        = igbvf_dev_configure,
 440         .dev_start            = igbvf_dev_start,
 441         .dev_stop             = igbvf_dev_stop,
 442         .dev_close            = igbvf_dev_close,
 443         .promiscuous_enable   = igbvf_promiscuous_enable,
 444         .promiscuous_disable  = igbvf_promiscuous_disable,
 445         .allmulticast_enable  = igbvf_allmulticast_enable,
 446         .allmulticast_disable = igbvf_allmulticast_disable,
 447         .link_update          = eth_igb_link_update,
 448         .stats_get            = eth_igbvf_stats_get,
 449         .xstats_get           = eth_igbvf_xstats_get,
 450         .xstats_get_names     = eth_igbvf_xstats_get_names,
 451         .stats_reset          = eth_igbvf_stats_reset,
 452         .xstats_reset         = eth_igbvf_stats_reset,
 453         .vlan_filter_set      = igbvf_vlan_filter_set,
 454         .dev_infos_get        = eth_igbvf_infos_get,
 455         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 456         .rx_queue_setup       = eth_igb_rx_queue_setup,
 457         .rx_queue_release     = eth_igb_rx_queue_release,
 458         .tx_queue_setup       = eth_igb_tx_queue_setup,
 459         .tx_queue_release     = eth_igb_tx_queue_release,
 460         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 461         .rxq_info_get         = igb_rxq_info_get,
 462         .txq_info_get         = igb_txq_info_get,
 463         .mac_addr_set         = igbvf_default_mac_addr_set,
 464         .get_reg              = igbvf_get_regs,
 465 };
 466
 467 /* store statistics names and its offset in stats structure */
 468 struct rte_igb_xstats_name_off {
 469         char name[RTE_ETH_XSTATS_NAME_SIZE];
 470         unsigned offset;
 471 };
 472
 473 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 474         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 475         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 476         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 477         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 478         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 479         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 480         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 481                 ecol)},
 482         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 483         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 484         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 485         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 486         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 487         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 488         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 489         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 490         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 491         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 492         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 493                 fcruc)},
 494         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 495         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 496         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 497         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 498         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 499                 prc1023)},
 500         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 501                 prc1522)},
 502         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 503         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 504         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 505         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 506         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 507         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 508         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 509         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 510         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 511         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 512         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 513         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 514         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 515         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 516         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 517         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 518         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 519         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 520                 ptc1023)},
 521         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 522                 ptc1522)},
 523         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 524         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 525         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 526         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 527         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 528         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 529         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 530
 531         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 532 };
 533
 534 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 535                 sizeof(rte_igb_stats_strings[0]))
 536
 537 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 538         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 539         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 540         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 541         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 542         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 543 };
 544
 545 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 546                 sizeof(rte_igbvf_stats_strings[0]))
 547
 548 /**
 549  * Atomically reads the link status information from global
 550  * structure rte_eth_dev.
 551  *
 552  * @param dev
 553  *   - Pointer to the structure rte_eth_dev to read from.
 554  *   - Pointer to the buffer to be saved with the link status.
 555  *
 556  * @return
 557  *   - On success, zero.
 558  *   - On failure, negative value.
 559  */
 560 static inline int
 561 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 562                                 struct rte_eth_link *link)
 563 {
 564         struct rte_eth_link *dst = link;
 565         struct rte_eth_link *src = &(dev->data->dev_link);
 566
 567         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 568                                         *(uint64_t *)src) == 0)
 569                 return -1;
 570
 571         return 0;
 572 }
 573
 574 /**
 575  * Atomically writes the link status information into global
 576  * structure rte_eth_dev.
 577  *
 578  * @param dev
 579  *   - Pointer to the structure rte_eth_dev to read from.
 580  *   - Pointer to the buffer to be saved with the link status.
 581  *
 582  * @return
 583  *   - On success, zero.
 584  *   - On failure, negative value.
 585  */
 586 static inline int
 587 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 588                                 struct rte_eth_link *link)
 589 {
 590         struct rte_eth_link *dst = &(dev->data->dev_link);
 591         struct rte_eth_link *src = link;
 592
 593         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 594                                         *(uint64_t *)src) == 0)
 595                 return -1;
 596
 597         return 0;
 598 }
 599
 600 static inline void
 601 igb_intr_enable(struct rte_eth_dev *dev)
 602 {
 603         struct e1000_interrupt *intr =
 604                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 605         struct e1000_hw *hw =
 606                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 607
 608         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 609         E1000_WRITE_FLUSH(hw);
 610 }
 611
 612 static void
 613 igb_intr_disable(struct e1000_hw *hw)
 614 {
 615         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 616         E1000_WRITE_FLUSH(hw);
 617 }
 618
 619 static inline void
 620 igbvf_intr_enable(struct rte_eth_dev *dev)
 621 {
 622         struct e1000_hw *hw =
 623                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 624
 625         /* only for mailbox */
 626         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 627         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 628         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 629         E1000_WRITE_FLUSH(hw);
 630 }
 631
 632 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 633 static void
 634 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 635 {
 636         uint32_t tmp = 0;
 637
 638         /* mailbox */
 639         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 640         tmp |= E1000_VTIVAR_VALID;
 641         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 642 }
 643
 644 static void
 645 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 646 {
 647         struct e1000_hw *hw =
 648                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 649
 650         /* Configure VF other cause ivar */
 651         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 652 }
 653
 654 static inline int32_t
 655 igb_pf_reset_hw(struct e1000_hw *hw)
 656 {
 657         uint32_t ctrl_ext;
 658         int32_t status;
 659
 660         status = e1000_reset_hw(hw);
 661
 662         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 663         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 664         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 665         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 666         E1000_WRITE_FLUSH(hw);
 667
 668         return status;
 669 }
 670
 671 static void
 672 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 673 {
 674         struct e1000_hw *hw =
 675                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 676
 677
 678         hw->vendor_id = pci_dev->id.vendor_id;
 679         hw->device_id = pci_dev->id.device_id;
 680         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 681         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 682
 683         e1000_set_mac_type(hw);
 684
 685         /* need to check if it is a vf device below */
 686 }
 687
 688 static int
 689 igb_reset_swfw_lock(struct e1000_hw *hw)
 690 {
 691         int ret_val;
 692
 693         /*
 694          * Do mac ops initialization manually here, since we will need
 695          * some function pointers set by this call.
 696          */
 697         ret_val = e1000_init_mac_params(hw);
 698         if (ret_val)
 699                 return ret_val;
 700
 701         /*
 702          * SMBI lock should not fail in this early stage. If this is the case,
 703          * it is due to an improper exit of the application.
 704          * So force the release of the faulty lock.
 705          */
 706         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 707                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 708         }
 709         e1000_put_hw_semaphore_generic(hw);
 710
 711         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 712                 uint16_t mask;
 713
 714                 /*
 715                  * Phy lock should not fail in this early stage. If this is the case,
 716                  * it is due to an improper exit of the application.
 717                  * So force the release of the faulty lock.
 718                  */
 719                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 720                 if (hw->bus.func > E1000_FUNC_1)
 721                         mask <<= 2;
 722                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 723                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 724                                     hw->bus.func);
 725                 }
 726                 hw->mac.ops.release_swfw_sync(hw, mask);
 727
 728                 /*
 729                  * This one is more tricky since it is common to all ports; but
 730                  * swfw_sync retries last long enough (1s) to be almost sure that if
 731                  * lock can not be taken it is due to an improper lock of the
 732                  * semaphore.
 733                  */
 734                 mask = E1000_SWFW_EEP_SM;
 735                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 736                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 737                 }
 738                 hw->mac.ops.release_swfw_sync(hw, mask);
 739         }
 740
 741         return E1000_SUCCESS;
 742 }
 743
 744 static int
 745 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 746 {
 747         int error = 0;
 748         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
 749         struct e1000_hw *hw =
 750                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 751         struct e1000_vfta * shadow_vfta =
 752                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 753         struct e1000_filter_info *filter_info =
 754                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 755         struct e1000_adapter *adapter =
 756                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 757
 758         uint32_t ctrl_ext;
 759
 760         eth_dev->dev_ops = &eth_igb_ops;
 761         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 762         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 763
 764         /* for secondary processes, we don't initialise any further as primary
 765          * has already done this work. Only check we don't need a different
 766          * RX function */
 767         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 768                 if (eth_dev->data->scattered_rx)
 769                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 770                 return 0;
 771         }
 772
 773         rte_eth_copy_pci_info(eth_dev, pci_dev);
 774
 775         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 776
 777         igb_identify_hardware(eth_dev, pci_dev);
 778         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 779                 error = -EIO;
 780                 goto err_late;
 781         }
 782
 783         e1000_get_bus_info(hw);
 784
 785         /* Reset any pending lock */
 786         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 787                 error = -EIO;
 788                 goto err_late;
 789         }
 790
 791         /* Finish initialization */
 792         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 793                 error = -EIO;
 794                 goto err_late;
 795         }
 796
 797         hw->mac.autoneg = 1;
 798         hw->phy.autoneg_wait_to_complete = 0;
 799         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 800
 801         /* Copper options */
 802         if (hw->phy.media_type == e1000_media_type_copper) {
 803                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 804                 hw->phy.disable_polarity_correction = 0;
 805                 hw->phy.ms_type = e1000_ms_hw_default;
 806         }
 807
 808         /*
 809          * Start from a known state, this is important in reading the nvm
 810          * and mac from that.
 811          */
 812         igb_pf_reset_hw(hw);
 813
 814         /* Make sure we have a good EEPROM before we read from it */
 815         if (e1000_validate_nvm_checksum(hw) < 0) {
 816                 /*
 817                  * Some PCI-E parts fail the first check due to
 818                  * the link being in sleep state, call it again,
 819                  * if it fails a second time its a real issue.
 820                  */
 821                 if (e1000_validate_nvm_checksum(hw) < 0) {
 822                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 823                         error = -EIO;
 824                         goto err_late;
 825                 }
 826         }
 827
 828         /* Read the permanent MAC address out of the EEPROM */
 829         if (e1000_read_mac_addr(hw) != 0) {
 830                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 831                 error = -EIO;
 832                 goto err_late;
 833         }
 834
 835         /* Allocate memory for storing MAC addresses */
 836         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 837                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 838         if (eth_dev->data->mac_addrs == NULL) {
 839                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 840                                                 "store MAC addresses",
 841                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 842                 error = -ENOMEM;
 843                 goto err_late;
 844         }
 845
 846         /* Copy the permanent MAC address */
 847         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 848
 849         /* initialize the vfta */
 850         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 851
 852         /* Now initialize the hardware */
 853         if (igb_hardware_init(hw) != 0) {
 854                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 855                 rte_free(eth_dev->data->mac_addrs);
 856                 eth_dev->data->mac_addrs = NULL;
 857                 error = -ENODEV;
 858                 goto err_late;
 859         }
 860         hw->mac.get_link_status = 1;
 861         adapter->stopped = 0;
 862
 863         /* Indicate SOL/IDER usage */
 864         if (e1000_check_reset_block(hw) < 0) {
 865                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 866                                         "SOL/IDER session");
 867         }
 868
 869         /* initialize PF if max_vfs not zero */
 870         igb_pf_host_init(eth_dev);
 871
 872         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 873         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 874         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 875         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 876         E1000_WRITE_FLUSH(hw);
 877
 878         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 879                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 880                      pci_dev->id.device_id);
 881
 882         rte_intr_callback_register(&pci_dev->intr_handle,
 883                                    eth_igb_interrupt_handler,
 884                                    (void *)eth_dev);
 885
 886         /* enable uio/vfio intr/eventfd mapping */
 887         rte_intr_enable(&pci_dev->intr_handle);
 888
 889         /* enable support intr */
 890         igb_intr_enable(eth_dev);
 891
 892         TAILQ_INIT(&filter_info->flex_list);
 893         filter_info->flex_mask = 0;
 894         TAILQ_INIT(&filter_info->twotuple_list);
 895         filter_info->twotuple_mask = 0;
 896         TAILQ_INIT(&filter_info->fivetuple_list);
 897         filter_info->fivetuple_mask = 0;
 898
 899         return 0;
 900
 901 err_late:
 902         igb_hw_control_release(hw);
 903
 904         return error;
 905 }
 906
 907 static int
 908 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 909 {
 910         struct rte_pci_device *pci_dev;
 911         struct rte_intr_handle *intr_handle;
 912         struct e1000_hw *hw;
 913         struct e1000_adapter *adapter =
 914                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 915
 916         PMD_INIT_FUNC_TRACE();
 917
 918         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 919                 return -EPERM;
 920
 921         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 922         pci_dev = E1000_DEV_TO_PCI(eth_dev);
 923         intr_handle = &pci_dev->intr_handle;
 924
 925         if (adapter->stopped == 0)
 926                 eth_igb_close(eth_dev);
 927
 928         eth_dev->dev_ops = NULL;
 929         eth_dev->rx_pkt_burst = NULL;
 930         eth_dev->tx_pkt_burst = NULL;
 931
 932         /* Reset any pending lock */
 933         igb_reset_swfw_lock(hw);
 934
 935         rte_free(eth_dev->data->mac_addrs);
 936         eth_dev->data->mac_addrs = NULL;
 937
 938         /* uninitialize PF if max_vfs not zero */
 939         igb_pf_host_uninit(eth_dev);
 940
 941         /* disable uio intr before callback unregister */
 942         rte_intr_disable(intr_handle);
 943         rte_intr_callback_unregister(intr_handle,
 944                                      eth_igb_interrupt_handler, eth_dev);
 945
 946         return 0;
 947 }
 948
 949 /*
 950  * Virtual Function device init
 951  */
 952 static int
 953 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 954 {
 955         struct rte_pci_device *pci_dev;
 956         struct rte_intr_handle *intr_handle;
 957         struct e1000_adapter *adapter =
 958                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 959         struct e1000_hw *hw =
 960                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 961         int diag;
 962         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 963
 964         PMD_INIT_FUNC_TRACE();
 965
 966         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 967         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 968         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 969
 970         /* for secondary processes, we don't initialise any further as primary
 971          * has already done this work. Only check we don't need a different
 972          * RX function */
 973         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 974                 if (eth_dev->data->scattered_rx)
 975                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 976                 return 0;
 977         }
 978
 979         pci_dev = E1000_DEV_TO_PCI(eth_dev);
 980         rte_eth_copy_pci_info(eth_dev, pci_dev);
 981
 982         hw->device_id = pci_dev->id.device_id;
 983         hw->vendor_id = pci_dev->id.vendor_id;
 984         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 985         adapter->stopped = 0;
 986
 987         /* Initialize the shared code (base driver) */
 988         diag = e1000_setup_init_funcs(hw, TRUE);
 989         if (diag != 0) {
 990                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 991                         diag);
 992                 return -EIO;
 993         }
 994
 995         /* init_mailbox_params */
 996         hw->mbx.ops.init_params(hw);
 997
 998         /* Disable the interrupts for VF */
 999         igbvf_intr_disable(hw);
1000
1001         diag = hw->mac.ops.reset_hw(hw);
1002
1003         /* Allocate memory for storing MAC addresses */
1004         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1005                 hw->mac.rar_entry_count, 0);
1006         if (eth_dev->data->mac_addrs == NULL) {
1007                 PMD_INIT_LOG(ERR,
1008                         "Failed to allocate %d bytes needed to store MAC "
1009                         "addresses",
1010                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1011                 return -ENOMEM;
1012         }
1013
1014         /* Generate a random MAC address, if none was assigned by PF. */
1015         if (is_zero_ether_addr(perm_addr)) {
1016                 eth_random_addr(perm_addr->addr_bytes);
1017                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1018                 if (diag) {
1019                         rte_free(eth_dev->data->mac_addrs);
1020                         eth_dev->data->mac_addrs = NULL;
1021                         return diag;
1022                 }
1023                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1024                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1025                              "%02x:%02x:%02x:%02x:%02x:%02x",
1026                              perm_addr->addr_bytes[0],
1027                              perm_addr->addr_bytes[1],
1028                              perm_addr->addr_bytes[2],
1029                              perm_addr->addr_bytes[3],
1030                              perm_addr->addr_bytes[4],
1031                              perm_addr->addr_bytes[5]);
1032         }
1033
1034         /* Copy the permanent MAC address */
1035         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1036                         &eth_dev->data->mac_addrs[0]);
1037
1038         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1039                      "mac.type=%s",
1040                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1041                      pci_dev->id.device_id, "igb_mac_82576_vf");
1042
1043         intr_handle = &pci_dev->intr_handle;
1044         rte_intr_callback_register(intr_handle,
1045                                    eth_igbvf_interrupt_handler, eth_dev);
1046
1047         return 0;
1048 }
1049
1050 static int
1051 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1052 {
1053         struct e1000_adapter *adapter =
1054                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1055         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
1056
1057         PMD_INIT_FUNC_TRACE();
1058
1059         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1060                 return -EPERM;
1061
1062         if (adapter->stopped == 0)
1063                 igbvf_dev_close(eth_dev);
1064
1065         eth_dev->dev_ops = NULL;
1066         eth_dev->rx_pkt_burst = NULL;
1067         eth_dev->tx_pkt_burst = NULL;
1068
1069         rte_free(eth_dev->data->mac_addrs);
1070         eth_dev->data->mac_addrs = NULL;
1071
1072         /* disable uio intr before callback unregister */
1073         rte_intr_disable(&pci_dev->intr_handle);
1074         rte_intr_callback_unregister(&pci_dev->intr_handle,
1075                                      eth_igbvf_interrupt_handler,
1076                                      (void *)eth_dev);
1077
1078         return 0;
1079 }
1080
1081 static struct eth_driver rte_igb_pmd = {
1082         .pci_drv = {
1083                 .id_table = pci_id_igb_map,
1084                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1085                         RTE_PCI_DRV_DETACHABLE,
1086                 .probe = rte_eth_dev_pci_probe,
1087                 .remove = rte_eth_dev_pci_remove,
1088         },
1089         .eth_dev_init = eth_igb_dev_init,
1090         .eth_dev_uninit = eth_igb_dev_uninit,
1091         .dev_private_size = sizeof(struct e1000_adapter),
1092 };
1093
1094 /*
1095  * virtual function driver struct
1096  */
1097 static struct eth_driver rte_igbvf_pmd = {
1098         .pci_drv = {
1099                 .id_table = pci_id_igbvf_map,
1100                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1101                 .probe = rte_eth_dev_pci_probe,
1102                 .remove = rte_eth_dev_pci_remove,
1103         },
1104         .eth_dev_init = eth_igbvf_dev_init,
1105         .eth_dev_uninit = eth_igbvf_dev_uninit,
1106         .dev_private_size = sizeof(struct e1000_adapter),
1107 };
1108
1109 static void
1110 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1111 {
1112         struct e1000_hw *hw =
1113                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1114         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1115         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1116         rctl |= E1000_RCTL_VFE;
1117         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1118 }
1119
1120 static int
1121 igb_check_mq_mode(struct rte_eth_dev *dev)
1122 {
1123         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1124         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1125         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1126         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1127
1128         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1129             tx_mq_mode == ETH_MQ_TX_DCB ||
1130             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1131                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1132                 return -EINVAL;
1133         }
1134         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1135                 /* Check multi-queue mode.
1136                  * To no break software we accept ETH_MQ_RX_NONE as this might
1137                  * be used to turn off VLAN filter.
1138                  */
1139
1140                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1141                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1142                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1143                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1144                 } else {
1145                         /* Only support one queue on VFs.
1146                          * RSS together with SRIOV is not supported.
1147                          */
1148                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1149                                         " wrong mq_mode rx %d.",
1150                                         rx_mq_mode);
1151                         return -EINVAL;
1152                 }
1153                 /* TX mode is not used here, so mode might be ignored.*/
1154                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1155                         /* SRIOV only works in VMDq enable mode */
1156                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1157                                         " TX mode %d is not supported. "
1158                                         " Driver will behave as %d mode.",
1159                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1160                 }
1161
1162                 /* check valid queue number */
1163                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1164                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1165                                         " only support one queue on VFs.");
1166                         return -EINVAL;
1167                 }
1168         } else {
1169                 /* To no break software that set invalid mode, only display
1170                  * warning if invalid mode is used.
1171                  */
1172                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1173                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1174                     rx_mq_mode != ETH_MQ_RX_RSS) {
1175                         /* RSS together with VMDq not supported*/
1176                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1177                                      rx_mq_mode);
1178                         return -EINVAL;
1179                 }
1180
1181                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1182                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1183                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1184                                         " Due to txmode is meaningless in this"
1185                                         " driver, just ignore.",
1186                                         tx_mq_mode);
1187                 }
1188         }
1189         return 0;
1190 }
1191
1192 static int
1193 eth_igb_configure(struct rte_eth_dev *dev)
1194 {
1195         struct e1000_interrupt *intr =
1196                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1197         int ret;
1198
1199         PMD_INIT_FUNC_TRACE();
1200
1201         /* multipe queue mode checking */
1202         ret  = igb_check_mq_mode(dev);
1203         if (ret != 0) {
1204                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1205                             ret);
1206                 return ret;
1207         }
1208
1209         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1210         PMD_INIT_FUNC_TRACE();
1211
1212         return 0;
1213 }
1214
1215 static int
1216 eth_igb_start(struct rte_eth_dev *dev)
1217 {
1218         struct e1000_hw *hw =
1219                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1220         struct e1000_adapter *adapter =
1221                 E1000_DEV_PRIVATE(dev->data->dev_private);
1222         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1223         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1224         int ret, mask;
1225         uint32_t intr_vector = 0;
1226         uint32_t ctrl_ext;
1227         uint32_t *speeds;
1228         int num_speeds;
1229         bool autoneg;
1230
1231         PMD_INIT_FUNC_TRACE();
1232
1233         /* disable uio/vfio intr/eventfd mapping */
1234         rte_intr_disable(intr_handle);
1235
1236         /* Power up the phy. Needed to make the link go Up */
1237         eth_igb_dev_set_link_up(dev);
1238
1239         /*
1240          * Packet Buffer Allocation (PBA)
1241          * Writing PBA sets the receive portion of the buffer
1242          * the remainder is used for the transmit buffer.
1243          */
1244         if (hw->mac.type == e1000_82575) {
1245                 uint32_t pba;
1246
1247                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1248                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1249         }
1250
1251         /* Put the address into the Receive Address Array */
1252         e1000_rar_set(hw, hw->mac.addr, 0);
1253
1254         /* Initialize the hardware */
1255         if (igb_hardware_init(hw)) {
1256                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1257                 return -EIO;
1258         }
1259         adapter->stopped = 0;
1260
1261         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1262
1263         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1264         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1265         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1266         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1267         E1000_WRITE_FLUSH(hw);
1268
1269         /* configure PF module if SRIOV enabled */
1270         igb_pf_host_configure(dev);
1271
1272         /* check and configure queue intr-vector mapping */
1273         if ((rte_intr_cap_multiple(intr_handle) ||
1274              !RTE_ETH_DEV_SRIOV(dev).active) &&
1275             dev->data->dev_conf.intr_conf.rxq != 0) {
1276                 intr_vector = dev->data->nb_rx_queues;
1277                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1278                         return -1;
1279         }
1280
1281         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1282                 intr_handle->intr_vec =
1283                         rte_zmalloc("intr_vec",
1284                                     dev->data->nb_rx_queues * sizeof(int), 0);
1285                 if (intr_handle->intr_vec == NULL) {
1286                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1287                                      " intr_vec\n", dev->data->nb_rx_queues);
1288                         return -ENOMEM;
1289                 }
1290         }
1291
1292         /* confiugre msix for rx interrupt */
1293         eth_igb_configure_msix_intr(dev);
1294
1295         /* Configure for OS presence */
1296         igb_init_manageability(hw);
1297
1298         eth_igb_tx_init(dev);
1299
1300         /* This can fail when allocating mbufs for descriptor rings */
1301         ret = eth_igb_rx_init(dev);
1302         if (ret) {
1303                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1304                 igb_dev_clear_queues(dev);
1305                 return ret;
1306         }
1307
1308         e1000_clear_hw_cntrs_base_generic(hw);
1309
1310         /*
1311          * VLAN Offload Settings
1312          */
1313         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1314                         ETH_VLAN_EXTEND_MASK;
1315         eth_igb_vlan_offload_set(dev, mask);
1316
1317         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1318                 /* Enable VLAN filter since VMDq always use VLAN filter */
1319                 igb_vmdq_vlan_hw_filter_enable(dev);
1320         }
1321
1322         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1323                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1324                 (hw->mac.type == e1000_i211)) {
1325                 /* Configure EITR with the maximum possible value (0xFFFF) */
1326                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1327         }
1328
1329         /* Setup link speed and duplex */
1330         speeds = &dev->data->dev_conf.link_speeds;
1331         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1332                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1333                 hw->mac.autoneg = 1;
1334         } else {
1335                 num_speeds = 0;
1336                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1337
1338                 /* Reset */
1339                 hw->phy.autoneg_advertised = 0;
1340
1341                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1342                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1343                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1344                         num_speeds = -1;
1345                         goto error_invalid_config;
1346                 }
1347                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1348                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1349                         num_speeds++;
1350                 }
1351                 if (*speeds & ETH_LINK_SPEED_10M) {
1352                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1353                         num_speeds++;
1354                 }
1355                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1356                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1357                         num_speeds++;
1358                 }
1359                 if (*speeds & ETH_LINK_SPEED_100M) {
1360                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1361                         num_speeds++;
1362                 }
1363                 if (*speeds & ETH_LINK_SPEED_1G) {
1364                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1365                         num_speeds++;
1366                 }
1367                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1368                         goto error_invalid_config;
1369
1370                 /* Set/reset the mac.autoneg based on the link speed,
1371                  * fixed or not
1372                  */
1373                 if (!autoneg) {
1374                         hw->mac.autoneg = 0;
1375                         hw->mac.forced_speed_duplex =
1376                                         hw->phy.autoneg_advertised;
1377                 } else {
1378                         hw->mac.autoneg = 1;
1379                 }
1380         }
1381
1382         e1000_setup_link(hw);
1383
1384         if (rte_intr_allow_others(intr_handle)) {
1385                 /* check if lsc interrupt is enabled */
1386                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1387                         eth_igb_lsc_interrupt_setup(dev);
1388         } else {
1389                 rte_intr_callback_unregister(intr_handle,
1390                                              eth_igb_interrupt_handler,
1391                                              (void *)dev);
1392                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1393                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1394                                      " no intr multiplex\n");
1395         }
1396
1397         /* check if rxq interrupt is enabled */
1398         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1399             rte_intr_dp_is_en(intr_handle))
1400                 eth_igb_rxq_interrupt_setup(dev);
1401
1402         /* enable uio/vfio intr/eventfd mapping */
1403         rte_intr_enable(intr_handle);
1404
1405         /* resume enabled intr since hw reset */
1406         igb_intr_enable(dev);
1407
1408         PMD_INIT_LOG(DEBUG, "<<");
1409
1410         return 0;
1411
1412 error_invalid_config:
1413         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1414                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1415         igb_dev_clear_queues(dev);
1416         return -EINVAL;
1417 }
1418
1419 /*********************************************************************
1420  *
1421  *  This routine disables all traffic on the adapter by issuing a
1422  *  global reset on the MAC.
1423  *
1424  **********************************************************************/
1425 static void
1426 eth_igb_stop(struct rte_eth_dev *dev)
1427 {
1428         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1429         struct e1000_filter_info *filter_info =
1430                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1431         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1432         struct rte_eth_link link;
1433         struct e1000_flex_filter *p_flex;
1434         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1435         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1436         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1437
1438         igb_intr_disable(hw);
1439
1440         /* disable intr eventfd mapping */
1441         rte_intr_disable(intr_handle);
1442
1443         igb_pf_reset_hw(hw);
1444         E1000_WRITE_REG(hw, E1000_WUC, 0);
1445
1446         /* Set bit for Go Link disconnect */
1447         if (hw->mac.type >= e1000_82580) {
1448                 uint32_t phpm_reg;
1449
1450                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1451                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1452                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1453         }
1454
1455         /* Power down the phy. Needed to make the link go Down */
1456         eth_igb_dev_set_link_down(dev);
1457
1458         igb_dev_clear_queues(dev);
1459
1460         /* clear the recorded link status */
1461         memset(&link, 0, sizeof(link));
1462         rte_igb_dev_atomic_write_link_status(dev, &link);
1463
1464         /* Remove all flex filters of the device */
1465         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1466                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1467                 rte_free(p_flex);
1468         }
1469         filter_info->flex_mask = 0;
1470
1471         /* Remove all ntuple filters of the device */
1472         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1473              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1474                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1475                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1476                              p_5tuple, entries);
1477                 rte_free(p_5tuple);
1478         }
1479         filter_info->fivetuple_mask = 0;
1480         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1481              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1482                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1483                 TAILQ_REMOVE(&filter_info->twotuple_list,
1484                              p_2tuple, entries);
1485                 rte_free(p_2tuple);
1486         }
1487         filter_info->twotuple_mask = 0;
1488
1489         if (!rte_intr_allow_others(intr_handle))
1490                 /* resume to the default handler */
1491                 rte_intr_callback_register(intr_handle,
1492                                            eth_igb_interrupt_handler,
1493                                            (void *)dev);
1494
1495         /* Clean datapath event and queue/vec mapping */
1496         rte_intr_efd_disable(intr_handle);
1497         if (intr_handle->intr_vec != NULL) {
1498                 rte_free(intr_handle->intr_vec);
1499                 intr_handle->intr_vec = NULL;
1500         }
1501 }
1502
1503 static int
1504 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1505 {
1506         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1507
1508         if (hw->phy.media_type == e1000_media_type_copper)
1509                 e1000_power_up_phy(hw);
1510         else
1511                 e1000_power_up_fiber_serdes_link(hw);
1512
1513         return 0;
1514 }
1515
1516 static int
1517 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1518 {
1519         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1520
1521         if (hw->phy.media_type == e1000_media_type_copper)
1522                 e1000_power_down_phy(hw);
1523         else
1524                 e1000_shutdown_fiber_serdes_link(hw);
1525
1526         return 0;
1527 }
1528
1529 static void
1530 eth_igb_close(struct rte_eth_dev *dev)
1531 {
1532         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1533         struct e1000_adapter *adapter =
1534                 E1000_DEV_PRIVATE(dev->data->dev_private);
1535         struct rte_eth_link link;
1536         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1537         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1538
1539         eth_igb_stop(dev);
1540         adapter->stopped = 1;
1541
1542         e1000_phy_hw_reset(hw);
1543         igb_release_manageability(hw);
1544         igb_hw_control_release(hw);
1545
1546         /* Clear bit for Go Link disconnect */
1547         if (hw->mac.type >= e1000_82580) {
1548                 uint32_t phpm_reg;
1549
1550                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1551                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1552                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1553         }
1554
1555         igb_dev_free_queues(dev);
1556
1557         if (intr_handle->intr_vec) {
1558                 rte_free(intr_handle->intr_vec);
1559                 intr_handle->intr_vec = NULL;
1560         }
1561
1562         memset(&link, 0, sizeof(link));
1563         rte_igb_dev_atomic_write_link_status(dev, &link);
1564 }
1565
1566 static int
1567 igb_get_rx_buffer_size(struct e1000_hw *hw)
1568 {
1569         uint32_t rx_buf_size;
1570         if (hw->mac.type == e1000_82576) {
1571                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1572         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1573                 /* PBS needs to be translated according to a lookup table */
1574                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1575                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1576                 rx_buf_size = (rx_buf_size << 10);
1577         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1578                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1579         } else {
1580                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1581         }
1582
1583         return rx_buf_size;
1584 }
1585
1586 /*********************************************************************
1587  *
1588  *  Initialize the hardware
1589  *
1590  **********************************************************************/
1591 static int
1592 igb_hardware_init(struct e1000_hw *hw)
1593 {
1594         uint32_t rx_buf_size;
1595         int diag;
1596
1597         /* Let the firmware know the OS is in control */
1598         igb_hw_control_acquire(hw);
1599
1600         /*
1601          * These parameters control the automatic generation (Tx) and
1602          * response (Rx) to Ethernet PAUSE frames.
1603          * - High water mark should allow for at least two standard size (1518)
1604          *   frames to be received after sending an XOFF.
1605          * - Low water mark works best when it is very near the high water mark.
1606          *   This allows the receiver to restart by sending XON when it has
1607          *   drained a bit. Here we use an arbitrary value of 1500 which will
1608          *   restart after one full frame is pulled from the buffer. There
1609          *   could be several smaller frames in the buffer and if so they will
1610          *   not trigger the XON until their total number reduces the buffer
1611          *   by 1500.
1612          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1613          */
1614         rx_buf_size = igb_get_rx_buffer_size(hw);
1615
1616         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1617         hw->fc.low_water = hw->fc.high_water - 1500;
1618         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1619         hw->fc.send_xon = 1;
1620
1621         /* Set Flow control, use the tunable location if sane */
1622         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1623                 hw->fc.requested_mode = igb_fc_setting;
1624         else
1625                 hw->fc.requested_mode = e1000_fc_none;
1626
1627         /* Issue a global reset */
1628         igb_pf_reset_hw(hw);
1629         E1000_WRITE_REG(hw, E1000_WUC, 0);
1630
1631         diag = e1000_init_hw(hw);
1632         if (diag < 0)
1633                 return diag;
1634
1635         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1636         e1000_get_phy_info(hw);
1637         e1000_check_for_link(hw);
1638
1639         return 0;
1640 }
1641
1642 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1643 static void
1644 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1645 {
1646         int pause_frames;
1647
1648         uint64_t old_gprc  = stats->gprc;
1649         uint64_t old_gptc  = stats->gptc;
1650         uint64_t old_tpr   = stats->tpr;
1651         uint64_t old_tpt   = stats->tpt;
1652         uint64_t old_rpthc = stats->rpthc;
1653         uint64_t old_hgptc = stats->hgptc;
1654
1655         if(hw->phy.media_type == e1000_media_type_copper ||
1656             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1657                 stats->symerrs +=
1658                     E1000_READ_REG(hw,E1000_SYMERRS);
1659                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1660         }
1661
1662         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1663         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1664         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1665         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1666
1667         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1668         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1669         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1670         stats->dc += E1000_READ_REG(hw, E1000_DC);
1671         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1672         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1673         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1674         /*
1675         ** For watchdog management we need to know if we have been
1676         ** paused during the last interval, so capture that here.
1677         */
1678         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1679         stats->xoffrxc += pause_frames;
1680         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1681         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1682         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1683         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1684         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1685         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1686         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1687         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1688         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1689         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1690         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1691         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1692
1693         /* For the 64-bit byte counters the low dword must be read first. */
1694         /* Both registers clear on the read of the high dword */
1695
1696         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1697         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1698         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1699         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1700         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1701         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1702         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1703
1704         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1705         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1706         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1707         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1708         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1709
1710         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1711         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1712
1713         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1714         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1715         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1716         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1717         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1718         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1719
1720         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1721         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1722         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1723         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1724         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1725         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1726         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1727         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1728
1729         /* Interrupt Counts */
1730
1731         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1732         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1733         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1734         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1735         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1736         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1737         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1738         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1739         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1740
1741         /* Host to Card Statistics */
1742
1743         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1744         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1745         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1746         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1747         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1748         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1749         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1750         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1751         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1752         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1753         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1754         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1755         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1756         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1757         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1758         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1759
1760         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1761         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1762         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1763         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1764         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1765         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1766 }
1767
1768 static void
1769 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1770 {
1771         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1772         struct e1000_hw_stats *stats =
1773                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1774
1775         igb_read_stats_registers(hw, stats);
1776
1777         if (rte_stats == NULL)
1778                 return;
1779
1780         /* Rx Errors */
1781         rte_stats->imissed = stats->mpc;
1782         rte_stats->ierrors = stats->crcerrs +
1783                              stats->rlec + stats->ruc + stats->roc +
1784                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1785
1786         /* Tx Errors */
1787         rte_stats->oerrors = stats->ecol + stats->latecol;
1788
1789         rte_stats->ipackets = stats->gprc;
1790         rte_stats->opackets = stats->gptc;
1791         rte_stats->ibytes   = stats->gorc;
1792         rte_stats->obytes   = stats->gotc;
1793 }
1794
1795 static void
1796 eth_igb_stats_reset(struct rte_eth_dev *dev)
1797 {
1798         struct e1000_hw_stats *hw_stats =
1799                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1800
1801         /* HW registers are cleared on read */
1802         eth_igb_stats_get(dev, NULL);
1803
1804         /* Reset software totals */
1805         memset(hw_stats, 0, sizeof(*hw_stats));
1806 }
1807
1808 static void
1809 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1810 {
1811         struct e1000_hw_stats *stats =
1812                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1813
1814         /* HW registers are cleared on read */
1815         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1816
1817         /* Reset software totals */
1818         memset(stats, 0, sizeof(*stats));
1819 }
1820
1821 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1822         struct rte_eth_xstat_name *xstats_names,
1823         __rte_unused unsigned limit)
1824 {
1825         unsigned i;
1826
1827         if (xstats_names == NULL)
1828                 return IGB_NB_XSTATS;
1829
1830         /* Note: limit checked in rte_eth_xstats_names() */
1831
1832         for (i = 0; i < IGB_NB_XSTATS; i++) {
1833                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1834                          "%s", rte_igb_stats_strings[i].name);
1835         }
1836
1837         return IGB_NB_XSTATS;
1838 }
1839
1840 static int
1841 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1842                    unsigned n)
1843 {
1844         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         struct e1000_hw_stats *hw_stats =
1846                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1847         unsigned i;
1848
1849         if (n < IGB_NB_XSTATS)
1850                 return IGB_NB_XSTATS;
1851
1852         igb_read_stats_registers(hw, hw_stats);
1853
1854         /* If this is a reset xstats is NULL, and we have cleared the
1855          * registers by reading them.
1856          */
1857         if (!xstats)
1858                 return 0;
1859
1860         /* Extended stats */
1861         for (i = 0; i < IGB_NB_XSTATS; i++) {
1862                 xstats[i].id = i;
1863                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1864                         rte_igb_stats_strings[i].offset);
1865         }
1866
1867         return IGB_NB_XSTATS;
1868 }
1869
1870 static void
1871 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1872 {
1873         /* Good Rx packets, include VF loopback */
1874         UPDATE_VF_STAT(E1000_VFGPRC,
1875             hw_stats->last_gprc, hw_stats->gprc);
1876
1877         /* Good Rx octets, include VF loopback */
1878         UPDATE_VF_STAT(E1000_VFGORC,
1879             hw_stats->last_gorc, hw_stats->gorc);
1880
1881         /* Good Tx packets, include VF loopback */
1882         UPDATE_VF_STAT(E1000_VFGPTC,
1883             hw_stats->last_gptc, hw_stats->gptc);
1884
1885         /* Good Tx octets, include VF loopback */
1886         UPDATE_VF_STAT(E1000_VFGOTC,
1887             hw_stats->last_gotc, hw_stats->gotc);
1888
1889         /* Rx Multicst packets */
1890         UPDATE_VF_STAT(E1000_VFMPRC,
1891             hw_stats->last_mprc, hw_stats->mprc);
1892
1893         /* Good Rx loopback packets */
1894         UPDATE_VF_STAT(E1000_VFGPRLBC,
1895             hw_stats->last_gprlbc, hw_stats->gprlbc);
1896
1897         /* Good Rx loopback octets */
1898         UPDATE_VF_STAT(E1000_VFGORLBC,
1899             hw_stats->last_gorlbc, hw_stats->gorlbc);
1900
1901         /* Good Tx loopback packets */
1902         UPDATE_VF_STAT(E1000_VFGPTLBC,
1903             hw_stats->last_gptlbc, hw_stats->gptlbc);
1904
1905         /* Good Tx loopback octets */
1906         UPDATE_VF_STAT(E1000_VFGOTLBC,
1907             hw_stats->last_gotlbc, hw_stats->gotlbc);
1908 }
1909
1910 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1911                                      struct rte_eth_xstat_name *xstats_names,
1912                                      __rte_unused unsigned limit)
1913 {
1914         unsigned i;
1915
1916         if (xstats_names != NULL)
1917                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1918                         snprintf(xstats_names[i].name,
1919                                 sizeof(xstats_names[i].name), "%s",
1920                                 rte_igbvf_stats_strings[i].name);
1921                 }
1922         return IGBVF_NB_XSTATS;
1923 }
1924
1925 static int
1926 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1927                      unsigned n)
1928 {
1929         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1931                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1932         unsigned i;
1933
1934         if (n < IGBVF_NB_XSTATS)
1935                 return IGBVF_NB_XSTATS;
1936
1937         igbvf_read_stats_registers(hw, hw_stats);
1938
1939         if (!xstats)
1940                 return 0;
1941
1942         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1943                 xstats[i].id = i;
1944                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1945                         rte_igbvf_stats_strings[i].offset);
1946         }
1947
1948         return IGBVF_NB_XSTATS;
1949 }
1950
1951 static void
1952 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1953 {
1954         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1955         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1956                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1957
1958         igbvf_read_stats_registers(hw, hw_stats);
1959
1960         if (rte_stats == NULL)
1961                 return;
1962
1963         rte_stats->ipackets = hw_stats->gprc;
1964         rte_stats->ibytes = hw_stats->gorc;
1965         rte_stats->opackets = hw_stats->gptc;
1966         rte_stats->obytes = hw_stats->gotc;
1967 }
1968
1969 static void
1970 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1971 {
1972         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1973                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1974
1975         /* Sync HW register to the last stats */
1976         eth_igbvf_stats_get(dev, NULL);
1977
1978         /* reset HW current stats*/
1979         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1980                offsetof(struct e1000_vf_stats, gprc));
1981 }
1982
1983 static void
1984 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1985 {
1986         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1987
1988         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1989         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1990         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1991         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1992         dev_info->rx_offload_capa =
1993                 DEV_RX_OFFLOAD_VLAN_STRIP |
1994                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1995                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1996                 DEV_RX_OFFLOAD_TCP_CKSUM;
1997         dev_info->tx_offload_capa =
1998                 DEV_TX_OFFLOAD_VLAN_INSERT |
1999                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2000                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2001                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2002                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2003                 DEV_TX_OFFLOAD_TCP_TSO;
2004
2005         switch (hw->mac.type) {
2006         case e1000_82575:
2007                 dev_info->max_rx_queues = 4;
2008                 dev_info->max_tx_queues = 4;
2009                 dev_info->max_vmdq_pools = 0;
2010                 break;
2011
2012         case e1000_82576:
2013                 dev_info->max_rx_queues = 16;
2014                 dev_info->max_tx_queues = 16;
2015                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2016                 dev_info->vmdq_queue_num = 16;
2017                 break;
2018
2019         case e1000_82580:
2020                 dev_info->max_rx_queues = 8;
2021                 dev_info->max_tx_queues = 8;
2022                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2023                 dev_info->vmdq_queue_num = 8;
2024                 break;
2025
2026         case e1000_i350:
2027                 dev_info->max_rx_queues = 8;
2028                 dev_info->max_tx_queues = 8;
2029                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2030                 dev_info->vmdq_queue_num = 8;
2031                 break;
2032
2033         case e1000_i354:
2034                 dev_info->max_rx_queues = 8;
2035                 dev_info->max_tx_queues = 8;
2036                 break;
2037
2038         case e1000_i210:
2039                 dev_info->max_rx_queues = 4;
2040                 dev_info->max_tx_queues = 4;
2041                 dev_info->max_vmdq_pools = 0;
2042                 break;
2043
2044         case e1000_i211:
2045                 dev_info->max_rx_queues = 2;
2046                 dev_info->max_tx_queues = 2;
2047                 dev_info->max_vmdq_pools = 0;
2048                 break;
2049
2050         default:
2051                 /* Should not happen */
2052                 break;
2053         }
2054         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2055         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2056         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2057
2058         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2059                 .rx_thresh = {
2060                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2061                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2062                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2063                 },
2064                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2065                 .rx_drop_en = 0,
2066         };
2067
2068         dev_info->default_txconf = (struct rte_eth_txconf) {
2069                 .tx_thresh = {
2070                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2071                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2072                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2073                 },
2074                 .txq_flags = 0,
2075         };
2076
2077         dev_info->rx_desc_lim = rx_desc_lim;
2078         dev_info->tx_desc_lim = tx_desc_lim;
2079
2080         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2081                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2082                         ETH_LINK_SPEED_1G;
2083 }
2084
2085 static const uint32_t *
2086 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2087 {
2088         static const uint32_t ptypes[] = {
2089                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2090                 RTE_PTYPE_L2_ETHER,
2091                 RTE_PTYPE_L3_IPV4,
2092                 RTE_PTYPE_L3_IPV4_EXT,
2093                 RTE_PTYPE_L3_IPV6,
2094                 RTE_PTYPE_L3_IPV6_EXT,
2095                 RTE_PTYPE_L4_TCP,
2096                 RTE_PTYPE_L4_UDP,
2097                 RTE_PTYPE_L4_SCTP,
2098                 RTE_PTYPE_TUNNEL_IP,
2099                 RTE_PTYPE_INNER_L3_IPV6,
2100                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2101                 RTE_PTYPE_INNER_L4_TCP,
2102                 RTE_PTYPE_INNER_L4_UDP,
2103                 RTE_PTYPE_UNKNOWN
2104         };
2105
2106         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2107             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2108                 return ptypes;
2109         return NULL;
2110 }
2111
2112 static void
2113 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2114 {
2115         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2116
2117         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2118         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2119         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2120         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2121         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2122                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2123                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2124                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2125         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2126                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2127                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2128                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2129                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2130                                 DEV_TX_OFFLOAD_TCP_TSO;
2131         switch (hw->mac.type) {
2132         case e1000_vfadapt:
2133                 dev_info->max_rx_queues = 2;
2134                 dev_info->max_tx_queues = 2;
2135                 break;
2136         case e1000_vfadapt_i350:
2137                 dev_info->max_rx_queues = 1;
2138                 dev_info->max_tx_queues = 1;
2139                 break;
2140         default:
2141                 /* Should not happen */
2142                 break;
2143         }
2144
2145         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2146                 .rx_thresh = {
2147                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2148                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2149                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2150                 },
2151                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2152                 .rx_drop_en = 0,
2153         };
2154
2155         dev_info->default_txconf = (struct rte_eth_txconf) {
2156                 .tx_thresh = {
2157                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2158                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2159                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2160                 },
2161                 .txq_flags = 0,
2162         };
2163
2164         dev_info->rx_desc_lim = rx_desc_lim;
2165         dev_info->tx_desc_lim = tx_desc_lim;
2166 }
2167
2168 /* return 0 means link status changed, -1 means not changed */
2169 static int
2170 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2171 {
2172         struct e1000_hw *hw =
2173                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2174         struct rte_eth_link link, old;
2175         int link_check, count;
2176
2177         link_check = 0;
2178         hw->mac.get_link_status = 1;
2179
2180         /* possible wait-to-complete in up to 9 seconds */
2181         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2182                 /* Read the real link status */
2183                 switch (hw->phy.media_type) {
2184                 case e1000_media_type_copper:
2185                         /* Do the work to read phy */
2186                         e1000_check_for_link(hw);
2187                         link_check = !hw->mac.get_link_status;
2188                         break;
2189
2190                 case e1000_media_type_fiber:
2191                         e1000_check_for_link(hw);
2192                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2193                                       E1000_STATUS_LU);
2194                         break;
2195
2196                 case e1000_media_type_internal_serdes:
2197                         e1000_check_for_link(hw);
2198                         link_check = hw->mac.serdes_has_link;
2199                         break;
2200
2201                 /* VF device is type_unknown */
2202                 case e1000_media_type_unknown:
2203                         eth_igbvf_link_update(hw);
2204                         link_check = !hw->mac.get_link_status;
2205                         break;
2206
2207                 default:
2208                         break;
2209                 }
2210                 if (link_check || wait_to_complete == 0)
2211                         break;
2212                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2213         }
2214         memset(&link, 0, sizeof(link));
2215         rte_igb_dev_atomic_read_link_status(dev, &link);
2216         old = link;
2217
2218         /* Now we check if a transition has happened */
2219         if (link_check) {
2220                 uint16_t duplex, speed;
2221                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2222                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2223                                 ETH_LINK_FULL_DUPLEX :
2224                                 ETH_LINK_HALF_DUPLEX;
2225                 link.link_speed = speed;
2226                 link.link_status = ETH_LINK_UP;
2227                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2228                                 ETH_LINK_SPEED_FIXED);
2229         } else if (!link_check) {
2230                 link.link_speed = 0;
2231                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2232                 link.link_status = ETH_LINK_DOWN;
2233                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2234         }
2235         rte_igb_dev_atomic_write_link_status(dev, &link);
2236
2237         /* not changed */
2238         if (old.link_status == link.link_status)
2239                 return -1;
2240
2241         /* changed */
2242         return 0;
2243 }
2244
2245 /*
2246  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2247  * For ASF and Pass Through versions of f/w this means
2248  * that the driver is loaded.
2249  */
2250 static void
2251 igb_hw_control_acquire(struct e1000_hw *hw)
2252 {
2253         uint32_t ctrl_ext;
2254
2255         /* Let firmware know the driver has taken over */
2256         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2257         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2258 }
2259
2260 /*
2261  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2262  * For ASF and Pass Through versions of f/w this means that the
2263  * driver is no longer loaded.
2264  */
2265 static void
2266 igb_hw_control_release(struct e1000_hw *hw)
2267 {
2268         uint32_t ctrl_ext;
2269
2270         /* Let firmware taken over control of h/w */
2271         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2272         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2273                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2274 }
2275
2276 /*
2277  * Bit of a misnomer, what this really means is
2278  * to enable OS management of the system... aka
2279  * to disable special hardware management features.
2280  */
2281 static void
2282 igb_init_manageability(struct e1000_hw *hw)
2283 {
2284         if (e1000_enable_mng_pass_thru(hw)) {
2285                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2286                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2287
2288                 /* disable hardware interception of ARP */
2289                 manc &= ~(E1000_MANC_ARP_EN);
2290
2291                 /* enable receiving management packets to the host */
2292                 manc |= E1000_MANC_EN_MNG2HOST;
2293                 manc2h |= 1 << 5;  /* Mng Port 623 */
2294                 manc2h |= 1 << 6;  /* Mng Port 664 */
2295                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2296                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2297         }
2298 }
2299
2300 static void
2301 igb_release_manageability(struct e1000_hw *hw)
2302 {
2303         if (e1000_enable_mng_pass_thru(hw)) {
2304                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2305
2306                 manc |= E1000_MANC_ARP_EN;
2307                 manc &= ~E1000_MANC_EN_MNG2HOST;
2308
2309                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2310         }
2311 }
2312
2313 static void
2314 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2315 {
2316         struct e1000_hw *hw =
2317                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2318         uint32_t rctl;
2319
2320         rctl = E1000_READ_REG(hw, E1000_RCTL);
2321         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2322         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2323 }
2324
2325 static void
2326 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2327 {
2328         struct e1000_hw *hw =
2329                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2330         uint32_t rctl;
2331
2332         rctl = E1000_READ_REG(hw, E1000_RCTL);
2333         rctl &= (~E1000_RCTL_UPE);
2334         if (dev->data->all_multicast == 1)
2335                 rctl |= E1000_RCTL_MPE;
2336         else
2337                 rctl &= (~E1000_RCTL_MPE);
2338         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2339 }
2340
2341 static void
2342 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2343 {
2344         struct e1000_hw *hw =
2345                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2346         uint32_t rctl;
2347
2348         rctl = E1000_READ_REG(hw, E1000_RCTL);
2349         rctl |= E1000_RCTL_MPE;
2350         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2351 }
2352
2353 static void
2354 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2355 {
2356         struct e1000_hw *hw =
2357                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2358         uint32_t rctl;
2359
2360         if (dev->data->promiscuous == 1)
2361                 return; /* must remain in all_multicast mode */
2362         rctl = E1000_READ_REG(hw, E1000_RCTL);
2363         rctl &= (~E1000_RCTL_MPE);
2364         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2365 }
2366
2367 static int
2368 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2369 {
2370         struct e1000_hw *hw =
2371                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2372         struct e1000_vfta * shadow_vfta =
2373                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2374         uint32_t vfta;
2375         uint32_t vid_idx;
2376         uint32_t vid_bit;
2377
2378         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2379                               E1000_VFTA_ENTRY_MASK);
2380         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2381         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2382         if (on)
2383                 vfta |= vid_bit;
2384         else
2385                 vfta &= ~vid_bit;
2386         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2387
2388         /* update local VFTA copy */
2389         shadow_vfta->vfta[vid_idx] = vfta;
2390
2391         return 0;
2392 }
2393
2394 static int
2395 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2396                       enum rte_vlan_type vlan_type,
2397                       uint16_t tpid)
2398 {
2399         struct e1000_hw *hw =
2400                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2401         uint32_t reg, qinq;
2402
2403         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2404         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2405
2406         /* only outer TPID of double VLAN can be configured*/
2407         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2408                 reg = E1000_READ_REG(hw, E1000_VET);
2409                 reg = (reg & (~E1000_VET_VET_EXT)) |
2410                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2411                 E1000_WRITE_REG(hw, E1000_VET, reg);
2412
2413                 return 0;
2414         }
2415
2416         /* all other TPID values are read-only*/
2417         PMD_DRV_LOG(ERR, "Not supported");
2418
2419         return -ENOTSUP;
2420 }
2421
2422 static void
2423 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2424 {
2425         struct e1000_hw *hw =
2426                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2427         uint32_t reg;
2428
2429         /* Filter Table Disable */
2430         reg = E1000_READ_REG(hw, E1000_RCTL);
2431         reg &= ~E1000_RCTL_CFIEN;
2432         reg &= ~E1000_RCTL_VFE;
2433         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2434 }
2435
2436 static void
2437 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2438 {
2439         struct e1000_hw *hw =
2440                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2441         struct e1000_vfta * shadow_vfta =
2442                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2443         uint32_t reg;
2444         int i;
2445
2446         /* Filter Table Enable, CFI not used for packet acceptance */
2447         reg = E1000_READ_REG(hw, E1000_RCTL);
2448         reg &= ~E1000_RCTL_CFIEN;
2449         reg |= E1000_RCTL_VFE;
2450         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2451
2452         /* restore VFTA table */
2453         for (i = 0; i < IGB_VFTA_SIZE; i++)
2454                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2455 }
2456
2457 static void
2458 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2459 {
2460         struct e1000_hw *hw =
2461                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2462         uint32_t reg;
2463
2464         /* VLAN Mode Disable */
2465         reg = E1000_READ_REG(hw, E1000_CTRL);
2466         reg &= ~E1000_CTRL_VME;
2467         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2468 }
2469
2470 static void
2471 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2472 {
2473         struct e1000_hw *hw =
2474                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2475         uint32_t reg;
2476
2477         /* VLAN Mode Enable */
2478         reg = E1000_READ_REG(hw, E1000_CTRL);
2479         reg |= E1000_CTRL_VME;
2480         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2481 }
2482
2483 static void
2484 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2485 {
2486         struct e1000_hw *hw =
2487                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2488         uint32_t reg;
2489
2490         /* CTRL_EXT: Extended VLAN */
2491         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2492         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2493         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2494
2495         /* Update maximum packet length */
2496         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2497                 E1000_WRITE_REG(hw, E1000_RLPML,
2498                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2499                                                 VLAN_TAG_SIZE);
2500 }
2501
2502 static void
2503 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2504 {
2505         struct e1000_hw *hw =
2506                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2507         uint32_t reg;
2508
2509         /* CTRL_EXT: Extended VLAN */
2510         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2511         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2512         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2513
2514         /* Update maximum packet length */
2515         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2516                 E1000_WRITE_REG(hw, E1000_RLPML,
2517                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2518                                                 2 * VLAN_TAG_SIZE);
2519 }
2520
2521 static void
2522 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2523 {
2524         if(mask & ETH_VLAN_STRIP_MASK){
2525                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2526                         igb_vlan_hw_strip_enable(dev);
2527                 else
2528                         igb_vlan_hw_strip_disable(dev);
2529         }
2530
2531         if(mask & ETH_VLAN_FILTER_MASK){
2532                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2533                         igb_vlan_hw_filter_enable(dev);
2534                 else
2535                         igb_vlan_hw_filter_disable(dev);
2536         }
2537
2538         if(mask & ETH_VLAN_EXTEND_MASK){
2539                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2540                         igb_vlan_hw_extend_enable(dev);
2541                 else
2542                         igb_vlan_hw_extend_disable(dev);
2543         }
2544 }
2545
2546
2547 /**
2548  * It enables the interrupt mask and then enable the interrupt.
2549  *
2550  * @param dev
2551  *  Pointer to struct rte_eth_dev.
2552  *
2553  * @return
2554  *  - On success, zero.
2555  *  - On failure, a negative value.
2556  */
2557 static int
2558 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2559 {
2560         struct e1000_interrupt *intr =
2561                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2562
2563         intr->mask |= E1000_ICR_LSC;
2564
2565         return 0;
2566 }
2567
2568 /* It clears the interrupt causes and enables the interrupt.
2569  * It will be called once only during nic initialized.
2570  *
2571  * @param dev
2572  *  Pointer to struct rte_eth_dev.
2573  *
2574  * @return
2575  *  - On success, zero.
2576  *  - On failure, a negative value.
2577  */
2578 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2579 {
2580         uint32_t mask, regval;
2581         struct e1000_hw *hw =
2582                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2583         struct rte_eth_dev_info dev_info;
2584
2585         memset(&dev_info, 0, sizeof(dev_info));
2586         eth_igb_infos_get(dev, &dev_info);
2587
2588         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2589         regval = E1000_READ_REG(hw, E1000_EIMS);
2590         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2591
2592         return 0;
2593 }
2594
2595 /*
2596  * It reads ICR and gets interrupt causes, check it and set a bit flag
2597  * to update link status.
2598  *
2599  * @param dev
2600  *  Pointer to struct rte_eth_dev.
2601  *
2602  * @return
2603  *  - On success, zero.
2604  *  - On failure, a negative value.
2605  */
2606 static int
2607 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2608 {
2609         uint32_t icr;
2610         struct e1000_hw *hw =
2611                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2612         struct e1000_interrupt *intr =
2613                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2614
2615         igb_intr_disable(hw);
2616
2617         /* read-on-clear nic registers here */
2618         icr = E1000_READ_REG(hw, E1000_ICR);
2619
2620         intr->flags = 0;
2621         if (icr & E1000_ICR_LSC) {
2622                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2623         }
2624
2625         if (icr & E1000_ICR_VMMB)
2626                 intr->flags |= E1000_FLAG_MAILBOX;
2627
2628         return 0;
2629 }
2630
2631 /*
2632  * It executes link_update after knowing an interrupt is prsent.
2633  *
2634  * @param dev
2635  *  Pointer to struct rte_eth_dev.
2636  *
2637  * @return
2638  *  - On success, zero.
2639  *  - On failure, a negative value.
2640  */
2641 static int
2642 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2643                          struct rte_intr_handle *intr_handle)
2644 {
2645         struct e1000_hw *hw =
2646                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647         struct e1000_interrupt *intr =
2648                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2649         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
2650         uint32_t tctl, rctl;
2651         struct rte_eth_link link;
2652         int ret;
2653
2654         if (intr->flags & E1000_FLAG_MAILBOX) {
2655                 igb_pf_mbx_process(dev);
2656                 intr->flags &= ~E1000_FLAG_MAILBOX;
2657         }
2658
2659         igb_intr_enable(dev);
2660         rte_intr_enable(intr_handle);
2661
2662         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2663                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2664
2665                 /* set get_link_status to check register later */
2666                 hw->mac.get_link_status = 1;
2667                 ret = eth_igb_link_update(dev, 0);
2668
2669                 /* check if link has changed */
2670                 if (ret < 0)
2671                         return 0;
2672
2673                 memset(&link, 0, sizeof(link));
2674                 rte_igb_dev_atomic_read_link_status(dev, &link);
2675                 if (link.link_status) {
2676                         PMD_INIT_LOG(INFO,
2677                                      " Port %d: Link Up - speed %u Mbps - %s",
2678                                      dev->data->port_id,
2679                                      (unsigned)link.link_speed,
2680                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2681                                      "full-duplex" : "half-duplex");
2682                 } else {
2683                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2684                                      dev->data->port_id);
2685                 }
2686
2687                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2688                              pci_dev->addr.domain,
2689                              pci_dev->addr.bus,
2690                              pci_dev->addr.devid,
2691                              pci_dev->addr.function);
2692                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2693                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2694                 if (link.link_status) {
2695                         /* enable Tx/Rx */
2696                         tctl |= E1000_TCTL_EN;
2697                         rctl |= E1000_RCTL_EN;
2698                 } else {
2699                         /* disable Tx/Rx */
2700                         tctl &= ~E1000_TCTL_EN;
2701                         rctl &= ~E1000_RCTL_EN;
2702                 }
2703                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2704                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2705                 E1000_WRITE_FLUSH(hw);
2706                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2707         }
2708
2709         return 0;
2710 }
2711
2712 /**
2713  * Interrupt handler which shall be registered at first.
2714  *
2715  * @param handle
2716  *  Pointer to interrupt handle.
2717  * @param param
2718  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2719  *
2720  * @return
2721  *  void
2722  */
2723 static void
2724 eth_igb_interrupt_handler(struct rte_intr_handle *handle, void *param)
2725 {
2726         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2727
2728         eth_igb_interrupt_get_status(dev);
2729         eth_igb_interrupt_action(dev, handle);
2730 }
2731
2732 static int
2733 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2734 {
2735         uint32_t eicr;
2736         struct e1000_hw *hw =
2737                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2738         struct e1000_interrupt *intr =
2739                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2740
2741         igbvf_intr_disable(hw);
2742
2743         /* read-on-clear nic registers here */
2744         eicr = E1000_READ_REG(hw, E1000_EICR);
2745         intr->flags = 0;
2746
2747         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2748                 intr->flags |= E1000_FLAG_MAILBOX;
2749
2750         return 0;
2751 }
2752
2753 void igbvf_mbx_process(struct rte_eth_dev *dev)
2754 {
2755         struct e1000_hw *hw =
2756                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2757         struct e1000_mbx_info *mbx = &hw->mbx;
2758         u32 in_msg = 0;
2759
2760         if (mbx->ops.read(hw, &in_msg, 1, 0))
2761                 return;
2762
2763         /* PF reset VF event */
2764         if (in_msg == E1000_PF_CONTROL_MSG)
2765                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2766 }
2767
2768 static int
2769 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2770 {
2771         struct e1000_interrupt *intr =
2772                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2773
2774         if (intr->flags & E1000_FLAG_MAILBOX) {
2775                 igbvf_mbx_process(dev);
2776                 intr->flags &= ~E1000_FLAG_MAILBOX;
2777         }
2778
2779         igbvf_intr_enable(dev);
2780         rte_intr_enable(intr_handle);
2781
2782         return 0;
2783 }
2784
2785 static void
2786 eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
2787                             void *param)
2788 {
2789         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2790
2791         eth_igbvf_interrupt_get_status(dev);
2792         eth_igbvf_interrupt_action(dev, handle);
2793 }
2794
2795 static int
2796 eth_igb_led_on(struct rte_eth_dev *dev)
2797 {
2798         struct e1000_hw *hw;
2799
2800         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2801         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2802 }
2803
2804 static int
2805 eth_igb_led_off(struct rte_eth_dev *dev)
2806 {
2807         struct e1000_hw *hw;
2808
2809         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2810         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2811 }
2812
2813 static int
2814 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2815 {
2816         struct e1000_hw *hw;
2817         uint32_t ctrl;
2818         int tx_pause;
2819         int rx_pause;
2820
2821         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2822         fc_conf->pause_time = hw->fc.pause_time;
2823         fc_conf->high_water = hw->fc.high_water;
2824         fc_conf->low_water = hw->fc.low_water;
2825         fc_conf->send_xon = hw->fc.send_xon;
2826         fc_conf->autoneg = hw->mac.autoneg;
2827
2828         /*
2829          * Return rx_pause and tx_pause status according to actual setting of
2830          * the TFCE and RFCE bits in the CTRL register.
2831          */
2832         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2833         if (ctrl & E1000_CTRL_TFCE)
2834                 tx_pause = 1;
2835         else
2836                 tx_pause = 0;
2837
2838         if (ctrl & E1000_CTRL_RFCE)
2839                 rx_pause = 1;
2840         else
2841                 rx_pause = 0;
2842
2843         if (rx_pause && tx_pause)
2844                 fc_conf->mode = RTE_FC_FULL;
2845         else if (rx_pause)
2846                 fc_conf->mode = RTE_FC_RX_PAUSE;
2847         else if (tx_pause)
2848                 fc_conf->mode = RTE_FC_TX_PAUSE;
2849         else
2850                 fc_conf->mode = RTE_FC_NONE;
2851
2852         return 0;
2853 }
2854
2855 static int
2856 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2857 {
2858         struct e1000_hw *hw;
2859         int err;
2860         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2861                 e1000_fc_none,
2862                 e1000_fc_rx_pause,
2863                 e1000_fc_tx_pause,
2864                 e1000_fc_full
2865         };
2866         uint32_t rx_buf_size;
2867         uint32_t max_high_water;
2868         uint32_t rctl;
2869
2870         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2871         if (fc_conf->autoneg != hw->mac.autoneg)
2872                 return -ENOTSUP;
2873         rx_buf_size = igb_get_rx_buffer_size(hw);
2874         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2875
2876         /* At least reserve one Ethernet frame for watermark */
2877         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2878         if ((fc_conf->high_water > max_high_water) ||
2879             (fc_conf->high_water < fc_conf->low_water)) {
2880                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2881                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2882                 return -EINVAL;
2883         }
2884
2885         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2886         hw->fc.pause_time     = fc_conf->pause_time;
2887         hw->fc.high_water     = fc_conf->high_water;
2888         hw->fc.low_water      = fc_conf->low_water;
2889         hw->fc.send_xon       = fc_conf->send_xon;
2890
2891         err = e1000_setup_link_generic(hw);
2892         if (err == E1000_SUCCESS) {
2893
2894                 /* check if we want to forward MAC frames - driver doesn't have native
2895                  * capability to do that, so we'll write the registers ourselves */
2896
2897                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2898
2899                 /* set or clear MFLCN.PMCF bit depending on configuration */
2900                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2901                         rctl |= E1000_RCTL_PMCF;
2902                 else
2903                         rctl &= ~E1000_RCTL_PMCF;
2904
2905                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2906                 E1000_WRITE_FLUSH(hw);
2907
2908                 return 0;
2909         }
2910
2911         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2912         return -EIO;
2913 }
2914
2915 #define E1000_RAH_POOLSEL_SHIFT      (18)
2916 static void
2917 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2918                 uint32_t index, __rte_unused uint32_t pool)
2919 {
2920         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2921         uint32_t rah;
2922
2923         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2924         rah = E1000_READ_REG(hw, E1000_RAH(index));
2925         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2926         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2927 }
2928
2929 static void
2930 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2931 {
2932         uint8_t addr[ETHER_ADDR_LEN];
2933         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2934
2935         memset(addr, 0, sizeof(addr));
2936
2937         e1000_rar_set(hw, addr, index);
2938 }
2939
2940 static void
2941 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2942                                 struct ether_addr *addr)
2943 {
2944         eth_igb_rar_clear(dev, 0);
2945
2946         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2947 }
2948 /*
2949  * Virtual Function operations
2950  */
2951 static void
2952 igbvf_intr_disable(struct e1000_hw *hw)
2953 {
2954         PMD_INIT_FUNC_TRACE();
2955
2956         /* Clear interrupt mask to stop from interrupts being generated */
2957         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2958
2959         E1000_WRITE_FLUSH(hw);
2960 }
2961
2962 static void
2963 igbvf_stop_adapter(struct rte_eth_dev *dev)
2964 {
2965         u32 reg_val;
2966         u16 i;
2967         struct rte_eth_dev_info dev_info;
2968         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2969
2970         memset(&dev_info, 0, sizeof(dev_info));
2971         eth_igbvf_infos_get(dev, &dev_info);
2972
2973         /* Clear interrupt mask to stop from interrupts being generated */
2974         igbvf_intr_disable(hw);
2975
2976         /* Clear any pending interrupts, flush previous writes */
2977         E1000_READ_REG(hw, E1000_EICR);
2978
2979         /* Disable the transmit unit.  Each queue must be disabled. */
2980         for (i = 0; i < dev_info.max_tx_queues; i++)
2981                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2982
2983         /* Disable the receive unit by stopping each queue */
2984         for (i = 0; i < dev_info.max_rx_queues; i++) {
2985                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2986                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2987                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2988                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2989                         ;
2990         }
2991
2992         /* flush all queues disables */
2993         E1000_WRITE_FLUSH(hw);
2994         msec_delay(2);
2995 }
2996
2997 static int eth_igbvf_link_update(struct e1000_hw *hw)
2998 {
2999         struct e1000_mbx_info *mbx = &hw->mbx;
3000         struct e1000_mac_info *mac = &hw->mac;
3001         int ret_val = E1000_SUCCESS;
3002
3003         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3004
3005         /*
3006          * We only want to run this if there has been a rst asserted.
3007          * in this case that could mean a link change, device reset,
3008          * or a virtual function reset
3009          */
3010
3011         /* If we were hit with a reset or timeout drop the link */
3012         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3013                 mac->get_link_status = TRUE;
3014
3015         if (!mac->get_link_status)
3016                 goto out;
3017
3018         /* if link status is down no point in checking to see if pf is up */
3019         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3020                 goto out;
3021
3022         /* if we passed all the tests above then the link is up and we no
3023          * longer need to check for link */
3024         mac->get_link_status = FALSE;
3025
3026 out:
3027         return ret_val;
3028 }
3029
3030
3031 static int
3032 igbvf_dev_configure(struct rte_eth_dev *dev)
3033 {
3034         struct rte_eth_conf* conf = &dev->data->dev_conf;
3035
3036         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3037                      dev->data->port_id);
3038
3039         /*
3040          * VF has no ability to enable/disable HW CRC
3041          * Keep the persistent behavior the same as Host PF
3042          */
3043 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3044         if (!conf->rxmode.hw_strip_crc) {
3045                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3046                 conf->rxmode.hw_strip_crc = 1;
3047         }
3048 #else
3049         if (conf->rxmode.hw_strip_crc) {
3050                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3051                 conf->rxmode.hw_strip_crc = 0;
3052         }
3053 #endif
3054
3055         return 0;
3056 }
3057
3058 static int
3059 igbvf_dev_start(struct rte_eth_dev *dev)
3060 {
3061         struct e1000_hw *hw =
3062                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3063         struct e1000_adapter *adapter =
3064                 E1000_DEV_PRIVATE(dev->data->dev_private);
3065         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3066         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3067         int ret;
3068         uint32_t intr_vector = 0;
3069
3070         PMD_INIT_FUNC_TRACE();
3071
3072         hw->mac.ops.reset_hw(hw);
3073         adapter->stopped = 0;
3074
3075         /* Set all vfta */
3076         igbvf_set_vfta_all(dev,1);
3077
3078         eth_igbvf_tx_init(dev);
3079
3080         /* This can fail when allocating mbufs for descriptor rings */
3081         ret = eth_igbvf_rx_init(dev);
3082         if (ret) {
3083                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3084                 igb_dev_clear_queues(dev);
3085                 return ret;
3086         }
3087
3088         /* check and configure queue intr-vector mapping */
3089         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3090                 intr_vector = dev->data->nb_rx_queues;
3091                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3092                 if (ret)
3093                         return ret;
3094         }
3095
3096         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3097                 intr_handle->intr_vec =
3098                         rte_zmalloc("intr_vec",
3099                                     dev->data->nb_rx_queues * sizeof(int), 0);
3100                 if (!intr_handle->intr_vec) {
3101                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3102                                      " intr_vec\n", dev->data->nb_rx_queues);
3103                         return -ENOMEM;
3104                 }
3105         }
3106
3107         eth_igbvf_configure_msix_intr(dev);
3108
3109         /* enable uio/vfio intr/eventfd mapping */
3110         rte_intr_enable(intr_handle);
3111
3112         /* resume enabled intr since hw reset */
3113         igbvf_intr_enable(dev);
3114
3115         return 0;
3116 }
3117
3118 static void
3119 igbvf_dev_stop(struct rte_eth_dev *dev)
3120 {
3121         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3122         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3123
3124         PMD_INIT_FUNC_TRACE();
3125
3126         igbvf_stop_adapter(dev);
3127
3128         /*
3129           * Clear what we set, but we still keep shadow_vfta to
3130           * restore after device starts
3131           */
3132         igbvf_set_vfta_all(dev,0);
3133
3134         igb_dev_clear_queues(dev);
3135
3136         /* disable intr eventfd mapping */
3137         rte_intr_disable(intr_handle);
3138
3139         /* Clean datapath event and queue/vec mapping */
3140         rte_intr_efd_disable(intr_handle);
3141         if (intr_handle->intr_vec) {
3142                 rte_free(intr_handle->intr_vec);
3143                 intr_handle->intr_vec = NULL;
3144         }
3145 }
3146
3147 static void
3148 igbvf_dev_close(struct rte_eth_dev *dev)
3149 {
3150         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3151         struct e1000_adapter *adapter =
3152                 E1000_DEV_PRIVATE(dev->data->dev_private);
3153         struct ether_addr addr;
3154
3155         PMD_INIT_FUNC_TRACE();
3156
3157         e1000_reset_hw(hw);
3158
3159         igbvf_dev_stop(dev);
3160         adapter->stopped = 1;
3161         igb_dev_free_queues(dev);
3162
3163         /**
3164          * reprogram the RAR with a zero mac address,
3165          * to ensure that the VF traffic goes to the PF
3166          * after stop, close and detach of the VF.
3167          **/
3168
3169         memset(&addr, 0, sizeof(addr));
3170         igbvf_default_mac_addr_set(dev, &addr);
3171 }
3172
3173 static void
3174 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3175 {
3176         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3177
3178         /* Set both unicast and multicast promisc */
3179         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3180 }
3181
3182 static void
3183 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3184 {
3185         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3186
3187         /* If in allmulticast mode leave multicast promisc */
3188         if (dev->data->all_multicast == 1)
3189                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3190         else
3191                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3192 }
3193
3194 static void
3195 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3196 {
3197         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3198
3199         /* In promiscuous mode multicast promisc already set */
3200         if (dev->data->promiscuous == 0)
3201                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3202 }
3203
3204 static void
3205 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3206 {
3207         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3208
3209         /* In promiscuous mode leave multicast promisc enabled */
3210         if (dev->data->promiscuous == 0)
3211                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3212 }
3213
3214 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3215 {
3216         struct e1000_mbx_info *mbx = &hw->mbx;
3217         uint32_t msgbuf[2];
3218         s32 err;
3219
3220         /* After set vlan, vlan strip will also be enabled in igb driver*/
3221         msgbuf[0] = E1000_VF_SET_VLAN;
3222         msgbuf[1] = vid;
3223         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3224         if (on)
3225                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3226
3227         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3228         if (err)
3229                 goto mbx_err;
3230
3231         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3232         if (err)
3233                 goto mbx_err;
3234
3235         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3236         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3237                 err = -EINVAL;
3238
3239 mbx_err:
3240         return err;
3241 }
3242
3243 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3244 {
3245         struct e1000_hw *hw =
3246                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3247         struct e1000_vfta * shadow_vfta =
3248                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3249         int i = 0, j = 0, vfta = 0, mask = 1;
3250
3251         for (i = 0; i < IGB_VFTA_SIZE; i++){
3252                 vfta = shadow_vfta->vfta[i];
3253                 if(vfta){
3254                         mask = 1;
3255                         for (j = 0; j < 32; j++){
3256                                 if(vfta & mask)
3257                                         igbvf_set_vfta(hw,
3258                                                 (uint16_t)((i<<5)+j), on);
3259                                 mask<<=1;
3260                         }
3261                 }
3262         }
3263
3264 }
3265
3266 static int
3267 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3268 {
3269         struct e1000_hw *hw =
3270                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3271         struct e1000_vfta * shadow_vfta =
3272                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3273         uint32_t vid_idx = 0;
3274         uint32_t vid_bit = 0;
3275         int ret = 0;
3276
3277         PMD_INIT_FUNC_TRACE();
3278
3279         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3280         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3281         if(ret){
3282                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3283                 return ret;
3284         }
3285         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3286         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3287
3288         /*Save what we set and retore it after device reset*/
3289         if (on)
3290                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3291         else
3292                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3293
3294         return 0;
3295 }
3296
3297 static void
3298 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3299 {
3300         struct e1000_hw *hw =
3301                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3302
3303         /* index is not used by rar_set() */
3304         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3305 }
3306
3307
3308 static int
3309 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3310                         struct rte_eth_rss_reta_entry64 *reta_conf,
3311                         uint16_t reta_size)
3312 {
3313         uint8_t i, j, mask;
3314         uint32_t reta, r;
3315         uint16_t idx, shift;
3316         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3317
3318         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3319                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3320                         "(%d) doesn't match the number hardware can supported "
3321                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3322                 return -EINVAL;
3323         }
3324
3325         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3326                 idx = i / RTE_RETA_GROUP_SIZE;
3327                 shift = i % RTE_RETA_GROUP_SIZE;
3328                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3329                                                 IGB_4_BIT_MASK);
3330                 if (!mask)
3331                         continue;
3332                 if (mask == IGB_4_BIT_MASK)
3333                         r = 0;
3334                 else
3335                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3336                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3337                         if (mask & (0x1 << j))
3338                                 reta |= reta_conf[idx].reta[shift + j] <<
3339                                                         (CHAR_BIT * j);
3340                         else
3341                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3342                 }
3343                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3344         }
3345
3346         return 0;
3347 }
3348
3349 static int
3350 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3351                        struct rte_eth_rss_reta_entry64 *reta_conf,
3352                        uint16_t reta_size)
3353 {
3354         uint8_t i, j, mask;
3355         uint32_t reta;
3356         uint16_t idx, shift;
3357         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3358
3359         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3360                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3361                         "(%d) doesn't match the number hardware can supported "
3362                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3363                 return -EINVAL;
3364         }
3365
3366         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3367                 idx = i / RTE_RETA_GROUP_SIZE;
3368                 shift = i % RTE_RETA_GROUP_SIZE;
3369                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3370                                                 IGB_4_BIT_MASK);
3371                 if (!mask)
3372                         continue;
3373                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3374                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3375                         if (mask & (0x1 << j))
3376                                 reta_conf[idx].reta[shift + j] =
3377                                         ((reta >> (CHAR_BIT * j)) &
3378                                                 IGB_8_BIT_MASK);
3379                 }
3380         }
3381
3382         return 0;
3383 }
3384
3385 #define MAC_TYPE_FILTER_SUP(type)    do {\
3386         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3387                 (type) != e1000_82576)\
3388                 return -ENOTSUP;\
3389 } while (0)
3390
3391 static int
3392 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3393                         struct rte_eth_syn_filter *filter,
3394                         bool add)
3395 {
3396         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3397         uint32_t synqf, rfctl;
3398
3399         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3400                 return -EINVAL;
3401
3402         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3403
3404         if (add) {
3405                 if (synqf & E1000_SYN_FILTER_ENABLE)
3406                         return -EINVAL;
3407
3408                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3409                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3410
3411                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3412                 if (filter->hig_pri)
3413                         rfctl |= E1000_RFCTL_SYNQFP;
3414                 else
3415                         rfctl &= ~E1000_RFCTL_SYNQFP;
3416
3417                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3418         } else {
3419                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3420                         return -ENOENT;
3421                 synqf = 0;
3422         }
3423
3424         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3425         E1000_WRITE_FLUSH(hw);
3426         return 0;
3427 }
3428
3429 static int
3430 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3431                         struct rte_eth_syn_filter *filter)
3432 {
3433         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3434         uint32_t synqf, rfctl;
3435
3436         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3437         if (synqf & E1000_SYN_FILTER_ENABLE) {
3438                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3439                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3440                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3441                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3442                 return 0;
3443         }
3444
3445         return -ENOENT;
3446 }
3447
3448 static int
3449 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3450                         enum rte_filter_op filter_op,
3451                         void *arg)
3452 {
3453         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3454         int ret;
3455
3456         MAC_TYPE_FILTER_SUP(hw->mac.type);
3457
3458         if (filter_op == RTE_ETH_FILTER_NOP)
3459                 return 0;
3460
3461         if (arg == NULL) {
3462                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3463                             filter_op);
3464                 return -EINVAL;
3465         }
3466
3467         switch (filter_op) {
3468         case RTE_ETH_FILTER_ADD:
3469                 ret = eth_igb_syn_filter_set(dev,
3470                                 (struct rte_eth_syn_filter *)arg,
3471                                 TRUE);
3472                 break;
3473         case RTE_ETH_FILTER_DELETE:
3474                 ret = eth_igb_syn_filter_set(dev,
3475                                 (struct rte_eth_syn_filter *)arg,
3476                                 FALSE);
3477                 break;
3478         case RTE_ETH_FILTER_GET:
3479                 ret = eth_igb_syn_filter_get(dev,
3480                                 (struct rte_eth_syn_filter *)arg);
3481                 break;
3482         default:
3483                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3484                 ret = -EINVAL;
3485                 break;
3486         }
3487
3488         return ret;
3489 }
3490
3491 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3492         if ((type) != e1000_82580 && (type) != e1000_i350)\
3493                 return -ENOSYS; \
3494 } while (0)
3495
3496 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3497 static inline int
3498 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3499                         struct e1000_2tuple_filter_info *filter_info)
3500 {
3501         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3502                 return -EINVAL;
3503         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3504                 return -EINVAL;  /* filter index is out of range. */
3505         if (filter->tcp_flags > TCP_FLAG_ALL)
3506                 return -EINVAL;  /* flags is invalid. */
3507
3508         switch (filter->dst_port_mask) {
3509         case UINT16_MAX:
3510                 filter_info->dst_port_mask = 0;
3511                 filter_info->dst_port = filter->dst_port;
3512                 break;
3513         case 0:
3514                 filter_info->dst_port_mask = 1;
3515                 break;
3516         default:
3517                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3518                 return -EINVAL;
3519         }
3520
3521         switch (filter->proto_mask) {
3522         case UINT8_MAX:
3523                 filter_info->proto_mask = 0;
3524                 filter_info->proto = filter->proto;
3525                 break;
3526         case 0:
3527                 filter_info->proto_mask = 1;
3528                 break;
3529         default:
3530                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3531                 return -EINVAL;
3532         }
3533
3534         filter_info->priority = (uint8_t)filter->priority;
3535         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3536                 filter_info->tcp_flags = filter->tcp_flags;
3537         else
3538                 filter_info->tcp_flags = 0;
3539
3540         return 0;
3541 }
3542
3543 static inline struct e1000_2tuple_filter *
3544 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3545                         struct e1000_2tuple_filter_info *key)
3546 {
3547         struct e1000_2tuple_filter *it;
3548
3549         TAILQ_FOREACH(it, filter_list, entries) {
3550                 if (memcmp(key, &it->filter_info,
3551                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3552                         return it;
3553                 }
3554         }
3555         return NULL;
3556 }
3557
3558 /*
3559  * igb_add_2tuple_filter - add a 2tuple filter
3560  *
3561  * @param
3562  * dev: Pointer to struct rte_eth_dev.
3563  * ntuple_filter: ponter to the filter that will be added.
3564  *
3565  * @return
3566  *    - On success, zero.
3567  *    - On failure, a negative value.
3568  */
3569 static int
3570 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3571                         struct rte_eth_ntuple_filter *ntuple_filter)
3572 {
3573         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3574         struct e1000_filter_info *filter_info =
3575                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3576         struct e1000_2tuple_filter *filter;
3577         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3578         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3579         int i, ret;
3580
3581         filter = rte_zmalloc("e1000_2tuple_filter",
3582                         sizeof(struct e1000_2tuple_filter), 0);
3583         if (filter == NULL)
3584                 return -ENOMEM;
3585
3586         ret = ntuple_filter_to_2tuple(ntuple_filter,
3587                                       &filter->filter_info);
3588         if (ret < 0) {
3589                 rte_free(filter);
3590                 return ret;
3591         }
3592         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3593                                          &filter->filter_info) != NULL) {
3594                 PMD_DRV_LOG(ERR, "filter exists.");
3595                 rte_free(filter);
3596                 return -EEXIST;
3597         }
3598         filter->queue = ntuple_filter->queue;
3599
3600         /*
3601          * look for an unused 2tuple filter index,
3602          * and insert the filter to list.
3603          */
3604         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3605                 if (!(filter_info->twotuple_mask & (1 << i))) {
3606                         filter_info->twotuple_mask |= 1 << i;
3607                         filter->index = i;
3608                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3609                                           filter,
3610                                           entries);
3611                         break;
3612                 }
3613         }
3614         if (i >= E1000_MAX_TTQF_FILTERS) {
3615                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3616                 rte_free(filter);
3617                 return -ENOSYS;
3618         }
3619
3620         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3621         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3622                 imir |= E1000_IMIR_PORT_BP;
3623         else
3624                 imir &= ~E1000_IMIR_PORT_BP;
3625
3626         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3627
3628         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3629         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3630         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3631         if (filter->filter_info.proto_mask == 0)
3632                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3633
3634         /* tcp flags bits setting. */
3635         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3636                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3637                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3638                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3639                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3640                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3641                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3642                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3643                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3644                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3645                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3646                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3647                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3648         } else
3649                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3650         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3651         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3652         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3653         return 0;
3654 }
3655
3656 /*
3657  * igb_remove_2tuple_filter - remove a 2tuple filter
3658  *
3659  * @param
3660  * dev: Pointer to struct rte_eth_dev.
3661  * ntuple_filter: ponter to the filter that will be removed.
3662  *
3663  * @return
3664  *    - On success, zero.
3665  *    - On failure, a negative value.
3666  */
3667 static int
3668 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3669                         struct rte_eth_ntuple_filter *ntuple_filter)
3670 {
3671         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3672         struct e1000_filter_info *filter_info =
3673                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3674         struct e1000_2tuple_filter_info filter_2tuple;
3675         struct e1000_2tuple_filter *filter;
3676         int ret;
3677
3678         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3679         ret = ntuple_filter_to_2tuple(ntuple_filter,
3680                                       &filter_2tuple);
3681         if (ret < 0)
3682                 return ret;
3683
3684         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3685                                          &filter_2tuple);
3686         if (filter == NULL) {
3687                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3688                 return -ENOENT;
3689         }
3690
3691         filter_info->twotuple_mask &= ~(1 << filter->index);
3692         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3693         rte_free(filter);
3694
3695         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3696         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3697         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3698         return 0;
3699 }
3700
3701 static inline struct e1000_flex_filter *
3702 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3703                         struct e1000_flex_filter_info *key)
3704 {
3705         struct e1000_flex_filter *it;
3706
3707         TAILQ_FOREACH(it, filter_list, entries) {
3708                 if (memcmp(key, &it->filter_info,
3709                         sizeof(struct e1000_flex_filter_info)) == 0)
3710                         return it;
3711         }
3712
3713         return NULL;
3714 }
3715
3716 static int
3717 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3718                         struct rte_eth_flex_filter *filter,
3719                         bool add)
3720 {
3721         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3722         struct e1000_filter_info *filter_info =
3723                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3724         struct e1000_flex_filter *flex_filter, *it;
3725         uint32_t wufc, queueing, mask;
3726         uint32_t reg_off;
3727         uint8_t shift, i, j = 0;
3728
3729         flex_filter = rte_zmalloc("e1000_flex_filter",
3730                         sizeof(struct e1000_flex_filter), 0);
3731         if (flex_filter == NULL)
3732                 return -ENOMEM;
3733
3734         flex_filter->filter_info.len = filter->len;
3735         flex_filter->filter_info.priority = filter->priority;
3736         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3737         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3738                 mask = 0;
3739                 /* reverse bits in flex filter's mask*/
3740                 for (shift = 0; shift < CHAR_BIT; shift++) {
3741                         if (filter->mask[i] & (0x01 << shift))
3742                                 mask |= (0x80 >> shift);
3743                 }
3744                 flex_filter->filter_info.mask[i] = mask;
3745         }
3746
3747         wufc = E1000_READ_REG(hw, E1000_WUFC);
3748         if (flex_filter->index < E1000_MAX_FHFT)
3749                 reg_off = E1000_FHFT(flex_filter->index);
3750         else
3751                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3752
3753         if (add) {
3754                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3755                                 &flex_filter->filter_info) != NULL) {
3756                         PMD_DRV_LOG(ERR, "filter exists.");
3757                         rte_free(flex_filter);
3758                         return -EEXIST;
3759                 }
3760                 flex_filter->queue = filter->queue;
3761                 /*
3762                  * look for an unused flex filter index
3763                  * and insert the filter into the list.
3764                  */
3765                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3766                         if (!(filter_info->flex_mask & (1 << i))) {
3767                                 filter_info->flex_mask |= 1 << i;
3768                                 flex_filter->index = i;
3769                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3770                                         flex_filter,
3771                                         entries);
3772                                 break;
3773                         }
3774                 }
3775                 if (i >= E1000_MAX_FLEX_FILTERS) {
3776                         PMD_DRV_LOG(ERR, "flex filters are full.");
3777                         rte_free(flex_filter);
3778                         return -ENOSYS;
3779                 }
3780
3781                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3782                                 (E1000_WUFC_FLX0 << flex_filter->index));
3783                 queueing = filter->len |
3784                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3785                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3786                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3787                                 queueing);
3788                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3789                         E1000_WRITE_REG(hw, reg_off,
3790                                         flex_filter->filter_info.dwords[j]);
3791                         reg_off += sizeof(uint32_t);
3792                         E1000_WRITE_REG(hw, reg_off,
3793                                         flex_filter->filter_info.dwords[++j]);
3794                         reg_off += sizeof(uint32_t);
3795                         E1000_WRITE_REG(hw, reg_off,
3796                                 (uint32_t)flex_filter->filter_info.mask[i]);
3797                         reg_off += sizeof(uint32_t) * 2;
3798                         ++j;
3799                 }
3800         } else {
3801                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3802                                 &flex_filter->filter_info);
3803                 if (it == NULL) {
3804                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3805                         rte_free(flex_filter);
3806                         return -ENOENT;
3807                 }
3808
3809                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3810                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3811                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3812                         (~(E1000_WUFC_FLX0 << it->index)));
3813
3814                 filter_info->flex_mask &= ~(1 << it->index);
3815                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3816                 rte_free(it);
3817                 rte_free(flex_filter);
3818         }
3819
3820         return 0;
3821 }
3822
3823 static int
3824 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3825                         struct rte_eth_flex_filter *filter)
3826 {
3827         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3828         struct e1000_filter_info *filter_info =
3829                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3830         struct e1000_flex_filter flex_filter, *it;
3831         uint32_t wufc, queueing, wufc_en = 0;
3832
3833         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3834         flex_filter.filter_info.len = filter->len;
3835         flex_filter.filter_info.priority = filter->priority;
3836         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3837         memcpy(flex_filter.filter_info.mask, filter->mask,
3838                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3839
3840         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3841                                 &flex_filter.filter_info);
3842         if (it == NULL) {
3843                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3844                 return -ENOENT;
3845         }
3846
3847         wufc = E1000_READ_REG(hw, E1000_WUFC);
3848         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3849
3850         if ((wufc & wufc_en) == wufc_en) {
3851                 uint32_t reg_off = 0;
3852                 if (it->index < E1000_MAX_FHFT)
3853                         reg_off = E1000_FHFT(it->index);
3854                 else
3855                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3856
3857                 queueing = E1000_READ_REG(hw,
3858                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3859                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3860                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3861                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3862                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3863                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3864                 return 0;
3865         }
3866         return -ENOENT;
3867 }
3868
3869 static int
3870 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3871                         enum rte_filter_op filter_op,
3872                         void *arg)
3873 {
3874         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3875         struct rte_eth_flex_filter *filter;
3876         int ret = 0;
3877
3878         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3879
3880         if (filter_op == RTE_ETH_FILTER_NOP)
3881                 return ret;
3882
3883         if (arg == NULL) {
3884                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3885                             filter_op);
3886                 return -EINVAL;
3887         }
3888
3889         filter = (struct rte_eth_flex_filter *)arg;
3890         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3891             || filter->len % sizeof(uint64_t) != 0) {
3892                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3893                 return -EINVAL;
3894         }
3895         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3896                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3897                 return -EINVAL;
3898         }
3899
3900         switch (filter_op) {
3901         case RTE_ETH_FILTER_ADD:
3902                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3903                 break;
3904         case RTE_ETH_FILTER_DELETE:
3905                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3906                 break;
3907         case RTE_ETH_FILTER_GET:
3908                 ret = eth_igb_get_flex_filter(dev, filter);
3909                 break;
3910         default:
3911                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3912                 ret = -EINVAL;
3913                 break;
3914         }
3915
3916         return ret;
3917 }
3918
3919 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3920 static inline int
3921 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3922                         struct e1000_5tuple_filter_info *filter_info)
3923 {
3924         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3925                 return -EINVAL;
3926         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3927                 return -EINVAL;  /* filter index is out of range. */
3928         if (filter->tcp_flags > TCP_FLAG_ALL)
3929                 return -EINVAL;  /* flags is invalid. */
3930
3931         switch (filter->dst_ip_mask) {
3932         case UINT32_MAX:
3933                 filter_info->dst_ip_mask = 0;
3934                 filter_info->dst_ip = filter->dst_ip;
3935                 break;
3936         case 0:
3937                 filter_info->dst_ip_mask = 1;
3938                 break;
3939         default:
3940                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3941                 return -EINVAL;
3942         }
3943
3944         switch (filter->src_ip_mask) {
3945         case UINT32_MAX:
3946                 filter_info->src_ip_mask = 0;
3947                 filter_info->src_ip = filter->src_ip;
3948                 break;
3949         case 0:
3950                 filter_info->src_ip_mask = 1;
3951                 break;
3952         default:
3953                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3954                 return -EINVAL;
3955         }
3956
3957         switch (filter->dst_port_mask) {
3958         case UINT16_MAX:
3959                 filter_info->dst_port_mask = 0;
3960                 filter_info->dst_port = filter->dst_port;
3961                 break;
3962         case 0:
3963                 filter_info->dst_port_mask = 1;
3964                 break;
3965         default:
3966                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3967                 return -EINVAL;
3968         }
3969
3970         switch (filter->src_port_mask) {
3971         case UINT16_MAX:
3972                 filter_info->src_port_mask = 0;
3973                 filter_info->src_port = filter->src_port;
3974                 break;
3975         case 0:
3976                 filter_info->src_port_mask = 1;
3977                 break;
3978         default:
3979                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3980                 return -EINVAL;
3981         }
3982
3983         switch (filter->proto_mask) {
3984         case UINT8_MAX:
3985                 filter_info->proto_mask = 0;
3986                 filter_info->proto = filter->proto;
3987                 break;
3988         case 0:
3989                 filter_info->proto_mask = 1;
3990                 break;
3991         default:
3992                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3993                 return -EINVAL;
3994         }
3995
3996         filter_info->priority = (uint8_t)filter->priority;
3997         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3998                 filter_info->tcp_flags = filter->tcp_flags;
3999         else
4000                 filter_info->tcp_flags = 0;
4001
4002         return 0;
4003 }
4004
4005 static inline struct e1000_5tuple_filter *
4006 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4007                         struct e1000_5tuple_filter_info *key)
4008 {
4009         struct e1000_5tuple_filter *it;
4010
4011         TAILQ_FOREACH(it, filter_list, entries) {
4012                 if (memcmp(key, &it->filter_info,
4013                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4014                         return it;
4015                 }
4016         }
4017         return NULL;
4018 }
4019
4020 /*
4021  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4022  *
4023  * @param
4024  * dev: Pointer to struct rte_eth_dev.
4025  * ntuple_filter: ponter to the filter that will be added.
4026  *
4027  * @return
4028  *    - On success, zero.
4029  *    - On failure, a negative value.
4030  */
4031 static int
4032 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4033                         struct rte_eth_ntuple_filter *ntuple_filter)
4034 {
4035         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4036         struct e1000_filter_info *filter_info =
4037                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4038         struct e1000_5tuple_filter *filter;
4039         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4040         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4041         uint8_t i;
4042         int ret;
4043
4044         filter = rte_zmalloc("e1000_5tuple_filter",
4045                         sizeof(struct e1000_5tuple_filter), 0);
4046         if (filter == NULL)
4047                 return -ENOMEM;
4048
4049         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4050                                             &filter->filter_info);
4051         if (ret < 0) {
4052                 rte_free(filter);
4053                 return ret;
4054         }
4055
4056         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4057                                          &filter->filter_info) != NULL) {
4058                 PMD_DRV_LOG(ERR, "filter exists.");
4059                 rte_free(filter);
4060                 return -EEXIST;
4061         }
4062         filter->queue = ntuple_filter->queue;
4063
4064         /*
4065          * look for an unused 5tuple filter index,
4066          * and insert the filter to list.
4067          */
4068         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4069                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4070                         filter_info->fivetuple_mask |= 1 << i;
4071                         filter->index = i;
4072                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4073                                           filter,
4074                                           entries);
4075                         break;
4076                 }
4077         }
4078         if (i >= E1000_MAX_FTQF_FILTERS) {
4079                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4080                 rte_free(filter);
4081                 return -ENOSYS;
4082         }
4083
4084         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4085         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4086                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4087         if (filter->filter_info.dst_ip_mask == 0)
4088                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4089         if (filter->filter_info.src_port_mask == 0)
4090                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4091         if (filter->filter_info.proto_mask == 0)
4092                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4093         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4094                 E1000_FTQF_QUEUE_MASK;
4095         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4096         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4097         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4098         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4099
4100         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4101         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4102
4103         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4104         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4105                 imir |= E1000_IMIR_PORT_BP;
4106         else
4107                 imir &= ~E1000_IMIR_PORT_BP;
4108         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4109
4110         /* tcp flags bits setting. */
4111         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4112                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4113                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4114                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4115                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4116                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4117                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4118                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4119                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4120                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4121                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4122                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4123                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4124         } else
4125                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4126         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4127         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4128         return 0;
4129 }
4130
4131 /*
4132  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4133  *
4134  * @param
4135  * dev: Pointer to struct rte_eth_dev.
4136  * ntuple_filter: ponter to the filter that will be removed.
4137  *
4138  * @return
4139  *    - On success, zero.
4140  *    - On failure, a negative value.
4141  */
4142 static int
4143 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4144                                 struct rte_eth_ntuple_filter *ntuple_filter)
4145 {
4146         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4147         struct e1000_filter_info *filter_info =
4148                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4149         struct e1000_5tuple_filter_info filter_5tuple;
4150         struct e1000_5tuple_filter *filter;
4151         int ret;
4152
4153         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4154         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4155                                             &filter_5tuple);
4156         if (ret < 0)
4157                 return ret;
4158
4159         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4160                                          &filter_5tuple);
4161         if (filter == NULL) {
4162                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4163                 return -ENOENT;
4164         }
4165
4166         filter_info->fivetuple_mask &= ~(1 << filter->index);
4167         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4168         rte_free(filter);
4169
4170         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4171                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4172         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4173         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4174         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4175         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4176         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4177         return 0;
4178 }
4179
4180 static int
4181 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4182 {
4183         uint32_t rctl;
4184         struct e1000_hw *hw;
4185         struct rte_eth_dev_info dev_info;
4186         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4187                                      VLAN_TAG_SIZE);
4188
4189         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4190
4191 #ifdef RTE_LIBRTE_82571_SUPPORT
4192         /* XXX: not bigger than max_rx_pktlen */
4193         if (hw->mac.type == e1000_82571)
4194                 return -ENOTSUP;
4195 #endif
4196         eth_igb_infos_get(dev, &dev_info);
4197
4198         /* check that mtu is within the allowed range */
4199         if ((mtu < ETHER_MIN_MTU) ||
4200             (frame_size > dev_info.max_rx_pktlen))
4201                 return -EINVAL;
4202
4203         /* refuse mtu that requires the support of scattered packets when this
4204          * feature has not been enabled before. */
4205         if (!dev->data->scattered_rx &&
4206             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4207                 return -EINVAL;
4208
4209         rctl = E1000_READ_REG(hw, E1000_RCTL);
4210
4211         /* switch to jumbo mode if needed */
4212         if (frame_size > ETHER_MAX_LEN) {
4213                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4214                 rctl |= E1000_RCTL_LPE;
4215         } else {
4216                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4217                 rctl &= ~E1000_RCTL_LPE;
4218         }
4219         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4220
4221         /* update max frame size */
4222         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4223
4224         E1000_WRITE_REG(hw, E1000_RLPML,
4225                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4226
4227         return 0;
4228 }
4229
4230 /*
4231  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4232  *
4233  * @param
4234  * dev: Pointer to struct rte_eth_dev.
4235  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4236  * add: if true, add filter, if false, remove filter
4237  *
4238  * @return
4239  *    - On success, zero.
4240  *    - On failure, a negative value.
4241  */
4242 static int
4243 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4244                         struct rte_eth_ntuple_filter *ntuple_filter,
4245                         bool add)
4246 {
4247         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4248         int ret;
4249
4250         switch (ntuple_filter->flags) {
4251         case RTE_5TUPLE_FLAGS:
4252         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4253                 if (hw->mac.type != e1000_82576)
4254                         return -ENOTSUP;
4255                 if (add)
4256                         ret = igb_add_5tuple_filter_82576(dev,
4257                                                           ntuple_filter);
4258                 else
4259                         ret = igb_remove_5tuple_filter_82576(dev,
4260                                                              ntuple_filter);
4261                 break;
4262         case RTE_2TUPLE_FLAGS:
4263         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4264                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4265                         return -ENOTSUP;
4266                 if (add)
4267                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4268                 else
4269                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4270                 break;
4271         default:
4272                 ret = -EINVAL;
4273                 break;
4274         }
4275
4276         return ret;
4277 }
4278
4279 /*
4280  * igb_get_ntuple_filter - get a ntuple filter
4281  *
4282  * @param
4283  * dev: Pointer to struct rte_eth_dev.
4284  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4285  *
4286  * @return
4287  *    - On success, zero.
4288  *    - On failure, a negative value.
4289  */
4290 static int
4291 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4292                         struct rte_eth_ntuple_filter *ntuple_filter)
4293 {
4294         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4295         struct e1000_filter_info *filter_info =
4296                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4297         struct e1000_5tuple_filter_info filter_5tuple;
4298         struct e1000_2tuple_filter_info filter_2tuple;
4299         struct e1000_5tuple_filter *p_5tuple_filter;
4300         struct e1000_2tuple_filter *p_2tuple_filter;
4301         int ret;
4302
4303         switch (ntuple_filter->flags) {
4304         case RTE_5TUPLE_FLAGS:
4305         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4306                 if (hw->mac.type != e1000_82576)
4307                         return -ENOTSUP;
4308                 memset(&filter_5tuple,
4309                         0,
4310                         sizeof(struct e1000_5tuple_filter_info));
4311                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4312                                                     &filter_5tuple);
4313                 if (ret < 0)
4314                         return ret;
4315                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4316                                         &filter_info->fivetuple_list,
4317                                         &filter_5tuple);
4318                 if (p_5tuple_filter == NULL) {
4319                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4320                         return -ENOENT;
4321                 }
4322                 ntuple_filter->queue = p_5tuple_filter->queue;
4323                 break;
4324         case RTE_2TUPLE_FLAGS:
4325         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4326                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4327                         return -ENOTSUP;
4328                 memset(&filter_2tuple,
4329                         0,
4330                         sizeof(struct e1000_2tuple_filter_info));
4331                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4332                 if (ret < 0)
4333                         return ret;
4334                 p_2tuple_filter = igb_2tuple_filter_lookup(
4335                                         &filter_info->twotuple_list,
4336                                         &filter_2tuple);
4337                 if (p_2tuple_filter == NULL) {
4338                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4339                         return -ENOENT;
4340                 }
4341                 ntuple_filter->queue = p_2tuple_filter->queue;
4342                 break;
4343         default:
4344                 ret = -EINVAL;
4345                 break;
4346         }
4347
4348         return 0;
4349 }
4350
4351 /*
4352  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4353  * @dev: pointer to rte_eth_dev structure
4354  * @filter_op:operation will be taken.
4355  * @arg: a pointer to specific structure corresponding to the filter_op
4356  */
4357 static int
4358 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4359                                 enum rte_filter_op filter_op,
4360                                 void *arg)
4361 {
4362         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4363         int ret;
4364
4365         MAC_TYPE_FILTER_SUP(hw->mac.type);
4366
4367         if (filter_op == RTE_ETH_FILTER_NOP)
4368                 return 0;
4369
4370         if (arg == NULL) {
4371                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4372                             filter_op);
4373                 return -EINVAL;
4374         }
4375
4376         switch (filter_op) {
4377         case RTE_ETH_FILTER_ADD:
4378                 ret = igb_add_del_ntuple_filter(dev,
4379                         (struct rte_eth_ntuple_filter *)arg,
4380                         TRUE);
4381                 break;
4382         case RTE_ETH_FILTER_DELETE:
4383                 ret = igb_add_del_ntuple_filter(dev,
4384                         (struct rte_eth_ntuple_filter *)arg,
4385                         FALSE);
4386                 break;
4387         case RTE_ETH_FILTER_GET:
4388                 ret = igb_get_ntuple_filter(dev,
4389                         (struct rte_eth_ntuple_filter *)arg);
4390                 break;
4391         default:
4392                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4393                 ret = -EINVAL;
4394                 break;
4395         }
4396         return ret;
4397 }
4398
4399 static inline int
4400 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4401                         uint16_t ethertype)
4402 {
4403         int i;
4404
4405         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4406                 if (filter_info->ethertype_filters[i] == ethertype &&
4407                     (filter_info->ethertype_mask & (1 << i)))
4408                         return i;
4409         }
4410         return -1;
4411 }
4412
4413 static inline int
4414 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4415                         uint16_t ethertype)
4416 {
4417         int i;
4418
4419         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4420                 if (!(filter_info->ethertype_mask & (1 << i))) {
4421                         filter_info->ethertype_mask |= 1 << i;
4422                         filter_info->ethertype_filters[i] = ethertype;
4423                         return i;
4424                 }
4425         }
4426         return -1;
4427 }
4428
4429 static inline int
4430 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4431                         uint8_t idx)
4432 {
4433         if (idx >= E1000_MAX_ETQF_FILTERS)
4434                 return -1;
4435         filter_info->ethertype_mask &= ~(1 << idx);
4436         filter_info->ethertype_filters[idx] = 0;
4437         return idx;
4438 }
4439
4440
4441 static int
4442 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4443                         struct rte_eth_ethertype_filter *filter,
4444                         bool add)
4445 {
4446         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4447         struct e1000_filter_info *filter_info =
4448                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4449         uint32_t etqf = 0;
4450         int ret;
4451
4452         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4453                 filter->ether_type == ETHER_TYPE_IPv6) {
4454                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4455                         " ethertype filter.", filter->ether_type);
4456                 return -EINVAL;
4457         }
4458
4459         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4460                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4461                 return -EINVAL;
4462         }
4463         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4464                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4465                 return -EINVAL;
4466         }
4467
4468         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4469         if (ret >= 0 && add) {
4470                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4471                             filter->ether_type);
4472                 return -EEXIST;
4473         }
4474         if (ret < 0 && !add) {
4475                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4476                             filter->ether_type);
4477                 return -ENOENT;
4478         }
4479
4480         if (add) {
4481                 ret = igb_ethertype_filter_insert(filter_info,
4482                         filter->ether_type);
4483                 if (ret < 0) {
4484                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4485                         return -ENOSYS;
4486                 }
4487
4488                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4489                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4490                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4491         } else {
4492                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4493                 if (ret < 0)
4494                         return -ENOSYS;
4495         }
4496         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4497         E1000_WRITE_FLUSH(hw);
4498
4499         return 0;
4500 }
4501
4502 static int
4503 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4504                         struct rte_eth_ethertype_filter *filter)
4505 {
4506         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4507         struct e1000_filter_info *filter_info =
4508                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4509         uint32_t etqf;
4510         int ret;
4511
4512         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4513         if (ret < 0) {
4514                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4515                             filter->ether_type);
4516                 return -ENOENT;
4517         }
4518
4519         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4520         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4521                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4522                 filter->flags = 0;
4523                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4524                                 E1000_ETQF_QUEUE_SHIFT;
4525                 return 0;
4526         }
4527
4528         return -ENOENT;
4529 }
4530
4531 /*
4532  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4533  * @dev: pointer to rte_eth_dev structure
4534  * @filter_op:operation will be taken.
4535  * @arg: a pointer to specific structure corresponding to the filter_op
4536  */
4537 static int
4538 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4539                                 enum rte_filter_op filter_op,
4540                                 void *arg)
4541 {
4542         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4543         int ret;
4544
4545         MAC_TYPE_FILTER_SUP(hw->mac.type);
4546
4547         if (filter_op == RTE_ETH_FILTER_NOP)
4548                 return 0;
4549
4550         if (arg == NULL) {
4551                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4552                             filter_op);
4553                 return -EINVAL;
4554         }
4555
4556         switch (filter_op) {
4557         case RTE_ETH_FILTER_ADD:
4558                 ret = igb_add_del_ethertype_filter(dev,
4559                         (struct rte_eth_ethertype_filter *)arg,
4560                         TRUE);
4561                 break;
4562         case RTE_ETH_FILTER_DELETE:
4563                 ret = igb_add_del_ethertype_filter(dev,
4564                         (struct rte_eth_ethertype_filter *)arg,
4565                         FALSE);
4566                 break;
4567         case RTE_ETH_FILTER_GET:
4568                 ret = igb_get_ethertype_filter(dev,
4569                         (struct rte_eth_ethertype_filter *)arg);
4570                 break;
4571         default:
4572                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4573                 ret = -EINVAL;
4574                 break;
4575         }
4576         return ret;
4577 }
4578
4579 static int
4580 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4581                      enum rte_filter_type filter_type,
4582                      enum rte_filter_op filter_op,
4583                      void *arg)
4584 {
4585         int ret = -EINVAL;
4586
4587         switch (filter_type) {
4588         case RTE_ETH_FILTER_NTUPLE:
4589                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4590                 break;
4591         case RTE_ETH_FILTER_ETHERTYPE:
4592                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4593                 break;
4594         case RTE_ETH_FILTER_SYN:
4595                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4596                 break;
4597         case RTE_ETH_FILTER_FLEXIBLE:
4598                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4599                 break;
4600         default:
4601                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4602                                                         filter_type);
4603                 break;
4604         }
4605
4606         return ret;
4607 }
4608
4609 static int
4610 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4611                          struct ether_addr *mc_addr_set,
4612                          uint32_t nb_mc_addr)
4613 {
4614         struct e1000_hw *hw;
4615
4616         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4617         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4618         return 0;
4619 }
4620
4621 static uint64_t
4622 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4623 {
4624         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4625         uint64_t systime_cycles;
4626
4627         switch (hw->mac.type) {
4628         case e1000_i210:
4629         case e1000_i211:
4630                 /*
4631                  * Need to read System Time Residue Register to be able
4632                  * to read the other two registers.
4633                  */
4634                 E1000_READ_REG(hw, E1000_SYSTIMR);
4635                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4636                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4637                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4638                                 * NSEC_PER_SEC;
4639                 break;
4640         case e1000_82580:
4641         case e1000_i350:
4642         case e1000_i354:
4643                 /*
4644                  * Need to read System Time Residue Register to be able
4645                  * to read the other two registers.
4646                  */
4647                 E1000_READ_REG(hw, E1000_SYSTIMR);
4648                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4649                 /* Only the 8 LSB are valid. */
4650                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4651                                 & 0xff) << 32;
4652                 break;
4653         default:
4654                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4655                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4656                                 << 32;
4657                 break;
4658         }
4659
4660         return systime_cycles;
4661 }
4662
4663 static uint64_t
4664 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4665 {
4666         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4667         uint64_t rx_tstamp_cycles;
4668
4669         switch (hw->mac.type) {
4670         case e1000_i210:
4671         case e1000_i211:
4672                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4673                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4674                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4675                                 * NSEC_PER_SEC;
4676                 break;
4677         case e1000_82580:
4678         case e1000_i350:
4679         case e1000_i354:
4680                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4681                 /* Only the 8 LSB are valid. */
4682                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4683                                 & 0xff) << 32;
4684                 break;
4685         default:
4686                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4687                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4688                                 << 32;
4689                 break;
4690         }
4691
4692         return rx_tstamp_cycles;
4693 }
4694
4695 static uint64_t
4696 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4697 {
4698         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4699         uint64_t tx_tstamp_cycles;
4700
4701         switch (hw->mac.type) {
4702         case e1000_i210:
4703         case e1000_i211:
4704                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4705                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4706                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4707                                 * NSEC_PER_SEC;
4708                 break;
4709         case e1000_82580:
4710         case e1000_i350:
4711         case e1000_i354:
4712                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4713                 /* Only the 8 LSB are valid. */
4714                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4715                                 & 0xff) << 32;
4716                 break;
4717         default:
4718                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4719                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4720                                 << 32;
4721                 break;
4722         }
4723
4724         return tx_tstamp_cycles;
4725 }
4726
4727 static void
4728 igb_start_timecounters(struct rte_eth_dev *dev)
4729 {
4730         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4731         struct e1000_adapter *adapter =
4732                 (struct e1000_adapter *)dev->data->dev_private;
4733         uint32_t incval = 1;
4734         uint32_t shift = 0;
4735         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4736
4737         switch (hw->mac.type) {
4738         case e1000_82580:
4739         case e1000_i350:
4740         case e1000_i354:
4741                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4742                 mask = (1ULL << 40) - 1;
4743                 /* fall-through */
4744         case e1000_i210:
4745         case e1000_i211:
4746                 /*
4747                  * Start incrementing the register
4748                  * used to timestamp PTP packets.
4749                  */
4750                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4751                 break;
4752         case e1000_82576:
4753                 incval = E1000_INCVALUE_82576;
4754                 shift = IGB_82576_TSYNC_SHIFT;
4755                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4756                                 E1000_INCPERIOD_82576 | incval);
4757                 break;
4758         default:
4759                 /* Not supported */
4760                 return;
4761         }
4762
4763         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4764         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4765         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4766
4767         adapter->systime_tc.cc_mask = mask;
4768         adapter->systime_tc.cc_shift = shift;
4769         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4770
4771         adapter->rx_tstamp_tc.cc_mask = mask;
4772         adapter->rx_tstamp_tc.cc_shift = shift;
4773         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4774
4775         adapter->tx_tstamp_tc.cc_mask = mask;
4776         adapter->tx_tstamp_tc.cc_shift = shift;
4777         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4778 }
4779
4780 static int
4781 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4782 {
4783         struct e1000_adapter *adapter =
4784                         (struct e1000_adapter *)dev->data->dev_private;
4785
4786         adapter->systime_tc.nsec += delta;
4787         adapter->rx_tstamp_tc.nsec += delta;
4788         adapter->tx_tstamp_tc.nsec += delta;
4789
4790         return 0;
4791 }
4792
4793 static int
4794 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4795 {
4796         uint64_t ns;
4797         struct e1000_adapter *adapter =
4798                         (struct e1000_adapter *)dev->data->dev_private;
4799
4800         ns = rte_timespec_to_ns(ts);
4801
4802         /* Set the timecounters to a new value. */
4803         adapter->systime_tc.nsec = ns;
4804         adapter->rx_tstamp_tc.nsec = ns;
4805         adapter->tx_tstamp_tc.nsec = ns;
4806
4807         return 0;
4808 }
4809
4810 static int
4811 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4812 {
4813         uint64_t ns, systime_cycles;
4814         struct e1000_adapter *adapter =
4815                         (struct e1000_adapter *)dev->data->dev_private;
4816
4817         systime_cycles = igb_read_systime_cyclecounter(dev);
4818         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4819         *ts = rte_ns_to_timespec(ns);
4820
4821         return 0;
4822 }
4823
4824 static int
4825 igb_timesync_enable(struct rte_eth_dev *dev)
4826 {
4827         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4828         uint32_t tsync_ctl;
4829         uint32_t tsauxc;
4830
4831         /* Stop the timesync system time. */
4832         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4833         /* Reset the timesync system time value. */
4834         switch (hw->mac.type) {
4835         case e1000_82580:
4836         case e1000_i350:
4837         case e1000_i354:
4838         case e1000_i210:
4839         case e1000_i211:
4840                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4841                 /* fall-through */
4842         case e1000_82576:
4843                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4844                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4845                 break;
4846         default:
4847                 /* Not supported. */
4848                 return -ENOTSUP;
4849         }
4850
4851         /* Enable system time for it isn't on by default. */
4852         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4853         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4854         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4855
4856         igb_start_timecounters(dev);
4857
4858         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4859         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4860                         (ETHER_TYPE_1588 |
4861                          E1000_ETQF_FILTER_ENABLE |
4862                          E1000_ETQF_1588));
4863
4864         /* Enable timestamping of received PTP packets. */
4865         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4866         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4867         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4868
4869         /* Enable Timestamping of transmitted PTP packets. */
4870         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4871         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4872         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4873
4874         return 0;
4875 }
4876
4877 static int
4878 igb_timesync_disable(struct rte_eth_dev *dev)
4879 {
4880         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4881         uint32_t tsync_ctl;
4882
4883         /* Disable timestamping of transmitted PTP packets. */
4884         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4885         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4886         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4887
4888         /* Disable timestamping of received PTP packets. */
4889         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4890         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4891         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4892
4893         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4894         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4895
4896         /* Stop incrementating the System Time registers. */
4897         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4898
4899         return 0;
4900 }
4901
4902 static int
4903 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4904                                struct timespec *timestamp,
4905                                uint32_t flags __rte_unused)
4906 {
4907         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4908         struct e1000_adapter *adapter =
4909                         (struct e1000_adapter *)dev->data->dev_private;
4910         uint32_t tsync_rxctl;
4911         uint64_t rx_tstamp_cycles;
4912         uint64_t ns;
4913
4914         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4915         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4916                 return -EINVAL;
4917
4918         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4919         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4920         *timestamp = rte_ns_to_timespec(ns);
4921
4922         return  0;
4923 }
4924
4925 static int
4926 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4927                                struct timespec *timestamp)
4928 {
4929         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4930         struct e1000_adapter *adapter =
4931                         (struct e1000_adapter *)dev->data->dev_private;
4932         uint32_t tsync_txctl;
4933         uint64_t tx_tstamp_cycles;
4934         uint64_t ns;
4935
4936         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4937         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4938                 return -EINVAL;
4939
4940         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4941         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4942         *timestamp = rte_ns_to_timespec(ns);
4943
4944         return  0;
4945 }
4946
4947 static int
4948 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4949 {
4950         int count = 0;
4951         int g_ind = 0;
4952         const struct reg_info *reg_group;
4953
4954         while ((reg_group = igb_regs[g_ind++]))
4955                 count += igb_reg_group_count(reg_group);
4956
4957         return count;
4958 }
4959
4960 static int
4961 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4962 {
4963         int count = 0;
4964         int g_ind = 0;
4965         const struct reg_info *reg_group;
4966
4967         while ((reg_group = igbvf_regs[g_ind++]))
4968                 count += igb_reg_group_count(reg_group);
4969
4970         return count;
4971 }
4972
4973 static int
4974 eth_igb_get_regs(struct rte_eth_dev *dev,
4975         struct rte_dev_reg_info *regs)
4976 {
4977         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4978         uint32_t *data = regs->data;
4979         int g_ind = 0;
4980         int count = 0;
4981         const struct reg_info *reg_group;
4982
4983         if (data == NULL) {
4984                 regs->length = eth_igb_get_reg_length(dev);
4985                 regs->width = sizeof(uint32_t);
4986                 return 0;
4987         }
4988
4989         /* Support only full register dump */
4990         if ((regs->length == 0) ||
4991             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4992                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4993                         hw->device_id;
4994                 while ((reg_group = igb_regs[g_ind++]))
4995                         count += igb_read_regs_group(dev, &data[count],
4996                                                         reg_group);
4997                 return 0;
4998         }
4999
5000         return -ENOTSUP;
5001 }
5002
5003 static int
5004 igbvf_get_regs(struct rte_eth_dev *dev,
5005         struct rte_dev_reg_info *regs)
5006 {
5007         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5008         uint32_t *data = regs->data;
5009         int g_ind = 0;
5010         int count = 0;
5011         const struct reg_info *reg_group;
5012
5013         if (data == NULL) {
5014                 regs->length = igbvf_get_reg_length(dev);
5015                 regs->width = sizeof(uint32_t);
5016                 return 0;
5017         }
5018
5019         /* Support only full register dump */
5020         if ((regs->length == 0) ||
5021             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5022                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5023                         hw->device_id;
5024                 while ((reg_group = igbvf_regs[g_ind++]))
5025                         count += igb_read_regs_group(dev, &data[count],
5026                                                         reg_group);
5027                 return 0;
5028         }
5029
5030         return -ENOTSUP;
5031 }
5032
5033 static int
5034 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5035 {
5036         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5037
5038         /* Return unit is byte count */
5039         return hw->nvm.word_size * 2;
5040 }
5041
5042 static int
5043 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5044         struct rte_dev_eeprom_info *in_eeprom)
5045 {
5046         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5047         struct e1000_nvm_info *nvm = &hw->nvm;
5048         uint16_t *data = in_eeprom->data;
5049         int first, length;
5050
5051         first = in_eeprom->offset >> 1;
5052         length = in_eeprom->length >> 1;
5053         if ((first >= hw->nvm.word_size) ||
5054             ((first + length) >= hw->nvm.word_size))
5055                 return -EINVAL;
5056
5057         in_eeprom->magic = hw->vendor_id |
5058                 ((uint32_t)hw->device_id << 16);
5059
5060         if ((nvm->ops.read) == NULL)
5061                 return -ENOTSUP;
5062
5063         return nvm->ops.read(hw, first, length, data);
5064 }
5065
5066 static int
5067 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5068         struct rte_dev_eeprom_info *in_eeprom)
5069 {
5070         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5071         struct e1000_nvm_info *nvm = &hw->nvm;
5072         uint16_t *data = in_eeprom->data;
5073         int first, length;
5074
5075         first = in_eeprom->offset >> 1;
5076         length = in_eeprom->length >> 1;
5077         if ((first >= hw->nvm.word_size) ||
5078             ((first + length) >= hw->nvm.word_size))
5079                 return -EINVAL;
5080
5081         in_eeprom->magic = (uint32_t)hw->vendor_id |
5082                 ((uint32_t)hw->device_id << 16);
5083
5084         if ((nvm->ops.write) == NULL)
5085                 return -ENOTSUP;
5086         return nvm->ops.write(hw,  first, length, data);
5087 }
5088
5089 static int
5090 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5091 {
5092         struct e1000_hw *hw =
5093                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5094         uint32_t mask = 1 << queue_id;
5095
5096         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5097         E1000_WRITE_FLUSH(hw);
5098
5099         return 0;
5100 }
5101
5102 static int
5103 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5104 {
5105         struct e1000_hw *hw =
5106                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5107         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5108         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5109         uint32_t mask = 1 << queue_id;
5110         uint32_t regval;
5111
5112         regval = E1000_READ_REG(hw, E1000_EIMS);
5113         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5114         E1000_WRITE_FLUSH(hw);
5115
5116         rte_intr_enable(intr_handle);
5117
5118         return 0;
5119 }
5120
5121 static void
5122 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5123                    uint8_t index, uint8_t offset)
5124 {
5125         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5126
5127         /* clear bits */
5128         val &= ~((uint32_t)0xFF << offset);
5129
5130         /* write vector and valid bit */
5131         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5132
5133         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5134 }
5135
5136 static void
5137 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5138                            uint8_t queue, uint8_t msix_vector)
5139 {
5140         uint32_t tmp = 0;
5141
5142         if (hw->mac.type == e1000_82575) {
5143                 if (direction == 0)
5144                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5145                 else if (direction == 1)
5146                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5147                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5148         } else if (hw->mac.type == e1000_82576) {
5149                 if ((direction == 0) || (direction == 1))
5150                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5151                                            ((queue & 0x8) << 1) +
5152                                            8 * direction);
5153         } else if ((hw->mac.type == e1000_82580) ||
5154                         (hw->mac.type == e1000_i350) ||
5155                         (hw->mac.type == e1000_i354) ||
5156                         (hw->mac.type == e1000_i210) ||
5157                         (hw->mac.type == e1000_i211)) {
5158                 if ((direction == 0) || (direction == 1))
5159                         eth_igb_write_ivar(hw, msix_vector,
5160                                            queue >> 1,
5161                                            ((queue & 0x1) << 4) +
5162                                            8 * direction);
5163         }
5164 }
5165
5166 /* Sets up the hardware to generate MSI-X interrupts properly
5167  * @hw
5168  *  board private structure
5169  */
5170 static void
5171 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5172 {
5173         int queue_id;
5174         uint32_t tmpval, regval, intr_mask;
5175         struct e1000_hw *hw =
5176                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5177         uint32_t vec = E1000_MISC_VEC_ID;
5178         uint32_t base = E1000_MISC_VEC_ID;
5179         uint32_t misc_shift = 0;
5180         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5181         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5182
5183         /* won't configure msix register if no mapping is done
5184          * between intr vector and event fd
5185          */
5186         if (!rte_intr_dp_is_en(intr_handle))
5187                 return;
5188
5189         if (rte_intr_allow_others(intr_handle)) {
5190                 vec = base = E1000_RX_VEC_START;
5191                 misc_shift = 1;
5192         }
5193
5194         /* set interrupt vector for other causes */
5195         if (hw->mac.type == e1000_82575) {
5196                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5197                 /* enable MSI-X PBA support */
5198                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5199
5200                 /* Auto-Mask interrupts upon ICR read */
5201                 tmpval |= E1000_CTRL_EXT_EIAME;
5202                 tmpval |= E1000_CTRL_EXT_IRCA;
5203
5204                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5205
5206                 /* enable msix_other interrupt */
5207                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5208                 regval = E1000_READ_REG(hw, E1000_EIAC);
5209                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5210                 regval = E1000_READ_REG(hw, E1000_EIAM);
5211                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5212         } else if ((hw->mac.type == e1000_82576) ||
5213                         (hw->mac.type == e1000_82580) ||
5214                         (hw->mac.type == e1000_i350) ||
5215                         (hw->mac.type == e1000_i354) ||
5216                         (hw->mac.type == e1000_i210) ||
5217                         (hw->mac.type == e1000_i211)) {
5218                 /* turn on MSI-X capability first */
5219                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5220                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5221                                         E1000_GPIE_NSICR);
5222                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5223                         misc_shift;
5224                 regval = E1000_READ_REG(hw, E1000_EIAC);
5225                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5226
5227                 /* enable msix_other interrupt */
5228                 regval = E1000_READ_REG(hw, E1000_EIMS);
5229                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5230                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5231                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5232         }
5233
5234         /* use EIAM to auto-mask when MSI-X interrupt
5235          * is asserted, this saves a register write for every interrupt
5236          */
5237         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5238                 misc_shift;
5239         regval = E1000_READ_REG(hw, E1000_EIAM);
5240         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5241
5242         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5243                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5244                 intr_handle->intr_vec[queue_id] = vec;
5245                 if (vec < base + intr_handle->nb_efd - 1)
5246                         vec++;
5247         }
5248
5249         E1000_WRITE_FLUSH(hw);
5250 }
5251
5252 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd.pci_drv);
5253 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5254 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio");
5255 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd.pci_drv);
5256 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5257 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio");