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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memory.h>
50 #include <rte_memzone.h>
52 #include <rte_atomic.h>
53 #include <rte_malloc.h>
56 #include "e1000_logs.h"
57 #include "base/e1000_api.h"
58 #include "e1000_ethdev.h"
62 * Default values for port configuration
64 #define IGB_DEFAULT_RX_FREE_THRESH 32
66 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
67 #define IGB_DEFAULT_RX_HTHRESH 8
68 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
70 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
71 #define IGB_DEFAULT_TX_HTHRESH 1
72 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
74 #define IGB_HKEY_MAX_INDEX 10
76 /* Bit shift and mask */
77 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
78 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
79 #define IGB_8_BIT_WIDTH CHAR_BIT
80 #define IGB_8_BIT_MASK UINT8_MAX
82 /* Additional timesync values. */
83 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
84 #define E1000_ETQF_FILTER_1588 3
85 #define IGB_82576_TSYNC_SHIFT 16
86 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
87 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
90 #define E1000_VTIVAR_MISC 0x01740
91 #define E1000_VTIVAR_MISC_MASK 0xFF
92 #define E1000_VTIVAR_VALID 0x80
93 #define E1000_VTIVAR_MISC_MAILBOX 0
94 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
96 /* External VLAN Enable bit mask */
97 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
99 /* External VLAN Ether Type bit mask and shift */
100 #define E1000_VET_VET_EXT 0xFFFF0000
101 #define E1000_VET_VET_EXT_SHIFT 16
103 static int eth_igb_configure(struct rte_eth_dev *dev);
104 static int eth_igb_start(struct rte_eth_dev *dev);
105 static void eth_igb_stop(struct rte_eth_dev *dev);
106 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
107 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
108 static void eth_igb_close(struct rte_eth_dev *dev);
109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
113 static int eth_igb_link_update(struct rte_eth_dev *dev,
114 int wait_to_complete);
115 static void eth_igb_stats_get(struct rte_eth_dev *dev,
116 struct rte_eth_stats *rte_stats);
117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
118 struct rte_eth_xstat *xstats, unsigned n);
119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
121 uint64_t *values, unsigned int n);
122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
123 struct rte_eth_xstat_name *xstats_names,
125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
126 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
128 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
131 char *fw_version, size_t fw_size);
132 static void eth_igb_infos_get(struct rte_eth_dev *dev,
133 struct rte_eth_dev_info *dev_info);
134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
136 struct rte_eth_dev_info *dev_info);
137 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
138 struct rte_eth_fc_conf *fc_conf);
139 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
140 struct rte_eth_fc_conf *fc_conf);
141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
145 struct rte_intr_handle *handle);
146 static void eth_igb_interrupt_handler(void *param);
147 static int igb_hardware_init(struct e1000_hw *hw);
148 static void igb_hw_control_acquire(struct e1000_hw *hw);
149 static void igb_hw_control_release(struct e1000_hw *hw);
150 static void igb_init_manageability(struct e1000_hw *hw);
151 static void igb_release_manageability(struct e1000_hw *hw);
153 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
156 uint16_t vlan_id, int on);
157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
158 enum rte_vlan_type vlan_type,
160 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
169 static int eth_igb_led_on(struct rte_eth_dev *dev);
170 static int eth_igb_led_off(struct rte_eth_dev *dev);
172 static void igb_intr_disable(struct e1000_hw *hw);
173 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
174 static int eth_igb_rar_set(struct rte_eth_dev *dev,
175 struct ether_addr *mac_addr,
176 uint32_t index, uint32_t pool);
177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
179 struct ether_addr *addr);
181 static void igbvf_intr_disable(struct e1000_hw *hw);
182 static int igbvf_dev_configure(struct rte_eth_dev *dev);
183 static int igbvf_dev_start(struct rte_eth_dev *dev);
184 static void igbvf_dev_stop(struct rte_eth_dev *dev);
185 static void igbvf_dev_close(struct rte_eth_dev *dev);
186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
190 static int eth_igbvf_link_update(struct e1000_hw *hw);
191 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
192 struct rte_eth_stats *rte_stats);
193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
194 struct rte_eth_xstat *xstats, unsigned n);
195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
196 struct rte_eth_xstat_name *xstats_names,
198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
200 uint16_t vlan_id, int on);
201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
204 struct ether_addr *addr);
205 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
206 static int igbvf_get_regs(struct rte_eth_dev *dev,
207 struct rte_dev_reg_info *regs);
209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
210 struct rte_eth_rss_reta_entry64 *reta_conf,
212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
213 struct rte_eth_rss_reta_entry64 *reta_conf,
216 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
217 struct rte_eth_syn_filter *filter);
218 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
219 enum rte_filter_op filter_op,
221 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
222 struct rte_eth_ntuple_filter *ntuple_filter);
223 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
224 struct rte_eth_ntuple_filter *ntuple_filter);
225 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
226 struct rte_eth_flex_filter *filter);
227 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
228 enum rte_filter_op filter_op,
230 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
231 struct rte_eth_ntuple_filter *ntuple_filter);
232 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
233 struct rte_eth_ntuple_filter *ntuple_filter);
234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
235 struct rte_eth_ntuple_filter *filter);
236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
237 enum rte_filter_op filter_op,
239 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
240 enum rte_filter_op filter_op,
242 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
243 struct rte_eth_ethertype_filter *filter);
244 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
245 enum rte_filter_type filter_type,
246 enum rte_filter_op filter_op,
248 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
249 static int eth_igb_get_regs(struct rte_eth_dev *dev,
250 struct rte_dev_reg_info *regs);
251 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
252 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
253 struct rte_dev_eeprom_info *eeprom);
254 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
255 struct rte_dev_eeprom_info *eeprom);
256 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
257 struct ether_addr *mc_addr_set,
258 uint32_t nb_mc_addr);
259 static int igb_timesync_enable(struct rte_eth_dev *dev);
260 static int igb_timesync_disable(struct rte_eth_dev *dev);
261 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
262 struct timespec *timestamp,
264 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
265 struct timespec *timestamp);
266 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
267 static int igb_timesync_read_time(struct rte_eth_dev *dev,
268 struct timespec *timestamp);
269 static int igb_timesync_write_time(struct rte_eth_dev *dev,
270 const struct timespec *timestamp);
271 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
273 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
275 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
276 uint8_t queue, uint8_t msix_vector);
277 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
278 uint8_t index, uint8_t offset);
279 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
280 static void eth_igbvf_interrupt_handler(void *param);
281 static void igbvf_mbx_process(struct rte_eth_dev *dev);
282 static int igb_filter_restore(struct rte_eth_dev *dev);
285 * Define VF Stats MACRO for Non "cleared on read" register
287 #define UPDATE_VF_STAT(reg, last, cur) \
289 u32 latest = E1000_READ_REG(hw, reg); \
290 cur += (latest - last) & UINT_MAX; \
294 #define IGB_FC_PAUSE_TIME 0x0680
295 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
296 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
298 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
300 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
303 * The set of PCI devices this driver supports
305 static const struct rte_pci_id pci_id_igb_map[] = {
306 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
307 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
308 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
317 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
320 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
321 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
322 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
323 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
324 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
326 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
327 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
328 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
329 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
330 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
331 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
332 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
333 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
334 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
335 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
336 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
337 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
338 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
339 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
340 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
341 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
342 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
343 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
344 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
345 { .vendor_id = 0, /* sentinel */ },
349 * The set of PCI devices this driver supports (for 82576&I350 VF)
351 static const struct rte_pci_id pci_id_igbvf_map[] = {
352 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
353 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
354 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
355 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
356 { .vendor_id = 0, /* sentinel */ },
359 static const struct rte_eth_desc_lim rx_desc_lim = {
360 .nb_max = E1000_MAX_RING_DESC,
361 .nb_min = E1000_MIN_RING_DESC,
362 .nb_align = IGB_RXD_ALIGN,
365 static const struct rte_eth_desc_lim tx_desc_lim = {
366 .nb_max = E1000_MAX_RING_DESC,
367 .nb_min = E1000_MIN_RING_DESC,
368 .nb_align = IGB_RXD_ALIGN,
369 .nb_seg_max = IGB_TX_MAX_SEG,
370 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
373 static const struct eth_dev_ops eth_igb_ops = {
374 .dev_configure = eth_igb_configure,
375 .dev_start = eth_igb_start,
376 .dev_stop = eth_igb_stop,
377 .dev_set_link_up = eth_igb_dev_set_link_up,
378 .dev_set_link_down = eth_igb_dev_set_link_down,
379 .dev_close = eth_igb_close,
380 .promiscuous_enable = eth_igb_promiscuous_enable,
381 .promiscuous_disable = eth_igb_promiscuous_disable,
382 .allmulticast_enable = eth_igb_allmulticast_enable,
383 .allmulticast_disable = eth_igb_allmulticast_disable,
384 .link_update = eth_igb_link_update,
385 .stats_get = eth_igb_stats_get,
386 .xstats_get = eth_igb_xstats_get,
387 .xstats_get_by_id = eth_igb_xstats_get_by_id,
388 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
389 .xstats_get_names = eth_igb_xstats_get_names,
390 .stats_reset = eth_igb_stats_reset,
391 .xstats_reset = eth_igb_xstats_reset,
392 .fw_version_get = eth_igb_fw_version_get,
393 .dev_infos_get = eth_igb_infos_get,
394 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
395 .mtu_set = eth_igb_mtu_set,
396 .vlan_filter_set = eth_igb_vlan_filter_set,
397 .vlan_tpid_set = eth_igb_vlan_tpid_set,
398 .vlan_offload_set = eth_igb_vlan_offload_set,
399 .rx_queue_setup = eth_igb_rx_queue_setup,
400 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
401 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
402 .rx_queue_release = eth_igb_rx_queue_release,
403 .rx_queue_count = eth_igb_rx_queue_count,
404 .rx_descriptor_done = eth_igb_rx_descriptor_done,
405 .rx_descriptor_status = eth_igb_rx_descriptor_status,
406 .tx_descriptor_status = eth_igb_tx_descriptor_status,
407 .tx_queue_setup = eth_igb_tx_queue_setup,
408 .tx_queue_release = eth_igb_tx_queue_release,
409 .tx_done_cleanup = eth_igb_tx_done_cleanup,
410 .dev_led_on = eth_igb_led_on,
411 .dev_led_off = eth_igb_led_off,
412 .flow_ctrl_get = eth_igb_flow_ctrl_get,
413 .flow_ctrl_set = eth_igb_flow_ctrl_set,
414 .mac_addr_add = eth_igb_rar_set,
415 .mac_addr_remove = eth_igb_rar_clear,
416 .mac_addr_set = eth_igb_default_mac_addr_set,
417 .reta_update = eth_igb_rss_reta_update,
418 .reta_query = eth_igb_rss_reta_query,
419 .rss_hash_update = eth_igb_rss_hash_update,
420 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
421 .filter_ctrl = eth_igb_filter_ctrl,
422 .set_mc_addr_list = eth_igb_set_mc_addr_list,
423 .rxq_info_get = igb_rxq_info_get,
424 .txq_info_get = igb_txq_info_get,
425 .timesync_enable = igb_timesync_enable,
426 .timesync_disable = igb_timesync_disable,
427 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
428 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
429 .get_reg = eth_igb_get_regs,
430 .get_eeprom_length = eth_igb_get_eeprom_length,
431 .get_eeprom = eth_igb_get_eeprom,
432 .set_eeprom = eth_igb_set_eeprom,
433 .timesync_adjust_time = igb_timesync_adjust_time,
434 .timesync_read_time = igb_timesync_read_time,
435 .timesync_write_time = igb_timesync_write_time,
439 * dev_ops for virtual function, bare necessities for basic vf
440 * operation have been implemented
442 static const struct eth_dev_ops igbvf_eth_dev_ops = {
443 .dev_configure = igbvf_dev_configure,
444 .dev_start = igbvf_dev_start,
445 .dev_stop = igbvf_dev_stop,
446 .dev_close = igbvf_dev_close,
447 .promiscuous_enable = igbvf_promiscuous_enable,
448 .promiscuous_disable = igbvf_promiscuous_disable,
449 .allmulticast_enable = igbvf_allmulticast_enable,
450 .allmulticast_disable = igbvf_allmulticast_disable,
451 .link_update = eth_igb_link_update,
452 .stats_get = eth_igbvf_stats_get,
453 .xstats_get = eth_igbvf_xstats_get,
454 .xstats_get_names = eth_igbvf_xstats_get_names,
455 .stats_reset = eth_igbvf_stats_reset,
456 .xstats_reset = eth_igbvf_stats_reset,
457 .vlan_filter_set = igbvf_vlan_filter_set,
458 .dev_infos_get = eth_igbvf_infos_get,
459 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
460 .rx_queue_setup = eth_igb_rx_queue_setup,
461 .rx_queue_release = eth_igb_rx_queue_release,
462 .tx_queue_setup = eth_igb_tx_queue_setup,
463 .tx_queue_release = eth_igb_tx_queue_release,
464 .set_mc_addr_list = eth_igb_set_mc_addr_list,
465 .rxq_info_get = igb_rxq_info_get,
466 .txq_info_get = igb_txq_info_get,
467 .mac_addr_set = igbvf_default_mac_addr_set,
468 .get_reg = igbvf_get_regs,
471 /* store statistics names and its offset in stats structure */
472 struct rte_igb_xstats_name_off {
473 char name[RTE_ETH_XSTATS_NAME_SIZE];
477 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
478 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
479 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
480 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
481 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
482 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
483 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
484 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
486 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
487 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
488 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
489 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
490 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
491 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
492 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
493 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
494 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
495 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
496 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
498 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
499 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
500 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
501 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
502 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
504 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
506 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
507 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
508 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
509 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
510 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
511 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
512 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
513 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
514 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
515 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
516 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
517 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
518 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
519 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
520 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
521 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
522 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
523 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
525 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
527 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
528 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
529 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
530 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
531 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
532 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
533 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
535 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
538 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
539 sizeof(rte_igb_stats_strings[0]))
541 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
542 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
543 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
544 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
545 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
546 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
549 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
550 sizeof(rte_igbvf_stats_strings[0]))
553 * Atomically reads the link status information from global
554 * structure rte_eth_dev.
557 * - Pointer to the structure rte_eth_dev to read from.
558 * - Pointer to the buffer to be saved with the link status.
561 * - On success, zero.
562 * - On failure, negative value.
565 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
566 struct rte_eth_link *link)
568 struct rte_eth_link *dst = link;
569 struct rte_eth_link *src = &(dev->data->dev_link);
571 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
572 *(uint64_t *)src) == 0)
579 * Atomically writes the link status information into global
580 * structure rte_eth_dev.
583 * - Pointer to the structure rte_eth_dev to read from.
584 * - Pointer to the buffer to be saved with the link status.
587 * - On success, zero.
588 * - On failure, negative value.
591 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
592 struct rte_eth_link *link)
594 struct rte_eth_link *dst = &(dev->data->dev_link);
595 struct rte_eth_link *src = link;
597 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
598 *(uint64_t *)src) == 0)
605 igb_intr_enable(struct rte_eth_dev *dev)
607 struct e1000_interrupt *intr =
608 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
609 struct e1000_hw *hw =
610 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
612 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
613 E1000_WRITE_FLUSH(hw);
617 igb_intr_disable(struct e1000_hw *hw)
619 E1000_WRITE_REG(hw, E1000_IMC, ~0);
620 E1000_WRITE_FLUSH(hw);
624 igbvf_intr_enable(struct rte_eth_dev *dev)
626 struct e1000_hw *hw =
627 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
629 /* only for mailbox */
630 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
631 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
632 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
633 E1000_WRITE_FLUSH(hw);
636 /* only for mailbox now. If RX/TX needed, should extend this function. */
638 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
643 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
644 tmp |= E1000_VTIVAR_VALID;
645 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
649 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
651 struct e1000_hw *hw =
652 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
654 /* Configure VF other cause ivar */
655 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
658 static inline int32_t
659 igb_pf_reset_hw(struct e1000_hw *hw)
664 status = e1000_reset_hw(hw);
666 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
667 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
668 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
669 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
670 E1000_WRITE_FLUSH(hw);
676 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
678 struct e1000_hw *hw =
679 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
682 hw->vendor_id = pci_dev->id.vendor_id;
683 hw->device_id = pci_dev->id.device_id;
684 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
685 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
687 e1000_set_mac_type(hw);
689 /* need to check if it is a vf device below */
693 igb_reset_swfw_lock(struct e1000_hw *hw)
698 * Do mac ops initialization manually here, since we will need
699 * some function pointers set by this call.
701 ret_val = e1000_init_mac_params(hw);
706 * SMBI lock should not fail in this early stage. If this is the case,
707 * it is due to an improper exit of the application.
708 * So force the release of the faulty lock.
710 if (e1000_get_hw_semaphore_generic(hw) < 0) {
711 PMD_DRV_LOG(DEBUG, "SMBI lock released");
713 e1000_put_hw_semaphore_generic(hw);
715 if (hw->mac.ops.acquire_swfw_sync != NULL) {
719 * Phy lock should not fail in this early stage. If this is the case,
720 * it is due to an improper exit of the application.
721 * So force the release of the faulty lock.
723 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
724 if (hw->bus.func > E1000_FUNC_1)
726 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
727 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
730 hw->mac.ops.release_swfw_sync(hw, mask);
733 * This one is more tricky since it is common to all ports; but
734 * swfw_sync retries last long enough (1s) to be almost sure that if
735 * lock can not be taken it is due to an improper lock of the
738 mask = E1000_SWFW_EEP_SM;
739 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
740 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
742 hw->mac.ops.release_swfw_sync(hw, mask);
745 return E1000_SUCCESS;
748 /* Remove all ntuple filters of the device */
749 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
751 struct e1000_filter_info *filter_info =
752 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
753 struct e1000_5tuple_filter *p_5tuple;
754 struct e1000_2tuple_filter *p_2tuple;
756 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
757 TAILQ_REMOVE(&filter_info->fivetuple_list,
761 filter_info->fivetuple_mask = 0;
762 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
763 TAILQ_REMOVE(&filter_info->twotuple_list,
767 filter_info->twotuple_mask = 0;
772 /* Remove all flex filters of the device */
773 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
775 struct e1000_filter_info *filter_info =
776 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
777 struct e1000_flex_filter *p_flex;
779 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
780 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
783 filter_info->flex_mask = 0;
789 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
792 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
793 struct e1000_hw *hw =
794 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
795 struct e1000_vfta * shadow_vfta =
796 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
797 struct e1000_filter_info *filter_info =
798 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
799 struct e1000_adapter *adapter =
800 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
804 eth_dev->dev_ops = ð_igb_ops;
805 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
806 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
807 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
809 /* for secondary processes, we don't initialise any further as primary
810 * has already done this work. Only check we don't need a different
812 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
813 if (eth_dev->data->scattered_rx)
814 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
818 rte_eth_copy_pci_info(eth_dev, pci_dev);
819 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
821 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
823 igb_identify_hardware(eth_dev, pci_dev);
824 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
829 e1000_get_bus_info(hw);
831 /* Reset any pending lock */
832 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
837 /* Finish initialization */
838 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
844 hw->phy.autoneg_wait_to_complete = 0;
845 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
848 if (hw->phy.media_type == e1000_media_type_copper) {
849 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
850 hw->phy.disable_polarity_correction = 0;
851 hw->phy.ms_type = e1000_ms_hw_default;
855 * Start from a known state, this is important in reading the nvm
860 /* Make sure we have a good EEPROM before we read from it */
861 if (e1000_validate_nvm_checksum(hw) < 0) {
863 * Some PCI-E parts fail the first check due to
864 * the link being in sleep state, call it again,
865 * if it fails a second time its a real issue.
867 if (e1000_validate_nvm_checksum(hw) < 0) {
868 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
874 /* Read the permanent MAC address out of the EEPROM */
875 if (e1000_read_mac_addr(hw) != 0) {
876 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
881 /* Allocate memory for storing MAC addresses */
882 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
883 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
884 if (eth_dev->data->mac_addrs == NULL) {
885 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
886 "store MAC addresses",
887 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
892 /* Copy the permanent MAC address */
893 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
895 /* initialize the vfta */
896 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
898 /* Now initialize the hardware */
899 if (igb_hardware_init(hw) != 0) {
900 PMD_INIT_LOG(ERR, "Hardware initialization failed");
901 rte_free(eth_dev->data->mac_addrs);
902 eth_dev->data->mac_addrs = NULL;
906 hw->mac.get_link_status = 1;
907 adapter->stopped = 0;
909 /* Indicate SOL/IDER usage */
910 if (e1000_check_reset_block(hw) < 0) {
911 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
915 /* initialize PF if max_vfs not zero */
916 igb_pf_host_init(eth_dev);
918 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
919 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
920 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
921 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
922 E1000_WRITE_FLUSH(hw);
924 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
925 eth_dev->data->port_id, pci_dev->id.vendor_id,
926 pci_dev->id.device_id);
928 rte_intr_callback_register(&pci_dev->intr_handle,
929 eth_igb_interrupt_handler,
932 /* enable uio/vfio intr/eventfd mapping */
933 rte_intr_enable(&pci_dev->intr_handle);
935 /* enable support intr */
936 igb_intr_enable(eth_dev);
938 /* initialize filter info */
939 memset(filter_info, 0,
940 sizeof(struct e1000_filter_info));
942 TAILQ_INIT(&filter_info->flex_list);
943 TAILQ_INIT(&filter_info->twotuple_list);
944 TAILQ_INIT(&filter_info->fivetuple_list);
946 TAILQ_INIT(&igb_filter_ntuple_list);
947 TAILQ_INIT(&igb_filter_ethertype_list);
948 TAILQ_INIT(&igb_filter_syn_list);
949 TAILQ_INIT(&igb_filter_flex_list);
950 TAILQ_INIT(&igb_flow_list);
955 igb_hw_control_release(hw);
961 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
963 struct rte_pci_device *pci_dev;
964 struct rte_intr_handle *intr_handle;
966 struct e1000_adapter *adapter =
967 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
968 struct e1000_filter_info *filter_info =
969 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
971 PMD_INIT_FUNC_TRACE();
973 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
976 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
977 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
978 intr_handle = &pci_dev->intr_handle;
980 if (adapter->stopped == 0)
981 eth_igb_close(eth_dev);
983 eth_dev->dev_ops = NULL;
984 eth_dev->rx_pkt_burst = NULL;
985 eth_dev->tx_pkt_burst = NULL;
987 /* Reset any pending lock */
988 igb_reset_swfw_lock(hw);
990 rte_free(eth_dev->data->mac_addrs);
991 eth_dev->data->mac_addrs = NULL;
993 /* uninitialize PF if max_vfs not zero */
994 igb_pf_host_uninit(eth_dev);
996 /* disable uio intr before callback unregister */
997 rte_intr_disable(intr_handle);
998 rte_intr_callback_unregister(intr_handle,
999 eth_igb_interrupt_handler, eth_dev);
1001 /* clear the SYN filter info */
1002 filter_info->syn_info = 0;
1004 /* clear the ethertype filters info */
1005 filter_info->ethertype_mask = 0;
1006 memset(filter_info->ethertype_filters, 0,
1007 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1009 /* remove all ntuple filters of the device */
1010 igb_ntuple_filter_uninit(eth_dev);
1012 /* remove all flex filters of the device */
1013 igb_flex_filter_uninit(eth_dev);
1015 /* clear all the filters list */
1016 igb_filterlist_flush(eth_dev);
1022 * Virtual Function device init
1025 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
1027 struct rte_pci_device *pci_dev;
1028 struct rte_intr_handle *intr_handle;
1029 struct e1000_adapter *adapter =
1030 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1031 struct e1000_hw *hw =
1032 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1034 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
1036 PMD_INIT_FUNC_TRACE();
1038 eth_dev->dev_ops = &igbvf_eth_dev_ops;
1039 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
1040 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
1041 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
1043 /* for secondary processes, we don't initialise any further as primary
1044 * has already done this work. Only check we don't need a different
1046 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1047 if (eth_dev->data->scattered_rx)
1048 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
1052 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1053 rte_eth_copy_pci_info(eth_dev, pci_dev);
1054 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1056 hw->device_id = pci_dev->id.device_id;
1057 hw->vendor_id = pci_dev->id.vendor_id;
1058 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1059 adapter->stopped = 0;
1061 /* Initialize the shared code (base driver) */
1062 diag = e1000_setup_init_funcs(hw, TRUE);
1064 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1069 /* init_mailbox_params */
1070 hw->mbx.ops.init_params(hw);
1072 /* Disable the interrupts for VF */
1073 igbvf_intr_disable(hw);
1075 diag = hw->mac.ops.reset_hw(hw);
1077 /* Allocate memory for storing MAC addresses */
1078 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1079 hw->mac.rar_entry_count, 0);
1080 if (eth_dev->data->mac_addrs == NULL) {
1082 "Failed to allocate %d bytes needed to store MAC "
1084 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1088 /* Generate a random MAC address, if none was assigned by PF. */
1089 if (is_zero_ether_addr(perm_addr)) {
1090 eth_random_addr(perm_addr->addr_bytes);
1091 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1092 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1093 "%02x:%02x:%02x:%02x:%02x:%02x",
1094 perm_addr->addr_bytes[0],
1095 perm_addr->addr_bytes[1],
1096 perm_addr->addr_bytes[2],
1097 perm_addr->addr_bytes[3],
1098 perm_addr->addr_bytes[4],
1099 perm_addr->addr_bytes[5]);
1102 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1104 rte_free(eth_dev->data->mac_addrs);
1105 eth_dev->data->mac_addrs = NULL;
1108 /* Copy the permanent MAC address */
1109 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1110 ð_dev->data->mac_addrs[0]);
1112 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1114 eth_dev->data->port_id, pci_dev->id.vendor_id,
1115 pci_dev->id.device_id, "igb_mac_82576_vf");
1117 intr_handle = &pci_dev->intr_handle;
1118 rte_intr_callback_register(intr_handle,
1119 eth_igbvf_interrupt_handler, eth_dev);
1125 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1127 struct e1000_adapter *adapter =
1128 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1129 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1131 PMD_INIT_FUNC_TRACE();
1133 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1136 if (adapter->stopped == 0)
1137 igbvf_dev_close(eth_dev);
1139 eth_dev->dev_ops = NULL;
1140 eth_dev->rx_pkt_burst = NULL;
1141 eth_dev->tx_pkt_burst = NULL;
1143 rte_free(eth_dev->data->mac_addrs);
1144 eth_dev->data->mac_addrs = NULL;
1146 /* disable uio intr before callback unregister */
1147 rte_intr_disable(&pci_dev->intr_handle);
1148 rte_intr_callback_unregister(&pci_dev->intr_handle,
1149 eth_igbvf_interrupt_handler,
1155 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1156 struct rte_pci_device *pci_dev)
1158 return rte_eth_dev_pci_generic_probe(pci_dev,
1159 sizeof(struct e1000_adapter), eth_igb_dev_init);
1162 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1164 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1167 static struct rte_pci_driver rte_igb_pmd = {
1168 .id_table = pci_id_igb_map,
1169 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1170 .probe = eth_igb_pci_probe,
1171 .remove = eth_igb_pci_remove,
1175 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1176 struct rte_pci_device *pci_dev)
1178 return rte_eth_dev_pci_generic_probe(pci_dev,
1179 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1182 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1184 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1188 * virtual function driver struct
1190 static struct rte_pci_driver rte_igbvf_pmd = {
1191 .id_table = pci_id_igbvf_map,
1192 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1193 .probe = eth_igbvf_pci_probe,
1194 .remove = eth_igbvf_pci_remove,
1198 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1200 struct e1000_hw *hw =
1201 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1202 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1203 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1204 rctl |= E1000_RCTL_VFE;
1205 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1209 igb_check_mq_mode(struct rte_eth_dev *dev)
1211 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1212 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1213 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1214 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1216 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1217 tx_mq_mode == ETH_MQ_TX_DCB ||
1218 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1219 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1222 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1223 /* Check multi-queue mode.
1224 * To no break software we accept ETH_MQ_RX_NONE as this might
1225 * be used to turn off VLAN filter.
1228 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1229 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1230 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1231 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1233 /* Only support one queue on VFs.
1234 * RSS together with SRIOV is not supported.
1236 PMD_INIT_LOG(ERR, "SRIOV is active,"
1237 " wrong mq_mode rx %d.",
1241 /* TX mode is not used here, so mode might be ignored.*/
1242 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1243 /* SRIOV only works in VMDq enable mode */
1244 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1245 " TX mode %d is not supported. "
1246 " Driver will behave as %d mode.",
1247 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1250 /* check valid queue number */
1251 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1252 PMD_INIT_LOG(ERR, "SRIOV is active,"
1253 " only support one queue on VFs.");
1257 /* To no break software that set invalid mode, only display
1258 * warning if invalid mode is used.
1260 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1261 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1262 rx_mq_mode != ETH_MQ_RX_RSS) {
1263 /* RSS together with VMDq not supported*/
1264 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1269 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1270 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1271 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1272 " Due to txmode is meaningless in this"
1273 " driver, just ignore.",
1281 eth_igb_configure(struct rte_eth_dev *dev)
1283 struct e1000_interrupt *intr =
1284 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1287 PMD_INIT_FUNC_TRACE();
1289 /* multipe queue mode checking */
1290 ret = igb_check_mq_mode(dev);
1292 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1297 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1298 PMD_INIT_FUNC_TRACE();
1304 eth_igb_start(struct rte_eth_dev *dev)
1306 struct e1000_hw *hw =
1307 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1308 struct e1000_adapter *adapter =
1309 E1000_DEV_PRIVATE(dev->data->dev_private);
1310 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1311 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1313 uint32_t intr_vector = 0;
1319 PMD_INIT_FUNC_TRACE();
1321 /* disable uio/vfio intr/eventfd mapping */
1322 rte_intr_disable(intr_handle);
1324 /* Power up the phy. Needed to make the link go Up */
1325 eth_igb_dev_set_link_up(dev);
1328 * Packet Buffer Allocation (PBA)
1329 * Writing PBA sets the receive portion of the buffer
1330 * the remainder is used for the transmit buffer.
1332 if (hw->mac.type == e1000_82575) {
1335 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1336 E1000_WRITE_REG(hw, E1000_PBA, pba);
1339 /* Put the address into the Receive Address Array */
1340 e1000_rar_set(hw, hw->mac.addr, 0);
1342 /* Initialize the hardware */
1343 if (igb_hardware_init(hw)) {
1344 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1347 adapter->stopped = 0;
1349 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1351 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1352 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1353 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1354 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1355 E1000_WRITE_FLUSH(hw);
1357 /* configure PF module if SRIOV enabled */
1358 igb_pf_host_configure(dev);
1360 /* check and configure queue intr-vector mapping */
1361 if ((rte_intr_cap_multiple(intr_handle) ||
1362 !RTE_ETH_DEV_SRIOV(dev).active) &&
1363 dev->data->dev_conf.intr_conf.rxq != 0) {
1364 intr_vector = dev->data->nb_rx_queues;
1365 if (rte_intr_efd_enable(intr_handle, intr_vector))
1369 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1370 intr_handle->intr_vec =
1371 rte_zmalloc("intr_vec",
1372 dev->data->nb_rx_queues * sizeof(int), 0);
1373 if (intr_handle->intr_vec == NULL) {
1374 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1375 " intr_vec", dev->data->nb_rx_queues);
1380 /* confiugre msix for rx interrupt */
1381 eth_igb_configure_msix_intr(dev);
1383 /* Configure for OS presence */
1384 igb_init_manageability(hw);
1386 eth_igb_tx_init(dev);
1388 /* This can fail when allocating mbufs for descriptor rings */
1389 ret = eth_igb_rx_init(dev);
1391 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1392 igb_dev_clear_queues(dev);
1396 e1000_clear_hw_cntrs_base_generic(hw);
1399 * VLAN Offload Settings
1401 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1402 ETH_VLAN_EXTEND_MASK;
1403 eth_igb_vlan_offload_set(dev, mask);
1405 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1406 /* Enable VLAN filter since VMDq always use VLAN filter */
1407 igb_vmdq_vlan_hw_filter_enable(dev);
1410 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1411 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1412 (hw->mac.type == e1000_i211)) {
1413 /* Configure EITR with the maximum possible value (0xFFFF) */
1414 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1417 /* Setup link speed and duplex */
1418 speeds = &dev->data->dev_conf.link_speeds;
1419 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1420 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1421 hw->mac.autoneg = 1;
1424 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1427 hw->phy.autoneg_advertised = 0;
1429 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1430 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1431 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1433 goto error_invalid_config;
1435 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1436 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1439 if (*speeds & ETH_LINK_SPEED_10M) {
1440 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1443 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1444 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1447 if (*speeds & ETH_LINK_SPEED_100M) {
1448 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1451 if (*speeds & ETH_LINK_SPEED_1G) {
1452 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1455 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1456 goto error_invalid_config;
1458 /* Set/reset the mac.autoneg based on the link speed,
1462 hw->mac.autoneg = 0;
1463 hw->mac.forced_speed_duplex =
1464 hw->phy.autoneg_advertised;
1466 hw->mac.autoneg = 1;
1470 e1000_setup_link(hw);
1472 if (rte_intr_allow_others(intr_handle)) {
1473 /* check if lsc interrupt is enabled */
1474 if (dev->data->dev_conf.intr_conf.lsc != 0)
1475 eth_igb_lsc_interrupt_setup(dev);
1477 rte_intr_callback_unregister(intr_handle,
1478 eth_igb_interrupt_handler,
1480 if (dev->data->dev_conf.intr_conf.lsc != 0)
1481 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1482 " no intr multiplex");
1485 /* check if rxq interrupt is enabled */
1486 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1487 rte_intr_dp_is_en(intr_handle))
1488 eth_igb_rxq_interrupt_setup(dev);
1490 /* enable uio/vfio intr/eventfd mapping */
1491 rte_intr_enable(intr_handle);
1493 /* resume enabled intr since hw reset */
1494 igb_intr_enable(dev);
1496 /* restore all types filter */
1497 igb_filter_restore(dev);
1499 PMD_INIT_LOG(DEBUG, "<<");
1503 error_invalid_config:
1504 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1505 dev->data->dev_conf.link_speeds, dev->data->port_id);
1506 igb_dev_clear_queues(dev);
1510 /*********************************************************************
1512 * This routine disables all traffic on the adapter by issuing a
1513 * global reset on the MAC.
1515 **********************************************************************/
1517 eth_igb_stop(struct rte_eth_dev *dev)
1519 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1520 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1521 struct rte_eth_link link;
1522 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1524 igb_intr_disable(hw);
1526 /* disable intr eventfd mapping */
1527 rte_intr_disable(intr_handle);
1529 igb_pf_reset_hw(hw);
1530 E1000_WRITE_REG(hw, E1000_WUC, 0);
1532 /* Set bit for Go Link disconnect */
1533 if (hw->mac.type >= e1000_82580) {
1536 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1537 phpm_reg |= E1000_82580_PM_GO_LINKD;
1538 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1541 /* Power down the phy. Needed to make the link go Down */
1542 eth_igb_dev_set_link_down(dev);
1544 igb_dev_clear_queues(dev);
1546 /* clear the recorded link status */
1547 memset(&link, 0, sizeof(link));
1548 rte_igb_dev_atomic_write_link_status(dev, &link);
1550 if (!rte_intr_allow_others(intr_handle))
1551 /* resume to the default handler */
1552 rte_intr_callback_register(intr_handle,
1553 eth_igb_interrupt_handler,
1556 /* Clean datapath event and queue/vec mapping */
1557 rte_intr_efd_disable(intr_handle);
1558 if (intr_handle->intr_vec != NULL) {
1559 rte_free(intr_handle->intr_vec);
1560 intr_handle->intr_vec = NULL;
1565 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1567 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1569 if (hw->phy.media_type == e1000_media_type_copper)
1570 e1000_power_up_phy(hw);
1572 e1000_power_up_fiber_serdes_link(hw);
1578 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1580 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1582 if (hw->phy.media_type == e1000_media_type_copper)
1583 e1000_power_down_phy(hw);
1585 e1000_shutdown_fiber_serdes_link(hw);
1591 eth_igb_close(struct rte_eth_dev *dev)
1593 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1594 struct e1000_adapter *adapter =
1595 E1000_DEV_PRIVATE(dev->data->dev_private);
1596 struct rte_eth_link link;
1597 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1598 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1601 adapter->stopped = 1;
1603 e1000_phy_hw_reset(hw);
1604 igb_release_manageability(hw);
1605 igb_hw_control_release(hw);
1607 /* Clear bit for Go Link disconnect */
1608 if (hw->mac.type >= e1000_82580) {
1611 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1612 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1613 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1616 igb_dev_free_queues(dev);
1618 if (intr_handle->intr_vec) {
1619 rte_free(intr_handle->intr_vec);
1620 intr_handle->intr_vec = NULL;
1623 memset(&link, 0, sizeof(link));
1624 rte_igb_dev_atomic_write_link_status(dev, &link);
1628 igb_get_rx_buffer_size(struct e1000_hw *hw)
1630 uint32_t rx_buf_size;
1631 if (hw->mac.type == e1000_82576) {
1632 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1633 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1634 /* PBS needs to be translated according to a lookup table */
1635 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1636 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1637 rx_buf_size = (rx_buf_size << 10);
1638 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1639 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1641 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1647 /*********************************************************************
1649 * Initialize the hardware
1651 **********************************************************************/
1653 igb_hardware_init(struct e1000_hw *hw)
1655 uint32_t rx_buf_size;
1658 /* Let the firmware know the OS is in control */
1659 igb_hw_control_acquire(hw);
1662 * These parameters control the automatic generation (Tx) and
1663 * response (Rx) to Ethernet PAUSE frames.
1664 * - High water mark should allow for at least two standard size (1518)
1665 * frames to be received after sending an XOFF.
1666 * - Low water mark works best when it is very near the high water mark.
1667 * This allows the receiver to restart by sending XON when it has
1668 * drained a bit. Here we use an arbitrary value of 1500 which will
1669 * restart after one full frame is pulled from the buffer. There
1670 * could be several smaller frames in the buffer and if so they will
1671 * not trigger the XON until their total number reduces the buffer
1673 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1675 rx_buf_size = igb_get_rx_buffer_size(hw);
1677 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1678 hw->fc.low_water = hw->fc.high_water - 1500;
1679 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1680 hw->fc.send_xon = 1;
1682 /* Set Flow control, use the tunable location if sane */
1683 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1684 hw->fc.requested_mode = igb_fc_setting;
1686 hw->fc.requested_mode = e1000_fc_none;
1688 /* Issue a global reset */
1689 igb_pf_reset_hw(hw);
1690 E1000_WRITE_REG(hw, E1000_WUC, 0);
1692 diag = e1000_init_hw(hw);
1696 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1697 e1000_get_phy_info(hw);
1698 e1000_check_for_link(hw);
1703 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1705 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1709 uint64_t old_gprc = stats->gprc;
1710 uint64_t old_gptc = stats->gptc;
1711 uint64_t old_tpr = stats->tpr;
1712 uint64_t old_tpt = stats->tpt;
1713 uint64_t old_rpthc = stats->rpthc;
1714 uint64_t old_hgptc = stats->hgptc;
1716 if(hw->phy.media_type == e1000_media_type_copper ||
1717 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1719 E1000_READ_REG(hw,E1000_SYMERRS);
1720 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1723 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1724 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1725 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1726 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1728 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1729 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1730 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1731 stats->dc += E1000_READ_REG(hw, E1000_DC);
1732 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1733 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1734 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1736 ** For watchdog management we need to know if we have been
1737 ** paused during the last interval, so capture that here.
1739 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1740 stats->xoffrxc += pause_frames;
1741 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1742 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1743 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1744 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1745 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1746 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1747 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1748 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1749 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1750 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1751 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1752 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1754 /* For the 64-bit byte counters the low dword must be read first. */
1755 /* Both registers clear on the read of the high dword */
1757 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1758 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1759 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1760 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1761 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1762 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1763 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1765 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1766 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1767 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1768 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1769 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1771 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1772 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1774 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1775 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1776 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1777 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1778 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1779 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1781 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1782 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1783 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1784 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1785 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1786 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1787 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1788 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1790 /* Interrupt Counts */
1792 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1793 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1794 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1795 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1796 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1797 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1798 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1799 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1800 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1802 /* Host to Card Statistics */
1804 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1805 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1806 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1807 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1808 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1809 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1810 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1811 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1812 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1813 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1814 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1815 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1816 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1817 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1818 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1819 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1821 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1822 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1823 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1824 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1825 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1826 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1830 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1832 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833 struct e1000_hw_stats *stats =
1834 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1836 igb_read_stats_registers(hw, stats);
1838 if (rte_stats == NULL)
1842 rte_stats->imissed = stats->mpc;
1843 rte_stats->ierrors = stats->crcerrs +
1844 stats->rlec + stats->ruc + stats->roc +
1845 stats->rxerrc + stats->algnerrc + stats->cexterr;
1848 rte_stats->oerrors = stats->ecol + stats->latecol;
1850 rte_stats->ipackets = stats->gprc;
1851 rte_stats->opackets = stats->gptc;
1852 rte_stats->ibytes = stats->gorc;
1853 rte_stats->obytes = stats->gotc;
1857 eth_igb_stats_reset(struct rte_eth_dev *dev)
1859 struct e1000_hw_stats *hw_stats =
1860 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1862 /* HW registers are cleared on read */
1863 eth_igb_stats_get(dev, NULL);
1865 /* Reset software totals */
1866 memset(hw_stats, 0, sizeof(*hw_stats));
1870 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1872 struct e1000_hw_stats *stats =
1873 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1875 /* HW registers are cleared on read */
1876 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1878 /* Reset software totals */
1879 memset(stats, 0, sizeof(*stats));
1882 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1883 struct rte_eth_xstat_name *xstats_names,
1884 __rte_unused unsigned int size)
1888 if (xstats_names == NULL)
1889 return IGB_NB_XSTATS;
1891 /* Note: limit checked in rte_eth_xstats_names() */
1893 for (i = 0; i < IGB_NB_XSTATS; i++) {
1894 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1895 "%s", rte_igb_stats_strings[i].name);
1898 return IGB_NB_XSTATS;
1901 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1902 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1908 if (xstats_names == NULL)
1909 return IGB_NB_XSTATS;
1911 for (i = 0; i < IGB_NB_XSTATS; i++)
1912 snprintf(xstats_names[i].name,
1913 sizeof(xstats_names[i].name),
1914 "%s", rte_igb_stats_strings[i].name);
1916 return IGB_NB_XSTATS;
1919 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1921 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1924 for (i = 0; i < limit; i++) {
1925 if (ids[i] >= IGB_NB_XSTATS) {
1926 PMD_INIT_LOG(ERR, "id value isn't valid");
1929 strcpy(xstats_names[i].name,
1930 xstats_names_copy[ids[i]].name);
1937 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1940 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941 struct e1000_hw_stats *hw_stats =
1942 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1945 if (n < IGB_NB_XSTATS)
1946 return IGB_NB_XSTATS;
1948 igb_read_stats_registers(hw, hw_stats);
1950 /* If this is a reset xstats is NULL, and we have cleared the
1951 * registers by reading them.
1956 /* Extended stats */
1957 for (i = 0; i < IGB_NB_XSTATS; i++) {
1959 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1960 rte_igb_stats_strings[i].offset);
1963 return IGB_NB_XSTATS;
1967 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1968 uint64_t *values, unsigned int n)
1973 struct e1000_hw *hw =
1974 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1975 struct e1000_hw_stats *hw_stats =
1976 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1978 if (n < IGB_NB_XSTATS)
1979 return IGB_NB_XSTATS;
1981 igb_read_stats_registers(hw, hw_stats);
1983 /* If this is a reset xstats is NULL, and we have cleared the
1984 * registers by reading them.
1989 /* Extended stats */
1990 for (i = 0; i < IGB_NB_XSTATS; i++)
1991 values[i] = *(uint64_t *)(((char *)hw_stats) +
1992 rte_igb_stats_strings[i].offset);
1994 return IGB_NB_XSTATS;
1997 uint64_t values_copy[IGB_NB_XSTATS];
1999 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2002 for (i = 0; i < n; i++) {
2003 if (ids[i] >= IGB_NB_XSTATS) {
2004 PMD_INIT_LOG(ERR, "id value isn't valid");
2007 values[i] = values_copy[ids[i]];
2014 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2016 /* Good Rx packets, include VF loopback */
2017 UPDATE_VF_STAT(E1000_VFGPRC,
2018 hw_stats->last_gprc, hw_stats->gprc);
2020 /* Good Rx octets, include VF loopback */
2021 UPDATE_VF_STAT(E1000_VFGORC,
2022 hw_stats->last_gorc, hw_stats->gorc);
2024 /* Good Tx packets, include VF loopback */
2025 UPDATE_VF_STAT(E1000_VFGPTC,
2026 hw_stats->last_gptc, hw_stats->gptc);
2028 /* Good Tx octets, include VF loopback */
2029 UPDATE_VF_STAT(E1000_VFGOTC,
2030 hw_stats->last_gotc, hw_stats->gotc);
2032 /* Rx Multicst packets */
2033 UPDATE_VF_STAT(E1000_VFMPRC,
2034 hw_stats->last_mprc, hw_stats->mprc);
2036 /* Good Rx loopback packets */
2037 UPDATE_VF_STAT(E1000_VFGPRLBC,
2038 hw_stats->last_gprlbc, hw_stats->gprlbc);
2040 /* Good Rx loopback octets */
2041 UPDATE_VF_STAT(E1000_VFGORLBC,
2042 hw_stats->last_gorlbc, hw_stats->gorlbc);
2044 /* Good Tx loopback packets */
2045 UPDATE_VF_STAT(E1000_VFGPTLBC,
2046 hw_stats->last_gptlbc, hw_stats->gptlbc);
2048 /* Good Tx loopback octets */
2049 UPDATE_VF_STAT(E1000_VFGOTLBC,
2050 hw_stats->last_gotlbc, hw_stats->gotlbc);
2053 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2054 struct rte_eth_xstat_name *xstats_names,
2055 __rte_unused unsigned limit)
2059 if (xstats_names != NULL)
2060 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2061 snprintf(xstats_names[i].name,
2062 sizeof(xstats_names[i].name), "%s",
2063 rte_igbvf_stats_strings[i].name);
2065 return IGBVF_NB_XSTATS;
2069 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2072 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2073 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2074 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2077 if (n < IGBVF_NB_XSTATS)
2078 return IGBVF_NB_XSTATS;
2080 igbvf_read_stats_registers(hw, hw_stats);
2085 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2087 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2088 rte_igbvf_stats_strings[i].offset);
2091 return IGBVF_NB_XSTATS;
2095 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2097 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2098 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2099 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2101 igbvf_read_stats_registers(hw, hw_stats);
2103 if (rte_stats == NULL)
2106 rte_stats->ipackets = hw_stats->gprc;
2107 rte_stats->ibytes = hw_stats->gorc;
2108 rte_stats->opackets = hw_stats->gptc;
2109 rte_stats->obytes = hw_stats->gotc;
2113 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2115 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2116 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2118 /* Sync HW register to the last stats */
2119 eth_igbvf_stats_get(dev, NULL);
2121 /* reset HW current stats*/
2122 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2123 offsetof(struct e1000_vf_stats, gprc));
2127 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2130 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2131 struct e1000_fw_version fw;
2134 e1000_get_fw_version(hw, &fw);
2136 switch (hw->mac.type) {
2139 if (!(e1000_get_flash_presence_i210(hw))) {
2140 ret = snprintf(fw_version, fw_size,
2142 fw.invm_major, fw.invm_minor,
2148 /* if option rom is valid, display its version too */
2150 ret = snprintf(fw_version, fw_size,
2151 "%d.%d, 0x%08x, %d.%d.%d",
2152 fw.eep_major, fw.eep_minor, fw.etrack_id,
2153 fw.or_major, fw.or_build, fw.or_patch);
2156 if (fw.etrack_id != 0X0000) {
2157 ret = snprintf(fw_version, fw_size,
2159 fw.eep_major, fw.eep_minor,
2162 ret = snprintf(fw_version, fw_size,
2164 fw.eep_major, fw.eep_minor,
2171 ret += 1; /* add the size of '\0' */
2172 if (fw_size < (u32)ret)
2179 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2181 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2183 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2184 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2185 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2186 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2187 dev_info->rx_offload_capa =
2188 DEV_RX_OFFLOAD_VLAN_STRIP |
2189 DEV_RX_OFFLOAD_IPV4_CKSUM |
2190 DEV_RX_OFFLOAD_UDP_CKSUM |
2191 DEV_RX_OFFLOAD_TCP_CKSUM;
2192 dev_info->tx_offload_capa =
2193 DEV_TX_OFFLOAD_VLAN_INSERT |
2194 DEV_TX_OFFLOAD_IPV4_CKSUM |
2195 DEV_TX_OFFLOAD_UDP_CKSUM |
2196 DEV_TX_OFFLOAD_TCP_CKSUM |
2197 DEV_TX_OFFLOAD_SCTP_CKSUM |
2198 DEV_TX_OFFLOAD_TCP_TSO;
2200 switch (hw->mac.type) {
2202 dev_info->max_rx_queues = 4;
2203 dev_info->max_tx_queues = 4;
2204 dev_info->max_vmdq_pools = 0;
2208 dev_info->max_rx_queues = 16;
2209 dev_info->max_tx_queues = 16;
2210 dev_info->max_vmdq_pools = ETH_8_POOLS;
2211 dev_info->vmdq_queue_num = 16;
2215 dev_info->max_rx_queues = 8;
2216 dev_info->max_tx_queues = 8;
2217 dev_info->max_vmdq_pools = ETH_8_POOLS;
2218 dev_info->vmdq_queue_num = 8;
2222 dev_info->max_rx_queues = 8;
2223 dev_info->max_tx_queues = 8;
2224 dev_info->max_vmdq_pools = ETH_8_POOLS;
2225 dev_info->vmdq_queue_num = 8;
2229 dev_info->max_rx_queues = 8;
2230 dev_info->max_tx_queues = 8;
2234 dev_info->max_rx_queues = 4;
2235 dev_info->max_tx_queues = 4;
2236 dev_info->max_vmdq_pools = 0;
2240 dev_info->max_rx_queues = 2;
2241 dev_info->max_tx_queues = 2;
2242 dev_info->max_vmdq_pools = 0;
2246 /* Should not happen */
2249 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2250 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2251 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2253 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2255 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2256 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2257 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2259 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2263 dev_info->default_txconf = (struct rte_eth_txconf) {
2265 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2266 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2267 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2272 dev_info->rx_desc_lim = rx_desc_lim;
2273 dev_info->tx_desc_lim = tx_desc_lim;
2275 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2276 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2280 static const uint32_t *
2281 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2283 static const uint32_t ptypes[] = {
2284 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2287 RTE_PTYPE_L3_IPV4_EXT,
2289 RTE_PTYPE_L3_IPV6_EXT,
2293 RTE_PTYPE_TUNNEL_IP,
2294 RTE_PTYPE_INNER_L3_IPV6,
2295 RTE_PTYPE_INNER_L3_IPV6_EXT,
2296 RTE_PTYPE_INNER_L4_TCP,
2297 RTE_PTYPE_INNER_L4_UDP,
2301 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2302 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2308 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2310 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2312 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2313 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2314 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2315 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2316 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2317 DEV_RX_OFFLOAD_IPV4_CKSUM |
2318 DEV_RX_OFFLOAD_UDP_CKSUM |
2319 DEV_RX_OFFLOAD_TCP_CKSUM;
2320 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2321 DEV_TX_OFFLOAD_IPV4_CKSUM |
2322 DEV_TX_OFFLOAD_UDP_CKSUM |
2323 DEV_TX_OFFLOAD_TCP_CKSUM |
2324 DEV_TX_OFFLOAD_SCTP_CKSUM |
2325 DEV_TX_OFFLOAD_TCP_TSO;
2326 switch (hw->mac.type) {
2328 dev_info->max_rx_queues = 2;
2329 dev_info->max_tx_queues = 2;
2331 case e1000_vfadapt_i350:
2332 dev_info->max_rx_queues = 1;
2333 dev_info->max_tx_queues = 1;
2336 /* Should not happen */
2340 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2342 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2343 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2344 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2346 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2350 dev_info->default_txconf = (struct rte_eth_txconf) {
2352 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2353 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2354 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2359 dev_info->rx_desc_lim = rx_desc_lim;
2360 dev_info->tx_desc_lim = tx_desc_lim;
2363 /* return 0 means link status changed, -1 means not changed */
2365 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2367 struct e1000_hw *hw =
2368 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2369 struct rte_eth_link link, old;
2370 int link_check, count;
2373 hw->mac.get_link_status = 1;
2375 /* possible wait-to-complete in up to 9 seconds */
2376 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2377 /* Read the real link status */
2378 switch (hw->phy.media_type) {
2379 case e1000_media_type_copper:
2380 /* Do the work to read phy */
2381 e1000_check_for_link(hw);
2382 link_check = !hw->mac.get_link_status;
2385 case e1000_media_type_fiber:
2386 e1000_check_for_link(hw);
2387 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2391 case e1000_media_type_internal_serdes:
2392 e1000_check_for_link(hw);
2393 link_check = hw->mac.serdes_has_link;
2396 /* VF device is type_unknown */
2397 case e1000_media_type_unknown:
2398 eth_igbvf_link_update(hw);
2399 link_check = !hw->mac.get_link_status;
2405 if (link_check || wait_to_complete == 0)
2407 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2409 memset(&link, 0, sizeof(link));
2410 rte_igb_dev_atomic_read_link_status(dev, &link);
2413 /* Now we check if a transition has happened */
2415 uint16_t duplex, speed;
2416 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2417 link.link_duplex = (duplex == FULL_DUPLEX) ?
2418 ETH_LINK_FULL_DUPLEX :
2419 ETH_LINK_HALF_DUPLEX;
2420 link.link_speed = speed;
2421 link.link_status = ETH_LINK_UP;
2422 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2423 ETH_LINK_SPEED_FIXED);
2424 } else if (!link_check) {
2425 link.link_speed = 0;
2426 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2427 link.link_status = ETH_LINK_DOWN;
2428 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2430 rte_igb_dev_atomic_write_link_status(dev, &link);
2433 if (old.link_status == link.link_status)
2441 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2442 * For ASF and Pass Through versions of f/w this means
2443 * that the driver is loaded.
2446 igb_hw_control_acquire(struct e1000_hw *hw)
2450 /* Let firmware know the driver has taken over */
2451 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2452 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2456 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2457 * For ASF and Pass Through versions of f/w this means that the
2458 * driver is no longer loaded.
2461 igb_hw_control_release(struct e1000_hw *hw)
2465 /* Let firmware taken over control of h/w */
2466 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2467 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2468 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2472 * Bit of a misnomer, what this really means is
2473 * to enable OS management of the system... aka
2474 * to disable special hardware management features.
2477 igb_init_manageability(struct e1000_hw *hw)
2479 if (e1000_enable_mng_pass_thru(hw)) {
2480 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2481 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2483 /* disable hardware interception of ARP */
2484 manc &= ~(E1000_MANC_ARP_EN);
2486 /* enable receiving management packets to the host */
2487 manc |= E1000_MANC_EN_MNG2HOST;
2488 manc2h |= 1 << 5; /* Mng Port 623 */
2489 manc2h |= 1 << 6; /* Mng Port 664 */
2490 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2491 E1000_WRITE_REG(hw, E1000_MANC, manc);
2496 igb_release_manageability(struct e1000_hw *hw)
2498 if (e1000_enable_mng_pass_thru(hw)) {
2499 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2501 manc |= E1000_MANC_ARP_EN;
2502 manc &= ~E1000_MANC_EN_MNG2HOST;
2504 E1000_WRITE_REG(hw, E1000_MANC, manc);
2509 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2511 struct e1000_hw *hw =
2512 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2515 rctl = E1000_READ_REG(hw, E1000_RCTL);
2516 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2517 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2521 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2523 struct e1000_hw *hw =
2524 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2527 rctl = E1000_READ_REG(hw, E1000_RCTL);
2528 rctl &= (~E1000_RCTL_UPE);
2529 if (dev->data->all_multicast == 1)
2530 rctl |= E1000_RCTL_MPE;
2532 rctl &= (~E1000_RCTL_MPE);
2533 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2537 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2539 struct e1000_hw *hw =
2540 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2543 rctl = E1000_READ_REG(hw, E1000_RCTL);
2544 rctl |= E1000_RCTL_MPE;
2545 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2549 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2551 struct e1000_hw *hw =
2552 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2555 if (dev->data->promiscuous == 1)
2556 return; /* must remain in all_multicast mode */
2557 rctl = E1000_READ_REG(hw, E1000_RCTL);
2558 rctl &= (~E1000_RCTL_MPE);
2559 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2563 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2565 struct e1000_hw *hw =
2566 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2567 struct e1000_vfta * shadow_vfta =
2568 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2573 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2574 E1000_VFTA_ENTRY_MASK);
2575 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2576 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2581 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2583 /* update local VFTA copy */
2584 shadow_vfta->vfta[vid_idx] = vfta;
2590 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2591 enum rte_vlan_type vlan_type,
2594 struct e1000_hw *hw =
2595 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2598 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2599 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2601 /* only outer TPID of double VLAN can be configured*/
2602 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2603 reg = E1000_READ_REG(hw, E1000_VET);
2604 reg = (reg & (~E1000_VET_VET_EXT)) |
2605 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2606 E1000_WRITE_REG(hw, E1000_VET, reg);
2611 /* all other TPID values are read-only*/
2612 PMD_DRV_LOG(ERR, "Not supported");
2618 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2620 struct e1000_hw *hw =
2621 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2624 /* Filter Table Disable */
2625 reg = E1000_READ_REG(hw, E1000_RCTL);
2626 reg &= ~E1000_RCTL_CFIEN;
2627 reg &= ~E1000_RCTL_VFE;
2628 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2632 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2634 struct e1000_hw *hw =
2635 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2636 struct e1000_vfta * shadow_vfta =
2637 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2641 /* Filter Table Enable, CFI not used for packet acceptance */
2642 reg = E1000_READ_REG(hw, E1000_RCTL);
2643 reg &= ~E1000_RCTL_CFIEN;
2644 reg |= E1000_RCTL_VFE;
2645 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2647 /* restore VFTA table */
2648 for (i = 0; i < IGB_VFTA_SIZE; i++)
2649 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2653 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2655 struct e1000_hw *hw =
2656 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2659 /* VLAN Mode Disable */
2660 reg = E1000_READ_REG(hw, E1000_CTRL);
2661 reg &= ~E1000_CTRL_VME;
2662 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2666 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2668 struct e1000_hw *hw =
2669 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2672 /* VLAN Mode Enable */
2673 reg = E1000_READ_REG(hw, E1000_CTRL);
2674 reg |= E1000_CTRL_VME;
2675 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2679 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2681 struct e1000_hw *hw =
2682 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2685 /* CTRL_EXT: Extended VLAN */
2686 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2687 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2688 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2690 /* Update maximum packet length */
2691 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2692 E1000_WRITE_REG(hw, E1000_RLPML,
2693 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2698 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2700 struct e1000_hw *hw =
2701 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2704 /* CTRL_EXT: Extended VLAN */
2705 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2706 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2707 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2709 /* Update maximum packet length */
2710 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2711 E1000_WRITE_REG(hw, E1000_RLPML,
2712 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2717 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2719 if(mask & ETH_VLAN_STRIP_MASK){
2720 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2721 igb_vlan_hw_strip_enable(dev);
2723 igb_vlan_hw_strip_disable(dev);
2726 if(mask & ETH_VLAN_FILTER_MASK){
2727 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2728 igb_vlan_hw_filter_enable(dev);
2730 igb_vlan_hw_filter_disable(dev);
2733 if(mask & ETH_VLAN_EXTEND_MASK){
2734 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2735 igb_vlan_hw_extend_enable(dev);
2737 igb_vlan_hw_extend_disable(dev);
2743 * It enables the interrupt mask and then enable the interrupt.
2746 * Pointer to struct rte_eth_dev.
2749 * - On success, zero.
2750 * - On failure, a negative value.
2753 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2755 struct e1000_interrupt *intr =
2756 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2758 intr->mask |= E1000_ICR_LSC;
2763 /* It clears the interrupt causes and enables the interrupt.
2764 * It will be called once only during nic initialized.
2767 * Pointer to struct rte_eth_dev.
2770 * - On success, zero.
2771 * - On failure, a negative value.
2773 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2775 uint32_t mask, regval;
2776 struct e1000_hw *hw =
2777 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2778 struct rte_eth_dev_info dev_info;
2780 memset(&dev_info, 0, sizeof(dev_info));
2781 eth_igb_infos_get(dev, &dev_info);
2783 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2784 regval = E1000_READ_REG(hw, E1000_EIMS);
2785 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2791 * It reads ICR and gets interrupt causes, check it and set a bit flag
2792 * to update link status.
2795 * Pointer to struct rte_eth_dev.
2798 * - On success, zero.
2799 * - On failure, a negative value.
2802 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2805 struct e1000_hw *hw =
2806 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2807 struct e1000_interrupt *intr =
2808 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2810 igb_intr_disable(hw);
2812 /* read-on-clear nic registers here */
2813 icr = E1000_READ_REG(hw, E1000_ICR);
2816 if (icr & E1000_ICR_LSC) {
2817 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2820 if (icr & E1000_ICR_VMMB)
2821 intr->flags |= E1000_FLAG_MAILBOX;
2827 * It executes link_update after knowing an interrupt is prsent.
2830 * Pointer to struct rte_eth_dev.
2833 * - On success, zero.
2834 * - On failure, a negative value.
2837 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2838 struct rte_intr_handle *intr_handle)
2840 struct e1000_hw *hw =
2841 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842 struct e1000_interrupt *intr =
2843 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2844 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2845 uint32_t tctl, rctl;
2846 struct rte_eth_link link;
2849 if (intr->flags & E1000_FLAG_MAILBOX) {
2850 igb_pf_mbx_process(dev);
2851 intr->flags &= ~E1000_FLAG_MAILBOX;
2854 igb_intr_enable(dev);
2855 rte_intr_enable(intr_handle);
2857 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2858 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2860 /* set get_link_status to check register later */
2861 hw->mac.get_link_status = 1;
2862 ret = eth_igb_link_update(dev, 0);
2864 /* check if link has changed */
2868 memset(&link, 0, sizeof(link));
2869 rte_igb_dev_atomic_read_link_status(dev, &link);
2870 if (link.link_status) {
2872 " Port %d: Link Up - speed %u Mbps - %s",
2874 (unsigned)link.link_speed,
2875 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2876 "full-duplex" : "half-duplex");
2878 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2879 dev->data->port_id);
2882 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2883 pci_dev->addr.domain,
2885 pci_dev->addr.devid,
2886 pci_dev->addr.function);
2887 tctl = E1000_READ_REG(hw, E1000_TCTL);
2888 rctl = E1000_READ_REG(hw, E1000_RCTL);
2889 if (link.link_status) {
2891 tctl |= E1000_TCTL_EN;
2892 rctl |= E1000_RCTL_EN;
2895 tctl &= ~E1000_TCTL_EN;
2896 rctl &= ~E1000_RCTL_EN;
2898 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2899 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2900 E1000_WRITE_FLUSH(hw);
2901 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2908 * Interrupt handler which shall be registered at first.
2911 * Pointer to interrupt handle.
2913 * The address of parameter (struct rte_eth_dev *) regsitered before.
2919 eth_igb_interrupt_handler(void *param)
2921 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2923 eth_igb_interrupt_get_status(dev);
2924 eth_igb_interrupt_action(dev, dev->intr_handle);
2928 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2931 struct e1000_hw *hw =
2932 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2933 struct e1000_interrupt *intr =
2934 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2936 igbvf_intr_disable(hw);
2938 /* read-on-clear nic registers here */
2939 eicr = E1000_READ_REG(hw, E1000_EICR);
2942 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2943 intr->flags |= E1000_FLAG_MAILBOX;
2948 void igbvf_mbx_process(struct rte_eth_dev *dev)
2950 struct e1000_hw *hw =
2951 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952 struct e1000_mbx_info *mbx = &hw->mbx;
2955 if (mbx->ops.read(hw, &in_msg, 1, 0))
2958 /* PF reset VF event */
2959 if (in_msg == E1000_PF_CONTROL_MSG)
2960 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2964 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2966 struct e1000_interrupt *intr =
2967 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2969 if (intr->flags & E1000_FLAG_MAILBOX) {
2970 igbvf_mbx_process(dev);
2971 intr->flags &= ~E1000_FLAG_MAILBOX;
2974 igbvf_intr_enable(dev);
2975 rte_intr_enable(intr_handle);
2981 eth_igbvf_interrupt_handler(void *param)
2983 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2985 eth_igbvf_interrupt_get_status(dev);
2986 eth_igbvf_interrupt_action(dev, dev->intr_handle);
2990 eth_igb_led_on(struct rte_eth_dev *dev)
2992 struct e1000_hw *hw;
2994 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2995 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2999 eth_igb_led_off(struct rte_eth_dev *dev)
3001 struct e1000_hw *hw;
3003 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3004 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3008 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3010 struct e1000_hw *hw;
3015 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3016 fc_conf->pause_time = hw->fc.pause_time;
3017 fc_conf->high_water = hw->fc.high_water;
3018 fc_conf->low_water = hw->fc.low_water;
3019 fc_conf->send_xon = hw->fc.send_xon;
3020 fc_conf->autoneg = hw->mac.autoneg;
3023 * Return rx_pause and tx_pause status according to actual setting of
3024 * the TFCE and RFCE bits in the CTRL register.
3026 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3027 if (ctrl & E1000_CTRL_TFCE)
3032 if (ctrl & E1000_CTRL_RFCE)
3037 if (rx_pause && tx_pause)
3038 fc_conf->mode = RTE_FC_FULL;
3040 fc_conf->mode = RTE_FC_RX_PAUSE;
3042 fc_conf->mode = RTE_FC_TX_PAUSE;
3044 fc_conf->mode = RTE_FC_NONE;
3050 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3052 struct e1000_hw *hw;
3054 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3060 uint32_t rx_buf_size;
3061 uint32_t max_high_water;
3064 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3065 if (fc_conf->autoneg != hw->mac.autoneg)
3067 rx_buf_size = igb_get_rx_buffer_size(hw);
3068 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3070 /* At least reserve one Ethernet frame for watermark */
3071 max_high_water = rx_buf_size - ETHER_MAX_LEN;
3072 if ((fc_conf->high_water > max_high_water) ||
3073 (fc_conf->high_water < fc_conf->low_water)) {
3074 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3075 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3079 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3080 hw->fc.pause_time = fc_conf->pause_time;
3081 hw->fc.high_water = fc_conf->high_water;
3082 hw->fc.low_water = fc_conf->low_water;
3083 hw->fc.send_xon = fc_conf->send_xon;
3085 err = e1000_setup_link_generic(hw);
3086 if (err == E1000_SUCCESS) {
3088 /* check if we want to forward MAC frames - driver doesn't have native
3089 * capability to do that, so we'll write the registers ourselves */
3091 rctl = E1000_READ_REG(hw, E1000_RCTL);
3093 /* set or clear MFLCN.PMCF bit depending on configuration */
3094 if (fc_conf->mac_ctrl_frame_fwd != 0)
3095 rctl |= E1000_RCTL_PMCF;
3097 rctl &= ~E1000_RCTL_PMCF;
3099 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3100 E1000_WRITE_FLUSH(hw);
3105 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3109 #define E1000_RAH_POOLSEL_SHIFT (18)
3111 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3112 uint32_t index, uint32_t pool)
3114 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3117 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3118 rah = E1000_READ_REG(hw, E1000_RAH(index));
3119 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3120 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3125 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3127 uint8_t addr[ETHER_ADDR_LEN];
3128 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3130 memset(addr, 0, sizeof(addr));
3132 e1000_rar_set(hw, addr, index);
3136 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3137 struct ether_addr *addr)
3139 eth_igb_rar_clear(dev, 0);
3141 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3144 * Virtual Function operations
3147 igbvf_intr_disable(struct e1000_hw *hw)
3149 PMD_INIT_FUNC_TRACE();
3151 /* Clear interrupt mask to stop from interrupts being generated */
3152 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3154 E1000_WRITE_FLUSH(hw);
3158 igbvf_stop_adapter(struct rte_eth_dev *dev)
3162 struct rte_eth_dev_info dev_info;
3163 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3165 memset(&dev_info, 0, sizeof(dev_info));
3166 eth_igbvf_infos_get(dev, &dev_info);
3168 /* Clear interrupt mask to stop from interrupts being generated */
3169 igbvf_intr_disable(hw);
3171 /* Clear any pending interrupts, flush previous writes */
3172 E1000_READ_REG(hw, E1000_EICR);
3174 /* Disable the transmit unit. Each queue must be disabled. */
3175 for (i = 0; i < dev_info.max_tx_queues; i++)
3176 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3178 /* Disable the receive unit by stopping each queue */
3179 for (i = 0; i < dev_info.max_rx_queues; i++) {
3180 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3181 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3182 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3183 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3187 /* flush all queues disables */
3188 E1000_WRITE_FLUSH(hw);
3192 static int eth_igbvf_link_update(struct e1000_hw *hw)
3194 struct e1000_mbx_info *mbx = &hw->mbx;
3195 struct e1000_mac_info *mac = &hw->mac;
3196 int ret_val = E1000_SUCCESS;
3198 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3201 * We only want to run this if there has been a rst asserted.
3202 * in this case that could mean a link change, device reset,
3203 * or a virtual function reset
3206 /* If we were hit with a reset or timeout drop the link */
3207 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3208 mac->get_link_status = TRUE;
3210 if (!mac->get_link_status)
3213 /* if link status is down no point in checking to see if pf is up */
3214 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3217 /* if we passed all the tests above then the link is up and we no
3218 * longer need to check for link */
3219 mac->get_link_status = FALSE;
3227 igbvf_dev_configure(struct rte_eth_dev *dev)
3229 struct rte_eth_conf* conf = &dev->data->dev_conf;
3231 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3232 dev->data->port_id);
3235 * VF has no ability to enable/disable HW CRC
3236 * Keep the persistent behavior the same as Host PF
3238 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3239 if (!conf->rxmode.hw_strip_crc) {
3240 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3241 conf->rxmode.hw_strip_crc = 1;
3244 if (conf->rxmode.hw_strip_crc) {
3245 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3246 conf->rxmode.hw_strip_crc = 0;
3254 igbvf_dev_start(struct rte_eth_dev *dev)
3256 struct e1000_hw *hw =
3257 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3258 struct e1000_adapter *adapter =
3259 E1000_DEV_PRIVATE(dev->data->dev_private);
3260 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3261 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3263 uint32_t intr_vector = 0;
3265 PMD_INIT_FUNC_TRACE();
3267 hw->mac.ops.reset_hw(hw);
3268 adapter->stopped = 0;
3271 igbvf_set_vfta_all(dev,1);
3273 eth_igbvf_tx_init(dev);
3275 /* This can fail when allocating mbufs for descriptor rings */
3276 ret = eth_igbvf_rx_init(dev);
3278 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3279 igb_dev_clear_queues(dev);
3283 /* check and configure queue intr-vector mapping */
3284 if (dev->data->dev_conf.intr_conf.rxq != 0) {
3285 intr_vector = dev->data->nb_rx_queues;
3286 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3291 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3292 intr_handle->intr_vec =
3293 rte_zmalloc("intr_vec",
3294 dev->data->nb_rx_queues * sizeof(int), 0);
3295 if (!intr_handle->intr_vec) {
3296 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3297 " intr_vec", dev->data->nb_rx_queues);
3302 eth_igbvf_configure_msix_intr(dev);
3304 /* enable uio/vfio intr/eventfd mapping */
3305 rte_intr_enable(intr_handle);
3307 /* resume enabled intr since hw reset */
3308 igbvf_intr_enable(dev);
3314 igbvf_dev_stop(struct rte_eth_dev *dev)
3316 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3317 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3319 PMD_INIT_FUNC_TRACE();
3321 igbvf_stop_adapter(dev);
3324 * Clear what we set, but we still keep shadow_vfta to
3325 * restore after device starts
3327 igbvf_set_vfta_all(dev,0);
3329 igb_dev_clear_queues(dev);
3331 /* disable intr eventfd mapping */
3332 rte_intr_disable(intr_handle);
3334 /* Clean datapath event and queue/vec mapping */
3335 rte_intr_efd_disable(intr_handle);
3336 if (intr_handle->intr_vec) {
3337 rte_free(intr_handle->intr_vec);
3338 intr_handle->intr_vec = NULL;
3343 igbvf_dev_close(struct rte_eth_dev *dev)
3345 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3346 struct e1000_adapter *adapter =
3347 E1000_DEV_PRIVATE(dev->data->dev_private);
3348 struct ether_addr addr;
3350 PMD_INIT_FUNC_TRACE();
3354 igbvf_dev_stop(dev);
3355 adapter->stopped = 1;
3356 igb_dev_free_queues(dev);
3359 * reprogram the RAR with a zero mac address,
3360 * to ensure that the VF traffic goes to the PF
3361 * after stop, close and detach of the VF.
3364 memset(&addr, 0, sizeof(addr));
3365 igbvf_default_mac_addr_set(dev, &addr);
3369 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3371 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3373 /* Set both unicast and multicast promisc */
3374 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3378 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3380 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3382 /* If in allmulticast mode leave multicast promisc */
3383 if (dev->data->all_multicast == 1)
3384 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3386 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3390 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3392 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3394 /* In promiscuous mode multicast promisc already set */
3395 if (dev->data->promiscuous == 0)
3396 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3400 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3402 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3404 /* In promiscuous mode leave multicast promisc enabled */
3405 if (dev->data->promiscuous == 0)
3406 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3409 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3411 struct e1000_mbx_info *mbx = &hw->mbx;
3415 /* After set vlan, vlan strip will also be enabled in igb driver*/
3416 msgbuf[0] = E1000_VF_SET_VLAN;
3418 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3420 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3422 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3426 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3430 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3431 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3438 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3440 struct e1000_hw *hw =
3441 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3442 struct e1000_vfta * shadow_vfta =
3443 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3444 int i = 0, j = 0, vfta = 0, mask = 1;
3446 for (i = 0; i < IGB_VFTA_SIZE; i++){
3447 vfta = shadow_vfta->vfta[i];
3450 for (j = 0; j < 32; j++){
3453 (uint16_t)((i<<5)+j), on);
3462 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3464 struct e1000_hw *hw =
3465 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3466 struct e1000_vfta * shadow_vfta =
3467 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3468 uint32_t vid_idx = 0;
3469 uint32_t vid_bit = 0;
3472 PMD_INIT_FUNC_TRACE();
3474 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3475 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3477 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3480 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3481 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3483 /*Save what we set and retore it after device reset*/
3485 shadow_vfta->vfta[vid_idx] |= vid_bit;
3487 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3493 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3495 struct e1000_hw *hw =
3496 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3498 /* index is not used by rar_set() */
3499 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3504 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3505 struct rte_eth_rss_reta_entry64 *reta_conf,
3510 uint16_t idx, shift;
3511 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3513 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3514 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3515 "(%d) doesn't match the number hardware can supported "
3516 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3520 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3521 idx = i / RTE_RETA_GROUP_SIZE;
3522 shift = i % RTE_RETA_GROUP_SIZE;
3523 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3527 if (mask == IGB_4_BIT_MASK)
3530 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3531 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3532 if (mask & (0x1 << j))
3533 reta |= reta_conf[idx].reta[shift + j] <<
3536 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3538 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3545 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3546 struct rte_eth_rss_reta_entry64 *reta_conf,
3551 uint16_t idx, shift;
3552 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3554 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3555 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3556 "(%d) doesn't match the number hardware can supported "
3557 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3561 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3562 idx = i / RTE_RETA_GROUP_SIZE;
3563 shift = i % RTE_RETA_GROUP_SIZE;
3564 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3568 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3569 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3570 if (mask & (0x1 << j))
3571 reta_conf[idx].reta[shift + j] =
3572 ((reta >> (CHAR_BIT * j)) &
3581 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3582 struct rte_eth_syn_filter *filter,
3585 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3586 struct e1000_filter_info *filter_info =
3587 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3588 uint32_t synqf, rfctl;
3590 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3593 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3596 if (synqf & E1000_SYN_FILTER_ENABLE)
3599 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3600 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3602 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3603 if (filter->hig_pri)
3604 rfctl |= E1000_RFCTL_SYNQFP;
3606 rfctl &= ~E1000_RFCTL_SYNQFP;
3608 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3610 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3615 filter_info->syn_info = synqf;
3616 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3617 E1000_WRITE_FLUSH(hw);
3622 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3623 struct rte_eth_syn_filter *filter)
3625 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3626 uint32_t synqf, rfctl;
3628 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3629 if (synqf & E1000_SYN_FILTER_ENABLE) {
3630 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3631 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3632 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3633 E1000_SYN_FILTER_QUEUE_SHIFT);
3641 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3642 enum rte_filter_op filter_op,
3645 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3648 MAC_TYPE_FILTER_SUP(hw->mac.type);
3650 if (filter_op == RTE_ETH_FILTER_NOP)
3654 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3659 switch (filter_op) {
3660 case RTE_ETH_FILTER_ADD:
3661 ret = eth_igb_syn_filter_set(dev,
3662 (struct rte_eth_syn_filter *)arg,
3665 case RTE_ETH_FILTER_DELETE:
3666 ret = eth_igb_syn_filter_set(dev,
3667 (struct rte_eth_syn_filter *)arg,
3670 case RTE_ETH_FILTER_GET:
3671 ret = eth_igb_syn_filter_get(dev,
3672 (struct rte_eth_syn_filter *)arg);
3675 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3683 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3685 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3686 struct e1000_2tuple_filter_info *filter_info)
3688 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3690 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3691 return -EINVAL; /* filter index is out of range. */
3692 if (filter->tcp_flags > TCP_FLAG_ALL)
3693 return -EINVAL; /* flags is invalid. */
3695 switch (filter->dst_port_mask) {
3697 filter_info->dst_port_mask = 0;
3698 filter_info->dst_port = filter->dst_port;
3701 filter_info->dst_port_mask = 1;
3704 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3708 switch (filter->proto_mask) {
3710 filter_info->proto_mask = 0;
3711 filter_info->proto = filter->proto;
3714 filter_info->proto_mask = 1;
3717 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3721 filter_info->priority = (uint8_t)filter->priority;
3722 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3723 filter_info->tcp_flags = filter->tcp_flags;
3725 filter_info->tcp_flags = 0;
3730 static inline struct e1000_2tuple_filter *
3731 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3732 struct e1000_2tuple_filter_info *key)
3734 struct e1000_2tuple_filter *it;
3736 TAILQ_FOREACH(it, filter_list, entries) {
3737 if (memcmp(key, &it->filter_info,
3738 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3745 /* inject a igb 2tuple filter to HW */
3747 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3748 struct e1000_2tuple_filter *filter)
3750 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3751 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3752 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3756 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3757 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3758 imir |= E1000_IMIR_PORT_BP;
3760 imir &= ~E1000_IMIR_PORT_BP;
3762 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3764 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3765 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3766 ttqf |= (uint32_t)(filter->filter_info.proto &
3767 E1000_TTQF_PROTOCOL_MASK);
3768 if (filter->filter_info.proto_mask == 0)
3769 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3771 /* tcp flags bits setting. */
3772 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3773 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3774 imir_ext |= E1000_IMIREXT_CTRL_URG;
3775 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3776 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3777 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3778 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3779 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3780 imir_ext |= E1000_IMIREXT_CTRL_RST;
3781 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3782 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3783 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3784 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3786 imir_ext |= E1000_IMIREXT_CTRL_BP;
3788 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3789 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3790 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3794 * igb_add_2tuple_filter - add a 2tuple filter
3797 * dev: Pointer to struct rte_eth_dev.
3798 * ntuple_filter: ponter to the filter that will be added.
3801 * - On success, zero.
3802 * - On failure, a negative value.
3805 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3806 struct rte_eth_ntuple_filter *ntuple_filter)
3808 struct e1000_filter_info *filter_info =
3809 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3810 struct e1000_2tuple_filter *filter;
3813 filter = rte_zmalloc("e1000_2tuple_filter",
3814 sizeof(struct e1000_2tuple_filter), 0);
3818 ret = ntuple_filter_to_2tuple(ntuple_filter,
3819 &filter->filter_info);
3824 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3825 &filter->filter_info) != NULL) {
3826 PMD_DRV_LOG(ERR, "filter exists.");
3830 filter->queue = ntuple_filter->queue;
3833 * look for an unused 2tuple filter index,
3834 * and insert the filter to list.
3836 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3837 if (!(filter_info->twotuple_mask & (1 << i))) {
3838 filter_info->twotuple_mask |= 1 << i;
3840 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3846 if (i >= E1000_MAX_TTQF_FILTERS) {
3847 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3852 igb_inject_2uple_filter(dev, filter);
3857 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3858 struct e1000_2tuple_filter *filter)
3860 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3861 struct e1000_filter_info *filter_info =
3862 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3864 filter_info->twotuple_mask &= ~(1 << filter->index);
3865 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3868 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3869 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3870 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3875 * igb_remove_2tuple_filter - remove a 2tuple filter
3878 * dev: Pointer to struct rte_eth_dev.
3879 * ntuple_filter: ponter to the filter that will be removed.
3882 * - On success, zero.
3883 * - On failure, a negative value.
3886 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3887 struct rte_eth_ntuple_filter *ntuple_filter)
3889 struct e1000_filter_info *filter_info =
3890 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3891 struct e1000_2tuple_filter_info filter_2tuple;
3892 struct e1000_2tuple_filter *filter;
3895 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3896 ret = ntuple_filter_to_2tuple(ntuple_filter,
3901 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3903 if (filter == NULL) {
3904 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3908 igb_delete_2tuple_filter(dev, filter);
3913 /* inject a igb flex filter to HW */
3915 igb_inject_flex_filter(struct rte_eth_dev *dev,
3916 struct e1000_flex_filter *filter)
3918 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3919 uint32_t wufc, queueing;
3923 wufc = E1000_READ_REG(hw, E1000_WUFC);
3924 if (filter->index < E1000_MAX_FHFT)
3925 reg_off = E1000_FHFT(filter->index);
3927 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3929 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3930 (E1000_WUFC_FLX0 << filter->index));
3931 queueing = filter->filter_info.len |
3932 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3933 (filter->filter_info.priority <<
3934 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3935 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3938 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3939 E1000_WRITE_REG(hw, reg_off,
3940 filter->filter_info.dwords[j]);
3941 reg_off += sizeof(uint32_t);
3942 E1000_WRITE_REG(hw, reg_off,
3943 filter->filter_info.dwords[++j]);
3944 reg_off += sizeof(uint32_t);
3945 E1000_WRITE_REG(hw, reg_off,
3946 (uint32_t)filter->filter_info.mask[i]);
3947 reg_off += sizeof(uint32_t) * 2;
3952 static inline struct e1000_flex_filter *
3953 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3954 struct e1000_flex_filter_info *key)
3956 struct e1000_flex_filter *it;
3958 TAILQ_FOREACH(it, filter_list, entries) {
3959 if (memcmp(key, &it->filter_info,
3960 sizeof(struct e1000_flex_filter_info)) == 0)
3967 /* remove a flex byte filter
3969 * dev: Pointer to struct rte_eth_dev.
3970 * filter: the pointer of the filter will be removed.
3973 igb_remove_flex_filter(struct rte_eth_dev *dev,
3974 struct e1000_flex_filter *filter)
3976 struct e1000_filter_info *filter_info =
3977 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3978 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3982 wufc = E1000_READ_REG(hw, E1000_WUFC);
3983 if (filter->index < E1000_MAX_FHFT)
3984 reg_off = E1000_FHFT(filter->index);
3986 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3988 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3989 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3991 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3992 (~(E1000_WUFC_FLX0 << filter->index)));
3994 filter_info->flex_mask &= ~(1 << filter->index);
3995 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4000 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4001 struct rte_eth_flex_filter *filter,
4004 struct e1000_filter_info *filter_info =
4005 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4006 struct e1000_flex_filter *flex_filter, *it;
4010 flex_filter = rte_zmalloc("e1000_flex_filter",
4011 sizeof(struct e1000_flex_filter), 0);
4012 if (flex_filter == NULL)
4015 flex_filter->filter_info.len = filter->len;
4016 flex_filter->filter_info.priority = filter->priority;
4017 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4018 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4020 /* reverse bits in flex filter's mask*/
4021 for (shift = 0; shift < CHAR_BIT; shift++) {
4022 if (filter->mask[i] & (0x01 << shift))
4023 mask |= (0x80 >> shift);
4025 flex_filter->filter_info.mask[i] = mask;
4028 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4029 &flex_filter->filter_info);
4030 if (it == NULL && !add) {
4031 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4032 rte_free(flex_filter);
4035 if (it != NULL && add) {
4036 PMD_DRV_LOG(ERR, "filter exists.");
4037 rte_free(flex_filter);
4042 flex_filter->queue = filter->queue;
4044 * look for an unused flex filter index
4045 * and insert the filter into the list.
4047 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4048 if (!(filter_info->flex_mask & (1 << i))) {
4049 filter_info->flex_mask |= 1 << i;
4050 flex_filter->index = i;
4051 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4057 if (i >= E1000_MAX_FLEX_FILTERS) {
4058 PMD_DRV_LOG(ERR, "flex filters are full.");
4059 rte_free(flex_filter);
4063 igb_inject_flex_filter(dev, flex_filter);
4066 igb_remove_flex_filter(dev, it);
4067 rte_free(flex_filter);
4074 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4075 struct rte_eth_flex_filter *filter)
4077 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4078 struct e1000_filter_info *filter_info =
4079 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4080 struct e1000_flex_filter flex_filter, *it;
4081 uint32_t wufc, queueing, wufc_en = 0;
4083 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4084 flex_filter.filter_info.len = filter->len;
4085 flex_filter.filter_info.priority = filter->priority;
4086 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4087 memcpy(flex_filter.filter_info.mask, filter->mask,
4088 RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
4090 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4091 &flex_filter.filter_info);
4093 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4097 wufc = E1000_READ_REG(hw, E1000_WUFC);
4098 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4100 if ((wufc & wufc_en) == wufc_en) {
4101 uint32_t reg_off = 0;
4102 if (it->index < E1000_MAX_FHFT)
4103 reg_off = E1000_FHFT(it->index);
4105 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4107 queueing = E1000_READ_REG(hw,
4108 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4109 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4110 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4111 E1000_FHFT_QUEUEING_PRIO_SHIFT;
4112 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4113 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4120 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4121 enum rte_filter_op filter_op,
4124 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4125 struct rte_eth_flex_filter *filter;
4128 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4130 if (filter_op == RTE_ETH_FILTER_NOP)
4134 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4139 filter = (struct rte_eth_flex_filter *)arg;
4140 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4141 || filter->len % sizeof(uint64_t) != 0) {
4142 PMD_DRV_LOG(ERR, "filter's length is out of range");
4145 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4146 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4150 switch (filter_op) {
4151 case RTE_ETH_FILTER_ADD:
4152 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4154 case RTE_ETH_FILTER_DELETE:
4155 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4157 case RTE_ETH_FILTER_GET:
4158 ret = eth_igb_get_flex_filter(dev, filter);
4161 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4169 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4171 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4172 struct e1000_5tuple_filter_info *filter_info)
4174 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4176 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4177 return -EINVAL; /* filter index is out of range. */
4178 if (filter->tcp_flags > TCP_FLAG_ALL)
4179 return -EINVAL; /* flags is invalid. */
4181 switch (filter->dst_ip_mask) {
4183 filter_info->dst_ip_mask = 0;
4184 filter_info->dst_ip = filter->dst_ip;
4187 filter_info->dst_ip_mask = 1;
4190 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4194 switch (filter->src_ip_mask) {
4196 filter_info->src_ip_mask = 0;
4197 filter_info->src_ip = filter->src_ip;
4200 filter_info->src_ip_mask = 1;
4203 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4207 switch (filter->dst_port_mask) {
4209 filter_info->dst_port_mask = 0;
4210 filter_info->dst_port = filter->dst_port;
4213 filter_info->dst_port_mask = 1;
4216 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4220 switch (filter->src_port_mask) {
4222 filter_info->src_port_mask = 0;
4223 filter_info->src_port = filter->src_port;
4226 filter_info->src_port_mask = 1;
4229 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4233 switch (filter->proto_mask) {
4235 filter_info->proto_mask = 0;
4236 filter_info->proto = filter->proto;
4239 filter_info->proto_mask = 1;
4242 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4246 filter_info->priority = (uint8_t)filter->priority;
4247 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4248 filter_info->tcp_flags = filter->tcp_flags;
4250 filter_info->tcp_flags = 0;
4255 static inline struct e1000_5tuple_filter *
4256 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4257 struct e1000_5tuple_filter_info *key)
4259 struct e1000_5tuple_filter *it;
4261 TAILQ_FOREACH(it, filter_list, entries) {
4262 if (memcmp(key, &it->filter_info,
4263 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4270 /* inject a igb 5-tuple filter to HW */
4272 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4273 struct e1000_5tuple_filter *filter)
4275 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4276 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4277 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4281 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4282 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4283 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4284 if (filter->filter_info.dst_ip_mask == 0)
4285 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4286 if (filter->filter_info.src_port_mask == 0)
4287 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4288 if (filter->filter_info.proto_mask == 0)
4289 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4290 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4291 E1000_FTQF_QUEUE_MASK;
4292 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4293 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4294 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4295 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4297 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4298 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4300 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4301 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4302 imir |= E1000_IMIR_PORT_BP;
4304 imir &= ~E1000_IMIR_PORT_BP;
4305 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4307 /* tcp flags bits setting. */
4308 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4309 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4310 imir_ext |= E1000_IMIREXT_CTRL_URG;
4311 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4312 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4313 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4314 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4315 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4316 imir_ext |= E1000_IMIREXT_CTRL_RST;
4317 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4318 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4319 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4320 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4322 imir_ext |= E1000_IMIREXT_CTRL_BP;
4324 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4325 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4329 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4332 * dev: Pointer to struct rte_eth_dev.
4333 * ntuple_filter: ponter to the filter that will be added.
4336 * - On success, zero.
4337 * - On failure, a negative value.
4340 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4341 struct rte_eth_ntuple_filter *ntuple_filter)
4343 struct e1000_filter_info *filter_info =
4344 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4345 struct e1000_5tuple_filter *filter;
4349 filter = rte_zmalloc("e1000_5tuple_filter",
4350 sizeof(struct e1000_5tuple_filter), 0);
4354 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4355 &filter->filter_info);
4361 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4362 &filter->filter_info) != NULL) {
4363 PMD_DRV_LOG(ERR, "filter exists.");
4367 filter->queue = ntuple_filter->queue;
4370 * look for an unused 5tuple filter index,
4371 * and insert the filter to list.
4373 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4374 if (!(filter_info->fivetuple_mask & (1 << i))) {
4375 filter_info->fivetuple_mask |= 1 << i;
4377 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4383 if (i >= E1000_MAX_FTQF_FILTERS) {
4384 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4389 igb_inject_5tuple_filter_82576(dev, filter);
4394 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4395 struct e1000_5tuple_filter *filter)
4397 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4398 struct e1000_filter_info *filter_info =
4399 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4401 filter_info->fivetuple_mask &= ~(1 << filter->index);
4402 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4405 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4406 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4407 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4408 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4409 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4410 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4411 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4416 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4419 * dev: Pointer to struct rte_eth_dev.
4420 * ntuple_filter: ponter to the filter that will be removed.
4423 * - On success, zero.
4424 * - On failure, a negative value.
4427 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4428 struct rte_eth_ntuple_filter *ntuple_filter)
4430 struct e1000_filter_info *filter_info =
4431 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4432 struct e1000_5tuple_filter_info filter_5tuple;
4433 struct e1000_5tuple_filter *filter;
4436 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4437 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4442 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4444 if (filter == NULL) {
4445 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4449 igb_delete_5tuple_filter_82576(dev, filter);
4455 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4458 struct e1000_hw *hw;
4459 struct rte_eth_dev_info dev_info;
4460 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4463 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4465 #ifdef RTE_LIBRTE_82571_SUPPORT
4466 /* XXX: not bigger than max_rx_pktlen */
4467 if (hw->mac.type == e1000_82571)
4470 eth_igb_infos_get(dev, &dev_info);
4472 /* check that mtu is within the allowed range */
4473 if ((mtu < ETHER_MIN_MTU) ||
4474 (frame_size > dev_info.max_rx_pktlen))
4477 /* refuse mtu that requires the support of scattered packets when this
4478 * feature has not been enabled before. */
4479 if (!dev->data->scattered_rx &&
4480 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4483 rctl = E1000_READ_REG(hw, E1000_RCTL);
4485 /* switch to jumbo mode if needed */
4486 if (frame_size > ETHER_MAX_LEN) {
4487 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4488 rctl |= E1000_RCTL_LPE;
4490 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4491 rctl &= ~E1000_RCTL_LPE;
4493 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4495 /* update max frame size */
4496 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4498 E1000_WRITE_REG(hw, E1000_RLPML,
4499 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4505 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4508 * dev: Pointer to struct rte_eth_dev.
4509 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4510 * add: if true, add filter, if false, remove filter
4513 * - On success, zero.
4514 * - On failure, a negative value.
4517 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4518 struct rte_eth_ntuple_filter *ntuple_filter,
4521 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4524 switch (ntuple_filter->flags) {
4525 case RTE_5TUPLE_FLAGS:
4526 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4527 if (hw->mac.type != e1000_82576)
4530 ret = igb_add_5tuple_filter_82576(dev,
4533 ret = igb_remove_5tuple_filter_82576(dev,
4536 case RTE_2TUPLE_FLAGS:
4537 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4538 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4539 hw->mac.type != e1000_i210 &&
4540 hw->mac.type != e1000_i211)
4543 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4545 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4556 * igb_get_ntuple_filter - get a ntuple filter
4559 * dev: Pointer to struct rte_eth_dev.
4560 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4563 * - On success, zero.
4564 * - On failure, a negative value.
4567 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4568 struct rte_eth_ntuple_filter *ntuple_filter)
4570 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4571 struct e1000_filter_info *filter_info =
4572 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4573 struct e1000_5tuple_filter_info filter_5tuple;
4574 struct e1000_2tuple_filter_info filter_2tuple;
4575 struct e1000_5tuple_filter *p_5tuple_filter;
4576 struct e1000_2tuple_filter *p_2tuple_filter;
4579 switch (ntuple_filter->flags) {
4580 case RTE_5TUPLE_FLAGS:
4581 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4582 if (hw->mac.type != e1000_82576)
4584 memset(&filter_5tuple,
4586 sizeof(struct e1000_5tuple_filter_info));
4587 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4591 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4592 &filter_info->fivetuple_list,
4594 if (p_5tuple_filter == NULL) {
4595 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4598 ntuple_filter->queue = p_5tuple_filter->queue;
4600 case RTE_2TUPLE_FLAGS:
4601 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4602 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4604 memset(&filter_2tuple,
4606 sizeof(struct e1000_2tuple_filter_info));
4607 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4610 p_2tuple_filter = igb_2tuple_filter_lookup(
4611 &filter_info->twotuple_list,
4613 if (p_2tuple_filter == NULL) {
4614 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4617 ntuple_filter->queue = p_2tuple_filter->queue;
4628 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4629 * @dev: pointer to rte_eth_dev structure
4630 * @filter_op:operation will be taken.
4631 * @arg: a pointer to specific structure corresponding to the filter_op
4634 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4635 enum rte_filter_op filter_op,
4638 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4641 MAC_TYPE_FILTER_SUP(hw->mac.type);
4643 if (filter_op == RTE_ETH_FILTER_NOP)
4647 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4652 switch (filter_op) {
4653 case RTE_ETH_FILTER_ADD:
4654 ret = igb_add_del_ntuple_filter(dev,
4655 (struct rte_eth_ntuple_filter *)arg,
4658 case RTE_ETH_FILTER_DELETE:
4659 ret = igb_add_del_ntuple_filter(dev,
4660 (struct rte_eth_ntuple_filter *)arg,
4663 case RTE_ETH_FILTER_GET:
4664 ret = igb_get_ntuple_filter(dev,
4665 (struct rte_eth_ntuple_filter *)arg);
4668 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4676 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4681 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4682 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4683 (filter_info->ethertype_mask & (1 << i)))
4690 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4691 uint16_t ethertype, uint32_t etqf)
4695 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4696 if (!(filter_info->ethertype_mask & (1 << i))) {
4697 filter_info->ethertype_mask |= 1 << i;
4698 filter_info->ethertype_filters[i].ethertype = ethertype;
4699 filter_info->ethertype_filters[i].etqf = etqf;
4707 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4710 if (idx >= E1000_MAX_ETQF_FILTERS)
4712 filter_info->ethertype_mask &= ~(1 << idx);
4713 filter_info->ethertype_filters[idx].ethertype = 0;
4714 filter_info->ethertype_filters[idx].etqf = 0;
4720 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4721 struct rte_eth_ethertype_filter *filter,
4724 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4725 struct e1000_filter_info *filter_info =
4726 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4730 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4731 filter->ether_type == ETHER_TYPE_IPv6) {
4732 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4733 " ethertype filter.", filter->ether_type);
4737 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4738 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4741 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4742 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4746 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4747 if (ret >= 0 && add) {
4748 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4749 filter->ether_type);
4752 if (ret < 0 && !add) {
4753 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4754 filter->ether_type);
4759 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4760 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4761 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4762 ret = igb_ethertype_filter_insert(filter_info,
4763 filter->ether_type, etqf);
4765 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4769 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4773 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4774 E1000_WRITE_FLUSH(hw);
4780 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4781 struct rte_eth_ethertype_filter *filter)
4783 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4784 struct e1000_filter_info *filter_info =
4785 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4789 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4791 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4792 filter->ether_type);
4796 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4797 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4798 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4800 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4801 E1000_ETQF_QUEUE_SHIFT;
4809 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4810 * @dev: pointer to rte_eth_dev structure
4811 * @filter_op:operation will be taken.
4812 * @arg: a pointer to specific structure corresponding to the filter_op
4815 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4816 enum rte_filter_op filter_op,
4819 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4822 MAC_TYPE_FILTER_SUP(hw->mac.type);
4824 if (filter_op == RTE_ETH_FILTER_NOP)
4828 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4833 switch (filter_op) {
4834 case RTE_ETH_FILTER_ADD:
4835 ret = igb_add_del_ethertype_filter(dev,
4836 (struct rte_eth_ethertype_filter *)arg,
4839 case RTE_ETH_FILTER_DELETE:
4840 ret = igb_add_del_ethertype_filter(dev,
4841 (struct rte_eth_ethertype_filter *)arg,
4844 case RTE_ETH_FILTER_GET:
4845 ret = igb_get_ethertype_filter(dev,
4846 (struct rte_eth_ethertype_filter *)arg);
4849 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4857 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4858 enum rte_filter_type filter_type,
4859 enum rte_filter_op filter_op,
4864 switch (filter_type) {
4865 case RTE_ETH_FILTER_NTUPLE:
4866 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4868 case RTE_ETH_FILTER_ETHERTYPE:
4869 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4871 case RTE_ETH_FILTER_SYN:
4872 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4874 case RTE_ETH_FILTER_FLEXIBLE:
4875 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4877 case RTE_ETH_FILTER_GENERIC:
4878 if (filter_op != RTE_ETH_FILTER_GET)
4880 *(const void **)arg = &igb_flow_ops;
4883 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4892 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4893 struct ether_addr *mc_addr_set,
4894 uint32_t nb_mc_addr)
4896 struct e1000_hw *hw;
4898 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4899 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4904 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4906 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4907 uint64_t systime_cycles;
4909 switch (hw->mac.type) {
4913 * Need to read System Time Residue Register to be able
4914 * to read the other two registers.
4916 E1000_READ_REG(hw, E1000_SYSTIMR);
4917 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4918 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4919 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4926 * Need to read System Time Residue Register to be able
4927 * to read the other two registers.
4929 E1000_READ_REG(hw, E1000_SYSTIMR);
4930 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4931 /* Only the 8 LSB are valid. */
4932 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4936 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4937 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4942 return systime_cycles;
4946 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4948 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4949 uint64_t rx_tstamp_cycles;
4951 switch (hw->mac.type) {
4954 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4955 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4956 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4962 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4963 /* Only the 8 LSB are valid. */
4964 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4968 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4969 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4974 return rx_tstamp_cycles;
4978 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4980 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4981 uint64_t tx_tstamp_cycles;
4983 switch (hw->mac.type) {
4986 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4987 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4988 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4994 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4995 /* Only the 8 LSB are valid. */
4996 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5000 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5001 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5006 return tx_tstamp_cycles;
5010 igb_start_timecounters(struct rte_eth_dev *dev)
5012 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5013 struct e1000_adapter *adapter =
5014 (struct e1000_adapter *)dev->data->dev_private;
5015 uint32_t incval = 1;
5017 uint64_t mask = E1000_CYCLECOUNTER_MASK;
5019 switch (hw->mac.type) {
5023 /* 32 LSB bits + 8 MSB bits = 40 bits */
5024 mask = (1ULL << 40) - 1;
5029 * Start incrementing the register
5030 * used to timestamp PTP packets.
5032 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5035 incval = E1000_INCVALUE_82576;
5036 shift = IGB_82576_TSYNC_SHIFT;
5037 E1000_WRITE_REG(hw, E1000_TIMINCA,
5038 E1000_INCPERIOD_82576 | incval);
5045 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5046 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5047 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5049 adapter->systime_tc.cc_mask = mask;
5050 adapter->systime_tc.cc_shift = shift;
5051 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5053 adapter->rx_tstamp_tc.cc_mask = mask;
5054 adapter->rx_tstamp_tc.cc_shift = shift;
5055 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5057 adapter->tx_tstamp_tc.cc_mask = mask;
5058 adapter->tx_tstamp_tc.cc_shift = shift;
5059 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5063 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5065 struct e1000_adapter *adapter =
5066 (struct e1000_adapter *)dev->data->dev_private;
5068 adapter->systime_tc.nsec += delta;
5069 adapter->rx_tstamp_tc.nsec += delta;
5070 adapter->tx_tstamp_tc.nsec += delta;
5076 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5079 struct e1000_adapter *adapter =
5080 (struct e1000_adapter *)dev->data->dev_private;
5082 ns = rte_timespec_to_ns(ts);
5084 /* Set the timecounters to a new value. */
5085 adapter->systime_tc.nsec = ns;
5086 adapter->rx_tstamp_tc.nsec = ns;
5087 adapter->tx_tstamp_tc.nsec = ns;
5093 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5095 uint64_t ns, systime_cycles;
5096 struct e1000_adapter *adapter =
5097 (struct e1000_adapter *)dev->data->dev_private;
5099 systime_cycles = igb_read_systime_cyclecounter(dev);
5100 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5101 *ts = rte_ns_to_timespec(ns);
5107 igb_timesync_enable(struct rte_eth_dev *dev)
5109 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5113 /* Stop the timesync system time. */
5114 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5115 /* Reset the timesync system time value. */
5116 switch (hw->mac.type) {
5122 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5125 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5126 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5129 /* Not supported. */
5133 /* Enable system time for it isn't on by default. */
5134 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5135 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5136 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5138 igb_start_timecounters(dev);
5140 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5141 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5143 E1000_ETQF_FILTER_ENABLE |
5146 /* Enable timestamping of received PTP packets. */
5147 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5148 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5149 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5151 /* Enable Timestamping of transmitted PTP packets. */
5152 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5153 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5154 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5160 igb_timesync_disable(struct rte_eth_dev *dev)
5162 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5165 /* Disable timestamping of transmitted PTP packets. */
5166 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5167 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5168 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5170 /* Disable timestamping of received PTP packets. */
5171 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5172 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5173 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5175 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5176 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5178 /* Stop incrementating the System Time registers. */
5179 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5185 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5186 struct timespec *timestamp,
5187 uint32_t flags __rte_unused)
5189 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5190 struct e1000_adapter *adapter =
5191 (struct e1000_adapter *)dev->data->dev_private;
5192 uint32_t tsync_rxctl;
5193 uint64_t rx_tstamp_cycles;
5196 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5197 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5200 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5201 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5202 *timestamp = rte_ns_to_timespec(ns);
5208 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5209 struct timespec *timestamp)
5211 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5212 struct e1000_adapter *adapter =
5213 (struct e1000_adapter *)dev->data->dev_private;
5214 uint32_t tsync_txctl;
5215 uint64_t tx_tstamp_cycles;
5218 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5219 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5222 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5223 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5224 *timestamp = rte_ns_to_timespec(ns);
5230 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5234 const struct reg_info *reg_group;
5236 while ((reg_group = igb_regs[g_ind++]))
5237 count += igb_reg_group_count(reg_group);
5243 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5247 const struct reg_info *reg_group;
5249 while ((reg_group = igbvf_regs[g_ind++]))
5250 count += igb_reg_group_count(reg_group);
5256 eth_igb_get_regs(struct rte_eth_dev *dev,
5257 struct rte_dev_reg_info *regs)
5259 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5260 uint32_t *data = regs->data;
5263 const struct reg_info *reg_group;
5266 regs->length = eth_igb_get_reg_length(dev);
5267 regs->width = sizeof(uint32_t);
5271 /* Support only full register dump */
5272 if ((regs->length == 0) ||
5273 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5274 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5276 while ((reg_group = igb_regs[g_ind++]))
5277 count += igb_read_regs_group(dev, &data[count],
5286 igbvf_get_regs(struct rte_eth_dev *dev,
5287 struct rte_dev_reg_info *regs)
5289 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5290 uint32_t *data = regs->data;
5293 const struct reg_info *reg_group;
5296 regs->length = igbvf_get_reg_length(dev);
5297 regs->width = sizeof(uint32_t);
5301 /* Support only full register dump */
5302 if ((regs->length == 0) ||
5303 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5304 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5306 while ((reg_group = igbvf_regs[g_ind++]))
5307 count += igb_read_regs_group(dev, &data[count],
5316 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5318 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5320 /* Return unit is byte count */
5321 return hw->nvm.word_size * 2;
5325 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5326 struct rte_dev_eeprom_info *in_eeprom)
5328 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5329 struct e1000_nvm_info *nvm = &hw->nvm;
5330 uint16_t *data = in_eeprom->data;
5333 first = in_eeprom->offset >> 1;
5334 length = in_eeprom->length >> 1;
5335 if ((first >= hw->nvm.word_size) ||
5336 ((first + length) >= hw->nvm.word_size))
5339 in_eeprom->magic = hw->vendor_id |
5340 ((uint32_t)hw->device_id << 16);
5342 if ((nvm->ops.read) == NULL)
5345 return nvm->ops.read(hw, first, length, data);
5349 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5350 struct rte_dev_eeprom_info *in_eeprom)
5352 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5353 struct e1000_nvm_info *nvm = &hw->nvm;
5354 uint16_t *data = in_eeprom->data;
5357 first = in_eeprom->offset >> 1;
5358 length = in_eeprom->length >> 1;
5359 if ((first >= hw->nvm.word_size) ||
5360 ((first + length) >= hw->nvm.word_size))
5363 in_eeprom->magic = (uint32_t)hw->vendor_id |
5364 ((uint32_t)hw->device_id << 16);
5366 if ((nvm->ops.write) == NULL)
5368 return nvm->ops.write(hw, first, length, data);
5372 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5374 struct e1000_hw *hw =
5375 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5376 uint32_t mask = 1 << queue_id;
5378 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5379 E1000_WRITE_FLUSH(hw);
5385 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5387 struct e1000_hw *hw =
5388 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5389 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5390 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5391 uint32_t mask = 1 << queue_id;
5394 regval = E1000_READ_REG(hw, E1000_EIMS);
5395 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5396 E1000_WRITE_FLUSH(hw);
5398 rte_intr_enable(intr_handle);
5404 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5405 uint8_t index, uint8_t offset)
5407 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5410 val &= ~((uint32_t)0xFF << offset);
5412 /* write vector and valid bit */
5413 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5415 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5419 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5420 uint8_t queue, uint8_t msix_vector)
5424 if (hw->mac.type == e1000_82575) {
5426 tmp = E1000_EICR_RX_QUEUE0 << queue;
5427 else if (direction == 1)
5428 tmp = E1000_EICR_TX_QUEUE0 << queue;
5429 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5430 } else if (hw->mac.type == e1000_82576) {
5431 if ((direction == 0) || (direction == 1))
5432 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5433 ((queue & 0x8) << 1) +
5435 } else if ((hw->mac.type == e1000_82580) ||
5436 (hw->mac.type == e1000_i350) ||
5437 (hw->mac.type == e1000_i354) ||
5438 (hw->mac.type == e1000_i210) ||
5439 (hw->mac.type == e1000_i211)) {
5440 if ((direction == 0) || (direction == 1))
5441 eth_igb_write_ivar(hw, msix_vector,
5443 ((queue & 0x1) << 4) +
5448 /* Sets up the hardware to generate MSI-X interrupts properly
5450 * board private structure
5453 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5456 uint32_t tmpval, regval, intr_mask;
5457 struct e1000_hw *hw =
5458 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5459 uint32_t vec = E1000_MISC_VEC_ID;
5460 uint32_t base = E1000_MISC_VEC_ID;
5461 uint32_t misc_shift = 0;
5462 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5463 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5465 /* won't configure msix register if no mapping is done
5466 * between intr vector and event fd
5468 if (!rte_intr_dp_is_en(intr_handle))
5471 if (rte_intr_allow_others(intr_handle)) {
5472 vec = base = E1000_RX_VEC_START;
5476 /* set interrupt vector for other causes */
5477 if (hw->mac.type == e1000_82575) {
5478 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5479 /* enable MSI-X PBA support */
5480 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5482 /* Auto-Mask interrupts upon ICR read */
5483 tmpval |= E1000_CTRL_EXT_EIAME;
5484 tmpval |= E1000_CTRL_EXT_IRCA;
5486 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5488 /* enable msix_other interrupt */
5489 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5490 regval = E1000_READ_REG(hw, E1000_EIAC);
5491 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5492 regval = E1000_READ_REG(hw, E1000_EIAM);
5493 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5494 } else if ((hw->mac.type == e1000_82576) ||
5495 (hw->mac.type == e1000_82580) ||
5496 (hw->mac.type == e1000_i350) ||
5497 (hw->mac.type == e1000_i354) ||
5498 (hw->mac.type == e1000_i210) ||
5499 (hw->mac.type == e1000_i211)) {
5500 /* turn on MSI-X capability first */
5501 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5502 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5504 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5506 regval = E1000_READ_REG(hw, E1000_EIAC);
5507 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5509 /* enable msix_other interrupt */
5510 regval = E1000_READ_REG(hw, E1000_EIMS);
5511 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5512 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5513 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5516 /* use EIAM to auto-mask when MSI-X interrupt
5517 * is asserted, this saves a register write for every interrupt
5519 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5521 regval = E1000_READ_REG(hw, E1000_EIAM);
5522 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5524 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5525 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5526 intr_handle->intr_vec[queue_id] = vec;
5527 if (vec < base + intr_handle->nb_efd - 1)
5531 E1000_WRITE_FLUSH(hw);
5534 /* restore n-tuple filter */
5536 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5538 struct e1000_filter_info *filter_info =
5539 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5540 struct e1000_5tuple_filter *p_5tuple;
5541 struct e1000_2tuple_filter *p_2tuple;
5543 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5544 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5547 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5548 igb_inject_2uple_filter(dev, p_2tuple);
5552 /* restore SYN filter */
5554 igb_syn_filter_restore(struct rte_eth_dev *dev)
5556 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5557 struct e1000_filter_info *filter_info =
5558 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5561 synqf = filter_info->syn_info;
5563 if (synqf & E1000_SYN_FILTER_ENABLE) {
5564 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5565 E1000_WRITE_FLUSH(hw);
5569 /* restore ethernet type filter */
5571 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5573 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5574 struct e1000_filter_info *filter_info =
5575 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5578 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5579 if (filter_info->ethertype_mask & (1 << i)) {
5580 E1000_WRITE_REG(hw, E1000_ETQF(i),
5581 filter_info->ethertype_filters[i].etqf);
5582 E1000_WRITE_FLUSH(hw);
5587 /* restore flex byte filter */
5589 igb_flex_filter_restore(struct rte_eth_dev *dev)
5591 struct e1000_filter_info *filter_info =
5592 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5593 struct e1000_flex_filter *flex_filter;
5595 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5596 igb_inject_flex_filter(dev, flex_filter);
5600 /* restore all types filter */
5602 igb_filter_restore(struct rte_eth_dev *dev)
5604 igb_ntuple_filter_restore(dev);
5605 igb_ethertype_filter_restore(dev);
5606 igb_syn_filter_restore(dev);
5607 igb_flex_filter_restore(dev);
5612 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5613 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5614 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5615 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5616 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5617 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");