drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "base/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59 #include "igb_regs.h"
  60
  61 /*
  62  * Default values for port configuration
  63  */
  64 #define IGB_DEFAULT_RX_FREE_THRESH  32
  65
  66 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  67 #define IGB_DEFAULT_RX_HTHRESH      8
  68 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  69
  70 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  71 #define IGB_DEFAULT_TX_HTHRESH      1
  72 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  73
  74 #define IGB_HKEY_MAX_INDEX 10
  75
  76 /* Bit shift and mask */
  77 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  78 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  79 #define IGB_8_BIT_WIDTH  CHAR_BIT
  80 #define IGB_8_BIT_MASK   UINT8_MAX
  81
  82 /* Additional timesync values. */
  83 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  84 #define E1000_ETQF_FILTER_1588       3
  85 #define IGB_82576_TSYNC_SHIFT        16
  86 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  87 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  89
  90 #define E1000_VTIVAR_MISC                0x01740
  91 #define E1000_VTIVAR_MISC_MASK           0xFF
  92 #define E1000_VTIVAR_VALID               0x80
  93 #define E1000_VTIVAR_MISC_MAILBOX        0
  94 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  95
  96 /* External VLAN Enable bit mask */
  97 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  98
  99 /* External VLAN Ether Type bit mask and shift */
 100 #define E1000_VET_VET_EXT            0xFFFF0000
 101 #define E1000_VET_VET_EXT_SHIFT      16
 102
 103 static int  eth_igb_configure(struct rte_eth_dev *dev);
 104 static int  eth_igb_start(struct rte_eth_dev *dev);
 105 static void eth_igb_stop(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 107 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 108 static void eth_igb_close(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 113 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 114                                 int wait_to_complete);
 115 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 116                                 struct rte_eth_stats *rte_stats);
 117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 118                               struct rte_eth_xstat *xstats, unsigned n);
 119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
 120                 const uint64_t *ids,
 121                 uint64_t *values, unsigned int n);
 122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 123                                     struct rte_eth_xstat_name *xstats_names,
 124                                     unsigned int size);
 125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
 126                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 127                 unsigned int limit);
 128 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 131                                    char *fw_version, size_t fw_size);
 132 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 133                               struct rte_eth_dev_info *dev_info);
 134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 136                                 struct rte_eth_dev_info *dev_info);
 137 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 138                                 struct rte_eth_fc_conf *fc_conf);
 139 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 140                                 struct rte_eth_fc_conf *fc_conf);
 141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 145                                     struct rte_intr_handle *handle);
 146 static void eth_igb_interrupt_handler(void *param);
 147 static int  igb_hardware_init(struct e1000_hw *hw);
 148 static void igb_hw_control_acquire(struct e1000_hw *hw);
 149 static void igb_hw_control_release(struct e1000_hw *hw);
 150 static void igb_init_manageability(struct e1000_hw *hw);
 151 static void igb_release_manageability(struct e1000_hw *hw);
 152
 153 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154
 155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 156                 uint16_t vlan_id, int on);
 157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 158                                  enum rte_vlan_type vlan_type,
 159                                  uint16_t tpid_id);
 160 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 161
 162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 168
 169 static int eth_igb_led_on(struct rte_eth_dev *dev);
 170 static int eth_igb_led_off(struct rte_eth_dev *dev);
 171
 172 static void igb_intr_disable(struct e1000_hw *hw);
 173 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 174 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 175                 struct ether_addr *mac_addr,
 176                 uint32_t index, uint32_t pool);
 177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 179                 struct ether_addr *addr);
 180
 181 static void igbvf_intr_disable(struct e1000_hw *hw);
 182 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 183 static int igbvf_dev_start(struct rte_eth_dev *dev);
 184 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 185 static void igbvf_dev_close(struct rte_eth_dev *dev);
 186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 190 static int eth_igbvf_link_update(struct e1000_hw *hw);
 191 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 192                                 struct rte_eth_stats *rte_stats);
 193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 194                                 struct rte_eth_xstat *xstats, unsigned n);
 195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 196                                       struct rte_eth_xstat_name *xstats_names,
 197                                       unsigned limit);
 198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 200                 uint16_t vlan_id, int on);
 201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 204                 struct ether_addr *addr);
 205 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 206 static int igbvf_get_regs(struct rte_eth_dev *dev,
 207                 struct rte_dev_reg_info *regs);
 208
 209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 210                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 211                                    uint16_t reta_size);
 212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 213                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 214                                   uint16_t reta_size);
 215
 216 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 217                         struct rte_eth_syn_filter *filter,
 218                         bool add);
 219 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 220                         struct rte_eth_syn_filter *filter);
 221 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 222                         enum rte_filter_op filter_op,
 223                         void *arg);
 224 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 225                         struct rte_eth_ntuple_filter *ntuple_filter);
 226 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 227                         struct rte_eth_ntuple_filter *ntuple_filter);
 228 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 229                         struct rte_eth_flex_filter *filter,
 230                         bool add);
 231 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 232                         struct rte_eth_flex_filter *filter);
 233 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 234                         enum rte_filter_op filter_op,
 235                         void *arg);
 236 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 237                         struct rte_eth_ntuple_filter *ntuple_filter);
 238 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 239                         struct rte_eth_ntuple_filter *ntuple_filter);
 240 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 241                         struct rte_eth_ntuple_filter *filter,
 242                         bool add);
 243 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 244                         struct rte_eth_ntuple_filter *filter);
 245 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 246                                 enum rte_filter_op filter_op,
 247                                 void *arg);
 248 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 249                         struct rte_eth_ethertype_filter *filter,
 250                         bool add);
 251 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 252                                 enum rte_filter_op filter_op,
 253                                 void *arg);
 254 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 255                         struct rte_eth_ethertype_filter *filter);
 256 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 257                      enum rte_filter_type filter_type,
 258                      enum rte_filter_op filter_op,
 259                      void *arg);
 260 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 261 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 262                 struct rte_dev_reg_info *regs);
 263 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 264 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 265                 struct rte_dev_eeprom_info *eeprom);
 266 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 267                 struct rte_dev_eeprom_info *eeprom);
 268 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 269                                     struct ether_addr *mc_addr_set,
 270                                     uint32_t nb_mc_addr);
 271 static int igb_timesync_enable(struct rte_eth_dev *dev);
 272 static int igb_timesync_disable(struct rte_eth_dev *dev);
 273 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 274                                           struct timespec *timestamp,
 275                                           uint32_t flags);
 276 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 277                                           struct timespec *timestamp);
 278 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 279 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 280                                   struct timespec *timestamp);
 281 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 282                                    const struct timespec *timestamp);
 283 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 284                                         uint16_t queue_id);
 285 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 286                                          uint16_t queue_id);
 287 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 288                                        uint8_t queue, uint8_t msix_vector);
 289 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 290                                uint8_t index, uint8_t offset);
 291 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 292 static void eth_igbvf_interrupt_handler(void *param);
 293 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 294
 295 /*
 296  * Define VF Stats MACRO for Non "cleared on read" register
 297  */
 298 #define UPDATE_VF_STAT(reg, last, cur)            \
 299 {                                                 \
 300         u32 latest = E1000_READ_REG(hw, reg);     \
 301         cur += (latest - last) & UINT_MAX;        \
 302         last = latest;                            \
 303 }
 304
 305 #define IGB_FC_PAUSE_TIME 0x0680
 306 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 307 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 308
 309 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 310
 311 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 312
 313 /*
 314  * The set of PCI devices this driver supports
 315  */
 316 static const struct rte_pci_id pci_id_igb_map[] = {
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 325
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 329
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 336
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 347         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 348         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 349         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 350         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 351         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 352         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 353         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 354         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 356         { .vendor_id = 0, /* sentinel */ },
 357 };
 358
 359 /*
 360  * The set of PCI devices this driver supports (for 82576&I350 VF)
 361  */
 362 static const struct rte_pci_id pci_id_igbvf_map[] = {
 363         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 364         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 365         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 366         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 367         { .vendor_id = 0, /* sentinel */ },
 368 };
 369
 370 static const struct rte_eth_desc_lim rx_desc_lim = {
 371         .nb_max = E1000_MAX_RING_DESC,
 372         .nb_min = E1000_MIN_RING_DESC,
 373         .nb_align = IGB_RXD_ALIGN,
 374 };
 375
 376 static const struct rte_eth_desc_lim tx_desc_lim = {
 377         .nb_max = E1000_MAX_RING_DESC,
 378         .nb_min = E1000_MIN_RING_DESC,
 379         .nb_align = IGB_RXD_ALIGN,
 380         .nb_seg_max = IGB_TX_MAX_SEG,
 381         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 382 };
 383
 384 static const struct eth_dev_ops eth_igb_ops = {
 385         .dev_configure        = eth_igb_configure,
 386         .dev_start            = eth_igb_start,
 387         .dev_stop             = eth_igb_stop,
 388         .dev_set_link_up      = eth_igb_dev_set_link_up,
 389         .dev_set_link_down    = eth_igb_dev_set_link_down,
 390         .dev_close            = eth_igb_close,
 391         .promiscuous_enable   = eth_igb_promiscuous_enable,
 392         .promiscuous_disable  = eth_igb_promiscuous_disable,
 393         .allmulticast_enable  = eth_igb_allmulticast_enable,
 394         .allmulticast_disable = eth_igb_allmulticast_disable,
 395         .link_update          = eth_igb_link_update,
 396         .stats_get            = eth_igb_stats_get,
 397         .xstats_get           = eth_igb_xstats_get,
 398         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 399         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 400         .xstats_get_names     = eth_igb_xstats_get_names,
 401         .stats_reset          = eth_igb_stats_reset,
 402         .xstats_reset         = eth_igb_xstats_reset,
 403         .fw_version_get       = eth_igb_fw_version_get,
 404         .dev_infos_get        = eth_igb_infos_get,
 405         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 406         .mtu_set              = eth_igb_mtu_set,
 407         .vlan_filter_set      = eth_igb_vlan_filter_set,
 408         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 409         .vlan_offload_set     = eth_igb_vlan_offload_set,
 410         .rx_queue_setup       = eth_igb_rx_queue_setup,
 411         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 412         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 413         .rx_queue_release     = eth_igb_rx_queue_release,
 414         .rx_queue_count       = eth_igb_rx_queue_count,
 415         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 416         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 417         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 418         .tx_queue_setup       = eth_igb_tx_queue_setup,
 419         .tx_queue_release     = eth_igb_tx_queue_release,
 420         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 421         .dev_led_on           = eth_igb_led_on,
 422         .dev_led_off          = eth_igb_led_off,
 423         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 424         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 425         .mac_addr_add         = eth_igb_rar_set,
 426         .mac_addr_remove      = eth_igb_rar_clear,
 427         .mac_addr_set         = eth_igb_default_mac_addr_set,
 428         .reta_update          = eth_igb_rss_reta_update,
 429         .reta_query           = eth_igb_rss_reta_query,
 430         .rss_hash_update      = eth_igb_rss_hash_update,
 431         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 432         .filter_ctrl          = eth_igb_filter_ctrl,
 433         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 434         .rxq_info_get         = igb_rxq_info_get,
 435         .txq_info_get         = igb_txq_info_get,
 436         .timesync_enable      = igb_timesync_enable,
 437         .timesync_disable     = igb_timesync_disable,
 438         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 439         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 440         .get_reg              = eth_igb_get_regs,
 441         .get_eeprom_length    = eth_igb_get_eeprom_length,
 442         .get_eeprom           = eth_igb_get_eeprom,
 443         .set_eeprom           = eth_igb_set_eeprom,
 444         .timesync_adjust_time = igb_timesync_adjust_time,
 445         .timesync_read_time   = igb_timesync_read_time,
 446         .timesync_write_time  = igb_timesync_write_time,
 447 };
 448
 449 /*
 450  * dev_ops for virtual function, bare necessities for basic vf
 451  * operation have been implemented
 452  */
 453 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 454         .dev_configure        = igbvf_dev_configure,
 455         .dev_start            = igbvf_dev_start,
 456         .dev_stop             = igbvf_dev_stop,
 457         .dev_close            = igbvf_dev_close,
 458         .promiscuous_enable   = igbvf_promiscuous_enable,
 459         .promiscuous_disable  = igbvf_promiscuous_disable,
 460         .allmulticast_enable  = igbvf_allmulticast_enable,
 461         .allmulticast_disable = igbvf_allmulticast_disable,
 462         .link_update          = eth_igb_link_update,
 463         .stats_get            = eth_igbvf_stats_get,
 464         .xstats_get           = eth_igbvf_xstats_get,
 465         .xstats_get_names     = eth_igbvf_xstats_get_names,
 466         .stats_reset          = eth_igbvf_stats_reset,
 467         .xstats_reset         = eth_igbvf_stats_reset,
 468         .vlan_filter_set      = igbvf_vlan_filter_set,
 469         .dev_infos_get        = eth_igbvf_infos_get,
 470         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 471         .rx_queue_setup       = eth_igb_rx_queue_setup,
 472         .rx_queue_release     = eth_igb_rx_queue_release,
 473         .tx_queue_setup       = eth_igb_tx_queue_setup,
 474         .tx_queue_release     = eth_igb_tx_queue_release,
 475         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 476         .rxq_info_get         = igb_rxq_info_get,
 477         .txq_info_get         = igb_txq_info_get,
 478         .mac_addr_set         = igbvf_default_mac_addr_set,
 479         .get_reg              = igbvf_get_regs,
 480 };
 481
 482 /* store statistics names and its offset in stats structure */
 483 struct rte_igb_xstats_name_off {
 484         char name[RTE_ETH_XSTATS_NAME_SIZE];
 485         unsigned offset;
 486 };
 487
 488 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 489         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 490         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 491         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 492         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 493         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 494         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 495         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 496                 ecol)},
 497         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 498         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 499         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 500         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 501         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 502         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 503         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 504         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 505         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 506         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 507         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 508                 fcruc)},
 509         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 510         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 511         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 512         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 513         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 514                 prc1023)},
 515         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 516                 prc1522)},
 517         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 518         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 519         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 520         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 521         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 522         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 523         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 524         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 525         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 526         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 527         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 528         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 529         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 530         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 531         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 532         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 533         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 534         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 535                 ptc1023)},
 536         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 537                 ptc1522)},
 538         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 539         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 540         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 541         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 542         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 543         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 544         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 545
 546         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 547 };
 548
 549 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 550                 sizeof(rte_igb_stats_strings[0]))
 551
 552 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 553         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 554         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 555         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 556         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 557         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 558 };
 559
 560 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 561                 sizeof(rte_igbvf_stats_strings[0]))
 562
 563 /**
 564  * Atomically reads the link status information from global
 565  * structure rte_eth_dev.
 566  *
 567  * @param dev
 568  *   - Pointer to the structure rte_eth_dev to read from.
 569  *   - Pointer to the buffer to be saved with the link status.
 570  *
 571  * @return
 572  *   - On success, zero.
 573  *   - On failure, negative value.
 574  */
 575 static inline int
 576 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 577                                 struct rte_eth_link *link)
 578 {
 579         struct rte_eth_link *dst = link;
 580         struct rte_eth_link *src = &(dev->data->dev_link);
 581
 582         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 583                                         *(uint64_t *)src) == 0)
 584                 return -1;
 585
 586         return 0;
 587 }
 588
 589 /**
 590  * Atomically writes the link status information into global
 591  * structure rte_eth_dev.
 592  *
 593  * @param dev
 594  *   - Pointer to the structure rte_eth_dev to read from.
 595  *   - Pointer to the buffer to be saved with the link status.
 596  *
 597  * @return
 598  *   - On success, zero.
 599  *   - On failure, negative value.
 600  */
 601 static inline int
 602 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 603                                 struct rte_eth_link *link)
 604 {
 605         struct rte_eth_link *dst = &(dev->data->dev_link);
 606         struct rte_eth_link *src = link;
 607
 608         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 609                                         *(uint64_t *)src) == 0)
 610                 return -1;
 611
 612         return 0;
 613 }
 614
 615 static inline void
 616 igb_intr_enable(struct rte_eth_dev *dev)
 617 {
 618         struct e1000_interrupt *intr =
 619                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 620         struct e1000_hw *hw =
 621                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 622
 623         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 624         E1000_WRITE_FLUSH(hw);
 625 }
 626
 627 static void
 628 igb_intr_disable(struct e1000_hw *hw)
 629 {
 630         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 631         E1000_WRITE_FLUSH(hw);
 632 }
 633
 634 static inline void
 635 igbvf_intr_enable(struct rte_eth_dev *dev)
 636 {
 637         struct e1000_hw *hw =
 638                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 639
 640         /* only for mailbox */
 641         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 642         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 643         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 644         E1000_WRITE_FLUSH(hw);
 645 }
 646
 647 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 648 static void
 649 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 650 {
 651         uint32_t tmp = 0;
 652
 653         /* mailbox */
 654         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 655         tmp |= E1000_VTIVAR_VALID;
 656         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 657 }
 658
 659 static void
 660 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 661 {
 662         struct e1000_hw *hw =
 663                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 664
 665         /* Configure VF other cause ivar */
 666         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 667 }
 668
 669 static inline int32_t
 670 igb_pf_reset_hw(struct e1000_hw *hw)
 671 {
 672         uint32_t ctrl_ext;
 673         int32_t status;
 674
 675         status = e1000_reset_hw(hw);
 676
 677         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 678         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 679         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 680         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 681         E1000_WRITE_FLUSH(hw);
 682
 683         return status;
 684 }
 685
 686 static void
 687 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 688 {
 689         struct e1000_hw *hw =
 690                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 691
 692
 693         hw->vendor_id = pci_dev->id.vendor_id;
 694         hw->device_id = pci_dev->id.device_id;
 695         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 696         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 697
 698         e1000_set_mac_type(hw);
 699
 700         /* need to check if it is a vf device below */
 701 }
 702
 703 static int
 704 igb_reset_swfw_lock(struct e1000_hw *hw)
 705 {
 706         int ret_val;
 707
 708         /*
 709          * Do mac ops initialization manually here, since we will need
 710          * some function pointers set by this call.
 711          */
 712         ret_val = e1000_init_mac_params(hw);
 713         if (ret_val)
 714                 return ret_val;
 715
 716         /*
 717          * SMBI lock should not fail in this early stage. If this is the case,
 718          * it is due to an improper exit of the application.
 719          * So force the release of the faulty lock.
 720          */
 721         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 722                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 723         }
 724         e1000_put_hw_semaphore_generic(hw);
 725
 726         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 727                 uint16_t mask;
 728
 729                 /*
 730                  * Phy lock should not fail in this early stage. If this is the case,
 731                  * it is due to an improper exit of the application.
 732                  * So force the release of the faulty lock.
 733                  */
 734                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 735                 if (hw->bus.func > E1000_FUNC_1)
 736                         mask <<= 2;
 737                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 738                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 739                                     hw->bus.func);
 740                 }
 741                 hw->mac.ops.release_swfw_sync(hw, mask);
 742
 743                 /*
 744                  * This one is more tricky since it is common to all ports; but
 745                  * swfw_sync retries last long enough (1s) to be almost sure that if
 746                  * lock can not be taken it is due to an improper lock of the
 747                  * semaphore.
 748                  */
 749                 mask = E1000_SWFW_EEP_SM;
 750                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 751                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 752                 }
 753                 hw->mac.ops.release_swfw_sync(hw, mask);
 754         }
 755
 756         return E1000_SUCCESS;
 757 }
 758
 759 static int
 760 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 761 {
 762         int error = 0;
 763         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
 764         struct e1000_hw *hw =
 765                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 766         struct e1000_vfta * shadow_vfta =
 767                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 768         struct e1000_filter_info *filter_info =
 769                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 770         struct e1000_adapter *adapter =
 771                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 772
 773         uint32_t ctrl_ext;
 774
 775         eth_dev->dev_ops = &eth_igb_ops;
 776         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 777         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 778         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 779
 780         /* for secondary processes, we don't initialise any further as primary
 781          * has already done this work. Only check we don't need a different
 782          * RX function */
 783         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 784                 if (eth_dev->data->scattered_rx)
 785                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 786                 return 0;
 787         }
 788
 789         rte_eth_copy_pci_info(eth_dev, pci_dev);
 790         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 791
 792         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 793
 794         igb_identify_hardware(eth_dev, pci_dev);
 795         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 796                 error = -EIO;
 797                 goto err_late;
 798         }
 799
 800         e1000_get_bus_info(hw);
 801
 802         /* Reset any pending lock */
 803         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 804                 error = -EIO;
 805                 goto err_late;
 806         }
 807
 808         /* Finish initialization */
 809         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 810                 error = -EIO;
 811                 goto err_late;
 812         }
 813
 814         hw->mac.autoneg = 1;
 815         hw->phy.autoneg_wait_to_complete = 0;
 816         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 817
 818         /* Copper options */
 819         if (hw->phy.media_type == e1000_media_type_copper) {
 820                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 821                 hw->phy.disable_polarity_correction = 0;
 822                 hw->phy.ms_type = e1000_ms_hw_default;
 823         }
 824
 825         /*
 826          * Start from a known state, this is important in reading the nvm
 827          * and mac from that.
 828          */
 829         igb_pf_reset_hw(hw);
 830
 831         /* Make sure we have a good EEPROM before we read from it */
 832         if (e1000_validate_nvm_checksum(hw) < 0) {
 833                 /*
 834                  * Some PCI-E parts fail the first check due to
 835                  * the link being in sleep state, call it again,
 836                  * if it fails a second time its a real issue.
 837                  */
 838                 if (e1000_validate_nvm_checksum(hw) < 0) {
 839                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 840                         error = -EIO;
 841                         goto err_late;
 842                 }
 843         }
 844
 845         /* Read the permanent MAC address out of the EEPROM */
 846         if (e1000_read_mac_addr(hw) != 0) {
 847                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 848                 error = -EIO;
 849                 goto err_late;
 850         }
 851
 852         /* Allocate memory for storing MAC addresses */
 853         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 854                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 855         if (eth_dev->data->mac_addrs == NULL) {
 856                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 857                                                 "store MAC addresses",
 858                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 859                 error = -ENOMEM;
 860                 goto err_late;
 861         }
 862
 863         /* Copy the permanent MAC address */
 864         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 865
 866         /* initialize the vfta */
 867         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 868
 869         /* Now initialize the hardware */
 870         if (igb_hardware_init(hw) != 0) {
 871                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 872                 rte_free(eth_dev->data->mac_addrs);
 873                 eth_dev->data->mac_addrs = NULL;
 874                 error = -ENODEV;
 875                 goto err_late;
 876         }
 877         hw->mac.get_link_status = 1;
 878         adapter->stopped = 0;
 879
 880         /* Indicate SOL/IDER usage */
 881         if (e1000_check_reset_block(hw) < 0) {
 882                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 883                                         "SOL/IDER session");
 884         }
 885
 886         /* initialize PF if max_vfs not zero */
 887         igb_pf_host_init(eth_dev);
 888
 889         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 890         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 891         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 892         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 893         E1000_WRITE_FLUSH(hw);
 894
 895         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 896                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 897                      pci_dev->id.device_id);
 898
 899         rte_intr_callback_register(&pci_dev->intr_handle,
 900                                    eth_igb_interrupt_handler,
 901                                    (void *)eth_dev);
 902
 903         /* enable uio/vfio intr/eventfd mapping */
 904         rte_intr_enable(&pci_dev->intr_handle);
 905
 906         /* enable support intr */
 907         igb_intr_enable(eth_dev);
 908
 909         TAILQ_INIT(&filter_info->flex_list);
 910         filter_info->flex_mask = 0;
 911         TAILQ_INIT(&filter_info->twotuple_list);
 912         filter_info->twotuple_mask = 0;
 913         TAILQ_INIT(&filter_info->fivetuple_list);
 914         filter_info->fivetuple_mask = 0;
 915
 916         return 0;
 917
 918 err_late:
 919         igb_hw_control_release(hw);
 920
 921         return error;
 922 }
 923
 924 static int
 925 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 926 {
 927         struct rte_pci_device *pci_dev;
 928         struct rte_intr_handle *intr_handle;
 929         struct e1000_hw *hw;
 930         struct e1000_adapter *adapter =
 931                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 932
 933         PMD_INIT_FUNC_TRACE();
 934
 935         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 936                 return -EPERM;
 937
 938         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 939         pci_dev = E1000_DEV_TO_PCI(eth_dev);
 940         intr_handle = &pci_dev->intr_handle;
 941
 942         if (adapter->stopped == 0)
 943                 eth_igb_close(eth_dev);
 944
 945         eth_dev->dev_ops = NULL;
 946         eth_dev->rx_pkt_burst = NULL;
 947         eth_dev->tx_pkt_burst = NULL;
 948
 949         /* Reset any pending lock */
 950         igb_reset_swfw_lock(hw);
 951
 952         rte_free(eth_dev->data->mac_addrs);
 953         eth_dev->data->mac_addrs = NULL;
 954
 955         /* uninitialize PF if max_vfs not zero */
 956         igb_pf_host_uninit(eth_dev);
 957
 958         /* disable uio intr before callback unregister */
 959         rte_intr_disable(intr_handle);
 960         rte_intr_callback_unregister(intr_handle,
 961                                      eth_igb_interrupt_handler, eth_dev);
 962
 963         return 0;
 964 }
 965
 966 /*
 967  * Virtual Function device init
 968  */
 969 static int
 970 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 971 {
 972         struct rte_pci_device *pci_dev;
 973         struct rte_intr_handle *intr_handle;
 974         struct e1000_adapter *adapter =
 975                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 976         struct e1000_hw *hw =
 977                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 978         int diag;
 979         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 980
 981         PMD_INIT_FUNC_TRACE();
 982
 983         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 984         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 985         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 986         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 987
 988         /* for secondary processes, we don't initialise any further as primary
 989          * has already done this work. Only check we don't need a different
 990          * RX function */
 991         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 992                 if (eth_dev->data->scattered_rx)
 993                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 994                 return 0;
 995         }
 996
 997         pci_dev = E1000_DEV_TO_PCI(eth_dev);
 998         rte_eth_copy_pci_info(eth_dev, pci_dev);
 999         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1000
1001         hw->device_id = pci_dev->id.device_id;
1002         hw->vendor_id = pci_dev->id.vendor_id;
1003         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1004         adapter->stopped = 0;
1005
1006         /* Initialize the shared code (base driver) */
1007         diag = e1000_setup_init_funcs(hw, TRUE);
1008         if (diag != 0) {
1009                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1010                         diag);
1011                 return -EIO;
1012         }
1013
1014         /* init_mailbox_params */
1015         hw->mbx.ops.init_params(hw);
1016
1017         /* Disable the interrupts for VF */
1018         igbvf_intr_disable(hw);
1019
1020         diag = hw->mac.ops.reset_hw(hw);
1021
1022         /* Allocate memory for storing MAC addresses */
1023         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1024                 hw->mac.rar_entry_count, 0);
1025         if (eth_dev->data->mac_addrs == NULL) {
1026                 PMD_INIT_LOG(ERR,
1027                         "Failed to allocate %d bytes needed to store MAC "
1028                         "addresses",
1029                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1030                 return -ENOMEM;
1031         }
1032
1033         /* Generate a random MAC address, if none was assigned by PF. */
1034         if (is_zero_ether_addr(perm_addr)) {
1035                 eth_random_addr(perm_addr->addr_bytes);
1036                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1037                 if (diag) {
1038                         rte_free(eth_dev->data->mac_addrs);
1039                         eth_dev->data->mac_addrs = NULL;
1040                         return diag;
1041                 }
1042                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1043                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1044                              "%02x:%02x:%02x:%02x:%02x:%02x",
1045                              perm_addr->addr_bytes[0],
1046                              perm_addr->addr_bytes[1],
1047                              perm_addr->addr_bytes[2],
1048                              perm_addr->addr_bytes[3],
1049                              perm_addr->addr_bytes[4],
1050                              perm_addr->addr_bytes[5]);
1051         }
1052
1053         /* Copy the permanent MAC address */
1054         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1055                         &eth_dev->data->mac_addrs[0]);
1056
1057         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1058                      "mac.type=%s",
1059                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1060                      pci_dev->id.device_id, "igb_mac_82576_vf");
1061
1062         intr_handle = &pci_dev->intr_handle;
1063         rte_intr_callback_register(intr_handle,
1064                                    eth_igbvf_interrupt_handler, eth_dev);
1065
1066         return 0;
1067 }
1068
1069 static int
1070 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1071 {
1072         struct e1000_adapter *adapter =
1073                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1074         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
1075
1076         PMD_INIT_FUNC_TRACE();
1077
1078         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1079                 return -EPERM;
1080
1081         if (adapter->stopped == 0)
1082                 igbvf_dev_close(eth_dev);
1083
1084         eth_dev->dev_ops = NULL;
1085         eth_dev->rx_pkt_burst = NULL;
1086         eth_dev->tx_pkt_burst = NULL;
1087
1088         rte_free(eth_dev->data->mac_addrs);
1089         eth_dev->data->mac_addrs = NULL;
1090
1091         /* disable uio intr before callback unregister */
1092         rte_intr_disable(&pci_dev->intr_handle);
1093         rte_intr_callback_unregister(&pci_dev->intr_handle,
1094                                      eth_igbvf_interrupt_handler,
1095                                      (void *)eth_dev);
1096
1097         return 0;
1098 }
1099
1100 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1101         struct rte_pci_device *pci_dev)
1102 {
1103         return rte_eth_dev_pci_generic_probe(pci_dev,
1104                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1105 }
1106
1107 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1108 {
1109         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1110 }
1111
1112 static struct rte_pci_driver rte_igb_pmd = {
1113         .id_table = pci_id_igb_map,
1114         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1115         .probe = eth_igb_pci_probe,
1116         .remove = eth_igb_pci_remove,
1117 };
1118
1119
1120 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1121         struct rte_pci_device *pci_dev)
1122 {
1123         return rte_eth_dev_pci_generic_probe(pci_dev,
1124                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1125 }
1126
1127 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1128 {
1129         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1130 }
1131
1132 /*
1133  * virtual function driver struct
1134  */
1135 static struct rte_pci_driver rte_igbvf_pmd = {
1136         .id_table = pci_id_igbvf_map,
1137         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1138         .probe = eth_igbvf_pci_probe,
1139         .remove = eth_igbvf_pci_remove,
1140 };
1141
1142 static void
1143 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1144 {
1145         struct e1000_hw *hw =
1146                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1147         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1148         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1149         rctl |= E1000_RCTL_VFE;
1150         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1151 }
1152
1153 static int
1154 igb_check_mq_mode(struct rte_eth_dev *dev)
1155 {
1156         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1157         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1158         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1159         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1160
1161         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1162             tx_mq_mode == ETH_MQ_TX_DCB ||
1163             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1164                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1165                 return -EINVAL;
1166         }
1167         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1168                 /* Check multi-queue mode.
1169                  * To no break software we accept ETH_MQ_RX_NONE as this might
1170                  * be used to turn off VLAN filter.
1171                  */
1172
1173                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1174                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1175                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1176                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1177                 } else {
1178                         /* Only support one queue on VFs.
1179                          * RSS together with SRIOV is not supported.
1180                          */
1181                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1182                                         " wrong mq_mode rx %d.",
1183                                         rx_mq_mode);
1184                         return -EINVAL;
1185                 }
1186                 /* TX mode is not used here, so mode might be ignored.*/
1187                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1188                         /* SRIOV only works in VMDq enable mode */
1189                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1190                                         " TX mode %d is not supported. "
1191                                         " Driver will behave as %d mode.",
1192                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1193                 }
1194
1195                 /* check valid queue number */
1196                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1197                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1198                                         " only support one queue on VFs.");
1199                         return -EINVAL;
1200                 }
1201         } else {
1202                 /* To no break software that set invalid mode, only display
1203                  * warning if invalid mode is used.
1204                  */
1205                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1206                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1207                     rx_mq_mode != ETH_MQ_RX_RSS) {
1208                         /* RSS together with VMDq not supported*/
1209                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1210                                      rx_mq_mode);
1211                         return -EINVAL;
1212                 }
1213
1214                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1215                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1216                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1217                                         " Due to txmode is meaningless in this"
1218                                         " driver, just ignore.",
1219                                         tx_mq_mode);
1220                 }
1221         }
1222         return 0;
1223 }
1224
1225 static int
1226 eth_igb_configure(struct rte_eth_dev *dev)
1227 {
1228         struct e1000_interrupt *intr =
1229                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1230         int ret;
1231
1232         PMD_INIT_FUNC_TRACE();
1233
1234         /* multipe queue mode checking */
1235         ret  = igb_check_mq_mode(dev);
1236         if (ret != 0) {
1237                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1238                             ret);
1239                 return ret;
1240         }
1241
1242         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1243         PMD_INIT_FUNC_TRACE();
1244
1245         return 0;
1246 }
1247
1248 static int
1249 eth_igb_start(struct rte_eth_dev *dev)
1250 {
1251         struct e1000_hw *hw =
1252                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1253         struct e1000_adapter *adapter =
1254                 E1000_DEV_PRIVATE(dev->data->dev_private);
1255         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1256         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1257         int ret, mask;
1258         uint32_t intr_vector = 0;
1259         uint32_t ctrl_ext;
1260         uint32_t *speeds;
1261         int num_speeds;
1262         bool autoneg;
1263
1264         PMD_INIT_FUNC_TRACE();
1265
1266         /* disable uio/vfio intr/eventfd mapping */
1267         rte_intr_disable(intr_handle);
1268
1269         /* Power up the phy. Needed to make the link go Up */
1270         eth_igb_dev_set_link_up(dev);
1271
1272         /*
1273          * Packet Buffer Allocation (PBA)
1274          * Writing PBA sets the receive portion of the buffer
1275          * the remainder is used for the transmit buffer.
1276          */
1277         if (hw->mac.type == e1000_82575) {
1278                 uint32_t pba;
1279
1280                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1281                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1282         }
1283
1284         /* Put the address into the Receive Address Array */
1285         e1000_rar_set(hw, hw->mac.addr, 0);
1286
1287         /* Initialize the hardware */
1288         if (igb_hardware_init(hw)) {
1289                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1290                 return -EIO;
1291         }
1292         adapter->stopped = 0;
1293
1294         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1295
1296         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1297         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1298         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1299         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1300         E1000_WRITE_FLUSH(hw);
1301
1302         /* configure PF module if SRIOV enabled */
1303         igb_pf_host_configure(dev);
1304
1305         /* check and configure queue intr-vector mapping */
1306         if ((rte_intr_cap_multiple(intr_handle) ||
1307              !RTE_ETH_DEV_SRIOV(dev).active) &&
1308             dev->data->dev_conf.intr_conf.rxq != 0) {
1309                 intr_vector = dev->data->nb_rx_queues;
1310                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1311                         return -1;
1312         }
1313
1314         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1315                 intr_handle->intr_vec =
1316                         rte_zmalloc("intr_vec",
1317                                     dev->data->nb_rx_queues * sizeof(int), 0);
1318                 if (intr_handle->intr_vec == NULL) {
1319                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1320                                      " intr_vec", dev->data->nb_rx_queues);
1321                         return -ENOMEM;
1322                 }
1323         }
1324
1325         /* confiugre msix for rx interrupt */
1326         eth_igb_configure_msix_intr(dev);
1327
1328         /* Configure for OS presence */
1329         igb_init_manageability(hw);
1330
1331         eth_igb_tx_init(dev);
1332
1333         /* This can fail when allocating mbufs for descriptor rings */
1334         ret = eth_igb_rx_init(dev);
1335         if (ret) {
1336                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1337                 igb_dev_clear_queues(dev);
1338                 return ret;
1339         }
1340
1341         e1000_clear_hw_cntrs_base_generic(hw);
1342
1343         /*
1344          * VLAN Offload Settings
1345          */
1346         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1347                         ETH_VLAN_EXTEND_MASK;
1348         eth_igb_vlan_offload_set(dev, mask);
1349
1350         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1351                 /* Enable VLAN filter since VMDq always use VLAN filter */
1352                 igb_vmdq_vlan_hw_filter_enable(dev);
1353         }
1354
1355         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1356                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1357                 (hw->mac.type == e1000_i211)) {
1358                 /* Configure EITR with the maximum possible value (0xFFFF) */
1359                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1360         }
1361
1362         /* Setup link speed and duplex */
1363         speeds = &dev->data->dev_conf.link_speeds;
1364         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1365                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1366                 hw->mac.autoneg = 1;
1367         } else {
1368                 num_speeds = 0;
1369                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1370
1371                 /* Reset */
1372                 hw->phy.autoneg_advertised = 0;
1373
1374                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1375                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1376                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1377                         num_speeds = -1;
1378                         goto error_invalid_config;
1379                 }
1380                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1381                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1382                         num_speeds++;
1383                 }
1384                 if (*speeds & ETH_LINK_SPEED_10M) {
1385                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1386                         num_speeds++;
1387                 }
1388                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1389                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1390                         num_speeds++;
1391                 }
1392                 if (*speeds & ETH_LINK_SPEED_100M) {
1393                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1394                         num_speeds++;
1395                 }
1396                 if (*speeds & ETH_LINK_SPEED_1G) {
1397                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1398                         num_speeds++;
1399                 }
1400                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1401                         goto error_invalid_config;
1402
1403                 /* Set/reset the mac.autoneg based on the link speed,
1404                  * fixed or not
1405                  */
1406                 if (!autoneg) {
1407                         hw->mac.autoneg = 0;
1408                         hw->mac.forced_speed_duplex =
1409                                         hw->phy.autoneg_advertised;
1410                 } else {
1411                         hw->mac.autoneg = 1;
1412                 }
1413         }
1414
1415         e1000_setup_link(hw);
1416
1417         if (rte_intr_allow_others(intr_handle)) {
1418                 /* check if lsc interrupt is enabled */
1419                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1420                         eth_igb_lsc_interrupt_setup(dev);
1421         } else {
1422                 rte_intr_callback_unregister(intr_handle,
1423                                              eth_igb_interrupt_handler,
1424                                              (void *)dev);
1425                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1426                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1427                                      " no intr multiplex");
1428         }
1429
1430         /* check if rxq interrupt is enabled */
1431         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1432             rte_intr_dp_is_en(intr_handle))
1433                 eth_igb_rxq_interrupt_setup(dev);
1434
1435         /* enable uio/vfio intr/eventfd mapping */
1436         rte_intr_enable(intr_handle);
1437
1438         /* resume enabled intr since hw reset */
1439         igb_intr_enable(dev);
1440
1441         PMD_INIT_LOG(DEBUG, "<<");
1442
1443         return 0;
1444
1445 error_invalid_config:
1446         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1447                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1448         igb_dev_clear_queues(dev);
1449         return -EINVAL;
1450 }
1451
1452 /*********************************************************************
1453  *
1454  *  This routine disables all traffic on the adapter by issuing a
1455  *  global reset on the MAC.
1456  *
1457  **********************************************************************/
1458 static void
1459 eth_igb_stop(struct rte_eth_dev *dev)
1460 {
1461         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1462         struct e1000_filter_info *filter_info =
1463                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1464         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1465         struct rte_eth_link link;
1466         struct e1000_flex_filter *p_flex;
1467         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1468         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1469         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1470
1471         igb_intr_disable(hw);
1472
1473         /* disable intr eventfd mapping */
1474         rte_intr_disable(intr_handle);
1475
1476         igb_pf_reset_hw(hw);
1477         E1000_WRITE_REG(hw, E1000_WUC, 0);
1478
1479         /* Set bit for Go Link disconnect */
1480         if (hw->mac.type >= e1000_82580) {
1481                 uint32_t phpm_reg;
1482
1483                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1484                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1485                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1486         }
1487
1488         /* Power down the phy. Needed to make the link go Down */
1489         eth_igb_dev_set_link_down(dev);
1490
1491         igb_dev_clear_queues(dev);
1492
1493         /* clear the recorded link status */
1494         memset(&link, 0, sizeof(link));
1495         rte_igb_dev_atomic_write_link_status(dev, &link);
1496
1497         /* Remove all flex filters of the device */
1498         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1499                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1500                 rte_free(p_flex);
1501         }
1502         filter_info->flex_mask = 0;
1503
1504         /* Remove all ntuple filters of the device */
1505         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1506              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1507                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1508                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1509                              p_5tuple, entries);
1510                 rte_free(p_5tuple);
1511         }
1512         filter_info->fivetuple_mask = 0;
1513         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1514              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1515                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1516                 TAILQ_REMOVE(&filter_info->twotuple_list,
1517                              p_2tuple, entries);
1518                 rte_free(p_2tuple);
1519         }
1520         filter_info->twotuple_mask = 0;
1521
1522         if (!rte_intr_allow_others(intr_handle))
1523                 /* resume to the default handler */
1524                 rte_intr_callback_register(intr_handle,
1525                                            eth_igb_interrupt_handler,
1526                                            (void *)dev);
1527
1528         /* Clean datapath event and queue/vec mapping */
1529         rte_intr_efd_disable(intr_handle);
1530         if (intr_handle->intr_vec != NULL) {
1531                 rte_free(intr_handle->intr_vec);
1532                 intr_handle->intr_vec = NULL;
1533         }
1534 }
1535
1536 static int
1537 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1538 {
1539         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1540
1541         if (hw->phy.media_type == e1000_media_type_copper)
1542                 e1000_power_up_phy(hw);
1543         else
1544                 e1000_power_up_fiber_serdes_link(hw);
1545
1546         return 0;
1547 }
1548
1549 static int
1550 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1551 {
1552         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1553
1554         if (hw->phy.media_type == e1000_media_type_copper)
1555                 e1000_power_down_phy(hw);
1556         else
1557                 e1000_shutdown_fiber_serdes_link(hw);
1558
1559         return 0;
1560 }
1561
1562 static void
1563 eth_igb_close(struct rte_eth_dev *dev)
1564 {
1565         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1566         struct e1000_adapter *adapter =
1567                 E1000_DEV_PRIVATE(dev->data->dev_private);
1568         struct rte_eth_link link;
1569         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1570         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1571
1572         eth_igb_stop(dev);
1573         adapter->stopped = 1;
1574
1575         e1000_phy_hw_reset(hw);
1576         igb_release_manageability(hw);
1577         igb_hw_control_release(hw);
1578
1579         /* Clear bit for Go Link disconnect */
1580         if (hw->mac.type >= e1000_82580) {
1581                 uint32_t phpm_reg;
1582
1583                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1584                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1585                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1586         }
1587
1588         igb_dev_free_queues(dev);
1589
1590         if (intr_handle->intr_vec) {
1591                 rte_free(intr_handle->intr_vec);
1592                 intr_handle->intr_vec = NULL;
1593         }
1594
1595         memset(&link, 0, sizeof(link));
1596         rte_igb_dev_atomic_write_link_status(dev, &link);
1597 }
1598
1599 static int
1600 igb_get_rx_buffer_size(struct e1000_hw *hw)
1601 {
1602         uint32_t rx_buf_size;
1603         if (hw->mac.type == e1000_82576) {
1604                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1605         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1606                 /* PBS needs to be translated according to a lookup table */
1607                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1608                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1609                 rx_buf_size = (rx_buf_size << 10);
1610         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1611                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1612         } else {
1613                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1614         }
1615
1616         return rx_buf_size;
1617 }
1618
1619 /*********************************************************************
1620  *
1621  *  Initialize the hardware
1622  *
1623  **********************************************************************/
1624 static int
1625 igb_hardware_init(struct e1000_hw *hw)
1626 {
1627         uint32_t rx_buf_size;
1628         int diag;
1629
1630         /* Let the firmware know the OS is in control */
1631         igb_hw_control_acquire(hw);
1632
1633         /*
1634          * These parameters control the automatic generation (Tx) and
1635          * response (Rx) to Ethernet PAUSE frames.
1636          * - High water mark should allow for at least two standard size (1518)
1637          *   frames to be received after sending an XOFF.
1638          * - Low water mark works best when it is very near the high water mark.
1639          *   This allows the receiver to restart by sending XON when it has
1640          *   drained a bit. Here we use an arbitrary value of 1500 which will
1641          *   restart after one full frame is pulled from the buffer. There
1642          *   could be several smaller frames in the buffer and if so they will
1643          *   not trigger the XON until their total number reduces the buffer
1644          *   by 1500.
1645          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1646          */
1647         rx_buf_size = igb_get_rx_buffer_size(hw);
1648
1649         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1650         hw->fc.low_water = hw->fc.high_water - 1500;
1651         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1652         hw->fc.send_xon = 1;
1653
1654         /* Set Flow control, use the tunable location if sane */
1655         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1656                 hw->fc.requested_mode = igb_fc_setting;
1657         else
1658                 hw->fc.requested_mode = e1000_fc_none;
1659
1660         /* Issue a global reset */
1661         igb_pf_reset_hw(hw);
1662         E1000_WRITE_REG(hw, E1000_WUC, 0);
1663
1664         diag = e1000_init_hw(hw);
1665         if (diag < 0)
1666                 return diag;
1667
1668         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1669         e1000_get_phy_info(hw);
1670         e1000_check_for_link(hw);
1671
1672         return 0;
1673 }
1674
1675 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1676 static void
1677 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1678 {
1679         int pause_frames;
1680
1681         uint64_t old_gprc  = stats->gprc;
1682         uint64_t old_gptc  = stats->gptc;
1683         uint64_t old_tpr   = stats->tpr;
1684         uint64_t old_tpt   = stats->tpt;
1685         uint64_t old_rpthc = stats->rpthc;
1686         uint64_t old_hgptc = stats->hgptc;
1687
1688         if(hw->phy.media_type == e1000_media_type_copper ||
1689             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1690                 stats->symerrs +=
1691                     E1000_READ_REG(hw,E1000_SYMERRS);
1692                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1693         }
1694
1695         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1696         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1697         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1698         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1699
1700         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1701         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1702         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1703         stats->dc += E1000_READ_REG(hw, E1000_DC);
1704         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1705         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1706         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1707         /*
1708         ** For watchdog management we need to know if we have been
1709         ** paused during the last interval, so capture that here.
1710         */
1711         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1712         stats->xoffrxc += pause_frames;
1713         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1714         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1715         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1716         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1717         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1718         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1719         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1720         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1721         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1722         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1723         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1724         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1725
1726         /* For the 64-bit byte counters the low dword must be read first. */
1727         /* Both registers clear on the read of the high dword */
1728
1729         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1730         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1731         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1732         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1733         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1734         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1735         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1736
1737         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1738         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1739         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1740         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1741         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1742
1743         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1744         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1745
1746         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1747         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1748         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1749         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1750         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1751         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1752
1753         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1754         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1755         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1756         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1757         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1758         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1759         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1760         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1761
1762         /* Interrupt Counts */
1763
1764         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1765         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1766         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1767         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1768         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1769         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1770         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1771         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1772         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1773
1774         /* Host to Card Statistics */
1775
1776         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1777         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1778         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1779         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1780         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1781         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1782         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1783         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1784         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1785         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1786         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1787         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1788         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1789         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1790         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1791         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1792
1793         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1794         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1795         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1796         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1797         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1798         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1799 }
1800
1801 static void
1802 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1803 {
1804         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1805         struct e1000_hw_stats *stats =
1806                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1807
1808         igb_read_stats_registers(hw, stats);
1809
1810         if (rte_stats == NULL)
1811                 return;
1812
1813         /* Rx Errors */
1814         rte_stats->imissed = stats->mpc;
1815         rte_stats->ierrors = stats->crcerrs +
1816                              stats->rlec + stats->ruc + stats->roc +
1817                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1818
1819         /* Tx Errors */
1820         rte_stats->oerrors = stats->ecol + stats->latecol;
1821
1822         rte_stats->ipackets = stats->gprc;
1823         rte_stats->opackets = stats->gptc;
1824         rte_stats->ibytes   = stats->gorc;
1825         rte_stats->obytes   = stats->gotc;
1826 }
1827
1828 static void
1829 eth_igb_stats_reset(struct rte_eth_dev *dev)
1830 {
1831         struct e1000_hw_stats *hw_stats =
1832                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1833
1834         /* HW registers are cleared on read */
1835         eth_igb_stats_get(dev, NULL);
1836
1837         /* Reset software totals */
1838         memset(hw_stats, 0, sizeof(*hw_stats));
1839 }
1840
1841 static void
1842 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1843 {
1844         struct e1000_hw_stats *stats =
1845                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1846
1847         /* HW registers are cleared on read */
1848         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1849
1850         /* Reset software totals */
1851         memset(stats, 0, sizeof(*stats));
1852 }
1853
1854 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1855         struct rte_eth_xstat_name *xstats_names,
1856         __rte_unused unsigned int size)
1857 {
1858         unsigned i;
1859
1860         if (xstats_names == NULL)
1861                 return IGB_NB_XSTATS;
1862
1863         /* Note: limit checked in rte_eth_xstats_names() */
1864
1865         for (i = 0; i < IGB_NB_XSTATS; i++) {
1866                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1867                          "%s", rte_igb_stats_strings[i].name);
1868         }
1869
1870         return IGB_NB_XSTATS;
1871 }
1872
1873 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1874                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1875                 unsigned int limit)
1876 {
1877         unsigned int i;
1878
1879         if (!ids) {
1880                 if (xstats_names == NULL)
1881                         return IGB_NB_XSTATS;
1882
1883                 for (i = 0; i < IGB_NB_XSTATS; i++)
1884                         snprintf(xstats_names[i].name,
1885                                         sizeof(xstats_names[i].name),
1886                                         "%s", rte_igb_stats_strings[i].name);
1887
1888                 return IGB_NB_XSTATS;
1889
1890         } else {
1891                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1892
1893                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1894                                 IGB_NB_XSTATS);
1895
1896                 for (i = 0; i < limit; i++) {
1897                         if (ids[i] >= IGB_NB_XSTATS) {
1898                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1899                                 return -1;
1900                         }
1901                         strcpy(xstats_names[i].name,
1902                                         xstats_names_copy[ids[i]].name);
1903                 }
1904                 return limit;
1905         }
1906 }
1907
1908 static int
1909 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1910                    unsigned n)
1911 {
1912         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913         struct e1000_hw_stats *hw_stats =
1914                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1915         unsigned i;
1916
1917         if (n < IGB_NB_XSTATS)
1918                 return IGB_NB_XSTATS;
1919
1920         igb_read_stats_registers(hw, hw_stats);
1921
1922         /* If this is a reset xstats is NULL, and we have cleared the
1923          * registers by reading them.
1924          */
1925         if (!xstats)
1926                 return 0;
1927
1928         /* Extended stats */
1929         for (i = 0; i < IGB_NB_XSTATS; i++) {
1930                 xstats[i].id = i;
1931                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1932                         rte_igb_stats_strings[i].offset);
1933         }
1934
1935         return IGB_NB_XSTATS;
1936 }
1937
1938 static int
1939 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1940                 uint64_t *values, unsigned int n)
1941 {
1942         unsigned int i;
1943
1944         if (!ids) {
1945                 struct e1000_hw *hw =
1946                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1947                 struct e1000_hw_stats *hw_stats =
1948                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1949
1950                 if (n < IGB_NB_XSTATS)
1951                         return IGB_NB_XSTATS;
1952
1953                 igb_read_stats_registers(hw, hw_stats);
1954
1955                 /* If this is a reset xstats is NULL, and we have cleared the
1956                  * registers by reading them.
1957                  */
1958                 if (!values)
1959                         return 0;
1960
1961                 /* Extended stats */
1962                 for (i = 0; i < IGB_NB_XSTATS; i++)
1963                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1964                                         rte_igb_stats_strings[i].offset);
1965
1966                 return IGB_NB_XSTATS;
1967
1968         } else {
1969                 uint64_t values_copy[IGB_NB_XSTATS];
1970
1971                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1972                                 IGB_NB_XSTATS);
1973
1974                 for (i = 0; i < n; i++) {
1975                         if (ids[i] >= IGB_NB_XSTATS) {
1976                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1977                                 return -1;
1978                         }
1979                         values[i] = values_copy[ids[i]];
1980                 }
1981                 return n;
1982         }
1983 }
1984
1985 static void
1986 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1987 {
1988         /* Good Rx packets, include VF loopback */
1989         UPDATE_VF_STAT(E1000_VFGPRC,
1990             hw_stats->last_gprc, hw_stats->gprc);
1991
1992         /* Good Rx octets, include VF loopback */
1993         UPDATE_VF_STAT(E1000_VFGORC,
1994             hw_stats->last_gorc, hw_stats->gorc);
1995
1996         /* Good Tx packets, include VF loopback */
1997         UPDATE_VF_STAT(E1000_VFGPTC,
1998             hw_stats->last_gptc, hw_stats->gptc);
1999
2000         /* Good Tx octets, include VF loopback */
2001         UPDATE_VF_STAT(E1000_VFGOTC,
2002             hw_stats->last_gotc, hw_stats->gotc);
2003
2004         /* Rx Multicst packets */
2005         UPDATE_VF_STAT(E1000_VFMPRC,
2006             hw_stats->last_mprc, hw_stats->mprc);
2007
2008         /* Good Rx loopback packets */
2009         UPDATE_VF_STAT(E1000_VFGPRLBC,
2010             hw_stats->last_gprlbc, hw_stats->gprlbc);
2011
2012         /* Good Rx loopback octets */
2013         UPDATE_VF_STAT(E1000_VFGORLBC,
2014             hw_stats->last_gorlbc, hw_stats->gorlbc);
2015
2016         /* Good Tx loopback packets */
2017         UPDATE_VF_STAT(E1000_VFGPTLBC,
2018             hw_stats->last_gptlbc, hw_stats->gptlbc);
2019
2020         /* Good Tx loopback octets */
2021         UPDATE_VF_STAT(E1000_VFGOTLBC,
2022             hw_stats->last_gotlbc, hw_stats->gotlbc);
2023 }
2024
2025 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2026                                      struct rte_eth_xstat_name *xstats_names,
2027                                      __rte_unused unsigned limit)
2028 {
2029         unsigned i;
2030
2031         if (xstats_names != NULL)
2032                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2033                         snprintf(xstats_names[i].name,
2034                                 sizeof(xstats_names[i].name), "%s",
2035                                 rte_igbvf_stats_strings[i].name);
2036                 }
2037         return IGBVF_NB_XSTATS;
2038 }
2039
2040 static int
2041 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2042                      unsigned n)
2043 {
2044         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2046                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2047         unsigned i;
2048
2049         if (n < IGBVF_NB_XSTATS)
2050                 return IGBVF_NB_XSTATS;
2051
2052         igbvf_read_stats_registers(hw, hw_stats);
2053
2054         if (!xstats)
2055                 return 0;
2056
2057         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2058                 xstats[i].id = i;
2059                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2060                         rte_igbvf_stats_strings[i].offset);
2061         }
2062
2063         return IGBVF_NB_XSTATS;
2064 }
2065
2066 static void
2067 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2068 {
2069         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2070         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2071                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2072
2073         igbvf_read_stats_registers(hw, hw_stats);
2074
2075         if (rte_stats == NULL)
2076                 return;
2077
2078         rte_stats->ipackets = hw_stats->gprc;
2079         rte_stats->ibytes = hw_stats->gorc;
2080         rte_stats->opackets = hw_stats->gptc;
2081         rte_stats->obytes = hw_stats->gotc;
2082 }
2083
2084 static void
2085 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2086 {
2087         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2088                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2089
2090         /* Sync HW register to the last stats */
2091         eth_igbvf_stats_get(dev, NULL);
2092
2093         /* reset HW current stats*/
2094         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2095                offsetof(struct e1000_vf_stats, gprc));
2096 }
2097
2098 static int
2099 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2100                        size_t fw_size)
2101 {
2102         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103         struct e1000_fw_version fw;
2104         int ret;
2105
2106         e1000_get_fw_version(hw, &fw);
2107
2108         switch (hw->mac.type) {
2109         case e1000_i210:
2110         case e1000_i211:
2111                 if (!(e1000_get_flash_presence_i210(hw))) {
2112                         ret = snprintf(fw_version, fw_size,
2113                                  "%2d.%2d-%d",
2114                                  fw.invm_major, fw.invm_minor,
2115                                  fw.invm_img_type);
2116                         break;
2117                 }
2118                 /* fall through */
2119         default:
2120                 /* if option rom is valid, display its version too */
2121                 if (fw.or_valid) {
2122                         ret = snprintf(fw_version, fw_size,
2123                                  "%d.%d, 0x%08x, %d.%d.%d",
2124                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2125                                  fw.or_major, fw.or_build, fw.or_patch);
2126                 /* no option rom */
2127                 } else {
2128                         if (fw.etrack_id != 0X0000) {
2129                                 ret = snprintf(fw_version, fw_size,
2130                                          "%d.%d, 0x%08x",
2131                                          fw.eep_major, fw.eep_minor,
2132                                          fw.etrack_id);
2133                         } else {
2134                                 ret = snprintf(fw_version, fw_size,
2135                                          "%d.%d.%d",
2136                                          fw.eep_major, fw.eep_minor,
2137                                          fw.eep_build);
2138                         }
2139                 }
2140                 break;
2141         }
2142
2143         ret += 1; /* add the size of '\0' */
2144         if (fw_size < (u32)ret)
2145                 return ret;
2146         else
2147                 return 0;
2148 }
2149
2150 static void
2151 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2152 {
2153         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2154
2155         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2156         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2157         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2158         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2159         dev_info->rx_offload_capa =
2160                 DEV_RX_OFFLOAD_VLAN_STRIP |
2161                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2162                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2163                 DEV_RX_OFFLOAD_TCP_CKSUM;
2164         dev_info->tx_offload_capa =
2165                 DEV_TX_OFFLOAD_VLAN_INSERT |
2166                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2167                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2168                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2169                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2170                 DEV_TX_OFFLOAD_TCP_TSO;
2171
2172         switch (hw->mac.type) {
2173         case e1000_82575:
2174                 dev_info->max_rx_queues = 4;
2175                 dev_info->max_tx_queues = 4;
2176                 dev_info->max_vmdq_pools = 0;
2177                 break;
2178
2179         case e1000_82576:
2180                 dev_info->max_rx_queues = 16;
2181                 dev_info->max_tx_queues = 16;
2182                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2183                 dev_info->vmdq_queue_num = 16;
2184                 break;
2185
2186         case e1000_82580:
2187                 dev_info->max_rx_queues = 8;
2188                 dev_info->max_tx_queues = 8;
2189                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2190                 dev_info->vmdq_queue_num = 8;
2191                 break;
2192
2193         case e1000_i350:
2194                 dev_info->max_rx_queues = 8;
2195                 dev_info->max_tx_queues = 8;
2196                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2197                 dev_info->vmdq_queue_num = 8;
2198                 break;
2199
2200         case e1000_i354:
2201                 dev_info->max_rx_queues = 8;
2202                 dev_info->max_tx_queues = 8;
2203                 break;
2204
2205         case e1000_i210:
2206                 dev_info->max_rx_queues = 4;
2207                 dev_info->max_tx_queues = 4;
2208                 dev_info->max_vmdq_pools = 0;
2209                 break;
2210
2211         case e1000_i211:
2212                 dev_info->max_rx_queues = 2;
2213                 dev_info->max_tx_queues = 2;
2214                 dev_info->max_vmdq_pools = 0;
2215                 break;
2216
2217         default:
2218                 /* Should not happen */
2219                 break;
2220         }
2221         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2222         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2223         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2224
2225         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2226                 .rx_thresh = {
2227                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2228                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2229                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2230                 },
2231                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2232                 .rx_drop_en = 0,
2233         };
2234
2235         dev_info->default_txconf = (struct rte_eth_txconf) {
2236                 .tx_thresh = {
2237                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2238                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2239                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2240                 },
2241                 .txq_flags = 0,
2242         };
2243
2244         dev_info->rx_desc_lim = rx_desc_lim;
2245         dev_info->tx_desc_lim = tx_desc_lim;
2246
2247         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2248                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2249                         ETH_LINK_SPEED_1G;
2250 }
2251
2252 static const uint32_t *
2253 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2254 {
2255         static const uint32_t ptypes[] = {
2256                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2257                 RTE_PTYPE_L2_ETHER,
2258                 RTE_PTYPE_L3_IPV4,
2259                 RTE_PTYPE_L3_IPV4_EXT,
2260                 RTE_PTYPE_L3_IPV6,
2261                 RTE_PTYPE_L3_IPV6_EXT,
2262                 RTE_PTYPE_L4_TCP,
2263                 RTE_PTYPE_L4_UDP,
2264                 RTE_PTYPE_L4_SCTP,
2265                 RTE_PTYPE_TUNNEL_IP,
2266                 RTE_PTYPE_INNER_L3_IPV6,
2267                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2268                 RTE_PTYPE_INNER_L4_TCP,
2269                 RTE_PTYPE_INNER_L4_UDP,
2270                 RTE_PTYPE_UNKNOWN
2271         };
2272
2273         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2274             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2275                 return ptypes;
2276         return NULL;
2277 }
2278
2279 static void
2280 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2281 {
2282         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2283
2284         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2285         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2286         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2287         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2288         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2289                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2290                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2291                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2292         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2293                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2294                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2295                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2296                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2297                                 DEV_TX_OFFLOAD_TCP_TSO;
2298         switch (hw->mac.type) {
2299         case e1000_vfadapt:
2300                 dev_info->max_rx_queues = 2;
2301                 dev_info->max_tx_queues = 2;
2302                 break;
2303         case e1000_vfadapt_i350:
2304                 dev_info->max_rx_queues = 1;
2305                 dev_info->max_tx_queues = 1;
2306                 break;
2307         default:
2308                 /* Should not happen */
2309                 break;
2310         }
2311
2312         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2313                 .rx_thresh = {
2314                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2315                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2316                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2317                 },
2318                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2319                 .rx_drop_en = 0,
2320         };
2321
2322         dev_info->default_txconf = (struct rte_eth_txconf) {
2323                 .tx_thresh = {
2324                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2325                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2326                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2327                 },
2328                 .txq_flags = 0,
2329         };
2330
2331         dev_info->rx_desc_lim = rx_desc_lim;
2332         dev_info->tx_desc_lim = tx_desc_lim;
2333 }
2334
2335 /* return 0 means link status changed, -1 means not changed */
2336 static int
2337 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2338 {
2339         struct e1000_hw *hw =
2340                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2341         struct rte_eth_link link, old;
2342         int link_check, count;
2343
2344         link_check = 0;
2345         hw->mac.get_link_status = 1;
2346
2347         /* possible wait-to-complete in up to 9 seconds */
2348         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2349                 /* Read the real link status */
2350                 switch (hw->phy.media_type) {
2351                 case e1000_media_type_copper:
2352                         /* Do the work to read phy */
2353                         e1000_check_for_link(hw);
2354                         link_check = !hw->mac.get_link_status;
2355                         break;
2356
2357                 case e1000_media_type_fiber:
2358                         e1000_check_for_link(hw);
2359                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2360                                       E1000_STATUS_LU);
2361                         break;
2362
2363                 case e1000_media_type_internal_serdes:
2364                         e1000_check_for_link(hw);
2365                         link_check = hw->mac.serdes_has_link;
2366                         break;
2367
2368                 /* VF device is type_unknown */
2369                 case e1000_media_type_unknown:
2370                         eth_igbvf_link_update(hw);
2371                         link_check = !hw->mac.get_link_status;
2372                         break;
2373
2374                 default:
2375                         break;
2376                 }
2377                 if (link_check || wait_to_complete == 0)
2378                         break;
2379                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2380         }
2381         memset(&link, 0, sizeof(link));
2382         rte_igb_dev_atomic_read_link_status(dev, &link);
2383         old = link;
2384
2385         /* Now we check if a transition has happened */
2386         if (link_check) {
2387                 uint16_t duplex, speed;
2388                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2389                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2390                                 ETH_LINK_FULL_DUPLEX :
2391                                 ETH_LINK_HALF_DUPLEX;
2392                 link.link_speed = speed;
2393                 link.link_status = ETH_LINK_UP;
2394                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2395                                 ETH_LINK_SPEED_FIXED);
2396         } else if (!link_check) {
2397                 link.link_speed = 0;
2398                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2399                 link.link_status = ETH_LINK_DOWN;
2400                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2401         }
2402         rte_igb_dev_atomic_write_link_status(dev, &link);
2403
2404         /* not changed */
2405         if (old.link_status == link.link_status)
2406                 return -1;
2407
2408         /* changed */
2409         return 0;
2410 }
2411
2412 /*
2413  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2414  * For ASF and Pass Through versions of f/w this means
2415  * that the driver is loaded.
2416  */
2417 static void
2418 igb_hw_control_acquire(struct e1000_hw *hw)
2419 {
2420         uint32_t ctrl_ext;
2421
2422         /* Let firmware know the driver has taken over */
2423         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2424         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2425 }
2426
2427 /*
2428  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2429  * For ASF and Pass Through versions of f/w this means that the
2430  * driver is no longer loaded.
2431  */
2432 static void
2433 igb_hw_control_release(struct e1000_hw *hw)
2434 {
2435         uint32_t ctrl_ext;
2436
2437         /* Let firmware taken over control of h/w */
2438         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2439         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2440                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2441 }
2442
2443 /*
2444  * Bit of a misnomer, what this really means is
2445  * to enable OS management of the system... aka
2446  * to disable special hardware management features.
2447  */
2448 static void
2449 igb_init_manageability(struct e1000_hw *hw)
2450 {
2451         if (e1000_enable_mng_pass_thru(hw)) {
2452                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2453                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2454
2455                 /* disable hardware interception of ARP */
2456                 manc &= ~(E1000_MANC_ARP_EN);
2457
2458                 /* enable receiving management packets to the host */
2459                 manc |= E1000_MANC_EN_MNG2HOST;
2460                 manc2h |= 1 << 5;  /* Mng Port 623 */
2461                 manc2h |= 1 << 6;  /* Mng Port 664 */
2462                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2463                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2464         }
2465 }
2466
2467 static void
2468 igb_release_manageability(struct e1000_hw *hw)
2469 {
2470         if (e1000_enable_mng_pass_thru(hw)) {
2471                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2472
2473                 manc |= E1000_MANC_ARP_EN;
2474                 manc &= ~E1000_MANC_EN_MNG2HOST;
2475
2476                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2477         }
2478 }
2479
2480 static void
2481 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2482 {
2483         struct e1000_hw *hw =
2484                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2485         uint32_t rctl;
2486
2487         rctl = E1000_READ_REG(hw, E1000_RCTL);
2488         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2489         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2490 }
2491
2492 static void
2493 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2494 {
2495         struct e1000_hw *hw =
2496                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2497         uint32_t rctl;
2498
2499         rctl = E1000_READ_REG(hw, E1000_RCTL);
2500         rctl &= (~E1000_RCTL_UPE);
2501         if (dev->data->all_multicast == 1)
2502                 rctl |= E1000_RCTL_MPE;
2503         else
2504                 rctl &= (~E1000_RCTL_MPE);
2505         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2506 }
2507
2508 static void
2509 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2510 {
2511         struct e1000_hw *hw =
2512                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2513         uint32_t rctl;
2514
2515         rctl = E1000_READ_REG(hw, E1000_RCTL);
2516         rctl |= E1000_RCTL_MPE;
2517         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2518 }
2519
2520 static void
2521 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2522 {
2523         struct e1000_hw *hw =
2524                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2525         uint32_t rctl;
2526
2527         if (dev->data->promiscuous == 1)
2528                 return; /* must remain in all_multicast mode */
2529         rctl = E1000_READ_REG(hw, E1000_RCTL);
2530         rctl &= (~E1000_RCTL_MPE);
2531         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2532 }
2533
2534 static int
2535 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2536 {
2537         struct e1000_hw *hw =
2538                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539         struct e1000_vfta * shadow_vfta =
2540                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2541         uint32_t vfta;
2542         uint32_t vid_idx;
2543         uint32_t vid_bit;
2544
2545         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2546                               E1000_VFTA_ENTRY_MASK);
2547         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2548         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2549         if (on)
2550                 vfta |= vid_bit;
2551         else
2552                 vfta &= ~vid_bit;
2553         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2554
2555         /* update local VFTA copy */
2556         shadow_vfta->vfta[vid_idx] = vfta;
2557
2558         return 0;
2559 }
2560
2561 static int
2562 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2563                       enum rte_vlan_type vlan_type,
2564                       uint16_t tpid)
2565 {
2566         struct e1000_hw *hw =
2567                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2568         uint32_t reg, qinq;
2569
2570         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2571         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2572
2573         /* only outer TPID of double VLAN can be configured*/
2574         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2575                 reg = E1000_READ_REG(hw, E1000_VET);
2576                 reg = (reg & (~E1000_VET_VET_EXT)) |
2577                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2578                 E1000_WRITE_REG(hw, E1000_VET, reg);
2579
2580                 return 0;
2581         }
2582
2583         /* all other TPID values are read-only*/
2584         PMD_DRV_LOG(ERR, "Not supported");
2585
2586         return -ENOTSUP;
2587 }
2588
2589 static void
2590 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2591 {
2592         struct e1000_hw *hw =
2593                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2594         uint32_t reg;
2595
2596         /* Filter Table Disable */
2597         reg = E1000_READ_REG(hw, E1000_RCTL);
2598         reg &= ~E1000_RCTL_CFIEN;
2599         reg &= ~E1000_RCTL_VFE;
2600         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2601 }
2602
2603 static void
2604 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2605 {
2606         struct e1000_hw *hw =
2607                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2608         struct e1000_vfta * shadow_vfta =
2609                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2610         uint32_t reg;
2611         int i;
2612
2613         /* Filter Table Enable, CFI not used for packet acceptance */
2614         reg = E1000_READ_REG(hw, E1000_RCTL);
2615         reg &= ~E1000_RCTL_CFIEN;
2616         reg |= E1000_RCTL_VFE;
2617         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2618
2619         /* restore VFTA table */
2620         for (i = 0; i < IGB_VFTA_SIZE; i++)
2621                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2622 }
2623
2624 static void
2625 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2626 {
2627         struct e1000_hw *hw =
2628                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2629         uint32_t reg;
2630
2631         /* VLAN Mode Disable */
2632         reg = E1000_READ_REG(hw, E1000_CTRL);
2633         reg &= ~E1000_CTRL_VME;
2634         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2635 }
2636
2637 static void
2638 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2639 {
2640         struct e1000_hw *hw =
2641                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2642         uint32_t reg;
2643
2644         /* VLAN Mode Enable */
2645         reg = E1000_READ_REG(hw, E1000_CTRL);
2646         reg |= E1000_CTRL_VME;
2647         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2648 }
2649
2650 static void
2651 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2652 {
2653         struct e1000_hw *hw =
2654                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2655         uint32_t reg;
2656
2657         /* CTRL_EXT: Extended VLAN */
2658         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2659         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2660         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2661
2662         /* Update maximum packet length */
2663         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2664                 E1000_WRITE_REG(hw, E1000_RLPML,
2665                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2666                                                 VLAN_TAG_SIZE);
2667 }
2668
2669 static void
2670 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2671 {
2672         struct e1000_hw *hw =
2673                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2674         uint32_t reg;
2675
2676         /* CTRL_EXT: Extended VLAN */
2677         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2678         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2679         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2680
2681         /* Update maximum packet length */
2682         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2683                 E1000_WRITE_REG(hw, E1000_RLPML,
2684                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2685                                                 2 * VLAN_TAG_SIZE);
2686 }
2687
2688 static void
2689 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2690 {
2691         if(mask & ETH_VLAN_STRIP_MASK){
2692                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2693                         igb_vlan_hw_strip_enable(dev);
2694                 else
2695                         igb_vlan_hw_strip_disable(dev);
2696         }
2697
2698         if(mask & ETH_VLAN_FILTER_MASK){
2699                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2700                         igb_vlan_hw_filter_enable(dev);
2701                 else
2702                         igb_vlan_hw_filter_disable(dev);
2703         }
2704
2705         if(mask & ETH_VLAN_EXTEND_MASK){
2706                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2707                         igb_vlan_hw_extend_enable(dev);
2708                 else
2709                         igb_vlan_hw_extend_disable(dev);
2710         }
2711 }
2712
2713
2714 /**
2715  * It enables the interrupt mask and then enable the interrupt.
2716  *
2717  * @param dev
2718  *  Pointer to struct rte_eth_dev.
2719  *
2720  * @return
2721  *  - On success, zero.
2722  *  - On failure, a negative value.
2723  */
2724 static int
2725 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2726 {
2727         struct e1000_interrupt *intr =
2728                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2729
2730         intr->mask |= E1000_ICR_LSC;
2731
2732         return 0;
2733 }
2734
2735 /* It clears the interrupt causes and enables the interrupt.
2736  * It will be called once only during nic initialized.
2737  *
2738  * @param dev
2739  *  Pointer to struct rte_eth_dev.
2740  *
2741  * @return
2742  *  - On success, zero.
2743  *  - On failure, a negative value.
2744  */
2745 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2746 {
2747         uint32_t mask, regval;
2748         struct e1000_hw *hw =
2749                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2750         struct rte_eth_dev_info dev_info;
2751
2752         memset(&dev_info, 0, sizeof(dev_info));
2753         eth_igb_infos_get(dev, &dev_info);
2754
2755         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2756         regval = E1000_READ_REG(hw, E1000_EIMS);
2757         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2758
2759         return 0;
2760 }
2761
2762 /*
2763  * It reads ICR and gets interrupt causes, check it and set a bit flag
2764  * to update link status.
2765  *
2766  * @param dev
2767  *  Pointer to struct rte_eth_dev.
2768  *
2769  * @return
2770  *  - On success, zero.
2771  *  - On failure, a negative value.
2772  */
2773 static int
2774 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2775 {
2776         uint32_t icr;
2777         struct e1000_hw *hw =
2778                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2779         struct e1000_interrupt *intr =
2780                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2781
2782         igb_intr_disable(hw);
2783
2784         /* read-on-clear nic registers here */
2785         icr = E1000_READ_REG(hw, E1000_ICR);
2786
2787         intr->flags = 0;
2788         if (icr & E1000_ICR_LSC) {
2789                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2790         }
2791
2792         if (icr & E1000_ICR_VMMB)
2793                 intr->flags |= E1000_FLAG_MAILBOX;
2794
2795         return 0;
2796 }
2797
2798 /*
2799  * It executes link_update after knowing an interrupt is prsent.
2800  *
2801  * @param dev
2802  *  Pointer to struct rte_eth_dev.
2803  *
2804  * @return
2805  *  - On success, zero.
2806  *  - On failure, a negative value.
2807  */
2808 static int
2809 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2810                          struct rte_intr_handle *intr_handle)
2811 {
2812         struct e1000_hw *hw =
2813                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2814         struct e1000_interrupt *intr =
2815                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2816         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
2817         uint32_t tctl, rctl;
2818         struct rte_eth_link link;
2819         int ret;
2820
2821         if (intr->flags & E1000_FLAG_MAILBOX) {
2822                 igb_pf_mbx_process(dev);
2823                 intr->flags &= ~E1000_FLAG_MAILBOX;
2824         }
2825
2826         igb_intr_enable(dev);
2827         rte_intr_enable(intr_handle);
2828
2829         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2830                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2831
2832                 /* set get_link_status to check register later */
2833                 hw->mac.get_link_status = 1;
2834                 ret = eth_igb_link_update(dev, 0);
2835
2836                 /* check if link has changed */
2837                 if (ret < 0)
2838                         return 0;
2839
2840                 memset(&link, 0, sizeof(link));
2841                 rte_igb_dev_atomic_read_link_status(dev, &link);
2842                 if (link.link_status) {
2843                         PMD_INIT_LOG(INFO,
2844                                      " Port %d: Link Up - speed %u Mbps - %s",
2845                                      dev->data->port_id,
2846                                      (unsigned)link.link_speed,
2847                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2848                                      "full-duplex" : "half-duplex");
2849                 } else {
2850                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2851                                      dev->data->port_id);
2852                 }
2853
2854                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2855                              pci_dev->addr.domain,
2856                              pci_dev->addr.bus,
2857                              pci_dev->addr.devid,
2858                              pci_dev->addr.function);
2859                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2860                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2861                 if (link.link_status) {
2862                         /* enable Tx/Rx */
2863                         tctl |= E1000_TCTL_EN;
2864                         rctl |= E1000_RCTL_EN;
2865                 } else {
2866                         /* disable Tx/Rx */
2867                         tctl &= ~E1000_TCTL_EN;
2868                         rctl &= ~E1000_RCTL_EN;
2869                 }
2870                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2871                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2872                 E1000_WRITE_FLUSH(hw);
2873                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2874         }
2875
2876         return 0;
2877 }
2878
2879 /**
2880  * Interrupt handler which shall be registered at first.
2881  *
2882  * @param handle
2883  *  Pointer to interrupt handle.
2884  * @param param
2885  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2886  *
2887  * @return
2888  *  void
2889  */
2890 static void
2891 eth_igb_interrupt_handler(void *param)
2892 {
2893         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2894
2895         eth_igb_interrupt_get_status(dev);
2896         eth_igb_interrupt_action(dev, dev->intr_handle);
2897 }
2898
2899 static int
2900 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2901 {
2902         uint32_t eicr;
2903         struct e1000_hw *hw =
2904                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2905         struct e1000_interrupt *intr =
2906                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2907
2908         igbvf_intr_disable(hw);
2909
2910         /* read-on-clear nic registers here */
2911         eicr = E1000_READ_REG(hw, E1000_EICR);
2912         intr->flags = 0;
2913
2914         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2915                 intr->flags |= E1000_FLAG_MAILBOX;
2916
2917         return 0;
2918 }
2919
2920 void igbvf_mbx_process(struct rte_eth_dev *dev)
2921 {
2922         struct e1000_hw *hw =
2923                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2924         struct e1000_mbx_info *mbx = &hw->mbx;
2925         u32 in_msg = 0;
2926
2927         if (mbx->ops.read(hw, &in_msg, 1, 0))
2928                 return;
2929
2930         /* PF reset VF event */
2931         if (in_msg == E1000_PF_CONTROL_MSG)
2932                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2933 }
2934
2935 static int
2936 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2937 {
2938         struct e1000_interrupt *intr =
2939                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2940
2941         if (intr->flags & E1000_FLAG_MAILBOX) {
2942                 igbvf_mbx_process(dev);
2943                 intr->flags &= ~E1000_FLAG_MAILBOX;
2944         }
2945
2946         igbvf_intr_enable(dev);
2947         rte_intr_enable(intr_handle);
2948
2949         return 0;
2950 }
2951
2952 static void
2953 eth_igbvf_interrupt_handler(void *param)
2954 {
2955         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2956
2957         eth_igbvf_interrupt_get_status(dev);
2958         eth_igbvf_interrupt_action(dev, dev->intr_handle);
2959 }
2960
2961 static int
2962 eth_igb_led_on(struct rte_eth_dev *dev)
2963 {
2964         struct e1000_hw *hw;
2965
2966         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2967         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2968 }
2969
2970 static int
2971 eth_igb_led_off(struct rte_eth_dev *dev)
2972 {
2973         struct e1000_hw *hw;
2974
2975         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2976         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2977 }
2978
2979 static int
2980 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2981 {
2982         struct e1000_hw *hw;
2983         uint32_t ctrl;
2984         int tx_pause;
2985         int rx_pause;
2986
2987         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2988         fc_conf->pause_time = hw->fc.pause_time;
2989         fc_conf->high_water = hw->fc.high_water;
2990         fc_conf->low_water = hw->fc.low_water;
2991         fc_conf->send_xon = hw->fc.send_xon;
2992         fc_conf->autoneg = hw->mac.autoneg;
2993
2994         /*
2995          * Return rx_pause and tx_pause status according to actual setting of
2996          * the TFCE and RFCE bits in the CTRL register.
2997          */
2998         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2999         if (ctrl & E1000_CTRL_TFCE)
3000                 tx_pause = 1;
3001         else
3002                 tx_pause = 0;
3003
3004         if (ctrl & E1000_CTRL_RFCE)
3005                 rx_pause = 1;
3006         else
3007                 rx_pause = 0;
3008
3009         if (rx_pause && tx_pause)
3010                 fc_conf->mode = RTE_FC_FULL;
3011         else if (rx_pause)
3012                 fc_conf->mode = RTE_FC_RX_PAUSE;
3013         else if (tx_pause)
3014                 fc_conf->mode = RTE_FC_TX_PAUSE;
3015         else
3016                 fc_conf->mode = RTE_FC_NONE;
3017
3018         return 0;
3019 }
3020
3021 static int
3022 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3023 {
3024         struct e1000_hw *hw;
3025         int err;
3026         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3027                 e1000_fc_none,
3028                 e1000_fc_rx_pause,
3029                 e1000_fc_tx_pause,
3030                 e1000_fc_full
3031         };
3032         uint32_t rx_buf_size;
3033         uint32_t max_high_water;
3034         uint32_t rctl;
3035
3036         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3037         if (fc_conf->autoneg != hw->mac.autoneg)
3038                 return -ENOTSUP;
3039         rx_buf_size = igb_get_rx_buffer_size(hw);
3040         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3041
3042         /* At least reserve one Ethernet frame for watermark */
3043         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3044         if ((fc_conf->high_water > max_high_water) ||
3045             (fc_conf->high_water < fc_conf->low_water)) {
3046                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3047                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3048                 return -EINVAL;
3049         }
3050
3051         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3052         hw->fc.pause_time     = fc_conf->pause_time;
3053         hw->fc.high_water     = fc_conf->high_water;
3054         hw->fc.low_water      = fc_conf->low_water;
3055         hw->fc.send_xon       = fc_conf->send_xon;
3056
3057         err = e1000_setup_link_generic(hw);
3058         if (err == E1000_SUCCESS) {
3059
3060                 /* check if we want to forward MAC frames - driver doesn't have native
3061                  * capability to do that, so we'll write the registers ourselves */
3062
3063                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3064
3065                 /* set or clear MFLCN.PMCF bit depending on configuration */
3066                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3067                         rctl |= E1000_RCTL_PMCF;
3068                 else
3069                         rctl &= ~E1000_RCTL_PMCF;
3070
3071                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3072                 E1000_WRITE_FLUSH(hw);
3073
3074                 return 0;
3075         }
3076
3077         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3078         return -EIO;
3079 }
3080
3081 #define E1000_RAH_POOLSEL_SHIFT      (18)
3082 static void
3083 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3084                 uint32_t index, __rte_unused uint32_t pool)
3085 {
3086         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3087         uint32_t rah;
3088
3089         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3090         rah = E1000_READ_REG(hw, E1000_RAH(index));
3091         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3092         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3093 }
3094
3095 static void
3096 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3097 {
3098         uint8_t addr[ETHER_ADDR_LEN];
3099         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3100
3101         memset(addr, 0, sizeof(addr));
3102
3103         e1000_rar_set(hw, addr, index);
3104 }
3105
3106 static void
3107 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3108                                 struct ether_addr *addr)
3109 {
3110         eth_igb_rar_clear(dev, 0);
3111
3112         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3113 }
3114 /*
3115  * Virtual Function operations
3116  */
3117 static void
3118 igbvf_intr_disable(struct e1000_hw *hw)
3119 {
3120         PMD_INIT_FUNC_TRACE();
3121
3122         /* Clear interrupt mask to stop from interrupts being generated */
3123         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3124
3125         E1000_WRITE_FLUSH(hw);
3126 }
3127
3128 static void
3129 igbvf_stop_adapter(struct rte_eth_dev *dev)
3130 {
3131         u32 reg_val;
3132         u16 i;
3133         struct rte_eth_dev_info dev_info;
3134         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3135
3136         memset(&dev_info, 0, sizeof(dev_info));
3137         eth_igbvf_infos_get(dev, &dev_info);
3138
3139         /* Clear interrupt mask to stop from interrupts being generated */
3140         igbvf_intr_disable(hw);
3141
3142         /* Clear any pending interrupts, flush previous writes */
3143         E1000_READ_REG(hw, E1000_EICR);
3144
3145         /* Disable the transmit unit.  Each queue must be disabled. */
3146         for (i = 0; i < dev_info.max_tx_queues; i++)
3147                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3148
3149         /* Disable the receive unit by stopping each queue */
3150         for (i = 0; i < dev_info.max_rx_queues; i++) {
3151                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3152                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3153                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3154                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3155                         ;
3156         }
3157
3158         /* flush all queues disables */
3159         E1000_WRITE_FLUSH(hw);
3160         msec_delay(2);
3161 }
3162
3163 static int eth_igbvf_link_update(struct e1000_hw *hw)
3164 {
3165         struct e1000_mbx_info *mbx = &hw->mbx;
3166         struct e1000_mac_info *mac = &hw->mac;
3167         int ret_val = E1000_SUCCESS;
3168
3169         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3170
3171         /*
3172          * We only want to run this if there has been a rst asserted.
3173          * in this case that could mean a link change, device reset,
3174          * or a virtual function reset
3175          */
3176
3177         /* If we were hit with a reset or timeout drop the link */
3178         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3179                 mac->get_link_status = TRUE;
3180
3181         if (!mac->get_link_status)
3182                 goto out;
3183
3184         /* if link status is down no point in checking to see if pf is up */
3185         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3186                 goto out;
3187
3188         /* if we passed all the tests above then the link is up and we no
3189          * longer need to check for link */
3190         mac->get_link_status = FALSE;
3191
3192 out:
3193         return ret_val;
3194 }
3195
3196
3197 static int
3198 igbvf_dev_configure(struct rte_eth_dev *dev)
3199 {
3200         struct rte_eth_conf* conf = &dev->data->dev_conf;
3201
3202         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3203                      dev->data->port_id);
3204
3205         /*
3206          * VF has no ability to enable/disable HW CRC
3207          * Keep the persistent behavior the same as Host PF
3208          */
3209 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3210         if (!conf->rxmode.hw_strip_crc) {
3211                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3212                 conf->rxmode.hw_strip_crc = 1;
3213         }
3214 #else
3215         if (conf->rxmode.hw_strip_crc) {
3216                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3217                 conf->rxmode.hw_strip_crc = 0;
3218         }
3219 #endif
3220
3221         return 0;
3222 }
3223
3224 static int
3225 igbvf_dev_start(struct rte_eth_dev *dev)
3226 {
3227         struct e1000_hw *hw =
3228                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3229         struct e1000_adapter *adapter =
3230                 E1000_DEV_PRIVATE(dev->data->dev_private);
3231         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3232         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3233         int ret;
3234         uint32_t intr_vector = 0;
3235
3236         PMD_INIT_FUNC_TRACE();
3237
3238         hw->mac.ops.reset_hw(hw);
3239         adapter->stopped = 0;
3240
3241         /* Set all vfta */
3242         igbvf_set_vfta_all(dev,1);
3243
3244         eth_igbvf_tx_init(dev);
3245
3246         /* This can fail when allocating mbufs for descriptor rings */
3247         ret = eth_igbvf_rx_init(dev);
3248         if (ret) {
3249                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3250                 igb_dev_clear_queues(dev);
3251                 return ret;
3252         }
3253
3254         /* check and configure queue intr-vector mapping */
3255         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3256                 intr_vector = dev->data->nb_rx_queues;
3257                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3258                 if (ret)
3259                         return ret;
3260         }
3261
3262         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3263                 intr_handle->intr_vec =
3264                         rte_zmalloc("intr_vec",
3265                                     dev->data->nb_rx_queues * sizeof(int), 0);
3266                 if (!intr_handle->intr_vec) {
3267                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3268                                      " intr_vec", dev->data->nb_rx_queues);
3269                         return -ENOMEM;
3270                 }
3271         }
3272
3273         eth_igbvf_configure_msix_intr(dev);
3274
3275         /* enable uio/vfio intr/eventfd mapping */
3276         rte_intr_enable(intr_handle);
3277
3278         /* resume enabled intr since hw reset */
3279         igbvf_intr_enable(dev);
3280
3281         return 0;
3282 }
3283
3284 static void
3285 igbvf_dev_stop(struct rte_eth_dev *dev)
3286 {
3287         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3288         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3289
3290         PMD_INIT_FUNC_TRACE();
3291
3292         igbvf_stop_adapter(dev);
3293
3294         /*
3295           * Clear what we set, but we still keep shadow_vfta to
3296           * restore after device starts
3297           */
3298         igbvf_set_vfta_all(dev,0);
3299
3300         igb_dev_clear_queues(dev);
3301
3302         /* disable intr eventfd mapping */
3303         rte_intr_disable(intr_handle);
3304
3305         /* Clean datapath event and queue/vec mapping */
3306         rte_intr_efd_disable(intr_handle);
3307         if (intr_handle->intr_vec) {
3308                 rte_free(intr_handle->intr_vec);
3309                 intr_handle->intr_vec = NULL;
3310         }
3311 }
3312
3313 static void
3314 igbvf_dev_close(struct rte_eth_dev *dev)
3315 {
3316         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3317         struct e1000_adapter *adapter =
3318                 E1000_DEV_PRIVATE(dev->data->dev_private);
3319         struct ether_addr addr;
3320
3321         PMD_INIT_FUNC_TRACE();
3322
3323         e1000_reset_hw(hw);
3324
3325         igbvf_dev_stop(dev);
3326         adapter->stopped = 1;
3327         igb_dev_free_queues(dev);
3328
3329         /**
3330          * reprogram the RAR with a zero mac address,
3331          * to ensure that the VF traffic goes to the PF
3332          * after stop, close and detach of the VF.
3333          **/
3334
3335         memset(&addr, 0, sizeof(addr));
3336         igbvf_default_mac_addr_set(dev, &addr);
3337 }
3338
3339 static void
3340 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3341 {
3342         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3343
3344         /* Set both unicast and multicast promisc */
3345         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3346 }
3347
3348 static void
3349 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3350 {
3351         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3352
3353         /* If in allmulticast mode leave multicast promisc */
3354         if (dev->data->all_multicast == 1)
3355                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3356         else
3357                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3358 }
3359
3360 static void
3361 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3362 {
3363         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3364
3365         /* In promiscuous mode multicast promisc already set */
3366         if (dev->data->promiscuous == 0)
3367                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3368 }
3369
3370 static void
3371 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3372 {
3373         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3374
3375         /* In promiscuous mode leave multicast promisc enabled */
3376         if (dev->data->promiscuous == 0)
3377                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3378 }
3379
3380 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3381 {
3382         struct e1000_mbx_info *mbx = &hw->mbx;
3383         uint32_t msgbuf[2];
3384         s32 err;
3385
3386         /* After set vlan, vlan strip will also be enabled in igb driver*/
3387         msgbuf[0] = E1000_VF_SET_VLAN;
3388         msgbuf[1] = vid;
3389         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3390         if (on)
3391                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3392
3393         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3394         if (err)
3395                 goto mbx_err;
3396
3397         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3398         if (err)
3399                 goto mbx_err;
3400
3401         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3402         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3403                 err = -EINVAL;
3404
3405 mbx_err:
3406         return err;
3407 }
3408
3409 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3410 {
3411         struct e1000_hw *hw =
3412                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3413         struct e1000_vfta * shadow_vfta =
3414                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3415         int i = 0, j = 0, vfta = 0, mask = 1;
3416
3417         for (i = 0; i < IGB_VFTA_SIZE; i++){
3418                 vfta = shadow_vfta->vfta[i];
3419                 if(vfta){
3420                         mask = 1;
3421                         for (j = 0; j < 32; j++){
3422                                 if(vfta & mask)
3423                                         igbvf_set_vfta(hw,
3424                                                 (uint16_t)((i<<5)+j), on);
3425                                 mask<<=1;
3426                         }
3427                 }
3428         }
3429
3430 }
3431
3432 static int
3433 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3434 {
3435         struct e1000_hw *hw =
3436                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3437         struct e1000_vfta * shadow_vfta =
3438                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3439         uint32_t vid_idx = 0;
3440         uint32_t vid_bit = 0;
3441         int ret = 0;
3442
3443         PMD_INIT_FUNC_TRACE();
3444
3445         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3446         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3447         if(ret){
3448                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3449                 return ret;
3450         }
3451         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3452         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3453
3454         /*Save what we set and retore it after device reset*/
3455         if (on)
3456                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3457         else
3458                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3459
3460         return 0;
3461 }
3462
3463 static void
3464 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3465 {
3466         struct e1000_hw *hw =
3467                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3468
3469         /* index is not used by rar_set() */
3470         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3471 }
3472
3473
3474 static int
3475 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3476                         struct rte_eth_rss_reta_entry64 *reta_conf,
3477                         uint16_t reta_size)
3478 {
3479         uint8_t i, j, mask;
3480         uint32_t reta, r;
3481         uint16_t idx, shift;
3482         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3483
3484         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3485                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3486                         "(%d) doesn't match the number hardware can supported "
3487                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3488                 return -EINVAL;
3489         }
3490
3491         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3492                 idx = i / RTE_RETA_GROUP_SIZE;
3493                 shift = i % RTE_RETA_GROUP_SIZE;
3494                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3495                                                 IGB_4_BIT_MASK);
3496                 if (!mask)
3497                         continue;
3498                 if (mask == IGB_4_BIT_MASK)
3499                         r = 0;
3500                 else
3501                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3502                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3503                         if (mask & (0x1 << j))
3504                                 reta |= reta_conf[idx].reta[shift + j] <<
3505                                                         (CHAR_BIT * j);
3506                         else
3507                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3508                 }
3509                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3510         }
3511
3512         return 0;
3513 }
3514
3515 static int
3516 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3517                        struct rte_eth_rss_reta_entry64 *reta_conf,
3518                        uint16_t reta_size)
3519 {
3520         uint8_t i, j, mask;
3521         uint32_t reta;
3522         uint16_t idx, shift;
3523         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3524
3525         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3526                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3527                         "(%d) doesn't match the number hardware can supported "
3528                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3529                 return -EINVAL;
3530         }
3531
3532         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3533                 idx = i / RTE_RETA_GROUP_SIZE;
3534                 shift = i % RTE_RETA_GROUP_SIZE;
3535                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3536                                                 IGB_4_BIT_MASK);
3537                 if (!mask)
3538                         continue;
3539                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3540                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3541                         if (mask & (0x1 << j))
3542                                 reta_conf[idx].reta[shift + j] =
3543                                         ((reta >> (CHAR_BIT * j)) &
3544                                                 IGB_8_BIT_MASK);
3545                 }
3546         }
3547
3548         return 0;
3549 }
3550
3551 #define MAC_TYPE_FILTER_SUP(type)    do {\
3552         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3553                 (type) != e1000_82576)\
3554                 return -ENOTSUP;\
3555 } while (0)
3556
3557 static int
3558 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3559                         struct rte_eth_syn_filter *filter,
3560                         bool add)
3561 {
3562         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3563         uint32_t synqf, rfctl;
3564
3565         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3566                 return -EINVAL;
3567
3568         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3569
3570         if (add) {
3571                 if (synqf & E1000_SYN_FILTER_ENABLE)
3572                         return -EINVAL;
3573
3574                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3575                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3576
3577                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3578                 if (filter->hig_pri)
3579                         rfctl |= E1000_RFCTL_SYNQFP;
3580                 else
3581                         rfctl &= ~E1000_RFCTL_SYNQFP;
3582
3583                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3584         } else {
3585                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3586                         return -ENOENT;
3587                 synqf = 0;
3588         }
3589
3590         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3591         E1000_WRITE_FLUSH(hw);
3592         return 0;
3593 }
3594
3595 static int
3596 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3597                         struct rte_eth_syn_filter *filter)
3598 {
3599         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3600         uint32_t synqf, rfctl;
3601
3602         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3603         if (synqf & E1000_SYN_FILTER_ENABLE) {
3604                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3605                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3606                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3607                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3608                 return 0;
3609         }
3610
3611         return -ENOENT;
3612 }
3613
3614 static int
3615 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3616                         enum rte_filter_op filter_op,
3617                         void *arg)
3618 {
3619         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3620         int ret;
3621
3622         MAC_TYPE_FILTER_SUP(hw->mac.type);
3623
3624         if (filter_op == RTE_ETH_FILTER_NOP)
3625                 return 0;
3626
3627         if (arg == NULL) {
3628                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3629                             filter_op);
3630                 return -EINVAL;
3631         }
3632
3633         switch (filter_op) {
3634         case RTE_ETH_FILTER_ADD:
3635                 ret = eth_igb_syn_filter_set(dev,
3636                                 (struct rte_eth_syn_filter *)arg,
3637                                 TRUE);
3638                 break;
3639         case RTE_ETH_FILTER_DELETE:
3640                 ret = eth_igb_syn_filter_set(dev,
3641                                 (struct rte_eth_syn_filter *)arg,
3642                                 FALSE);
3643                 break;
3644         case RTE_ETH_FILTER_GET:
3645                 ret = eth_igb_syn_filter_get(dev,
3646                                 (struct rte_eth_syn_filter *)arg);
3647                 break;
3648         default:
3649                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3650                 ret = -EINVAL;
3651                 break;
3652         }
3653
3654         return ret;
3655 }
3656
3657 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3658         if ((type) != e1000_82580 && (type) != e1000_i350)\
3659                 return -ENOSYS; \
3660 } while (0)
3661
3662 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3663 static inline int
3664 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3665                         struct e1000_2tuple_filter_info *filter_info)
3666 {
3667         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3668                 return -EINVAL;
3669         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3670                 return -EINVAL;  /* filter index is out of range. */
3671         if (filter->tcp_flags > TCP_FLAG_ALL)
3672                 return -EINVAL;  /* flags is invalid. */
3673
3674         switch (filter->dst_port_mask) {
3675         case UINT16_MAX:
3676                 filter_info->dst_port_mask = 0;
3677                 filter_info->dst_port = filter->dst_port;
3678                 break;
3679         case 0:
3680                 filter_info->dst_port_mask = 1;
3681                 break;
3682         default:
3683                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3684                 return -EINVAL;
3685         }
3686
3687         switch (filter->proto_mask) {
3688         case UINT8_MAX:
3689                 filter_info->proto_mask = 0;
3690                 filter_info->proto = filter->proto;
3691                 break;
3692         case 0:
3693                 filter_info->proto_mask = 1;
3694                 break;
3695         default:
3696                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3697                 return -EINVAL;
3698         }
3699
3700         filter_info->priority = (uint8_t)filter->priority;
3701         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3702                 filter_info->tcp_flags = filter->tcp_flags;
3703         else
3704                 filter_info->tcp_flags = 0;
3705
3706         return 0;
3707 }
3708
3709 static inline struct e1000_2tuple_filter *
3710 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3711                         struct e1000_2tuple_filter_info *key)
3712 {
3713         struct e1000_2tuple_filter *it;
3714
3715         TAILQ_FOREACH(it, filter_list, entries) {
3716                 if (memcmp(key, &it->filter_info,
3717                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3718                         return it;
3719                 }
3720         }
3721         return NULL;
3722 }
3723
3724 /*
3725  * igb_add_2tuple_filter - add a 2tuple filter
3726  *
3727  * @param
3728  * dev: Pointer to struct rte_eth_dev.
3729  * ntuple_filter: ponter to the filter that will be added.
3730  *
3731  * @return
3732  *    - On success, zero.
3733  *    - On failure, a negative value.
3734  */
3735 static int
3736 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3737                         struct rte_eth_ntuple_filter *ntuple_filter)
3738 {
3739         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3740         struct e1000_filter_info *filter_info =
3741                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3742         struct e1000_2tuple_filter *filter;
3743         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3744         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3745         int i, ret;
3746
3747         filter = rte_zmalloc("e1000_2tuple_filter",
3748                         sizeof(struct e1000_2tuple_filter), 0);
3749         if (filter == NULL)
3750                 return -ENOMEM;
3751
3752         ret = ntuple_filter_to_2tuple(ntuple_filter,
3753                                       &filter->filter_info);
3754         if (ret < 0) {
3755                 rte_free(filter);
3756                 return ret;
3757         }
3758         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3759                                          &filter->filter_info) != NULL) {
3760                 PMD_DRV_LOG(ERR, "filter exists.");
3761                 rte_free(filter);
3762                 return -EEXIST;
3763         }
3764         filter->queue = ntuple_filter->queue;
3765
3766         /*
3767          * look for an unused 2tuple filter index,
3768          * and insert the filter to list.
3769          */
3770         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3771                 if (!(filter_info->twotuple_mask & (1 << i))) {
3772                         filter_info->twotuple_mask |= 1 << i;
3773                         filter->index = i;
3774                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3775                                           filter,
3776                                           entries);
3777                         break;
3778                 }
3779         }
3780         if (i >= E1000_MAX_TTQF_FILTERS) {
3781                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3782                 rte_free(filter);
3783                 return -ENOSYS;
3784         }
3785
3786         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3787         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3788                 imir |= E1000_IMIR_PORT_BP;
3789         else
3790                 imir &= ~E1000_IMIR_PORT_BP;
3791
3792         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3793
3794         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3795         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3796         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3797         if (filter->filter_info.proto_mask == 0)
3798                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3799
3800         /* tcp flags bits setting. */
3801         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3802                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3803                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3804                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3805                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3806                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3807                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3808                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3809                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3810                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3811                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3812                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3813                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3814         } else
3815                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3816         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3817         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3818         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3819         return 0;
3820 }
3821
3822 /*
3823  * igb_remove_2tuple_filter - remove a 2tuple filter
3824  *
3825  * @param
3826  * dev: Pointer to struct rte_eth_dev.
3827  * ntuple_filter: ponter to the filter that will be removed.
3828  *
3829  * @return
3830  *    - On success, zero.
3831  *    - On failure, a negative value.
3832  */
3833 static int
3834 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3835                         struct rte_eth_ntuple_filter *ntuple_filter)
3836 {
3837         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3838         struct e1000_filter_info *filter_info =
3839                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3840         struct e1000_2tuple_filter_info filter_2tuple;
3841         struct e1000_2tuple_filter *filter;
3842         int ret;
3843
3844         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3845         ret = ntuple_filter_to_2tuple(ntuple_filter,
3846                                       &filter_2tuple);
3847         if (ret < 0)
3848                 return ret;
3849
3850         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3851                                          &filter_2tuple);
3852         if (filter == NULL) {
3853                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3854                 return -ENOENT;
3855         }
3856
3857         filter_info->twotuple_mask &= ~(1 << filter->index);
3858         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3859         rte_free(filter);
3860
3861         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3862         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3863         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3864         return 0;
3865 }
3866
3867 static inline struct e1000_flex_filter *
3868 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3869                         struct e1000_flex_filter_info *key)
3870 {
3871         struct e1000_flex_filter *it;
3872
3873         TAILQ_FOREACH(it, filter_list, entries) {
3874                 if (memcmp(key, &it->filter_info,
3875                         sizeof(struct e1000_flex_filter_info)) == 0)
3876                         return it;
3877         }
3878
3879         return NULL;
3880 }
3881
3882 static int
3883 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3884                         struct rte_eth_flex_filter *filter,
3885                         bool add)
3886 {
3887         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3888         struct e1000_filter_info *filter_info =
3889                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3890         struct e1000_flex_filter *flex_filter, *it;
3891         uint32_t wufc, queueing, mask;
3892         uint32_t reg_off;
3893         uint8_t shift, i, j = 0;
3894
3895         flex_filter = rte_zmalloc("e1000_flex_filter",
3896                         sizeof(struct e1000_flex_filter), 0);
3897         if (flex_filter == NULL)
3898                 return -ENOMEM;
3899
3900         flex_filter->filter_info.len = filter->len;
3901         flex_filter->filter_info.priority = filter->priority;
3902         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3903         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3904                 mask = 0;
3905                 /* reverse bits in flex filter's mask*/
3906                 for (shift = 0; shift < CHAR_BIT; shift++) {
3907                         if (filter->mask[i] & (0x01 << shift))
3908                                 mask |= (0x80 >> shift);
3909                 }
3910                 flex_filter->filter_info.mask[i] = mask;
3911         }
3912
3913         wufc = E1000_READ_REG(hw, E1000_WUFC);
3914         if (flex_filter->index < E1000_MAX_FHFT)
3915                 reg_off = E1000_FHFT(flex_filter->index);
3916         else
3917                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3918
3919         if (add) {
3920                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3921                                 &flex_filter->filter_info) != NULL) {
3922                         PMD_DRV_LOG(ERR, "filter exists.");
3923                         rte_free(flex_filter);
3924                         return -EEXIST;
3925                 }
3926                 flex_filter->queue = filter->queue;
3927                 /*
3928                  * look for an unused flex filter index
3929                  * and insert the filter into the list.
3930                  */
3931                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3932                         if (!(filter_info->flex_mask & (1 << i))) {
3933                                 filter_info->flex_mask |= 1 << i;
3934                                 flex_filter->index = i;
3935                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3936                                         flex_filter,
3937                                         entries);
3938                                 break;
3939                         }
3940                 }
3941                 if (i >= E1000_MAX_FLEX_FILTERS) {
3942                         PMD_DRV_LOG(ERR, "flex filters are full.");
3943                         rte_free(flex_filter);
3944                         return -ENOSYS;
3945                 }
3946
3947                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3948                                 (E1000_WUFC_FLX0 << flex_filter->index));
3949                 queueing = filter->len |
3950                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3951                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3952                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3953                                 queueing);
3954                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3955                         E1000_WRITE_REG(hw, reg_off,
3956                                         flex_filter->filter_info.dwords[j]);
3957                         reg_off += sizeof(uint32_t);
3958                         E1000_WRITE_REG(hw, reg_off,
3959                                         flex_filter->filter_info.dwords[++j]);
3960                         reg_off += sizeof(uint32_t);
3961                         E1000_WRITE_REG(hw, reg_off,
3962                                 (uint32_t)flex_filter->filter_info.mask[i]);
3963                         reg_off += sizeof(uint32_t) * 2;
3964                         ++j;
3965                 }
3966         } else {
3967                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3968                                 &flex_filter->filter_info);
3969                 if (it == NULL) {
3970                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3971                         rte_free(flex_filter);
3972                         return -ENOENT;
3973                 }
3974
3975                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3976                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3977                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3978                         (~(E1000_WUFC_FLX0 << it->index)));
3979
3980                 filter_info->flex_mask &= ~(1 << it->index);
3981                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3982                 rte_free(it);
3983                 rte_free(flex_filter);
3984         }
3985
3986         return 0;
3987 }
3988
3989 static int
3990 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3991                         struct rte_eth_flex_filter *filter)
3992 {
3993         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3994         struct e1000_filter_info *filter_info =
3995                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3996         struct e1000_flex_filter flex_filter, *it;
3997         uint32_t wufc, queueing, wufc_en = 0;
3998
3999         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4000         flex_filter.filter_info.len = filter->len;
4001         flex_filter.filter_info.priority = filter->priority;
4002         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4003         memcpy(flex_filter.filter_info.mask, filter->mask,
4004                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
4005
4006         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4007                                 &flex_filter.filter_info);
4008         if (it == NULL) {
4009                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4010                 return -ENOENT;
4011         }
4012
4013         wufc = E1000_READ_REG(hw, E1000_WUFC);
4014         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4015
4016         if ((wufc & wufc_en) == wufc_en) {
4017                 uint32_t reg_off = 0;
4018                 if (it->index < E1000_MAX_FHFT)
4019                         reg_off = E1000_FHFT(it->index);
4020                 else
4021                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4022
4023                 queueing = E1000_READ_REG(hw,
4024                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4025                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4026                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4027                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4028                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4029                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4030                 return 0;
4031         }
4032         return -ENOENT;
4033 }
4034
4035 static int
4036 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4037                         enum rte_filter_op filter_op,
4038                         void *arg)
4039 {
4040         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4041         struct rte_eth_flex_filter *filter;
4042         int ret = 0;
4043
4044         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4045
4046         if (filter_op == RTE_ETH_FILTER_NOP)
4047                 return ret;
4048
4049         if (arg == NULL) {
4050                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4051                             filter_op);
4052                 return -EINVAL;
4053         }
4054
4055         filter = (struct rte_eth_flex_filter *)arg;
4056         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4057             || filter->len % sizeof(uint64_t) != 0) {
4058                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4059                 return -EINVAL;
4060         }
4061         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4062                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4063                 return -EINVAL;
4064         }
4065
4066         switch (filter_op) {
4067         case RTE_ETH_FILTER_ADD:
4068                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4069                 break;
4070         case RTE_ETH_FILTER_DELETE:
4071                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4072                 break;
4073         case RTE_ETH_FILTER_GET:
4074                 ret = eth_igb_get_flex_filter(dev, filter);
4075                 break;
4076         default:
4077                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4078                 ret = -EINVAL;
4079                 break;
4080         }
4081
4082         return ret;
4083 }
4084
4085 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4086 static inline int
4087 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4088                         struct e1000_5tuple_filter_info *filter_info)
4089 {
4090         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4091                 return -EINVAL;
4092         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4093                 return -EINVAL;  /* filter index is out of range. */
4094         if (filter->tcp_flags > TCP_FLAG_ALL)
4095                 return -EINVAL;  /* flags is invalid. */
4096
4097         switch (filter->dst_ip_mask) {
4098         case UINT32_MAX:
4099                 filter_info->dst_ip_mask = 0;
4100                 filter_info->dst_ip = filter->dst_ip;
4101                 break;
4102         case 0:
4103                 filter_info->dst_ip_mask = 1;
4104                 break;
4105         default:
4106                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4107                 return -EINVAL;
4108         }
4109
4110         switch (filter->src_ip_mask) {
4111         case UINT32_MAX:
4112                 filter_info->src_ip_mask = 0;
4113                 filter_info->src_ip = filter->src_ip;
4114                 break;
4115         case 0:
4116                 filter_info->src_ip_mask = 1;
4117                 break;
4118         default:
4119                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4120                 return -EINVAL;
4121         }
4122
4123         switch (filter->dst_port_mask) {
4124         case UINT16_MAX:
4125                 filter_info->dst_port_mask = 0;
4126                 filter_info->dst_port = filter->dst_port;
4127                 break;
4128         case 0:
4129                 filter_info->dst_port_mask = 1;
4130                 break;
4131         default:
4132                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4133                 return -EINVAL;
4134         }
4135
4136         switch (filter->src_port_mask) {
4137         case UINT16_MAX:
4138                 filter_info->src_port_mask = 0;
4139                 filter_info->src_port = filter->src_port;
4140                 break;
4141         case 0:
4142                 filter_info->src_port_mask = 1;
4143                 break;
4144         default:
4145                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4146                 return -EINVAL;
4147         }
4148
4149         switch (filter->proto_mask) {
4150         case UINT8_MAX:
4151                 filter_info->proto_mask = 0;
4152                 filter_info->proto = filter->proto;
4153                 break;
4154         case 0:
4155                 filter_info->proto_mask = 1;
4156                 break;
4157         default:
4158                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4159                 return -EINVAL;
4160         }
4161
4162         filter_info->priority = (uint8_t)filter->priority;
4163         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4164                 filter_info->tcp_flags = filter->tcp_flags;
4165         else
4166                 filter_info->tcp_flags = 0;
4167
4168         return 0;
4169 }
4170
4171 static inline struct e1000_5tuple_filter *
4172 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4173                         struct e1000_5tuple_filter_info *key)
4174 {
4175         struct e1000_5tuple_filter *it;
4176
4177         TAILQ_FOREACH(it, filter_list, entries) {
4178                 if (memcmp(key, &it->filter_info,
4179                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4180                         return it;
4181                 }
4182         }
4183         return NULL;
4184 }
4185
4186 /*
4187  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4188  *
4189  * @param
4190  * dev: Pointer to struct rte_eth_dev.
4191  * ntuple_filter: ponter to the filter that will be added.
4192  *
4193  * @return
4194  *    - On success, zero.
4195  *    - On failure, a negative value.
4196  */
4197 static int
4198 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4199                         struct rte_eth_ntuple_filter *ntuple_filter)
4200 {
4201         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4202         struct e1000_filter_info *filter_info =
4203                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4204         struct e1000_5tuple_filter *filter;
4205         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4206         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4207         uint8_t i;
4208         int ret;
4209
4210         filter = rte_zmalloc("e1000_5tuple_filter",
4211                         sizeof(struct e1000_5tuple_filter), 0);
4212         if (filter == NULL)
4213                 return -ENOMEM;
4214
4215         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4216                                             &filter->filter_info);
4217         if (ret < 0) {
4218                 rte_free(filter);
4219                 return ret;
4220         }
4221
4222         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4223                                          &filter->filter_info) != NULL) {
4224                 PMD_DRV_LOG(ERR, "filter exists.");
4225                 rte_free(filter);
4226                 return -EEXIST;
4227         }
4228         filter->queue = ntuple_filter->queue;
4229
4230         /*
4231          * look for an unused 5tuple filter index,
4232          * and insert the filter to list.
4233          */
4234         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4235                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4236                         filter_info->fivetuple_mask |= 1 << i;
4237                         filter->index = i;
4238                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4239                                           filter,
4240                                           entries);
4241                         break;
4242                 }
4243         }
4244         if (i >= E1000_MAX_FTQF_FILTERS) {
4245                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4246                 rte_free(filter);
4247                 return -ENOSYS;
4248         }
4249
4250         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4251         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4252                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4253         if (filter->filter_info.dst_ip_mask == 0)
4254                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4255         if (filter->filter_info.src_port_mask == 0)
4256                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4257         if (filter->filter_info.proto_mask == 0)
4258                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4259         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4260                 E1000_FTQF_QUEUE_MASK;
4261         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4262         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4263         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4264         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4265
4266         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4267         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4268
4269         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4270         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4271                 imir |= E1000_IMIR_PORT_BP;
4272         else
4273                 imir &= ~E1000_IMIR_PORT_BP;
4274         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4275
4276         /* tcp flags bits setting. */
4277         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4278                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4279                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4280                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4281                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4282                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4283                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4284                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4285                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4286                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4287                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4288                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4289                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4290         } else
4291                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4292         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4293         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4294         return 0;
4295 }
4296
4297 /*
4298  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4299  *
4300  * @param
4301  * dev: Pointer to struct rte_eth_dev.
4302  * ntuple_filter: ponter to the filter that will be removed.
4303  *
4304  * @return
4305  *    - On success, zero.
4306  *    - On failure, a negative value.
4307  */
4308 static int
4309 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4310                                 struct rte_eth_ntuple_filter *ntuple_filter)
4311 {
4312         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4313         struct e1000_filter_info *filter_info =
4314                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4315         struct e1000_5tuple_filter_info filter_5tuple;
4316         struct e1000_5tuple_filter *filter;
4317         int ret;
4318
4319         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4320         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4321                                             &filter_5tuple);
4322         if (ret < 0)
4323                 return ret;
4324
4325         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4326                                          &filter_5tuple);
4327         if (filter == NULL) {
4328                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4329                 return -ENOENT;
4330         }
4331
4332         filter_info->fivetuple_mask &= ~(1 << filter->index);
4333         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4334         rte_free(filter);
4335
4336         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4337                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4338         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4339         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4340         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4341         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4342         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4343         return 0;
4344 }
4345
4346 static int
4347 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4348 {
4349         uint32_t rctl;
4350         struct e1000_hw *hw;
4351         struct rte_eth_dev_info dev_info;
4352         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4353                                      VLAN_TAG_SIZE);
4354
4355         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4356
4357 #ifdef RTE_LIBRTE_82571_SUPPORT
4358         /* XXX: not bigger than max_rx_pktlen */
4359         if (hw->mac.type == e1000_82571)
4360                 return -ENOTSUP;
4361 #endif
4362         eth_igb_infos_get(dev, &dev_info);
4363
4364         /* check that mtu is within the allowed range */
4365         if ((mtu < ETHER_MIN_MTU) ||
4366             (frame_size > dev_info.max_rx_pktlen))
4367                 return -EINVAL;
4368
4369         /* refuse mtu that requires the support of scattered packets when this
4370          * feature has not been enabled before. */
4371         if (!dev->data->scattered_rx &&
4372             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4373                 return -EINVAL;
4374
4375         rctl = E1000_READ_REG(hw, E1000_RCTL);
4376
4377         /* switch to jumbo mode if needed */
4378         if (frame_size > ETHER_MAX_LEN) {
4379                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4380                 rctl |= E1000_RCTL_LPE;
4381         } else {
4382                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4383                 rctl &= ~E1000_RCTL_LPE;
4384         }
4385         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4386
4387         /* update max frame size */
4388         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4389
4390         E1000_WRITE_REG(hw, E1000_RLPML,
4391                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4392
4393         return 0;
4394 }
4395
4396 /*
4397  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4398  *
4399  * @param
4400  * dev: Pointer to struct rte_eth_dev.
4401  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4402  * add: if true, add filter, if false, remove filter
4403  *
4404  * @return
4405  *    - On success, zero.
4406  *    - On failure, a negative value.
4407  */
4408 static int
4409 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4410                         struct rte_eth_ntuple_filter *ntuple_filter,
4411                         bool add)
4412 {
4413         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4414         int ret;
4415
4416         switch (ntuple_filter->flags) {
4417         case RTE_5TUPLE_FLAGS:
4418         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4419                 if (hw->mac.type != e1000_82576)
4420                         return -ENOTSUP;
4421                 if (add)
4422                         ret = igb_add_5tuple_filter_82576(dev,
4423                                                           ntuple_filter);
4424                 else
4425                         ret = igb_remove_5tuple_filter_82576(dev,
4426                                                              ntuple_filter);
4427                 break;
4428         case RTE_2TUPLE_FLAGS:
4429         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4430                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4431                         return -ENOTSUP;
4432                 if (add)
4433                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4434                 else
4435                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4436                 break;
4437         default:
4438                 ret = -EINVAL;
4439                 break;
4440         }
4441
4442         return ret;
4443 }
4444
4445 /*
4446  * igb_get_ntuple_filter - get a ntuple filter
4447  *
4448  * @param
4449  * dev: Pointer to struct rte_eth_dev.
4450  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4451  *
4452  * @return
4453  *    - On success, zero.
4454  *    - On failure, a negative value.
4455  */
4456 static int
4457 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4458                         struct rte_eth_ntuple_filter *ntuple_filter)
4459 {
4460         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4461         struct e1000_filter_info *filter_info =
4462                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4463         struct e1000_5tuple_filter_info filter_5tuple;
4464         struct e1000_2tuple_filter_info filter_2tuple;
4465         struct e1000_5tuple_filter *p_5tuple_filter;
4466         struct e1000_2tuple_filter *p_2tuple_filter;
4467         int ret;
4468
4469         switch (ntuple_filter->flags) {
4470         case RTE_5TUPLE_FLAGS:
4471         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4472                 if (hw->mac.type != e1000_82576)
4473                         return -ENOTSUP;
4474                 memset(&filter_5tuple,
4475                         0,
4476                         sizeof(struct e1000_5tuple_filter_info));
4477                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4478                                                     &filter_5tuple);
4479                 if (ret < 0)
4480                         return ret;
4481                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4482                                         &filter_info->fivetuple_list,
4483                                         &filter_5tuple);
4484                 if (p_5tuple_filter == NULL) {
4485                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4486                         return -ENOENT;
4487                 }
4488                 ntuple_filter->queue = p_5tuple_filter->queue;
4489                 break;
4490         case RTE_2TUPLE_FLAGS:
4491         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4492                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4493                         return -ENOTSUP;
4494                 memset(&filter_2tuple,
4495                         0,
4496                         sizeof(struct e1000_2tuple_filter_info));
4497                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4498                 if (ret < 0)
4499                         return ret;
4500                 p_2tuple_filter = igb_2tuple_filter_lookup(
4501                                         &filter_info->twotuple_list,
4502                                         &filter_2tuple);
4503                 if (p_2tuple_filter == NULL) {
4504                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4505                         return -ENOENT;
4506                 }
4507                 ntuple_filter->queue = p_2tuple_filter->queue;
4508                 break;
4509         default:
4510                 ret = -EINVAL;
4511                 break;
4512         }
4513
4514         return 0;
4515 }
4516
4517 /*
4518  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4519  * @dev: pointer to rte_eth_dev structure
4520  * @filter_op:operation will be taken.
4521  * @arg: a pointer to specific structure corresponding to the filter_op
4522  */
4523 static int
4524 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4525                                 enum rte_filter_op filter_op,
4526                                 void *arg)
4527 {
4528         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4529         int ret;
4530
4531         MAC_TYPE_FILTER_SUP(hw->mac.type);
4532
4533         if (filter_op == RTE_ETH_FILTER_NOP)
4534                 return 0;
4535
4536         if (arg == NULL) {
4537                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4538                             filter_op);
4539                 return -EINVAL;
4540         }
4541
4542         switch (filter_op) {
4543         case RTE_ETH_FILTER_ADD:
4544                 ret = igb_add_del_ntuple_filter(dev,
4545                         (struct rte_eth_ntuple_filter *)arg,
4546                         TRUE);
4547                 break;
4548         case RTE_ETH_FILTER_DELETE:
4549                 ret = igb_add_del_ntuple_filter(dev,
4550                         (struct rte_eth_ntuple_filter *)arg,
4551                         FALSE);
4552                 break;
4553         case RTE_ETH_FILTER_GET:
4554                 ret = igb_get_ntuple_filter(dev,
4555                         (struct rte_eth_ntuple_filter *)arg);
4556                 break;
4557         default:
4558                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4559                 ret = -EINVAL;
4560                 break;
4561         }
4562         return ret;
4563 }
4564
4565 static inline int
4566 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4567                         uint16_t ethertype)
4568 {
4569         int i;
4570
4571         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4572                 if (filter_info->ethertype_filters[i] == ethertype &&
4573                     (filter_info->ethertype_mask & (1 << i)))
4574                         return i;
4575         }
4576         return -1;
4577 }
4578
4579 static inline int
4580 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4581                         uint16_t ethertype)
4582 {
4583         int i;
4584
4585         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4586                 if (!(filter_info->ethertype_mask & (1 << i))) {
4587                         filter_info->ethertype_mask |= 1 << i;
4588                         filter_info->ethertype_filters[i] = ethertype;
4589                         return i;
4590                 }
4591         }
4592         return -1;
4593 }
4594
4595 static inline int
4596 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4597                         uint8_t idx)
4598 {
4599         if (idx >= E1000_MAX_ETQF_FILTERS)
4600                 return -1;
4601         filter_info->ethertype_mask &= ~(1 << idx);
4602         filter_info->ethertype_filters[idx] = 0;
4603         return idx;
4604 }
4605
4606
4607 static int
4608 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4609                         struct rte_eth_ethertype_filter *filter,
4610                         bool add)
4611 {
4612         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4613         struct e1000_filter_info *filter_info =
4614                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4615         uint32_t etqf = 0;
4616         int ret;
4617
4618         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4619                 filter->ether_type == ETHER_TYPE_IPv6) {
4620                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4621                         " ethertype filter.", filter->ether_type);
4622                 return -EINVAL;
4623         }
4624
4625         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4626                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4627                 return -EINVAL;
4628         }
4629         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4630                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4631                 return -EINVAL;
4632         }
4633
4634         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4635         if (ret >= 0 && add) {
4636                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4637                             filter->ether_type);
4638                 return -EEXIST;
4639         }
4640         if (ret < 0 && !add) {
4641                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4642                             filter->ether_type);
4643                 return -ENOENT;
4644         }
4645
4646         if (add) {
4647                 ret = igb_ethertype_filter_insert(filter_info,
4648                         filter->ether_type);
4649                 if (ret < 0) {
4650                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4651                         return -ENOSYS;
4652                 }
4653
4654                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4655                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4656                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4657         } else {
4658                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4659                 if (ret < 0)
4660                         return -ENOSYS;
4661         }
4662         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4663         E1000_WRITE_FLUSH(hw);
4664
4665         return 0;
4666 }
4667
4668 static int
4669 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4670                         struct rte_eth_ethertype_filter *filter)
4671 {
4672         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4673         struct e1000_filter_info *filter_info =
4674                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4675         uint32_t etqf;
4676         int ret;
4677
4678         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4679         if (ret < 0) {
4680                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4681                             filter->ether_type);
4682                 return -ENOENT;
4683         }
4684
4685         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4686         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4687                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4688                 filter->flags = 0;
4689                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4690                                 E1000_ETQF_QUEUE_SHIFT;
4691                 return 0;
4692         }
4693
4694         return -ENOENT;
4695 }
4696
4697 /*
4698  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4699  * @dev: pointer to rte_eth_dev structure
4700  * @filter_op:operation will be taken.
4701  * @arg: a pointer to specific structure corresponding to the filter_op
4702  */
4703 static int
4704 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4705                                 enum rte_filter_op filter_op,
4706                                 void *arg)
4707 {
4708         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4709         int ret;
4710
4711         MAC_TYPE_FILTER_SUP(hw->mac.type);
4712
4713         if (filter_op == RTE_ETH_FILTER_NOP)
4714                 return 0;
4715
4716         if (arg == NULL) {
4717                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4718                             filter_op);
4719                 return -EINVAL;
4720         }
4721
4722         switch (filter_op) {
4723         case RTE_ETH_FILTER_ADD:
4724                 ret = igb_add_del_ethertype_filter(dev,
4725                         (struct rte_eth_ethertype_filter *)arg,
4726                         TRUE);
4727                 break;
4728         case RTE_ETH_FILTER_DELETE:
4729                 ret = igb_add_del_ethertype_filter(dev,
4730                         (struct rte_eth_ethertype_filter *)arg,
4731                         FALSE);
4732                 break;
4733         case RTE_ETH_FILTER_GET:
4734                 ret = igb_get_ethertype_filter(dev,
4735                         (struct rte_eth_ethertype_filter *)arg);
4736                 break;
4737         default:
4738                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4739                 ret = -EINVAL;
4740                 break;
4741         }
4742         return ret;
4743 }
4744
4745 static int
4746 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4747                      enum rte_filter_type filter_type,
4748                      enum rte_filter_op filter_op,
4749                      void *arg)
4750 {
4751         int ret = -EINVAL;
4752
4753         switch (filter_type) {
4754         case RTE_ETH_FILTER_NTUPLE:
4755                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4756                 break;
4757         case RTE_ETH_FILTER_ETHERTYPE:
4758                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4759                 break;
4760         case RTE_ETH_FILTER_SYN:
4761                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4762                 break;
4763         case RTE_ETH_FILTER_FLEXIBLE:
4764                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4765                 break;
4766         default:
4767                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4768                                                         filter_type);
4769                 break;
4770         }
4771
4772         return ret;
4773 }
4774
4775 static int
4776 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4777                          struct ether_addr *mc_addr_set,
4778                          uint32_t nb_mc_addr)
4779 {
4780         struct e1000_hw *hw;
4781
4782         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4783         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4784         return 0;
4785 }
4786
4787 static uint64_t
4788 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4789 {
4790         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4791         uint64_t systime_cycles;
4792
4793         switch (hw->mac.type) {
4794         case e1000_i210:
4795         case e1000_i211:
4796                 /*
4797                  * Need to read System Time Residue Register to be able
4798                  * to read the other two registers.
4799                  */
4800                 E1000_READ_REG(hw, E1000_SYSTIMR);
4801                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4802                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4803                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4804                                 * NSEC_PER_SEC;
4805                 break;
4806         case e1000_82580:
4807         case e1000_i350:
4808         case e1000_i354:
4809                 /*
4810                  * Need to read System Time Residue Register to be able
4811                  * to read the other two registers.
4812                  */
4813                 E1000_READ_REG(hw, E1000_SYSTIMR);
4814                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4815                 /* Only the 8 LSB are valid. */
4816                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4817                                 & 0xff) << 32;
4818                 break;
4819         default:
4820                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4821                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4822                                 << 32;
4823                 break;
4824         }
4825
4826         return systime_cycles;
4827 }
4828
4829 static uint64_t
4830 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4831 {
4832         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4833         uint64_t rx_tstamp_cycles;
4834
4835         switch (hw->mac.type) {
4836         case e1000_i210:
4837         case e1000_i211:
4838                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4839                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4840                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4841                                 * NSEC_PER_SEC;
4842                 break;
4843         case e1000_82580:
4844         case e1000_i350:
4845         case e1000_i354:
4846                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4847                 /* Only the 8 LSB are valid. */
4848                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4849                                 & 0xff) << 32;
4850                 break;
4851         default:
4852                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4853                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4854                                 << 32;
4855                 break;
4856         }
4857
4858         return rx_tstamp_cycles;
4859 }
4860
4861 static uint64_t
4862 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4863 {
4864         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4865         uint64_t tx_tstamp_cycles;
4866
4867         switch (hw->mac.type) {
4868         case e1000_i210:
4869         case e1000_i211:
4870                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4871                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4872                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4873                                 * NSEC_PER_SEC;
4874                 break;
4875         case e1000_82580:
4876         case e1000_i350:
4877         case e1000_i354:
4878                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4879                 /* Only the 8 LSB are valid. */
4880                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4881                                 & 0xff) << 32;
4882                 break;
4883         default:
4884                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4885                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4886                                 << 32;
4887                 break;
4888         }
4889
4890         return tx_tstamp_cycles;
4891 }
4892
4893 static void
4894 igb_start_timecounters(struct rte_eth_dev *dev)
4895 {
4896         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4897         struct e1000_adapter *adapter =
4898                 (struct e1000_adapter *)dev->data->dev_private;
4899         uint32_t incval = 1;
4900         uint32_t shift = 0;
4901         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4902
4903         switch (hw->mac.type) {
4904         case e1000_82580:
4905         case e1000_i350:
4906         case e1000_i354:
4907                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4908                 mask = (1ULL << 40) - 1;
4909                 /* fall-through */
4910         case e1000_i210:
4911         case e1000_i211:
4912                 /*
4913                  * Start incrementing the register
4914                  * used to timestamp PTP packets.
4915                  */
4916                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4917                 break;
4918         case e1000_82576:
4919                 incval = E1000_INCVALUE_82576;
4920                 shift = IGB_82576_TSYNC_SHIFT;
4921                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4922                                 E1000_INCPERIOD_82576 | incval);
4923                 break;
4924         default:
4925                 /* Not supported */
4926                 return;
4927         }
4928
4929         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4930         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4931         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4932
4933         adapter->systime_tc.cc_mask = mask;
4934         adapter->systime_tc.cc_shift = shift;
4935         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4936
4937         adapter->rx_tstamp_tc.cc_mask = mask;
4938         adapter->rx_tstamp_tc.cc_shift = shift;
4939         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4940
4941         adapter->tx_tstamp_tc.cc_mask = mask;
4942         adapter->tx_tstamp_tc.cc_shift = shift;
4943         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4944 }
4945
4946 static int
4947 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4948 {
4949         struct e1000_adapter *adapter =
4950                         (struct e1000_adapter *)dev->data->dev_private;
4951
4952         adapter->systime_tc.nsec += delta;
4953         adapter->rx_tstamp_tc.nsec += delta;
4954         adapter->tx_tstamp_tc.nsec += delta;
4955
4956         return 0;
4957 }
4958
4959 static int
4960 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4961 {
4962         uint64_t ns;
4963         struct e1000_adapter *adapter =
4964                         (struct e1000_adapter *)dev->data->dev_private;
4965
4966         ns = rte_timespec_to_ns(ts);
4967
4968         /* Set the timecounters to a new value. */
4969         adapter->systime_tc.nsec = ns;
4970         adapter->rx_tstamp_tc.nsec = ns;
4971         adapter->tx_tstamp_tc.nsec = ns;
4972
4973         return 0;
4974 }
4975
4976 static int
4977 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4978 {
4979         uint64_t ns, systime_cycles;
4980         struct e1000_adapter *adapter =
4981                         (struct e1000_adapter *)dev->data->dev_private;
4982
4983         systime_cycles = igb_read_systime_cyclecounter(dev);
4984         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4985         *ts = rte_ns_to_timespec(ns);
4986
4987         return 0;
4988 }
4989
4990 static int
4991 igb_timesync_enable(struct rte_eth_dev *dev)
4992 {
4993         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4994         uint32_t tsync_ctl;
4995         uint32_t tsauxc;
4996
4997         /* Stop the timesync system time. */
4998         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4999         /* Reset the timesync system time value. */
5000         switch (hw->mac.type) {
5001         case e1000_82580:
5002         case e1000_i350:
5003         case e1000_i354:
5004         case e1000_i210:
5005         case e1000_i211:
5006                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5007                 /* fall-through */
5008         case e1000_82576:
5009                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5010                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5011                 break;
5012         default:
5013                 /* Not supported. */
5014                 return -ENOTSUP;
5015         }
5016
5017         /* Enable system time for it isn't on by default. */
5018         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5019         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5020         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5021
5022         igb_start_timecounters(dev);
5023
5024         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5025         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5026                         (ETHER_TYPE_1588 |
5027                          E1000_ETQF_FILTER_ENABLE |
5028                          E1000_ETQF_1588));
5029
5030         /* Enable timestamping of received PTP packets. */
5031         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5032         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5033         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5034
5035         /* Enable Timestamping of transmitted PTP packets. */
5036         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5037         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5038         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5039
5040         return 0;
5041 }
5042
5043 static int
5044 igb_timesync_disable(struct rte_eth_dev *dev)
5045 {
5046         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5047         uint32_t tsync_ctl;
5048
5049         /* Disable timestamping of transmitted PTP packets. */
5050         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5051         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5052         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5053
5054         /* Disable timestamping of received PTP packets. */
5055         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5056         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5057         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5058
5059         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5060         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5061
5062         /* Stop incrementating the System Time registers. */
5063         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5064
5065         return 0;
5066 }
5067
5068 static int
5069 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5070                                struct timespec *timestamp,
5071                                uint32_t flags __rte_unused)
5072 {
5073         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5074         struct e1000_adapter *adapter =
5075                         (struct e1000_adapter *)dev->data->dev_private;
5076         uint32_t tsync_rxctl;
5077         uint64_t rx_tstamp_cycles;
5078         uint64_t ns;
5079
5080         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5081         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5082                 return -EINVAL;
5083
5084         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5085         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5086         *timestamp = rte_ns_to_timespec(ns);
5087
5088         return  0;
5089 }
5090
5091 static int
5092 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5093                                struct timespec *timestamp)
5094 {
5095         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5096         struct e1000_adapter *adapter =
5097                         (struct e1000_adapter *)dev->data->dev_private;
5098         uint32_t tsync_txctl;
5099         uint64_t tx_tstamp_cycles;
5100         uint64_t ns;
5101
5102         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5103         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5104                 return -EINVAL;
5105
5106         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5107         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5108         *timestamp = rte_ns_to_timespec(ns);
5109
5110         return  0;
5111 }
5112
5113 static int
5114 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5115 {
5116         int count = 0;
5117         int g_ind = 0;
5118         const struct reg_info *reg_group;
5119
5120         while ((reg_group = igb_regs[g_ind++]))
5121                 count += igb_reg_group_count(reg_group);
5122
5123         return count;
5124 }
5125
5126 static int
5127 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5128 {
5129         int count = 0;
5130         int g_ind = 0;
5131         const struct reg_info *reg_group;
5132
5133         while ((reg_group = igbvf_regs[g_ind++]))
5134                 count += igb_reg_group_count(reg_group);
5135
5136         return count;
5137 }
5138
5139 static int
5140 eth_igb_get_regs(struct rte_eth_dev *dev,
5141         struct rte_dev_reg_info *regs)
5142 {
5143         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5144         uint32_t *data = regs->data;
5145         int g_ind = 0;
5146         int count = 0;
5147         const struct reg_info *reg_group;
5148
5149         if (data == NULL) {
5150                 regs->length = eth_igb_get_reg_length(dev);
5151                 regs->width = sizeof(uint32_t);
5152                 return 0;
5153         }
5154
5155         /* Support only full register dump */
5156         if ((regs->length == 0) ||
5157             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5158                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5159                         hw->device_id;
5160                 while ((reg_group = igb_regs[g_ind++]))
5161                         count += igb_read_regs_group(dev, &data[count],
5162                                                         reg_group);
5163                 return 0;
5164         }
5165
5166         return -ENOTSUP;
5167 }
5168
5169 static int
5170 igbvf_get_regs(struct rte_eth_dev *dev,
5171         struct rte_dev_reg_info *regs)
5172 {
5173         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5174         uint32_t *data = regs->data;
5175         int g_ind = 0;
5176         int count = 0;
5177         const struct reg_info *reg_group;
5178
5179         if (data == NULL) {
5180                 regs->length = igbvf_get_reg_length(dev);
5181                 regs->width = sizeof(uint32_t);
5182                 return 0;
5183         }
5184
5185         /* Support only full register dump */
5186         if ((regs->length == 0) ||
5187             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5188                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5189                         hw->device_id;
5190                 while ((reg_group = igbvf_regs[g_ind++]))
5191                         count += igb_read_regs_group(dev, &data[count],
5192                                                         reg_group);
5193                 return 0;
5194         }
5195
5196         return -ENOTSUP;
5197 }
5198
5199 static int
5200 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5201 {
5202         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5203
5204         /* Return unit is byte count */
5205         return hw->nvm.word_size * 2;
5206 }
5207
5208 static int
5209 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5210         struct rte_dev_eeprom_info *in_eeprom)
5211 {
5212         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5213         struct e1000_nvm_info *nvm = &hw->nvm;
5214         uint16_t *data = in_eeprom->data;
5215         int first, length;
5216
5217         first = in_eeprom->offset >> 1;
5218         length = in_eeprom->length >> 1;
5219         if ((first >= hw->nvm.word_size) ||
5220             ((first + length) >= hw->nvm.word_size))
5221                 return -EINVAL;
5222
5223         in_eeprom->magic = hw->vendor_id |
5224                 ((uint32_t)hw->device_id << 16);
5225
5226         if ((nvm->ops.read) == NULL)
5227                 return -ENOTSUP;
5228
5229         return nvm->ops.read(hw, first, length, data);
5230 }
5231
5232 static int
5233 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5234         struct rte_dev_eeprom_info *in_eeprom)
5235 {
5236         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5237         struct e1000_nvm_info *nvm = &hw->nvm;
5238         uint16_t *data = in_eeprom->data;
5239         int first, length;
5240
5241         first = in_eeprom->offset >> 1;
5242         length = in_eeprom->length >> 1;
5243         if ((first >= hw->nvm.word_size) ||
5244             ((first + length) >= hw->nvm.word_size))
5245                 return -EINVAL;
5246
5247         in_eeprom->magic = (uint32_t)hw->vendor_id |
5248                 ((uint32_t)hw->device_id << 16);
5249
5250         if ((nvm->ops.write) == NULL)
5251                 return -ENOTSUP;
5252         return nvm->ops.write(hw,  first, length, data);
5253 }
5254
5255 static int
5256 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5257 {
5258         struct e1000_hw *hw =
5259                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5260         uint32_t mask = 1 << queue_id;
5261
5262         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5263         E1000_WRITE_FLUSH(hw);
5264
5265         return 0;
5266 }
5267
5268 static int
5269 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5270 {
5271         struct e1000_hw *hw =
5272                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5273         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5274         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5275         uint32_t mask = 1 << queue_id;
5276         uint32_t regval;
5277
5278         regval = E1000_READ_REG(hw, E1000_EIMS);
5279         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5280         E1000_WRITE_FLUSH(hw);
5281
5282         rte_intr_enable(intr_handle);
5283
5284         return 0;
5285 }
5286
5287 static void
5288 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5289                    uint8_t index, uint8_t offset)
5290 {
5291         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5292
5293         /* clear bits */
5294         val &= ~((uint32_t)0xFF << offset);
5295
5296         /* write vector and valid bit */
5297         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5298
5299         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5300 }
5301
5302 static void
5303 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5304                            uint8_t queue, uint8_t msix_vector)
5305 {
5306         uint32_t tmp = 0;
5307
5308         if (hw->mac.type == e1000_82575) {
5309                 if (direction == 0)
5310                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5311                 else if (direction == 1)
5312                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5313                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5314         } else if (hw->mac.type == e1000_82576) {
5315                 if ((direction == 0) || (direction == 1))
5316                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5317                                            ((queue & 0x8) << 1) +
5318                                            8 * direction);
5319         } else if ((hw->mac.type == e1000_82580) ||
5320                         (hw->mac.type == e1000_i350) ||
5321                         (hw->mac.type == e1000_i354) ||
5322                         (hw->mac.type == e1000_i210) ||
5323                         (hw->mac.type == e1000_i211)) {
5324                 if ((direction == 0) || (direction == 1))
5325                         eth_igb_write_ivar(hw, msix_vector,
5326                                            queue >> 1,
5327                                            ((queue & 0x1) << 4) +
5328                                            8 * direction);
5329         }
5330 }
5331
5332 /* Sets up the hardware to generate MSI-X interrupts properly
5333  * @hw
5334  *  board private structure
5335  */
5336 static void
5337 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5338 {
5339         int queue_id;
5340         uint32_t tmpval, regval, intr_mask;
5341         struct e1000_hw *hw =
5342                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5343         uint32_t vec = E1000_MISC_VEC_ID;
5344         uint32_t base = E1000_MISC_VEC_ID;
5345         uint32_t misc_shift = 0;
5346         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5347         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5348
5349         /* won't configure msix register if no mapping is done
5350          * between intr vector and event fd
5351          */
5352         if (!rte_intr_dp_is_en(intr_handle))
5353                 return;
5354
5355         if (rte_intr_allow_others(intr_handle)) {
5356                 vec = base = E1000_RX_VEC_START;
5357                 misc_shift = 1;
5358         }
5359
5360         /* set interrupt vector for other causes */
5361         if (hw->mac.type == e1000_82575) {
5362                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5363                 /* enable MSI-X PBA support */
5364                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5365
5366                 /* Auto-Mask interrupts upon ICR read */
5367                 tmpval |= E1000_CTRL_EXT_EIAME;
5368                 tmpval |= E1000_CTRL_EXT_IRCA;
5369
5370                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5371
5372                 /* enable msix_other interrupt */
5373                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5374                 regval = E1000_READ_REG(hw, E1000_EIAC);
5375                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5376                 regval = E1000_READ_REG(hw, E1000_EIAM);
5377                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5378         } else if ((hw->mac.type == e1000_82576) ||
5379                         (hw->mac.type == e1000_82580) ||
5380                         (hw->mac.type == e1000_i350) ||
5381                         (hw->mac.type == e1000_i354) ||
5382                         (hw->mac.type == e1000_i210) ||
5383                         (hw->mac.type == e1000_i211)) {
5384                 /* turn on MSI-X capability first */
5385                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5386                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5387                                         E1000_GPIE_NSICR);
5388                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5389                         misc_shift;
5390                 regval = E1000_READ_REG(hw, E1000_EIAC);
5391                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5392
5393                 /* enable msix_other interrupt */
5394                 regval = E1000_READ_REG(hw, E1000_EIMS);
5395                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5396                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5397                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5398         }
5399
5400         /* use EIAM to auto-mask when MSI-X interrupt
5401          * is asserted, this saves a register write for every interrupt
5402          */
5403         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5404                 misc_shift;
5405         regval = E1000_READ_REG(hw, E1000_EIAM);
5406         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5407
5408         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5409                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5410                 intr_handle->intr_vec[queue_id] = vec;
5411                 if (vec < base + intr_handle->nb_efd - 1)
5412                         vec++;
5413         }
5414
5415         E1000_WRITE_FLUSH(hw);
5416 }
5417
5418 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5419 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5420 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio");
5421 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5422 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5423 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio");