drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "base/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59 #include "igb_regs.h"
  60
  61 /*
  62  * Default values for port configuration
  63  */
  64 #define IGB_DEFAULT_RX_FREE_THRESH  32
  65
  66 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  67 #define IGB_DEFAULT_RX_HTHRESH      8
  68 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  69
  70 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  71 #define IGB_DEFAULT_TX_HTHRESH      1
  72 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  73
  74 #define IGB_HKEY_MAX_INDEX 10
  75
  76 /* Bit shift and mask */
  77 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  78 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  79 #define IGB_8_BIT_WIDTH  CHAR_BIT
  80 #define IGB_8_BIT_MASK   UINT8_MAX
  81
  82 /* Additional timesync values. */
  83 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  84 #define E1000_ETQF_FILTER_1588       3
  85 #define IGB_82576_TSYNC_SHIFT        16
  86 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  87 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  89
  90 #define E1000_VTIVAR_MISC                0x01740
  91 #define E1000_VTIVAR_MISC_MASK           0xFF
  92 #define E1000_VTIVAR_VALID               0x80
  93 #define E1000_VTIVAR_MISC_MAILBOX        0
  94 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  95
  96 /* External VLAN Enable bit mask */
  97 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  98
  99 /* External VLAN Ether Type bit mask and shift */
 100 #define E1000_VET_VET_EXT            0xFFFF0000
 101 #define E1000_VET_VET_EXT_SHIFT      16
 102
 103 static int  eth_igb_configure(struct rte_eth_dev *dev);
 104 static int  eth_igb_start(struct rte_eth_dev *dev);
 105 static void eth_igb_stop(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 107 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 108 static void eth_igb_close(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 113 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 114                                 int wait_to_complete);
 115 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 116                                 struct rte_eth_stats *rte_stats);
 117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 118                               struct rte_eth_xstat *xstats, unsigned n);
 119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
 120                 const uint64_t *ids,
 121                 uint64_t *values, unsigned int n);
 122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 123                                     struct rte_eth_xstat_name *xstats_names,
 124                                     unsigned int size);
 125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
 126                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 127                 unsigned int limit);
 128 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 131                                    char *fw_version, size_t fw_size);
 132 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 133                               struct rte_eth_dev_info *dev_info);
 134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 136                                 struct rte_eth_dev_info *dev_info);
 137 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 138                                 struct rte_eth_fc_conf *fc_conf);
 139 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 140                                 struct rte_eth_fc_conf *fc_conf);
 141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 145                                     struct rte_intr_handle *handle);
 146 static void eth_igb_interrupt_handler(void *param);
 147 static int  igb_hardware_init(struct e1000_hw *hw);
 148 static void igb_hw_control_acquire(struct e1000_hw *hw);
 149 static void igb_hw_control_release(struct e1000_hw *hw);
 150 static void igb_init_manageability(struct e1000_hw *hw);
 151 static void igb_release_manageability(struct e1000_hw *hw);
 152
 153 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154
 155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 156                 uint16_t vlan_id, int on);
 157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 158                                  enum rte_vlan_type vlan_type,
 159                                  uint16_t tpid_id);
 160 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 161
 162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 168
 169 static int eth_igb_led_on(struct rte_eth_dev *dev);
 170 static int eth_igb_led_off(struct rte_eth_dev *dev);
 171
 172 static void igb_intr_disable(struct e1000_hw *hw);
 173 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 174 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 175                            struct ether_addr *mac_addr,
 176                            uint32_t index, uint32_t pool);
 177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 179                 struct ether_addr *addr);
 180
 181 static void igbvf_intr_disable(struct e1000_hw *hw);
 182 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 183 static int igbvf_dev_start(struct rte_eth_dev *dev);
 184 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 185 static void igbvf_dev_close(struct rte_eth_dev *dev);
 186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 190 static int eth_igbvf_link_update(struct e1000_hw *hw);
 191 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 192                                 struct rte_eth_stats *rte_stats);
 193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 194                                 struct rte_eth_xstat *xstats, unsigned n);
 195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 196                                       struct rte_eth_xstat_name *xstats_names,
 197                                       unsigned limit);
 198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 200                 uint16_t vlan_id, int on);
 201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 204                 struct ether_addr *addr);
 205 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 206 static int igbvf_get_regs(struct rte_eth_dev *dev,
 207                 struct rte_dev_reg_info *regs);
 208
 209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 210                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 211                                    uint16_t reta_size);
 212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 213                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 214                                   uint16_t reta_size);
 215
 216 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 217                         struct rte_eth_syn_filter *filter);
 218 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 219                         enum rte_filter_op filter_op,
 220                         void *arg);
 221 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 222                         struct rte_eth_ntuple_filter *ntuple_filter);
 223 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 224                         struct rte_eth_ntuple_filter *ntuple_filter);
 225 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 226                         struct rte_eth_flex_filter *filter);
 227 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 228                         enum rte_filter_op filter_op,
 229                         void *arg);
 230 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 231                         struct rte_eth_ntuple_filter *ntuple_filter);
 232 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 233                         struct rte_eth_ntuple_filter *ntuple_filter);
 234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 235                         struct rte_eth_ntuple_filter *filter);
 236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 237                                 enum rte_filter_op filter_op,
 238                                 void *arg);
 239 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 240                                 enum rte_filter_op filter_op,
 241                                 void *arg);
 242 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 243                         struct rte_eth_ethertype_filter *filter);
 244 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 245                      enum rte_filter_type filter_type,
 246                      enum rte_filter_op filter_op,
 247                      void *arg);
 248 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 249 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 250                 struct rte_dev_reg_info *regs);
 251 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 252 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 253                 struct rte_dev_eeprom_info *eeprom);
 254 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 255                 struct rte_dev_eeprom_info *eeprom);
 256 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 257                                     struct ether_addr *mc_addr_set,
 258                                     uint32_t nb_mc_addr);
 259 static int igb_timesync_enable(struct rte_eth_dev *dev);
 260 static int igb_timesync_disable(struct rte_eth_dev *dev);
 261 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 262                                           struct timespec *timestamp,
 263                                           uint32_t flags);
 264 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 265                                           struct timespec *timestamp);
 266 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 267 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 268                                   struct timespec *timestamp);
 269 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 270                                    const struct timespec *timestamp);
 271 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 272                                         uint16_t queue_id);
 273 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 274                                          uint16_t queue_id);
 275 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 276                                        uint8_t queue, uint8_t msix_vector);
 277 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 278                                uint8_t index, uint8_t offset);
 279 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 280 static void eth_igbvf_interrupt_handler(void *param);
 281 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 282 static int igb_filter_restore(struct rte_eth_dev *dev);
 283
 284 /*
 285  * Define VF Stats MACRO for Non "cleared on read" register
 286  */
 287 #define UPDATE_VF_STAT(reg, last, cur)            \
 288 {                                                 \
 289         u32 latest = E1000_READ_REG(hw, reg);     \
 290         cur += (latest - last) & UINT_MAX;        \
 291         last = latest;                            \
 292 }
 293
 294 #define IGB_FC_PAUSE_TIME 0x0680
 295 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 296 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 297
 298 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 299
 300 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 301
 302 /*
 303  * The set of PCI devices this driver supports
 304  */
 305 static const struct rte_pci_id pci_id_igb_map[] = {
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 314
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 318
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 325
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 345         { .vendor_id = 0, /* sentinel */ },
 346 };
 347
 348 /*
 349  * The set of PCI devices this driver supports (for 82576&I350 VF)
 350  */
 351 static const struct rte_pci_id pci_id_igbvf_map[] = {
 352         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 353         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 354         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 356         { .vendor_id = 0, /* sentinel */ },
 357 };
 358
 359 static const struct rte_eth_desc_lim rx_desc_lim = {
 360         .nb_max = E1000_MAX_RING_DESC,
 361         .nb_min = E1000_MIN_RING_DESC,
 362         .nb_align = IGB_RXD_ALIGN,
 363 };
 364
 365 static const struct rte_eth_desc_lim tx_desc_lim = {
 366         .nb_max = E1000_MAX_RING_DESC,
 367         .nb_min = E1000_MIN_RING_DESC,
 368         .nb_align = IGB_RXD_ALIGN,
 369         .nb_seg_max = IGB_TX_MAX_SEG,
 370         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 371 };
 372
 373 static const struct eth_dev_ops eth_igb_ops = {
 374         .dev_configure        = eth_igb_configure,
 375         .dev_start            = eth_igb_start,
 376         .dev_stop             = eth_igb_stop,
 377         .dev_set_link_up      = eth_igb_dev_set_link_up,
 378         .dev_set_link_down    = eth_igb_dev_set_link_down,
 379         .dev_close            = eth_igb_close,
 380         .promiscuous_enable   = eth_igb_promiscuous_enable,
 381         .promiscuous_disable  = eth_igb_promiscuous_disable,
 382         .allmulticast_enable  = eth_igb_allmulticast_enable,
 383         .allmulticast_disable = eth_igb_allmulticast_disable,
 384         .link_update          = eth_igb_link_update,
 385         .stats_get            = eth_igb_stats_get,
 386         .xstats_get           = eth_igb_xstats_get,
 387         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 388         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 389         .xstats_get_names     = eth_igb_xstats_get_names,
 390         .stats_reset          = eth_igb_stats_reset,
 391         .xstats_reset         = eth_igb_xstats_reset,
 392         .fw_version_get       = eth_igb_fw_version_get,
 393         .dev_infos_get        = eth_igb_infos_get,
 394         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 395         .mtu_set              = eth_igb_mtu_set,
 396         .vlan_filter_set      = eth_igb_vlan_filter_set,
 397         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 398         .vlan_offload_set     = eth_igb_vlan_offload_set,
 399         .rx_queue_setup       = eth_igb_rx_queue_setup,
 400         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 401         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 402         .rx_queue_release     = eth_igb_rx_queue_release,
 403         .rx_queue_count       = eth_igb_rx_queue_count,
 404         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 405         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 406         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 407         .tx_queue_setup       = eth_igb_tx_queue_setup,
 408         .tx_queue_release     = eth_igb_tx_queue_release,
 409         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 410         .dev_led_on           = eth_igb_led_on,
 411         .dev_led_off          = eth_igb_led_off,
 412         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 413         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 414         .mac_addr_add         = eth_igb_rar_set,
 415         .mac_addr_remove      = eth_igb_rar_clear,
 416         .mac_addr_set         = eth_igb_default_mac_addr_set,
 417         .reta_update          = eth_igb_rss_reta_update,
 418         .reta_query           = eth_igb_rss_reta_query,
 419         .rss_hash_update      = eth_igb_rss_hash_update,
 420         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 421         .filter_ctrl          = eth_igb_filter_ctrl,
 422         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 423         .rxq_info_get         = igb_rxq_info_get,
 424         .txq_info_get         = igb_txq_info_get,
 425         .timesync_enable      = igb_timesync_enable,
 426         .timesync_disable     = igb_timesync_disable,
 427         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 428         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 429         .get_reg              = eth_igb_get_regs,
 430         .get_eeprom_length    = eth_igb_get_eeprom_length,
 431         .get_eeprom           = eth_igb_get_eeprom,
 432         .set_eeprom           = eth_igb_set_eeprom,
 433         .timesync_adjust_time = igb_timesync_adjust_time,
 434         .timesync_read_time   = igb_timesync_read_time,
 435         .timesync_write_time  = igb_timesync_write_time,
 436 };
 437
 438 /*
 439  * dev_ops for virtual function, bare necessities for basic vf
 440  * operation have been implemented
 441  */
 442 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 443         .dev_configure        = igbvf_dev_configure,
 444         .dev_start            = igbvf_dev_start,
 445         .dev_stop             = igbvf_dev_stop,
 446         .dev_close            = igbvf_dev_close,
 447         .promiscuous_enable   = igbvf_promiscuous_enable,
 448         .promiscuous_disable  = igbvf_promiscuous_disable,
 449         .allmulticast_enable  = igbvf_allmulticast_enable,
 450         .allmulticast_disable = igbvf_allmulticast_disable,
 451         .link_update          = eth_igb_link_update,
 452         .stats_get            = eth_igbvf_stats_get,
 453         .xstats_get           = eth_igbvf_xstats_get,
 454         .xstats_get_names     = eth_igbvf_xstats_get_names,
 455         .stats_reset          = eth_igbvf_stats_reset,
 456         .xstats_reset         = eth_igbvf_stats_reset,
 457         .vlan_filter_set      = igbvf_vlan_filter_set,
 458         .dev_infos_get        = eth_igbvf_infos_get,
 459         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 460         .rx_queue_setup       = eth_igb_rx_queue_setup,
 461         .rx_queue_release     = eth_igb_rx_queue_release,
 462         .tx_queue_setup       = eth_igb_tx_queue_setup,
 463         .tx_queue_release     = eth_igb_tx_queue_release,
 464         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 465         .rxq_info_get         = igb_rxq_info_get,
 466         .txq_info_get         = igb_txq_info_get,
 467         .mac_addr_set         = igbvf_default_mac_addr_set,
 468         .get_reg              = igbvf_get_regs,
 469 };
 470
 471 /* store statistics names and its offset in stats structure */
 472 struct rte_igb_xstats_name_off {
 473         char name[RTE_ETH_XSTATS_NAME_SIZE];
 474         unsigned offset;
 475 };
 476
 477 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 478         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 479         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 480         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 481         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 482         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 483         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 484         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 485                 ecol)},
 486         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 487         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 488         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 489         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 490         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 491         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 492         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 493         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 494         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 495         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 496         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 497                 fcruc)},
 498         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 499         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 500         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 501         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 502         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 503                 prc1023)},
 504         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 505                 prc1522)},
 506         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 507         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 508         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 509         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 510         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 511         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 512         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 513         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 514         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 515         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 516         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 517         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 518         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 519         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 520         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 521         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 522         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 523         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 524                 ptc1023)},
 525         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 526                 ptc1522)},
 527         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 528         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 529         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 530         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 531         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 532         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 533         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 534
 535         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 536 };
 537
 538 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 539                 sizeof(rte_igb_stats_strings[0]))
 540
 541 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 542         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 543         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 544         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 545         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 546         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 547 };
 548
 549 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 550                 sizeof(rte_igbvf_stats_strings[0]))
 551
 552 /**
 553  * Atomically reads the link status information from global
 554  * structure rte_eth_dev.
 555  *
 556  * @param dev
 557  *   - Pointer to the structure rte_eth_dev to read from.
 558  *   - Pointer to the buffer to be saved with the link status.
 559  *
 560  * @return
 561  *   - On success, zero.
 562  *   - On failure, negative value.
 563  */
 564 static inline int
 565 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 566                                 struct rte_eth_link *link)
 567 {
 568         struct rte_eth_link *dst = link;
 569         struct rte_eth_link *src = &(dev->data->dev_link);
 570
 571         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 572                                         *(uint64_t *)src) == 0)
 573                 return -1;
 574
 575         return 0;
 576 }
 577
 578 /**
 579  * Atomically writes the link status information into global
 580  * structure rte_eth_dev.
 581  *
 582  * @param dev
 583  *   - Pointer to the structure rte_eth_dev to read from.
 584  *   - Pointer to the buffer to be saved with the link status.
 585  *
 586  * @return
 587  *   - On success, zero.
 588  *   - On failure, negative value.
 589  */
 590 static inline int
 591 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 592                                 struct rte_eth_link *link)
 593 {
 594         struct rte_eth_link *dst = &(dev->data->dev_link);
 595         struct rte_eth_link *src = link;
 596
 597         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 598                                         *(uint64_t *)src) == 0)
 599                 return -1;
 600
 601         return 0;
 602 }
 603
 604 static inline void
 605 igb_intr_enable(struct rte_eth_dev *dev)
 606 {
 607         struct e1000_interrupt *intr =
 608                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 609         struct e1000_hw *hw =
 610                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 611
 612         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 613         E1000_WRITE_FLUSH(hw);
 614 }
 615
 616 static void
 617 igb_intr_disable(struct e1000_hw *hw)
 618 {
 619         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 620         E1000_WRITE_FLUSH(hw);
 621 }
 622
 623 static inline void
 624 igbvf_intr_enable(struct rte_eth_dev *dev)
 625 {
 626         struct e1000_hw *hw =
 627                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 628
 629         /* only for mailbox */
 630         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 631         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 632         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 633         E1000_WRITE_FLUSH(hw);
 634 }
 635
 636 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 637 static void
 638 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 639 {
 640         uint32_t tmp = 0;
 641
 642         /* mailbox */
 643         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 644         tmp |= E1000_VTIVAR_VALID;
 645         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 646 }
 647
 648 static void
 649 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 650 {
 651         struct e1000_hw *hw =
 652                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 653
 654         /* Configure VF other cause ivar */
 655         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 656 }
 657
 658 static inline int32_t
 659 igb_pf_reset_hw(struct e1000_hw *hw)
 660 {
 661         uint32_t ctrl_ext;
 662         int32_t status;
 663
 664         status = e1000_reset_hw(hw);
 665
 666         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 667         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 668         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 669         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 670         E1000_WRITE_FLUSH(hw);
 671
 672         return status;
 673 }
 674
 675 static void
 676 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 677 {
 678         struct e1000_hw *hw =
 679                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 680
 681
 682         hw->vendor_id = pci_dev->id.vendor_id;
 683         hw->device_id = pci_dev->id.device_id;
 684         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 685         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 686
 687         e1000_set_mac_type(hw);
 688
 689         /* need to check if it is a vf device below */
 690 }
 691
 692 static int
 693 igb_reset_swfw_lock(struct e1000_hw *hw)
 694 {
 695         int ret_val;
 696
 697         /*
 698          * Do mac ops initialization manually here, since we will need
 699          * some function pointers set by this call.
 700          */
 701         ret_val = e1000_init_mac_params(hw);
 702         if (ret_val)
 703                 return ret_val;
 704
 705         /*
 706          * SMBI lock should not fail in this early stage. If this is the case,
 707          * it is due to an improper exit of the application.
 708          * So force the release of the faulty lock.
 709          */
 710         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 711                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 712         }
 713         e1000_put_hw_semaphore_generic(hw);
 714
 715         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 716                 uint16_t mask;
 717
 718                 /*
 719                  * Phy lock should not fail in this early stage. If this is the case,
 720                  * it is due to an improper exit of the application.
 721                  * So force the release of the faulty lock.
 722                  */
 723                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 724                 if (hw->bus.func > E1000_FUNC_1)
 725                         mask <<= 2;
 726                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 727                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 728                                     hw->bus.func);
 729                 }
 730                 hw->mac.ops.release_swfw_sync(hw, mask);
 731
 732                 /*
 733                  * This one is more tricky since it is common to all ports; but
 734                  * swfw_sync retries last long enough (1s) to be almost sure that if
 735                  * lock can not be taken it is due to an improper lock of the
 736                  * semaphore.
 737                  */
 738                 mask = E1000_SWFW_EEP_SM;
 739                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 740                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 741                 }
 742                 hw->mac.ops.release_swfw_sync(hw, mask);
 743         }
 744
 745         return E1000_SUCCESS;
 746 }
 747
 748 /* Remove all ntuple filters of the device */
 749 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 750 {
 751         struct e1000_filter_info *filter_info =
 752                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 753         struct e1000_5tuple_filter *p_5tuple;
 754         struct e1000_2tuple_filter *p_2tuple;
 755
 756         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 757                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 758                         p_5tuple, entries);
 759                         rte_free(p_5tuple);
 760         }
 761         filter_info->fivetuple_mask = 0;
 762         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 763                 TAILQ_REMOVE(&filter_info->twotuple_list,
 764                         p_2tuple, entries);
 765                         rte_free(p_2tuple);
 766         }
 767         filter_info->twotuple_mask = 0;
 768
 769         return 0;
 770 }
 771
 772 /* Remove all flex filters of the device */
 773 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 774 {
 775         struct e1000_filter_info *filter_info =
 776                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 777         struct e1000_flex_filter *p_flex;
 778
 779         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 780                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 781                 rte_free(p_flex);
 782         }
 783         filter_info->flex_mask = 0;
 784
 785         return 0;
 786 }
 787
 788 static int
 789 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 790 {
 791         int error = 0;
 792         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 793         struct e1000_hw *hw =
 794                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 795         struct e1000_vfta * shadow_vfta =
 796                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 797         struct e1000_filter_info *filter_info =
 798                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 799         struct e1000_adapter *adapter =
 800                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 801
 802         uint32_t ctrl_ext;
 803
 804         eth_dev->dev_ops = &eth_igb_ops;
 805         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 806         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 807         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 808
 809         /* for secondary processes, we don't initialise any further as primary
 810          * has already done this work. Only check we don't need a different
 811          * RX function */
 812         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 813                 if (eth_dev->data->scattered_rx)
 814                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 815                 return 0;
 816         }
 817
 818         rte_eth_copy_pci_info(eth_dev, pci_dev);
 819         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 820
 821         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 822
 823         igb_identify_hardware(eth_dev, pci_dev);
 824         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 825                 error = -EIO;
 826                 goto err_late;
 827         }
 828
 829         e1000_get_bus_info(hw);
 830
 831         /* Reset any pending lock */
 832         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 833                 error = -EIO;
 834                 goto err_late;
 835         }
 836
 837         /* Finish initialization */
 838         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 839                 error = -EIO;
 840                 goto err_late;
 841         }
 842
 843         hw->mac.autoneg = 1;
 844         hw->phy.autoneg_wait_to_complete = 0;
 845         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 846
 847         /* Copper options */
 848         if (hw->phy.media_type == e1000_media_type_copper) {
 849                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 850                 hw->phy.disable_polarity_correction = 0;
 851                 hw->phy.ms_type = e1000_ms_hw_default;
 852         }
 853
 854         /*
 855          * Start from a known state, this is important in reading the nvm
 856          * and mac from that.
 857          */
 858         igb_pf_reset_hw(hw);
 859
 860         /* Make sure we have a good EEPROM before we read from it */
 861         if (e1000_validate_nvm_checksum(hw) < 0) {
 862                 /*
 863                  * Some PCI-E parts fail the first check due to
 864                  * the link being in sleep state, call it again,
 865                  * if it fails a second time its a real issue.
 866                  */
 867                 if (e1000_validate_nvm_checksum(hw) < 0) {
 868                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 869                         error = -EIO;
 870                         goto err_late;
 871                 }
 872         }
 873
 874         /* Read the permanent MAC address out of the EEPROM */
 875         if (e1000_read_mac_addr(hw) != 0) {
 876                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 877                 error = -EIO;
 878                 goto err_late;
 879         }
 880
 881         /* Allocate memory for storing MAC addresses */
 882         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 883                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 884         if (eth_dev->data->mac_addrs == NULL) {
 885                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 886                                                 "store MAC addresses",
 887                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 888                 error = -ENOMEM;
 889                 goto err_late;
 890         }
 891
 892         /* Copy the permanent MAC address */
 893         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 894
 895         /* initialize the vfta */
 896         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 897
 898         /* Now initialize the hardware */
 899         if (igb_hardware_init(hw) != 0) {
 900                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 901                 rte_free(eth_dev->data->mac_addrs);
 902                 eth_dev->data->mac_addrs = NULL;
 903                 error = -ENODEV;
 904                 goto err_late;
 905         }
 906         hw->mac.get_link_status = 1;
 907         adapter->stopped = 0;
 908
 909         /* Indicate SOL/IDER usage */
 910         if (e1000_check_reset_block(hw) < 0) {
 911                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 912                                         "SOL/IDER session");
 913         }
 914
 915         /* initialize PF if max_vfs not zero */
 916         igb_pf_host_init(eth_dev);
 917
 918         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 919         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 920         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 921         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 922         E1000_WRITE_FLUSH(hw);
 923
 924         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 925                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 926                      pci_dev->id.device_id);
 927
 928         rte_intr_callback_register(&pci_dev->intr_handle,
 929                                    eth_igb_interrupt_handler,
 930                                    (void *)eth_dev);
 931
 932         /* enable uio/vfio intr/eventfd mapping */
 933         rte_intr_enable(&pci_dev->intr_handle);
 934
 935         /* enable support intr */
 936         igb_intr_enable(eth_dev);
 937
 938         /* initialize filter info */
 939         memset(filter_info, 0,
 940                sizeof(struct e1000_filter_info));
 941
 942         TAILQ_INIT(&filter_info->flex_list);
 943         TAILQ_INIT(&filter_info->twotuple_list);
 944         TAILQ_INIT(&filter_info->fivetuple_list);
 945
 946         TAILQ_INIT(&igb_filter_ntuple_list);
 947         TAILQ_INIT(&igb_filter_ethertype_list);
 948         TAILQ_INIT(&igb_filter_syn_list);
 949         TAILQ_INIT(&igb_filter_flex_list);
 950         TAILQ_INIT(&igb_flow_list);
 951
 952         return 0;
 953
 954 err_late:
 955         igb_hw_control_release(hw);
 956
 957         return error;
 958 }
 959
 960 static int
 961 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 962 {
 963         struct rte_pci_device *pci_dev;
 964         struct rte_intr_handle *intr_handle;
 965         struct e1000_hw *hw;
 966         struct e1000_adapter *adapter =
 967                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 968         struct e1000_filter_info *filter_info =
 969                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 970
 971         PMD_INIT_FUNC_TRACE();
 972
 973         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 974                 return -EPERM;
 975
 976         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 977         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 978         intr_handle = &pci_dev->intr_handle;
 979
 980         if (adapter->stopped == 0)
 981                 eth_igb_close(eth_dev);
 982
 983         eth_dev->dev_ops = NULL;
 984         eth_dev->rx_pkt_burst = NULL;
 985         eth_dev->tx_pkt_burst = NULL;
 986
 987         /* Reset any pending lock */
 988         igb_reset_swfw_lock(hw);
 989
 990         rte_free(eth_dev->data->mac_addrs);
 991         eth_dev->data->mac_addrs = NULL;
 992
 993         /* uninitialize PF if max_vfs not zero */
 994         igb_pf_host_uninit(eth_dev);
 995
 996         /* disable uio intr before callback unregister */
 997         rte_intr_disable(intr_handle);
 998         rte_intr_callback_unregister(intr_handle,
 999                                      eth_igb_interrupt_handler, eth_dev);
1000
1001         /* clear the SYN filter info */
1002         filter_info->syn_info = 0;
1003
1004         /* clear the ethertype filters info */
1005         filter_info->ethertype_mask = 0;
1006         memset(filter_info->ethertype_filters, 0,
1007                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1008
1009         /* remove all ntuple filters of the device */
1010         igb_ntuple_filter_uninit(eth_dev);
1011
1012         /* remove all flex filters of the device */
1013         igb_flex_filter_uninit(eth_dev);
1014
1015         /* clear all the filters list */
1016         igb_filterlist_flush(eth_dev);
1017
1018         return 0;
1019 }
1020
1021 /*
1022  * Virtual Function device init
1023  */
1024 static int
1025 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
1026 {
1027         struct rte_pci_device *pci_dev;
1028         struct rte_intr_handle *intr_handle;
1029         struct e1000_adapter *adapter =
1030                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1031         struct e1000_hw *hw =
1032                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1033         int diag;
1034         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
1035
1036         PMD_INIT_FUNC_TRACE();
1037
1038         eth_dev->dev_ops = &igbvf_eth_dev_ops;
1039         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
1040         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
1041         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
1042
1043         /* for secondary processes, we don't initialise any further as primary
1044          * has already done this work. Only check we don't need a different
1045          * RX function */
1046         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1047                 if (eth_dev->data->scattered_rx)
1048                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
1049                 return 0;
1050         }
1051
1052         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1053         rte_eth_copy_pci_info(eth_dev, pci_dev);
1054         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1055
1056         hw->device_id = pci_dev->id.device_id;
1057         hw->vendor_id = pci_dev->id.vendor_id;
1058         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1059         adapter->stopped = 0;
1060
1061         /* Initialize the shared code (base driver) */
1062         diag = e1000_setup_init_funcs(hw, TRUE);
1063         if (diag != 0) {
1064                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1065                         diag);
1066                 return -EIO;
1067         }
1068
1069         /* init_mailbox_params */
1070         hw->mbx.ops.init_params(hw);
1071
1072         /* Disable the interrupts for VF */
1073         igbvf_intr_disable(hw);
1074
1075         diag = hw->mac.ops.reset_hw(hw);
1076
1077         /* Allocate memory for storing MAC addresses */
1078         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1079                 hw->mac.rar_entry_count, 0);
1080         if (eth_dev->data->mac_addrs == NULL) {
1081                 PMD_INIT_LOG(ERR,
1082                         "Failed to allocate %d bytes needed to store MAC "
1083                         "addresses",
1084                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1085                 return -ENOMEM;
1086         }
1087
1088         /* Generate a random MAC address, if none was assigned by PF. */
1089         if (is_zero_ether_addr(perm_addr)) {
1090                 eth_random_addr(perm_addr->addr_bytes);
1091                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1092                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1093                              "%02x:%02x:%02x:%02x:%02x:%02x",
1094                              perm_addr->addr_bytes[0],
1095                              perm_addr->addr_bytes[1],
1096                              perm_addr->addr_bytes[2],
1097                              perm_addr->addr_bytes[3],
1098                              perm_addr->addr_bytes[4],
1099                              perm_addr->addr_bytes[5]);
1100         }
1101
1102         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1103         if (diag) {
1104                 rte_free(eth_dev->data->mac_addrs);
1105                 eth_dev->data->mac_addrs = NULL;
1106                 return diag;
1107         }
1108         /* Copy the permanent MAC address */
1109         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1110                         &eth_dev->data->mac_addrs[0]);
1111
1112         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1113                      "mac.type=%s",
1114                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1115                      pci_dev->id.device_id, "igb_mac_82576_vf");
1116
1117         intr_handle = &pci_dev->intr_handle;
1118         rte_intr_callback_register(intr_handle,
1119                                    eth_igbvf_interrupt_handler, eth_dev);
1120
1121         return 0;
1122 }
1123
1124 static int
1125 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1126 {
1127         struct e1000_adapter *adapter =
1128                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1129         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1130
1131         PMD_INIT_FUNC_TRACE();
1132
1133         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1134                 return -EPERM;
1135
1136         if (adapter->stopped == 0)
1137                 igbvf_dev_close(eth_dev);
1138
1139         eth_dev->dev_ops = NULL;
1140         eth_dev->rx_pkt_burst = NULL;
1141         eth_dev->tx_pkt_burst = NULL;
1142
1143         rte_free(eth_dev->data->mac_addrs);
1144         eth_dev->data->mac_addrs = NULL;
1145
1146         /* disable uio intr before callback unregister */
1147         rte_intr_disable(&pci_dev->intr_handle);
1148         rte_intr_callback_unregister(&pci_dev->intr_handle,
1149                                      eth_igbvf_interrupt_handler,
1150                                      (void *)eth_dev);
1151
1152         return 0;
1153 }
1154
1155 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1156         struct rte_pci_device *pci_dev)
1157 {
1158         return rte_eth_dev_pci_generic_probe(pci_dev,
1159                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1160 }
1161
1162 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1163 {
1164         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1165 }
1166
1167 static struct rte_pci_driver rte_igb_pmd = {
1168         .id_table = pci_id_igb_map,
1169         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1170         .probe = eth_igb_pci_probe,
1171         .remove = eth_igb_pci_remove,
1172 };
1173
1174
1175 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1176         struct rte_pci_device *pci_dev)
1177 {
1178         return rte_eth_dev_pci_generic_probe(pci_dev,
1179                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1180 }
1181
1182 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1183 {
1184         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1185 }
1186
1187 /*
1188  * virtual function driver struct
1189  */
1190 static struct rte_pci_driver rte_igbvf_pmd = {
1191         .id_table = pci_id_igbvf_map,
1192         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1193         .probe = eth_igbvf_pci_probe,
1194         .remove = eth_igbvf_pci_remove,
1195 };
1196
1197 static void
1198 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1199 {
1200         struct e1000_hw *hw =
1201                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1202         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1203         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1204         rctl |= E1000_RCTL_VFE;
1205         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1206 }
1207
1208 static int
1209 igb_check_mq_mode(struct rte_eth_dev *dev)
1210 {
1211         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1212         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1213         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1214         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1215
1216         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1217             tx_mq_mode == ETH_MQ_TX_DCB ||
1218             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1219                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1220                 return -EINVAL;
1221         }
1222         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1223                 /* Check multi-queue mode.
1224                  * To no break software we accept ETH_MQ_RX_NONE as this might
1225                  * be used to turn off VLAN filter.
1226                  */
1227
1228                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1229                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1230                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1231                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1232                 } else {
1233                         /* Only support one queue on VFs.
1234                          * RSS together with SRIOV is not supported.
1235                          */
1236                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1237                                         " wrong mq_mode rx %d.",
1238                                         rx_mq_mode);
1239                         return -EINVAL;
1240                 }
1241                 /* TX mode is not used here, so mode might be ignored.*/
1242                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1243                         /* SRIOV only works in VMDq enable mode */
1244                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1245                                         " TX mode %d is not supported. "
1246                                         " Driver will behave as %d mode.",
1247                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1248                 }
1249
1250                 /* check valid queue number */
1251                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1252                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1253                                         " only support one queue on VFs.");
1254                         return -EINVAL;
1255                 }
1256         } else {
1257                 /* To no break software that set invalid mode, only display
1258                  * warning if invalid mode is used.
1259                  */
1260                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1261                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1262                     rx_mq_mode != ETH_MQ_RX_RSS) {
1263                         /* RSS together with VMDq not supported*/
1264                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1265                                      rx_mq_mode);
1266                         return -EINVAL;
1267                 }
1268
1269                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1270                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1271                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1272                                         " Due to txmode is meaningless in this"
1273                                         " driver, just ignore.",
1274                                         tx_mq_mode);
1275                 }
1276         }
1277         return 0;
1278 }
1279
1280 static int
1281 eth_igb_configure(struct rte_eth_dev *dev)
1282 {
1283         struct e1000_interrupt *intr =
1284                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1285         int ret;
1286
1287         PMD_INIT_FUNC_TRACE();
1288
1289         /* multipe queue mode checking */
1290         ret  = igb_check_mq_mode(dev);
1291         if (ret != 0) {
1292                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1293                             ret);
1294                 return ret;
1295         }
1296
1297         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1298         PMD_INIT_FUNC_TRACE();
1299
1300         return 0;
1301 }
1302
1303 static int
1304 eth_igb_start(struct rte_eth_dev *dev)
1305 {
1306         struct e1000_hw *hw =
1307                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1308         struct e1000_adapter *adapter =
1309                 E1000_DEV_PRIVATE(dev->data->dev_private);
1310         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1311         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1312         int ret, mask;
1313         uint32_t intr_vector = 0;
1314         uint32_t ctrl_ext;
1315         uint32_t *speeds;
1316         int num_speeds;
1317         bool autoneg;
1318
1319         PMD_INIT_FUNC_TRACE();
1320
1321         /* disable uio/vfio intr/eventfd mapping */
1322         rte_intr_disable(intr_handle);
1323
1324         /* Power up the phy. Needed to make the link go Up */
1325         eth_igb_dev_set_link_up(dev);
1326
1327         /*
1328          * Packet Buffer Allocation (PBA)
1329          * Writing PBA sets the receive portion of the buffer
1330          * the remainder is used for the transmit buffer.
1331          */
1332         if (hw->mac.type == e1000_82575) {
1333                 uint32_t pba;
1334
1335                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1336                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1337         }
1338
1339         /* Put the address into the Receive Address Array */
1340         e1000_rar_set(hw, hw->mac.addr, 0);
1341
1342         /* Initialize the hardware */
1343         if (igb_hardware_init(hw)) {
1344                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1345                 return -EIO;
1346         }
1347         adapter->stopped = 0;
1348
1349         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1350
1351         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1352         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1353         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1354         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1355         E1000_WRITE_FLUSH(hw);
1356
1357         /* configure PF module if SRIOV enabled */
1358         igb_pf_host_configure(dev);
1359
1360         /* check and configure queue intr-vector mapping */
1361         if ((rte_intr_cap_multiple(intr_handle) ||
1362              !RTE_ETH_DEV_SRIOV(dev).active) &&
1363             dev->data->dev_conf.intr_conf.rxq != 0) {
1364                 intr_vector = dev->data->nb_rx_queues;
1365                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1366                         return -1;
1367         }
1368
1369         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1370                 intr_handle->intr_vec =
1371                         rte_zmalloc("intr_vec",
1372                                     dev->data->nb_rx_queues * sizeof(int), 0);
1373                 if (intr_handle->intr_vec == NULL) {
1374                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1375                                      " intr_vec", dev->data->nb_rx_queues);
1376                         return -ENOMEM;
1377                 }
1378         }
1379
1380         /* confiugre msix for rx interrupt */
1381         eth_igb_configure_msix_intr(dev);
1382
1383         /* Configure for OS presence */
1384         igb_init_manageability(hw);
1385
1386         eth_igb_tx_init(dev);
1387
1388         /* This can fail when allocating mbufs for descriptor rings */
1389         ret = eth_igb_rx_init(dev);
1390         if (ret) {
1391                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1392                 igb_dev_clear_queues(dev);
1393                 return ret;
1394         }
1395
1396         e1000_clear_hw_cntrs_base_generic(hw);
1397
1398         /*
1399          * VLAN Offload Settings
1400          */
1401         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1402                         ETH_VLAN_EXTEND_MASK;
1403         eth_igb_vlan_offload_set(dev, mask);
1404
1405         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1406                 /* Enable VLAN filter since VMDq always use VLAN filter */
1407                 igb_vmdq_vlan_hw_filter_enable(dev);
1408         }
1409
1410         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1411                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1412                 (hw->mac.type == e1000_i211)) {
1413                 /* Configure EITR with the maximum possible value (0xFFFF) */
1414                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1415         }
1416
1417         /* Setup link speed and duplex */
1418         speeds = &dev->data->dev_conf.link_speeds;
1419         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1420                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1421                 hw->mac.autoneg = 1;
1422         } else {
1423                 num_speeds = 0;
1424                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1425
1426                 /* Reset */
1427                 hw->phy.autoneg_advertised = 0;
1428
1429                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1430                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1431                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1432                         num_speeds = -1;
1433                         goto error_invalid_config;
1434                 }
1435                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1436                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1437                         num_speeds++;
1438                 }
1439                 if (*speeds & ETH_LINK_SPEED_10M) {
1440                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1441                         num_speeds++;
1442                 }
1443                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1444                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1445                         num_speeds++;
1446                 }
1447                 if (*speeds & ETH_LINK_SPEED_100M) {
1448                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1449                         num_speeds++;
1450                 }
1451                 if (*speeds & ETH_LINK_SPEED_1G) {
1452                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1453                         num_speeds++;
1454                 }
1455                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1456                         goto error_invalid_config;
1457
1458                 /* Set/reset the mac.autoneg based on the link speed,
1459                  * fixed or not
1460                  */
1461                 if (!autoneg) {
1462                         hw->mac.autoneg = 0;
1463                         hw->mac.forced_speed_duplex =
1464                                         hw->phy.autoneg_advertised;
1465                 } else {
1466                         hw->mac.autoneg = 1;
1467                 }
1468         }
1469
1470         e1000_setup_link(hw);
1471
1472         if (rte_intr_allow_others(intr_handle)) {
1473                 /* check if lsc interrupt is enabled */
1474                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1475                         eth_igb_lsc_interrupt_setup(dev);
1476         } else {
1477                 rte_intr_callback_unregister(intr_handle,
1478                                              eth_igb_interrupt_handler,
1479                                              (void *)dev);
1480                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1481                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1482                                      " no intr multiplex");
1483         }
1484
1485         /* check if rxq interrupt is enabled */
1486         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1487             rte_intr_dp_is_en(intr_handle))
1488                 eth_igb_rxq_interrupt_setup(dev);
1489
1490         /* enable uio/vfio intr/eventfd mapping */
1491         rte_intr_enable(intr_handle);
1492
1493         /* resume enabled intr since hw reset */
1494         igb_intr_enable(dev);
1495
1496         /* restore all types filter */
1497         igb_filter_restore(dev);
1498
1499         PMD_INIT_LOG(DEBUG, "<<");
1500
1501         return 0;
1502
1503 error_invalid_config:
1504         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1505                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1506         igb_dev_clear_queues(dev);
1507         return -EINVAL;
1508 }
1509
1510 /*********************************************************************
1511  *
1512  *  This routine disables all traffic on the adapter by issuing a
1513  *  global reset on the MAC.
1514  *
1515  **********************************************************************/
1516 static void
1517 eth_igb_stop(struct rte_eth_dev *dev)
1518 {
1519         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1520         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1521         struct rte_eth_link link;
1522         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1523
1524         igb_intr_disable(hw);
1525
1526         /* disable intr eventfd mapping */
1527         rte_intr_disable(intr_handle);
1528
1529         igb_pf_reset_hw(hw);
1530         E1000_WRITE_REG(hw, E1000_WUC, 0);
1531
1532         /* Set bit for Go Link disconnect */
1533         if (hw->mac.type >= e1000_82580) {
1534                 uint32_t phpm_reg;
1535
1536                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1537                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1538                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1539         }
1540
1541         /* Power down the phy. Needed to make the link go Down */
1542         eth_igb_dev_set_link_down(dev);
1543
1544         igb_dev_clear_queues(dev);
1545
1546         /* clear the recorded link status */
1547         memset(&link, 0, sizeof(link));
1548         rte_igb_dev_atomic_write_link_status(dev, &link);
1549
1550         if (!rte_intr_allow_others(intr_handle))
1551                 /* resume to the default handler */
1552                 rte_intr_callback_register(intr_handle,
1553                                            eth_igb_interrupt_handler,
1554                                            (void *)dev);
1555
1556         /* Clean datapath event and queue/vec mapping */
1557         rte_intr_efd_disable(intr_handle);
1558         if (intr_handle->intr_vec != NULL) {
1559                 rte_free(intr_handle->intr_vec);
1560                 intr_handle->intr_vec = NULL;
1561         }
1562 }
1563
1564 static int
1565 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1566 {
1567         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1568
1569         if (hw->phy.media_type == e1000_media_type_copper)
1570                 e1000_power_up_phy(hw);
1571         else
1572                 e1000_power_up_fiber_serdes_link(hw);
1573
1574         return 0;
1575 }
1576
1577 static int
1578 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1579 {
1580         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1581
1582         if (hw->phy.media_type == e1000_media_type_copper)
1583                 e1000_power_down_phy(hw);
1584         else
1585                 e1000_shutdown_fiber_serdes_link(hw);
1586
1587         return 0;
1588 }
1589
1590 static void
1591 eth_igb_close(struct rte_eth_dev *dev)
1592 {
1593         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1594         struct e1000_adapter *adapter =
1595                 E1000_DEV_PRIVATE(dev->data->dev_private);
1596         struct rte_eth_link link;
1597         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1598         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1599
1600         eth_igb_stop(dev);
1601         adapter->stopped = 1;
1602
1603         e1000_phy_hw_reset(hw);
1604         igb_release_manageability(hw);
1605         igb_hw_control_release(hw);
1606
1607         /* Clear bit for Go Link disconnect */
1608         if (hw->mac.type >= e1000_82580) {
1609                 uint32_t phpm_reg;
1610
1611                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1612                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1613                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1614         }
1615
1616         igb_dev_free_queues(dev);
1617
1618         if (intr_handle->intr_vec) {
1619                 rte_free(intr_handle->intr_vec);
1620                 intr_handle->intr_vec = NULL;
1621         }
1622
1623         memset(&link, 0, sizeof(link));
1624         rte_igb_dev_atomic_write_link_status(dev, &link);
1625 }
1626
1627 static int
1628 igb_get_rx_buffer_size(struct e1000_hw *hw)
1629 {
1630         uint32_t rx_buf_size;
1631         if (hw->mac.type == e1000_82576) {
1632                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1633         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1634                 /* PBS needs to be translated according to a lookup table */
1635                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1636                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1637                 rx_buf_size = (rx_buf_size << 10);
1638         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1639                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1640         } else {
1641                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1642         }
1643
1644         return rx_buf_size;
1645 }
1646
1647 /*********************************************************************
1648  *
1649  *  Initialize the hardware
1650  *
1651  **********************************************************************/
1652 static int
1653 igb_hardware_init(struct e1000_hw *hw)
1654 {
1655         uint32_t rx_buf_size;
1656         int diag;
1657
1658         /* Let the firmware know the OS is in control */
1659         igb_hw_control_acquire(hw);
1660
1661         /*
1662          * These parameters control the automatic generation (Tx) and
1663          * response (Rx) to Ethernet PAUSE frames.
1664          * - High water mark should allow for at least two standard size (1518)
1665          *   frames to be received after sending an XOFF.
1666          * - Low water mark works best when it is very near the high water mark.
1667          *   This allows the receiver to restart by sending XON when it has
1668          *   drained a bit. Here we use an arbitrary value of 1500 which will
1669          *   restart after one full frame is pulled from the buffer. There
1670          *   could be several smaller frames in the buffer and if so they will
1671          *   not trigger the XON until their total number reduces the buffer
1672          *   by 1500.
1673          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1674          */
1675         rx_buf_size = igb_get_rx_buffer_size(hw);
1676
1677         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1678         hw->fc.low_water = hw->fc.high_water - 1500;
1679         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1680         hw->fc.send_xon = 1;
1681
1682         /* Set Flow control, use the tunable location if sane */
1683         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1684                 hw->fc.requested_mode = igb_fc_setting;
1685         else
1686                 hw->fc.requested_mode = e1000_fc_none;
1687
1688         /* Issue a global reset */
1689         igb_pf_reset_hw(hw);
1690         E1000_WRITE_REG(hw, E1000_WUC, 0);
1691
1692         diag = e1000_init_hw(hw);
1693         if (diag < 0)
1694                 return diag;
1695
1696         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1697         e1000_get_phy_info(hw);
1698         e1000_check_for_link(hw);
1699
1700         return 0;
1701 }
1702
1703 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1704 static void
1705 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1706 {
1707         int pause_frames;
1708
1709         uint64_t old_gprc  = stats->gprc;
1710         uint64_t old_gptc  = stats->gptc;
1711         uint64_t old_tpr   = stats->tpr;
1712         uint64_t old_tpt   = stats->tpt;
1713         uint64_t old_rpthc = stats->rpthc;
1714         uint64_t old_hgptc = stats->hgptc;
1715
1716         if(hw->phy.media_type == e1000_media_type_copper ||
1717             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1718                 stats->symerrs +=
1719                     E1000_READ_REG(hw,E1000_SYMERRS);
1720                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1721         }
1722
1723         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1724         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1725         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1726         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1727
1728         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1729         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1730         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1731         stats->dc += E1000_READ_REG(hw, E1000_DC);
1732         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1733         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1734         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1735         /*
1736         ** For watchdog management we need to know if we have been
1737         ** paused during the last interval, so capture that here.
1738         */
1739         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1740         stats->xoffrxc += pause_frames;
1741         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1742         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1743         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1744         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1745         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1746         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1747         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1748         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1749         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1750         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1751         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1752         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1753
1754         /* For the 64-bit byte counters the low dword must be read first. */
1755         /* Both registers clear on the read of the high dword */
1756
1757         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1758         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1759         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1760         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1761         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1762         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1763         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1764
1765         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1766         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1767         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1768         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1769         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1770
1771         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1772         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1773
1774         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1775         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1776         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1777         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1778         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1779         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1780
1781         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1782         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1783         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1784         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1785         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1786         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1787         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1788         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1789
1790         /* Interrupt Counts */
1791
1792         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1793         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1794         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1795         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1796         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1797         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1798         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1799         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1800         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1801
1802         /* Host to Card Statistics */
1803
1804         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1805         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1806         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1807         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1808         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1809         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1810         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1811         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1812         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1813         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1814         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1815         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1816         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1817         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1818         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1819         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1820
1821         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1822         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1823         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1824         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1825         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1826         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1827 }
1828
1829 static void
1830 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1831 {
1832         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833         struct e1000_hw_stats *stats =
1834                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1835
1836         igb_read_stats_registers(hw, stats);
1837
1838         if (rte_stats == NULL)
1839                 return;
1840
1841         /* Rx Errors */
1842         rte_stats->imissed = stats->mpc;
1843         rte_stats->ierrors = stats->crcerrs +
1844                              stats->rlec + stats->ruc + stats->roc +
1845                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1846
1847         /* Tx Errors */
1848         rte_stats->oerrors = stats->ecol + stats->latecol;
1849
1850         rte_stats->ipackets = stats->gprc;
1851         rte_stats->opackets = stats->gptc;
1852         rte_stats->ibytes   = stats->gorc;
1853         rte_stats->obytes   = stats->gotc;
1854 }
1855
1856 static void
1857 eth_igb_stats_reset(struct rte_eth_dev *dev)
1858 {
1859         struct e1000_hw_stats *hw_stats =
1860                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1861
1862         /* HW registers are cleared on read */
1863         eth_igb_stats_get(dev, NULL);
1864
1865         /* Reset software totals */
1866         memset(hw_stats, 0, sizeof(*hw_stats));
1867 }
1868
1869 static void
1870 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1871 {
1872         struct e1000_hw_stats *stats =
1873                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1874
1875         /* HW registers are cleared on read */
1876         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1877
1878         /* Reset software totals */
1879         memset(stats, 0, sizeof(*stats));
1880 }
1881
1882 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1883         struct rte_eth_xstat_name *xstats_names,
1884         __rte_unused unsigned int size)
1885 {
1886         unsigned i;
1887
1888         if (xstats_names == NULL)
1889                 return IGB_NB_XSTATS;
1890
1891         /* Note: limit checked in rte_eth_xstats_names() */
1892
1893         for (i = 0; i < IGB_NB_XSTATS; i++) {
1894                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1895                          "%s", rte_igb_stats_strings[i].name);
1896         }
1897
1898         return IGB_NB_XSTATS;
1899 }
1900
1901 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1902                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1903                 unsigned int limit)
1904 {
1905         unsigned int i;
1906
1907         if (!ids) {
1908                 if (xstats_names == NULL)
1909                         return IGB_NB_XSTATS;
1910
1911                 for (i = 0; i < IGB_NB_XSTATS; i++)
1912                         snprintf(xstats_names[i].name,
1913                                         sizeof(xstats_names[i].name),
1914                                         "%s", rte_igb_stats_strings[i].name);
1915
1916                 return IGB_NB_XSTATS;
1917
1918         } else {
1919                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1920
1921                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1922                                 IGB_NB_XSTATS);
1923
1924                 for (i = 0; i < limit; i++) {
1925                         if (ids[i] >= IGB_NB_XSTATS) {
1926                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1927                                 return -1;
1928                         }
1929                         strcpy(xstats_names[i].name,
1930                                         xstats_names_copy[ids[i]].name);
1931                 }
1932                 return limit;
1933         }
1934 }
1935
1936 static int
1937 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1938                    unsigned n)
1939 {
1940         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941         struct e1000_hw_stats *hw_stats =
1942                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1943         unsigned i;
1944
1945         if (n < IGB_NB_XSTATS)
1946                 return IGB_NB_XSTATS;
1947
1948         igb_read_stats_registers(hw, hw_stats);
1949
1950         /* If this is a reset xstats is NULL, and we have cleared the
1951          * registers by reading them.
1952          */
1953         if (!xstats)
1954                 return 0;
1955
1956         /* Extended stats */
1957         for (i = 0; i < IGB_NB_XSTATS; i++) {
1958                 xstats[i].id = i;
1959                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1960                         rte_igb_stats_strings[i].offset);
1961         }
1962
1963         return IGB_NB_XSTATS;
1964 }
1965
1966 static int
1967 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1968                 uint64_t *values, unsigned int n)
1969 {
1970         unsigned int i;
1971
1972         if (!ids) {
1973                 struct e1000_hw *hw =
1974                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1975                 struct e1000_hw_stats *hw_stats =
1976                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1977
1978                 if (n < IGB_NB_XSTATS)
1979                         return IGB_NB_XSTATS;
1980
1981                 igb_read_stats_registers(hw, hw_stats);
1982
1983                 /* If this is a reset xstats is NULL, and we have cleared the
1984                  * registers by reading them.
1985                  */
1986                 if (!values)
1987                         return 0;
1988
1989                 /* Extended stats */
1990                 for (i = 0; i < IGB_NB_XSTATS; i++)
1991                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1992                                         rte_igb_stats_strings[i].offset);
1993
1994                 return IGB_NB_XSTATS;
1995
1996         } else {
1997                 uint64_t values_copy[IGB_NB_XSTATS];
1998
1999                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2000                                 IGB_NB_XSTATS);
2001
2002                 for (i = 0; i < n; i++) {
2003                         if (ids[i] >= IGB_NB_XSTATS) {
2004                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2005                                 return -1;
2006                         }
2007                         values[i] = values_copy[ids[i]];
2008                 }
2009                 return n;
2010         }
2011 }
2012
2013 static void
2014 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2015 {
2016         /* Good Rx packets, include VF loopback */
2017         UPDATE_VF_STAT(E1000_VFGPRC,
2018             hw_stats->last_gprc, hw_stats->gprc);
2019
2020         /* Good Rx octets, include VF loopback */
2021         UPDATE_VF_STAT(E1000_VFGORC,
2022             hw_stats->last_gorc, hw_stats->gorc);
2023
2024         /* Good Tx packets, include VF loopback */
2025         UPDATE_VF_STAT(E1000_VFGPTC,
2026             hw_stats->last_gptc, hw_stats->gptc);
2027
2028         /* Good Tx octets, include VF loopback */
2029         UPDATE_VF_STAT(E1000_VFGOTC,
2030             hw_stats->last_gotc, hw_stats->gotc);
2031
2032         /* Rx Multicst packets */
2033         UPDATE_VF_STAT(E1000_VFMPRC,
2034             hw_stats->last_mprc, hw_stats->mprc);
2035
2036         /* Good Rx loopback packets */
2037         UPDATE_VF_STAT(E1000_VFGPRLBC,
2038             hw_stats->last_gprlbc, hw_stats->gprlbc);
2039
2040         /* Good Rx loopback octets */
2041         UPDATE_VF_STAT(E1000_VFGORLBC,
2042             hw_stats->last_gorlbc, hw_stats->gorlbc);
2043
2044         /* Good Tx loopback packets */
2045         UPDATE_VF_STAT(E1000_VFGPTLBC,
2046             hw_stats->last_gptlbc, hw_stats->gptlbc);
2047
2048         /* Good Tx loopback octets */
2049         UPDATE_VF_STAT(E1000_VFGOTLBC,
2050             hw_stats->last_gotlbc, hw_stats->gotlbc);
2051 }
2052
2053 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2054                                      struct rte_eth_xstat_name *xstats_names,
2055                                      __rte_unused unsigned limit)
2056 {
2057         unsigned i;
2058
2059         if (xstats_names != NULL)
2060                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2061                         snprintf(xstats_names[i].name,
2062                                 sizeof(xstats_names[i].name), "%s",
2063                                 rte_igbvf_stats_strings[i].name);
2064                 }
2065         return IGBVF_NB_XSTATS;
2066 }
2067
2068 static int
2069 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2070                      unsigned n)
2071 {
2072         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2073         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2074                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2075         unsigned i;
2076
2077         if (n < IGBVF_NB_XSTATS)
2078                 return IGBVF_NB_XSTATS;
2079
2080         igbvf_read_stats_registers(hw, hw_stats);
2081
2082         if (!xstats)
2083                 return 0;
2084
2085         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2086                 xstats[i].id = i;
2087                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2088                         rte_igbvf_stats_strings[i].offset);
2089         }
2090
2091         return IGBVF_NB_XSTATS;
2092 }
2093
2094 static void
2095 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2096 {
2097         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2098         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2099                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2100
2101         igbvf_read_stats_registers(hw, hw_stats);
2102
2103         if (rte_stats == NULL)
2104                 return;
2105
2106         rte_stats->ipackets = hw_stats->gprc;
2107         rte_stats->ibytes = hw_stats->gorc;
2108         rte_stats->opackets = hw_stats->gptc;
2109         rte_stats->obytes = hw_stats->gotc;
2110 }
2111
2112 static void
2113 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2114 {
2115         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2116                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2117
2118         /* Sync HW register to the last stats */
2119         eth_igbvf_stats_get(dev, NULL);
2120
2121         /* reset HW current stats*/
2122         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2123                offsetof(struct e1000_vf_stats, gprc));
2124 }
2125
2126 static int
2127 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2128                        size_t fw_size)
2129 {
2130         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2131         struct e1000_fw_version fw;
2132         int ret;
2133
2134         e1000_get_fw_version(hw, &fw);
2135
2136         switch (hw->mac.type) {
2137         case e1000_i210:
2138         case e1000_i211:
2139                 if (!(e1000_get_flash_presence_i210(hw))) {
2140                         ret = snprintf(fw_version, fw_size,
2141                                  "%2d.%2d-%d",
2142                                  fw.invm_major, fw.invm_minor,
2143                                  fw.invm_img_type);
2144                         break;
2145                 }
2146                 /* fall through */
2147         default:
2148                 /* if option rom is valid, display its version too */
2149                 if (fw.or_valid) {
2150                         ret = snprintf(fw_version, fw_size,
2151                                  "%d.%d, 0x%08x, %d.%d.%d",
2152                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2153                                  fw.or_major, fw.or_build, fw.or_patch);
2154                 /* no option rom */
2155                 } else {
2156                         if (fw.etrack_id != 0X0000) {
2157                                 ret = snprintf(fw_version, fw_size,
2158                                          "%d.%d, 0x%08x",
2159                                          fw.eep_major, fw.eep_minor,
2160                                          fw.etrack_id);
2161                         } else {
2162                                 ret = snprintf(fw_version, fw_size,
2163                                          "%d.%d.%d",
2164                                          fw.eep_major, fw.eep_minor,
2165                                          fw.eep_build);
2166                         }
2167                 }
2168                 break;
2169         }
2170
2171         ret += 1; /* add the size of '\0' */
2172         if (fw_size < (u32)ret)
2173                 return ret;
2174         else
2175                 return 0;
2176 }
2177
2178 static void
2179 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2180 {
2181         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2182
2183         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2184         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2185         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2186         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2187         dev_info->rx_offload_capa =
2188                 DEV_RX_OFFLOAD_VLAN_STRIP |
2189                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2190                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2191                 DEV_RX_OFFLOAD_TCP_CKSUM;
2192         dev_info->tx_offload_capa =
2193                 DEV_TX_OFFLOAD_VLAN_INSERT |
2194                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2195                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2196                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2197                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2198                 DEV_TX_OFFLOAD_TCP_TSO;
2199
2200         switch (hw->mac.type) {
2201         case e1000_82575:
2202                 dev_info->max_rx_queues = 4;
2203                 dev_info->max_tx_queues = 4;
2204                 dev_info->max_vmdq_pools = 0;
2205                 break;
2206
2207         case e1000_82576:
2208                 dev_info->max_rx_queues = 16;
2209                 dev_info->max_tx_queues = 16;
2210                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2211                 dev_info->vmdq_queue_num = 16;
2212                 break;
2213
2214         case e1000_82580:
2215                 dev_info->max_rx_queues = 8;
2216                 dev_info->max_tx_queues = 8;
2217                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2218                 dev_info->vmdq_queue_num = 8;
2219                 break;
2220
2221         case e1000_i350:
2222                 dev_info->max_rx_queues = 8;
2223                 dev_info->max_tx_queues = 8;
2224                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2225                 dev_info->vmdq_queue_num = 8;
2226                 break;
2227
2228         case e1000_i354:
2229                 dev_info->max_rx_queues = 8;
2230                 dev_info->max_tx_queues = 8;
2231                 break;
2232
2233         case e1000_i210:
2234                 dev_info->max_rx_queues = 4;
2235                 dev_info->max_tx_queues = 4;
2236                 dev_info->max_vmdq_pools = 0;
2237                 break;
2238
2239         case e1000_i211:
2240                 dev_info->max_rx_queues = 2;
2241                 dev_info->max_tx_queues = 2;
2242                 dev_info->max_vmdq_pools = 0;
2243                 break;
2244
2245         default:
2246                 /* Should not happen */
2247                 break;
2248         }
2249         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2250         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2251         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2252
2253         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2254                 .rx_thresh = {
2255                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2256                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2257                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2258                 },
2259                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2260                 .rx_drop_en = 0,
2261         };
2262
2263         dev_info->default_txconf = (struct rte_eth_txconf) {
2264                 .tx_thresh = {
2265                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2266                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2267                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2268                 },
2269                 .txq_flags = 0,
2270         };
2271
2272         dev_info->rx_desc_lim = rx_desc_lim;
2273         dev_info->tx_desc_lim = tx_desc_lim;
2274
2275         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2276                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2277                         ETH_LINK_SPEED_1G;
2278 }
2279
2280 static const uint32_t *
2281 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2282 {
2283         static const uint32_t ptypes[] = {
2284                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2285                 RTE_PTYPE_L2_ETHER,
2286                 RTE_PTYPE_L3_IPV4,
2287                 RTE_PTYPE_L3_IPV4_EXT,
2288                 RTE_PTYPE_L3_IPV6,
2289                 RTE_PTYPE_L3_IPV6_EXT,
2290                 RTE_PTYPE_L4_TCP,
2291                 RTE_PTYPE_L4_UDP,
2292                 RTE_PTYPE_L4_SCTP,
2293                 RTE_PTYPE_TUNNEL_IP,
2294                 RTE_PTYPE_INNER_L3_IPV6,
2295                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2296                 RTE_PTYPE_INNER_L4_TCP,
2297                 RTE_PTYPE_INNER_L4_UDP,
2298                 RTE_PTYPE_UNKNOWN
2299         };
2300
2301         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2302             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2303                 return ptypes;
2304         return NULL;
2305 }
2306
2307 static void
2308 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2309 {
2310         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2311
2312         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2313         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2314         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2315         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2316         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2317                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2318                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2319                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2320         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2321                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2322                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2323                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2324                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2325                                 DEV_TX_OFFLOAD_TCP_TSO;
2326         switch (hw->mac.type) {
2327         case e1000_vfadapt:
2328                 dev_info->max_rx_queues = 2;
2329                 dev_info->max_tx_queues = 2;
2330                 break;
2331         case e1000_vfadapt_i350:
2332                 dev_info->max_rx_queues = 1;
2333                 dev_info->max_tx_queues = 1;
2334                 break;
2335         default:
2336                 /* Should not happen */
2337                 break;
2338         }
2339
2340         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2341                 .rx_thresh = {
2342                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2343                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2344                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2345                 },
2346                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2347                 .rx_drop_en = 0,
2348         };
2349
2350         dev_info->default_txconf = (struct rte_eth_txconf) {
2351                 .tx_thresh = {
2352                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2353                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2354                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2355                 },
2356                 .txq_flags = 0,
2357         };
2358
2359         dev_info->rx_desc_lim = rx_desc_lim;
2360         dev_info->tx_desc_lim = tx_desc_lim;
2361 }
2362
2363 /* return 0 means link status changed, -1 means not changed */
2364 static int
2365 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2366 {
2367         struct e1000_hw *hw =
2368                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2369         struct rte_eth_link link, old;
2370         int link_check, count;
2371
2372         link_check = 0;
2373         hw->mac.get_link_status = 1;
2374
2375         /* possible wait-to-complete in up to 9 seconds */
2376         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2377                 /* Read the real link status */
2378                 switch (hw->phy.media_type) {
2379                 case e1000_media_type_copper:
2380                         /* Do the work to read phy */
2381                         e1000_check_for_link(hw);
2382                         link_check = !hw->mac.get_link_status;
2383                         break;
2384
2385                 case e1000_media_type_fiber:
2386                         e1000_check_for_link(hw);
2387                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2388                                       E1000_STATUS_LU);
2389                         break;
2390
2391                 case e1000_media_type_internal_serdes:
2392                         e1000_check_for_link(hw);
2393                         link_check = hw->mac.serdes_has_link;
2394                         break;
2395
2396                 /* VF device is type_unknown */
2397                 case e1000_media_type_unknown:
2398                         eth_igbvf_link_update(hw);
2399                         link_check = !hw->mac.get_link_status;
2400                         break;
2401
2402                 default:
2403                         break;
2404                 }
2405                 if (link_check || wait_to_complete == 0)
2406                         break;
2407                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2408         }
2409         memset(&link, 0, sizeof(link));
2410         rte_igb_dev_atomic_read_link_status(dev, &link);
2411         old = link;
2412
2413         /* Now we check if a transition has happened */
2414         if (link_check) {
2415                 uint16_t duplex, speed;
2416                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2417                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2418                                 ETH_LINK_FULL_DUPLEX :
2419                                 ETH_LINK_HALF_DUPLEX;
2420                 link.link_speed = speed;
2421                 link.link_status = ETH_LINK_UP;
2422                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2423                                 ETH_LINK_SPEED_FIXED);
2424         } else if (!link_check) {
2425                 link.link_speed = 0;
2426                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2427                 link.link_status = ETH_LINK_DOWN;
2428                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2429         }
2430         rte_igb_dev_atomic_write_link_status(dev, &link);
2431
2432         /* not changed */
2433         if (old.link_status == link.link_status)
2434                 return -1;
2435
2436         /* changed */
2437         return 0;
2438 }
2439
2440 /*
2441  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2442  * For ASF and Pass Through versions of f/w this means
2443  * that the driver is loaded.
2444  */
2445 static void
2446 igb_hw_control_acquire(struct e1000_hw *hw)
2447 {
2448         uint32_t ctrl_ext;
2449
2450         /* Let firmware know the driver has taken over */
2451         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2452         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2453 }
2454
2455 /*
2456  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2457  * For ASF and Pass Through versions of f/w this means that the
2458  * driver is no longer loaded.
2459  */
2460 static void
2461 igb_hw_control_release(struct e1000_hw *hw)
2462 {
2463         uint32_t ctrl_ext;
2464
2465         /* Let firmware taken over control of h/w */
2466         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2467         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2468                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2469 }
2470
2471 /*
2472  * Bit of a misnomer, what this really means is
2473  * to enable OS management of the system... aka
2474  * to disable special hardware management features.
2475  */
2476 static void
2477 igb_init_manageability(struct e1000_hw *hw)
2478 {
2479         if (e1000_enable_mng_pass_thru(hw)) {
2480                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2481                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2482
2483                 /* disable hardware interception of ARP */
2484                 manc &= ~(E1000_MANC_ARP_EN);
2485
2486                 /* enable receiving management packets to the host */
2487                 manc |= E1000_MANC_EN_MNG2HOST;
2488                 manc2h |= 1 << 5;  /* Mng Port 623 */
2489                 manc2h |= 1 << 6;  /* Mng Port 664 */
2490                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2491                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2492         }
2493 }
2494
2495 static void
2496 igb_release_manageability(struct e1000_hw *hw)
2497 {
2498         if (e1000_enable_mng_pass_thru(hw)) {
2499                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2500
2501                 manc |= E1000_MANC_ARP_EN;
2502                 manc &= ~E1000_MANC_EN_MNG2HOST;
2503
2504                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2505         }
2506 }
2507
2508 static void
2509 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2510 {
2511         struct e1000_hw *hw =
2512                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2513         uint32_t rctl;
2514
2515         rctl = E1000_READ_REG(hw, E1000_RCTL);
2516         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2517         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2518 }
2519
2520 static void
2521 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2522 {
2523         struct e1000_hw *hw =
2524                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2525         uint32_t rctl;
2526
2527         rctl = E1000_READ_REG(hw, E1000_RCTL);
2528         rctl &= (~E1000_RCTL_UPE);
2529         if (dev->data->all_multicast == 1)
2530                 rctl |= E1000_RCTL_MPE;
2531         else
2532                 rctl &= (~E1000_RCTL_MPE);
2533         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2534 }
2535
2536 static void
2537 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2538 {
2539         struct e1000_hw *hw =
2540                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541         uint32_t rctl;
2542
2543         rctl = E1000_READ_REG(hw, E1000_RCTL);
2544         rctl |= E1000_RCTL_MPE;
2545         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2546 }
2547
2548 static void
2549 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2550 {
2551         struct e1000_hw *hw =
2552                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2553         uint32_t rctl;
2554
2555         if (dev->data->promiscuous == 1)
2556                 return; /* must remain in all_multicast mode */
2557         rctl = E1000_READ_REG(hw, E1000_RCTL);
2558         rctl &= (~E1000_RCTL_MPE);
2559         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2560 }
2561
2562 static int
2563 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2564 {
2565         struct e1000_hw *hw =
2566                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2567         struct e1000_vfta * shadow_vfta =
2568                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2569         uint32_t vfta;
2570         uint32_t vid_idx;
2571         uint32_t vid_bit;
2572
2573         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2574                               E1000_VFTA_ENTRY_MASK);
2575         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2576         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2577         if (on)
2578                 vfta |= vid_bit;
2579         else
2580                 vfta &= ~vid_bit;
2581         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2582
2583         /* update local VFTA copy */
2584         shadow_vfta->vfta[vid_idx] = vfta;
2585
2586         return 0;
2587 }
2588
2589 static int
2590 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2591                       enum rte_vlan_type vlan_type,
2592                       uint16_t tpid)
2593 {
2594         struct e1000_hw *hw =
2595                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2596         uint32_t reg, qinq;
2597
2598         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2599         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2600
2601         /* only outer TPID of double VLAN can be configured*/
2602         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2603                 reg = E1000_READ_REG(hw, E1000_VET);
2604                 reg = (reg & (~E1000_VET_VET_EXT)) |
2605                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2606                 E1000_WRITE_REG(hw, E1000_VET, reg);
2607
2608                 return 0;
2609         }
2610
2611         /* all other TPID values are read-only*/
2612         PMD_DRV_LOG(ERR, "Not supported");
2613
2614         return -ENOTSUP;
2615 }
2616
2617 static void
2618 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2619 {
2620         struct e1000_hw *hw =
2621                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2622         uint32_t reg;
2623
2624         /* Filter Table Disable */
2625         reg = E1000_READ_REG(hw, E1000_RCTL);
2626         reg &= ~E1000_RCTL_CFIEN;
2627         reg &= ~E1000_RCTL_VFE;
2628         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2629 }
2630
2631 static void
2632 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2633 {
2634         struct e1000_hw *hw =
2635                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2636         struct e1000_vfta * shadow_vfta =
2637                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2638         uint32_t reg;
2639         int i;
2640
2641         /* Filter Table Enable, CFI not used for packet acceptance */
2642         reg = E1000_READ_REG(hw, E1000_RCTL);
2643         reg &= ~E1000_RCTL_CFIEN;
2644         reg |= E1000_RCTL_VFE;
2645         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2646
2647         /* restore VFTA table */
2648         for (i = 0; i < IGB_VFTA_SIZE; i++)
2649                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2650 }
2651
2652 static void
2653 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2654 {
2655         struct e1000_hw *hw =
2656                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2657         uint32_t reg;
2658
2659         /* VLAN Mode Disable */
2660         reg = E1000_READ_REG(hw, E1000_CTRL);
2661         reg &= ~E1000_CTRL_VME;
2662         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2663 }
2664
2665 static void
2666 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2667 {
2668         struct e1000_hw *hw =
2669                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2670         uint32_t reg;
2671
2672         /* VLAN Mode Enable */
2673         reg = E1000_READ_REG(hw, E1000_CTRL);
2674         reg |= E1000_CTRL_VME;
2675         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2676 }
2677
2678 static void
2679 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2680 {
2681         struct e1000_hw *hw =
2682                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2683         uint32_t reg;
2684
2685         /* CTRL_EXT: Extended VLAN */
2686         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2687         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2688         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2689
2690         /* Update maximum packet length */
2691         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2692                 E1000_WRITE_REG(hw, E1000_RLPML,
2693                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2694                                                 VLAN_TAG_SIZE);
2695 }
2696
2697 static void
2698 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2699 {
2700         struct e1000_hw *hw =
2701                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2702         uint32_t reg;
2703
2704         /* CTRL_EXT: Extended VLAN */
2705         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2706         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2707         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2708
2709         /* Update maximum packet length */
2710         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2711                 E1000_WRITE_REG(hw, E1000_RLPML,
2712                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2713                                                 2 * VLAN_TAG_SIZE);
2714 }
2715
2716 static void
2717 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2718 {
2719         if(mask & ETH_VLAN_STRIP_MASK){
2720                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2721                         igb_vlan_hw_strip_enable(dev);
2722                 else
2723                         igb_vlan_hw_strip_disable(dev);
2724         }
2725
2726         if(mask & ETH_VLAN_FILTER_MASK){
2727                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2728                         igb_vlan_hw_filter_enable(dev);
2729                 else
2730                         igb_vlan_hw_filter_disable(dev);
2731         }
2732
2733         if(mask & ETH_VLAN_EXTEND_MASK){
2734                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2735                         igb_vlan_hw_extend_enable(dev);
2736                 else
2737                         igb_vlan_hw_extend_disable(dev);
2738         }
2739 }
2740
2741
2742 /**
2743  * It enables the interrupt mask and then enable the interrupt.
2744  *
2745  * @param dev
2746  *  Pointer to struct rte_eth_dev.
2747  *
2748  * @return
2749  *  - On success, zero.
2750  *  - On failure, a negative value.
2751  */
2752 static int
2753 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2754 {
2755         struct e1000_interrupt *intr =
2756                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2757
2758         intr->mask |= E1000_ICR_LSC;
2759
2760         return 0;
2761 }
2762
2763 /* It clears the interrupt causes and enables the interrupt.
2764  * It will be called once only during nic initialized.
2765  *
2766  * @param dev
2767  *  Pointer to struct rte_eth_dev.
2768  *
2769  * @return
2770  *  - On success, zero.
2771  *  - On failure, a negative value.
2772  */
2773 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2774 {
2775         uint32_t mask, regval;
2776         struct e1000_hw *hw =
2777                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2778         struct rte_eth_dev_info dev_info;
2779
2780         memset(&dev_info, 0, sizeof(dev_info));
2781         eth_igb_infos_get(dev, &dev_info);
2782
2783         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2784         regval = E1000_READ_REG(hw, E1000_EIMS);
2785         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2786
2787         return 0;
2788 }
2789
2790 /*
2791  * It reads ICR and gets interrupt causes, check it and set a bit flag
2792  * to update link status.
2793  *
2794  * @param dev
2795  *  Pointer to struct rte_eth_dev.
2796  *
2797  * @return
2798  *  - On success, zero.
2799  *  - On failure, a negative value.
2800  */
2801 static int
2802 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2803 {
2804         uint32_t icr;
2805         struct e1000_hw *hw =
2806                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2807         struct e1000_interrupt *intr =
2808                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2809
2810         igb_intr_disable(hw);
2811
2812         /* read-on-clear nic registers here */
2813         icr = E1000_READ_REG(hw, E1000_ICR);
2814
2815         intr->flags = 0;
2816         if (icr & E1000_ICR_LSC) {
2817                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2818         }
2819
2820         if (icr & E1000_ICR_VMMB)
2821                 intr->flags |= E1000_FLAG_MAILBOX;
2822
2823         return 0;
2824 }
2825
2826 /*
2827  * It executes link_update after knowing an interrupt is prsent.
2828  *
2829  * @param dev
2830  *  Pointer to struct rte_eth_dev.
2831  *
2832  * @return
2833  *  - On success, zero.
2834  *  - On failure, a negative value.
2835  */
2836 static int
2837 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2838                          struct rte_intr_handle *intr_handle)
2839 {
2840         struct e1000_hw *hw =
2841                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842         struct e1000_interrupt *intr =
2843                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2844         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2845         uint32_t tctl, rctl;
2846         struct rte_eth_link link;
2847         int ret;
2848
2849         if (intr->flags & E1000_FLAG_MAILBOX) {
2850                 igb_pf_mbx_process(dev);
2851                 intr->flags &= ~E1000_FLAG_MAILBOX;
2852         }
2853
2854         igb_intr_enable(dev);
2855         rte_intr_enable(intr_handle);
2856
2857         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2858                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2859
2860                 /* set get_link_status to check register later */
2861                 hw->mac.get_link_status = 1;
2862                 ret = eth_igb_link_update(dev, 0);
2863
2864                 /* check if link has changed */
2865                 if (ret < 0)
2866                         return 0;
2867
2868                 memset(&link, 0, sizeof(link));
2869                 rte_igb_dev_atomic_read_link_status(dev, &link);
2870                 if (link.link_status) {
2871                         PMD_INIT_LOG(INFO,
2872                                      " Port %d: Link Up - speed %u Mbps - %s",
2873                                      dev->data->port_id,
2874                                      (unsigned)link.link_speed,
2875                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2876                                      "full-duplex" : "half-duplex");
2877                 } else {
2878                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2879                                      dev->data->port_id);
2880                 }
2881
2882                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2883                              pci_dev->addr.domain,
2884                              pci_dev->addr.bus,
2885                              pci_dev->addr.devid,
2886                              pci_dev->addr.function);
2887                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2888                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2889                 if (link.link_status) {
2890                         /* enable Tx/Rx */
2891                         tctl |= E1000_TCTL_EN;
2892                         rctl |= E1000_RCTL_EN;
2893                 } else {
2894                         /* disable Tx/Rx */
2895                         tctl &= ~E1000_TCTL_EN;
2896                         rctl &= ~E1000_RCTL_EN;
2897                 }
2898                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2899                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2900                 E1000_WRITE_FLUSH(hw);
2901                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2902                                               NULL, NULL);
2903         }
2904
2905         return 0;
2906 }
2907
2908 /**
2909  * Interrupt handler which shall be registered at first.
2910  *
2911  * @param handle
2912  *  Pointer to interrupt handle.
2913  * @param param
2914  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2915  *
2916  * @return
2917  *  void
2918  */
2919 static void
2920 eth_igb_interrupt_handler(void *param)
2921 {
2922         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2923
2924         eth_igb_interrupt_get_status(dev);
2925         eth_igb_interrupt_action(dev, dev->intr_handle);
2926 }
2927
2928 static int
2929 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2930 {
2931         uint32_t eicr;
2932         struct e1000_hw *hw =
2933                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2934         struct e1000_interrupt *intr =
2935                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2936
2937         igbvf_intr_disable(hw);
2938
2939         /* read-on-clear nic registers here */
2940         eicr = E1000_READ_REG(hw, E1000_EICR);
2941         intr->flags = 0;
2942
2943         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2944                 intr->flags |= E1000_FLAG_MAILBOX;
2945
2946         return 0;
2947 }
2948
2949 void igbvf_mbx_process(struct rte_eth_dev *dev)
2950 {
2951         struct e1000_hw *hw =
2952                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2953         struct e1000_mbx_info *mbx = &hw->mbx;
2954         u32 in_msg = 0;
2955
2956         if (mbx->ops.read(hw, &in_msg, 1, 0))
2957                 return;
2958
2959         /* PF reset VF event */
2960         if (in_msg == E1000_PF_CONTROL_MSG)
2961                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2962                                               NULL, NULL);
2963 }
2964
2965 static int
2966 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2967 {
2968         struct e1000_interrupt *intr =
2969                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2970
2971         if (intr->flags & E1000_FLAG_MAILBOX) {
2972                 igbvf_mbx_process(dev);
2973                 intr->flags &= ~E1000_FLAG_MAILBOX;
2974         }
2975
2976         igbvf_intr_enable(dev);
2977         rte_intr_enable(intr_handle);
2978
2979         return 0;
2980 }
2981
2982 static void
2983 eth_igbvf_interrupt_handler(void *param)
2984 {
2985         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2986
2987         eth_igbvf_interrupt_get_status(dev);
2988         eth_igbvf_interrupt_action(dev, dev->intr_handle);
2989 }
2990
2991 static int
2992 eth_igb_led_on(struct rte_eth_dev *dev)
2993 {
2994         struct e1000_hw *hw;
2995
2996         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2997         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2998 }
2999
3000 static int
3001 eth_igb_led_off(struct rte_eth_dev *dev)
3002 {
3003         struct e1000_hw *hw;
3004
3005         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3006         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3007 }
3008
3009 static int
3010 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3011 {
3012         struct e1000_hw *hw;
3013         uint32_t ctrl;
3014         int tx_pause;
3015         int rx_pause;
3016
3017         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3018         fc_conf->pause_time = hw->fc.pause_time;
3019         fc_conf->high_water = hw->fc.high_water;
3020         fc_conf->low_water = hw->fc.low_water;
3021         fc_conf->send_xon = hw->fc.send_xon;
3022         fc_conf->autoneg = hw->mac.autoneg;
3023
3024         /*
3025          * Return rx_pause and tx_pause status according to actual setting of
3026          * the TFCE and RFCE bits in the CTRL register.
3027          */
3028         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3029         if (ctrl & E1000_CTRL_TFCE)
3030                 tx_pause = 1;
3031         else
3032                 tx_pause = 0;
3033
3034         if (ctrl & E1000_CTRL_RFCE)
3035                 rx_pause = 1;
3036         else
3037                 rx_pause = 0;
3038
3039         if (rx_pause && tx_pause)
3040                 fc_conf->mode = RTE_FC_FULL;
3041         else if (rx_pause)
3042                 fc_conf->mode = RTE_FC_RX_PAUSE;
3043         else if (tx_pause)
3044                 fc_conf->mode = RTE_FC_TX_PAUSE;
3045         else
3046                 fc_conf->mode = RTE_FC_NONE;
3047
3048         return 0;
3049 }
3050
3051 static int
3052 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3053 {
3054         struct e1000_hw *hw;
3055         int err;
3056         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3057                 e1000_fc_none,
3058                 e1000_fc_rx_pause,
3059                 e1000_fc_tx_pause,
3060                 e1000_fc_full
3061         };
3062         uint32_t rx_buf_size;
3063         uint32_t max_high_water;
3064         uint32_t rctl;
3065
3066         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3067         if (fc_conf->autoneg != hw->mac.autoneg)
3068                 return -ENOTSUP;
3069         rx_buf_size = igb_get_rx_buffer_size(hw);
3070         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3071
3072         /* At least reserve one Ethernet frame for watermark */
3073         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3074         if ((fc_conf->high_water > max_high_water) ||
3075             (fc_conf->high_water < fc_conf->low_water)) {
3076                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3077                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3078                 return -EINVAL;
3079         }
3080
3081         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3082         hw->fc.pause_time     = fc_conf->pause_time;
3083         hw->fc.high_water     = fc_conf->high_water;
3084         hw->fc.low_water      = fc_conf->low_water;
3085         hw->fc.send_xon       = fc_conf->send_xon;
3086
3087         err = e1000_setup_link_generic(hw);
3088         if (err == E1000_SUCCESS) {
3089
3090                 /* check if we want to forward MAC frames - driver doesn't have native
3091                  * capability to do that, so we'll write the registers ourselves */
3092
3093                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3094
3095                 /* set or clear MFLCN.PMCF bit depending on configuration */
3096                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3097                         rctl |= E1000_RCTL_PMCF;
3098                 else
3099                         rctl &= ~E1000_RCTL_PMCF;
3100
3101                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3102                 E1000_WRITE_FLUSH(hw);
3103
3104                 return 0;
3105         }
3106
3107         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3108         return -EIO;
3109 }
3110
3111 #define E1000_RAH_POOLSEL_SHIFT      (18)
3112 static int
3113 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3114                 uint32_t index, uint32_t pool)
3115 {
3116         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3117         uint32_t rah;
3118
3119         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3120         rah = E1000_READ_REG(hw, E1000_RAH(index));
3121         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3122         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3123         return 0;
3124 }
3125
3126 static void
3127 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3128 {
3129         uint8_t addr[ETHER_ADDR_LEN];
3130         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3131
3132         memset(addr, 0, sizeof(addr));
3133
3134         e1000_rar_set(hw, addr, index);
3135 }
3136
3137 static void
3138 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3139                                 struct ether_addr *addr)
3140 {
3141         eth_igb_rar_clear(dev, 0);
3142
3143         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3144 }
3145 /*
3146  * Virtual Function operations
3147  */
3148 static void
3149 igbvf_intr_disable(struct e1000_hw *hw)
3150 {
3151         PMD_INIT_FUNC_TRACE();
3152
3153         /* Clear interrupt mask to stop from interrupts being generated */
3154         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3155
3156         E1000_WRITE_FLUSH(hw);
3157 }
3158
3159 static void
3160 igbvf_stop_adapter(struct rte_eth_dev *dev)
3161 {
3162         u32 reg_val;
3163         u16 i;
3164         struct rte_eth_dev_info dev_info;
3165         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3166
3167         memset(&dev_info, 0, sizeof(dev_info));
3168         eth_igbvf_infos_get(dev, &dev_info);
3169
3170         /* Clear interrupt mask to stop from interrupts being generated */
3171         igbvf_intr_disable(hw);
3172
3173         /* Clear any pending interrupts, flush previous writes */
3174         E1000_READ_REG(hw, E1000_EICR);
3175
3176         /* Disable the transmit unit.  Each queue must be disabled. */
3177         for (i = 0; i < dev_info.max_tx_queues; i++)
3178                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3179
3180         /* Disable the receive unit by stopping each queue */
3181         for (i = 0; i < dev_info.max_rx_queues; i++) {
3182                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3183                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3184                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3185                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3186                         ;
3187         }
3188
3189         /* flush all queues disables */
3190         E1000_WRITE_FLUSH(hw);
3191         msec_delay(2);
3192 }
3193
3194 static int eth_igbvf_link_update(struct e1000_hw *hw)
3195 {
3196         struct e1000_mbx_info *mbx = &hw->mbx;
3197         struct e1000_mac_info *mac = &hw->mac;
3198         int ret_val = E1000_SUCCESS;
3199
3200         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3201
3202         /*
3203          * We only want to run this if there has been a rst asserted.
3204          * in this case that could mean a link change, device reset,
3205          * or a virtual function reset
3206          */
3207
3208         /* If we were hit with a reset or timeout drop the link */
3209         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3210                 mac->get_link_status = TRUE;
3211
3212         if (!mac->get_link_status)
3213                 goto out;
3214
3215         /* if link status is down no point in checking to see if pf is up */
3216         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3217                 goto out;
3218
3219         /* if we passed all the tests above then the link is up and we no
3220          * longer need to check for link */
3221         mac->get_link_status = FALSE;
3222
3223 out:
3224         return ret_val;
3225 }
3226
3227
3228 static int
3229 igbvf_dev_configure(struct rte_eth_dev *dev)
3230 {
3231         struct rte_eth_conf* conf = &dev->data->dev_conf;
3232
3233         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3234                      dev->data->port_id);
3235
3236         /*
3237          * VF has no ability to enable/disable HW CRC
3238          * Keep the persistent behavior the same as Host PF
3239          */
3240 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3241         if (!conf->rxmode.hw_strip_crc) {
3242                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3243                 conf->rxmode.hw_strip_crc = 1;
3244         }
3245 #else
3246         if (conf->rxmode.hw_strip_crc) {
3247                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3248                 conf->rxmode.hw_strip_crc = 0;
3249         }
3250 #endif
3251
3252         return 0;
3253 }
3254
3255 static int
3256 igbvf_dev_start(struct rte_eth_dev *dev)
3257 {
3258         struct e1000_hw *hw =
3259                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3260         struct e1000_adapter *adapter =
3261                 E1000_DEV_PRIVATE(dev->data->dev_private);
3262         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3263         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3264         int ret;
3265         uint32_t intr_vector = 0;
3266
3267         PMD_INIT_FUNC_TRACE();
3268
3269         hw->mac.ops.reset_hw(hw);
3270         adapter->stopped = 0;
3271
3272         /* Set all vfta */
3273         igbvf_set_vfta_all(dev,1);
3274
3275         eth_igbvf_tx_init(dev);
3276
3277         /* This can fail when allocating mbufs for descriptor rings */
3278         ret = eth_igbvf_rx_init(dev);
3279         if (ret) {
3280                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3281                 igb_dev_clear_queues(dev);
3282                 return ret;
3283         }
3284
3285         /* check and configure queue intr-vector mapping */
3286         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3287                 intr_vector = dev->data->nb_rx_queues;
3288                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3289                 if (ret)
3290                         return ret;
3291         }
3292
3293         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3294                 intr_handle->intr_vec =
3295                         rte_zmalloc("intr_vec",
3296                                     dev->data->nb_rx_queues * sizeof(int), 0);
3297                 if (!intr_handle->intr_vec) {
3298                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3299                                      " intr_vec", dev->data->nb_rx_queues);
3300                         return -ENOMEM;
3301                 }
3302         }
3303
3304         eth_igbvf_configure_msix_intr(dev);
3305
3306         /* enable uio/vfio intr/eventfd mapping */
3307         rte_intr_enable(intr_handle);
3308
3309         /* resume enabled intr since hw reset */
3310         igbvf_intr_enable(dev);
3311
3312         return 0;
3313 }
3314
3315 static void
3316 igbvf_dev_stop(struct rte_eth_dev *dev)
3317 {
3318         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3319         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3320
3321         PMD_INIT_FUNC_TRACE();
3322
3323         igbvf_stop_adapter(dev);
3324
3325         /*
3326           * Clear what we set, but we still keep shadow_vfta to
3327           * restore after device starts
3328           */
3329         igbvf_set_vfta_all(dev,0);
3330
3331         igb_dev_clear_queues(dev);
3332
3333         /* disable intr eventfd mapping */
3334         rte_intr_disable(intr_handle);
3335
3336         /* Clean datapath event and queue/vec mapping */
3337         rte_intr_efd_disable(intr_handle);
3338         if (intr_handle->intr_vec) {
3339                 rte_free(intr_handle->intr_vec);
3340                 intr_handle->intr_vec = NULL;
3341         }
3342 }
3343
3344 static void
3345 igbvf_dev_close(struct rte_eth_dev *dev)
3346 {
3347         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3348         struct e1000_adapter *adapter =
3349                 E1000_DEV_PRIVATE(dev->data->dev_private);
3350         struct ether_addr addr;
3351
3352         PMD_INIT_FUNC_TRACE();
3353
3354         e1000_reset_hw(hw);
3355
3356         igbvf_dev_stop(dev);
3357         adapter->stopped = 1;
3358         igb_dev_free_queues(dev);
3359
3360         /**
3361          * reprogram the RAR with a zero mac address,
3362          * to ensure that the VF traffic goes to the PF
3363          * after stop, close and detach of the VF.
3364          **/
3365
3366         memset(&addr, 0, sizeof(addr));
3367         igbvf_default_mac_addr_set(dev, &addr);
3368 }
3369
3370 static void
3371 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3372 {
3373         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3374
3375         /* Set both unicast and multicast promisc */
3376         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3377 }
3378
3379 static void
3380 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3381 {
3382         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3383
3384         /* If in allmulticast mode leave multicast promisc */
3385         if (dev->data->all_multicast == 1)
3386                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3387         else
3388                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3389 }
3390
3391 static void
3392 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3393 {
3394         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3395
3396         /* In promiscuous mode multicast promisc already set */
3397         if (dev->data->promiscuous == 0)
3398                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3399 }
3400
3401 static void
3402 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3403 {
3404         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3405
3406         /* In promiscuous mode leave multicast promisc enabled */
3407         if (dev->data->promiscuous == 0)
3408                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3409 }
3410
3411 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3412 {
3413         struct e1000_mbx_info *mbx = &hw->mbx;
3414         uint32_t msgbuf[2];
3415         s32 err;
3416
3417         /* After set vlan, vlan strip will also be enabled in igb driver*/
3418         msgbuf[0] = E1000_VF_SET_VLAN;
3419         msgbuf[1] = vid;
3420         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3421         if (on)
3422                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3423
3424         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3425         if (err)
3426                 goto mbx_err;
3427
3428         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3429         if (err)
3430                 goto mbx_err;
3431
3432         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3433         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3434                 err = -EINVAL;
3435
3436 mbx_err:
3437         return err;
3438 }
3439
3440 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3441 {
3442         struct e1000_hw *hw =
3443                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3444         struct e1000_vfta * shadow_vfta =
3445                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3446         int i = 0, j = 0, vfta = 0, mask = 1;
3447
3448         for (i = 0; i < IGB_VFTA_SIZE; i++){
3449                 vfta = shadow_vfta->vfta[i];
3450                 if(vfta){
3451                         mask = 1;
3452                         for (j = 0; j < 32; j++){
3453                                 if(vfta & mask)
3454                                         igbvf_set_vfta(hw,
3455                                                 (uint16_t)((i<<5)+j), on);
3456                                 mask<<=1;
3457                         }
3458                 }
3459         }
3460
3461 }
3462
3463 static int
3464 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3465 {
3466         struct e1000_hw *hw =
3467                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3468         struct e1000_vfta * shadow_vfta =
3469                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3470         uint32_t vid_idx = 0;
3471         uint32_t vid_bit = 0;
3472         int ret = 0;
3473
3474         PMD_INIT_FUNC_TRACE();
3475
3476         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3477         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3478         if(ret){
3479                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3480                 return ret;
3481         }
3482         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3483         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3484
3485         /*Save what we set and retore it after device reset*/
3486         if (on)
3487                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3488         else
3489                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3490
3491         return 0;
3492 }
3493
3494 static void
3495 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3496 {
3497         struct e1000_hw *hw =
3498                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3499
3500         /* index is not used by rar_set() */
3501         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3502 }
3503
3504
3505 static int
3506 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3507                         struct rte_eth_rss_reta_entry64 *reta_conf,
3508                         uint16_t reta_size)
3509 {
3510         uint8_t i, j, mask;
3511         uint32_t reta, r;
3512         uint16_t idx, shift;
3513         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3514
3515         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3516                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3517                         "(%d) doesn't match the number hardware can supported "
3518                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3519                 return -EINVAL;
3520         }
3521
3522         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3523                 idx = i / RTE_RETA_GROUP_SIZE;
3524                 shift = i % RTE_RETA_GROUP_SIZE;
3525                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3526                                                 IGB_4_BIT_MASK);
3527                 if (!mask)
3528                         continue;
3529                 if (mask == IGB_4_BIT_MASK)
3530                         r = 0;
3531                 else
3532                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3533                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3534                         if (mask & (0x1 << j))
3535                                 reta |= reta_conf[idx].reta[shift + j] <<
3536                                                         (CHAR_BIT * j);
3537                         else
3538                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3539                 }
3540                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3541         }
3542
3543         return 0;
3544 }
3545
3546 static int
3547 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3548                        struct rte_eth_rss_reta_entry64 *reta_conf,
3549                        uint16_t reta_size)
3550 {
3551         uint8_t i, j, mask;
3552         uint32_t reta;
3553         uint16_t idx, shift;
3554         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3555
3556         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3557                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3558                         "(%d) doesn't match the number hardware can supported "
3559                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3560                 return -EINVAL;
3561         }
3562
3563         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3564                 idx = i / RTE_RETA_GROUP_SIZE;
3565                 shift = i % RTE_RETA_GROUP_SIZE;
3566                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3567                                                 IGB_4_BIT_MASK);
3568                 if (!mask)
3569                         continue;
3570                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3571                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3572                         if (mask & (0x1 << j))
3573                                 reta_conf[idx].reta[shift + j] =
3574                                         ((reta >> (CHAR_BIT * j)) &
3575                                                 IGB_8_BIT_MASK);
3576                 }
3577         }
3578
3579         return 0;
3580 }
3581
3582 int
3583 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3584                         struct rte_eth_syn_filter *filter,
3585                         bool add)
3586 {
3587         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3588         struct e1000_filter_info *filter_info =
3589                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3590         uint32_t synqf, rfctl;
3591
3592         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3593                 return -EINVAL;
3594
3595         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3596
3597         if (add) {
3598                 if (synqf & E1000_SYN_FILTER_ENABLE)
3599                         return -EINVAL;
3600
3601                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3602                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3603
3604                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3605                 if (filter->hig_pri)
3606                         rfctl |= E1000_RFCTL_SYNQFP;
3607                 else
3608                         rfctl &= ~E1000_RFCTL_SYNQFP;
3609
3610                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3611         } else {
3612                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3613                         return -ENOENT;
3614                 synqf = 0;
3615         }
3616
3617         filter_info->syn_info = synqf;
3618         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3619         E1000_WRITE_FLUSH(hw);
3620         return 0;
3621 }
3622
3623 static int
3624 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3625                         struct rte_eth_syn_filter *filter)
3626 {
3627         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3628         uint32_t synqf, rfctl;
3629
3630         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3631         if (synqf & E1000_SYN_FILTER_ENABLE) {
3632                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3633                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3634                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3635                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3636                 return 0;
3637         }
3638
3639         return -ENOENT;
3640 }
3641
3642 static int
3643 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3644                         enum rte_filter_op filter_op,
3645                         void *arg)
3646 {
3647         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3648         int ret;
3649
3650         MAC_TYPE_FILTER_SUP(hw->mac.type);
3651
3652         if (filter_op == RTE_ETH_FILTER_NOP)
3653                 return 0;
3654
3655         if (arg == NULL) {
3656                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3657                             filter_op);
3658                 return -EINVAL;
3659         }
3660
3661         switch (filter_op) {
3662         case RTE_ETH_FILTER_ADD:
3663                 ret = eth_igb_syn_filter_set(dev,
3664                                 (struct rte_eth_syn_filter *)arg,
3665                                 TRUE);
3666                 break;
3667         case RTE_ETH_FILTER_DELETE:
3668                 ret = eth_igb_syn_filter_set(dev,
3669                                 (struct rte_eth_syn_filter *)arg,
3670                                 FALSE);
3671                 break;
3672         case RTE_ETH_FILTER_GET:
3673                 ret = eth_igb_syn_filter_get(dev,
3674                                 (struct rte_eth_syn_filter *)arg);
3675                 break;
3676         default:
3677                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3678                 ret = -EINVAL;
3679                 break;
3680         }
3681
3682         return ret;
3683 }
3684
3685 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3686 static inline int
3687 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3688                         struct e1000_2tuple_filter_info *filter_info)
3689 {
3690         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3691                 return -EINVAL;
3692         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3693                 return -EINVAL;  /* filter index is out of range. */
3694         if (filter->tcp_flags > TCP_FLAG_ALL)
3695                 return -EINVAL;  /* flags is invalid. */
3696
3697         switch (filter->dst_port_mask) {
3698         case UINT16_MAX:
3699                 filter_info->dst_port_mask = 0;
3700                 filter_info->dst_port = filter->dst_port;
3701                 break;
3702         case 0:
3703                 filter_info->dst_port_mask = 1;
3704                 break;
3705         default:
3706                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3707                 return -EINVAL;
3708         }
3709
3710         switch (filter->proto_mask) {
3711         case UINT8_MAX:
3712                 filter_info->proto_mask = 0;
3713                 filter_info->proto = filter->proto;
3714                 break;
3715         case 0:
3716                 filter_info->proto_mask = 1;
3717                 break;
3718         default:
3719                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3720                 return -EINVAL;
3721         }
3722
3723         filter_info->priority = (uint8_t)filter->priority;
3724         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3725                 filter_info->tcp_flags = filter->tcp_flags;
3726         else
3727                 filter_info->tcp_flags = 0;
3728
3729         return 0;
3730 }
3731
3732 static inline struct e1000_2tuple_filter *
3733 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3734                         struct e1000_2tuple_filter_info *key)
3735 {
3736         struct e1000_2tuple_filter *it;
3737
3738         TAILQ_FOREACH(it, filter_list, entries) {
3739                 if (memcmp(key, &it->filter_info,
3740                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3741                         return it;
3742                 }
3743         }
3744         return NULL;
3745 }
3746
3747 /* inject a igb 2tuple filter to HW */
3748 static inline void
3749 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3750                            struct e1000_2tuple_filter *filter)
3751 {
3752         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3753         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3754         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3755         int i;
3756
3757         i = filter->index;
3758         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3759         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3760                 imir |= E1000_IMIR_PORT_BP;
3761         else
3762                 imir &= ~E1000_IMIR_PORT_BP;
3763
3764         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3765
3766         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3767         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3768         ttqf |= (uint32_t)(filter->filter_info.proto &
3769                                                 E1000_TTQF_PROTOCOL_MASK);
3770         if (filter->filter_info.proto_mask == 0)
3771                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3772
3773         /* tcp flags bits setting. */
3774         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3775                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3776                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3777                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3778                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3779                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3780                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3781                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3782                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3783                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3784                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3785                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3786                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3787         } else {
3788                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3789         }
3790         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3791         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3792         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3793 }
3794
3795 /*
3796  * igb_add_2tuple_filter - add a 2tuple filter
3797  *
3798  * @param
3799  * dev: Pointer to struct rte_eth_dev.
3800  * ntuple_filter: ponter to the filter that will be added.
3801  *
3802  * @return
3803  *    - On success, zero.
3804  *    - On failure, a negative value.
3805  */
3806 static int
3807 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3808                         struct rte_eth_ntuple_filter *ntuple_filter)
3809 {
3810         struct e1000_filter_info *filter_info =
3811                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3812         struct e1000_2tuple_filter *filter;
3813         int i, ret;
3814
3815         filter = rte_zmalloc("e1000_2tuple_filter",
3816                         sizeof(struct e1000_2tuple_filter), 0);
3817         if (filter == NULL)
3818                 return -ENOMEM;
3819
3820         ret = ntuple_filter_to_2tuple(ntuple_filter,
3821                                       &filter->filter_info);
3822         if (ret < 0) {
3823                 rte_free(filter);
3824                 return ret;
3825         }
3826         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3827                                          &filter->filter_info) != NULL) {
3828                 PMD_DRV_LOG(ERR, "filter exists.");
3829                 rte_free(filter);
3830                 return -EEXIST;
3831         }
3832         filter->queue = ntuple_filter->queue;
3833
3834         /*
3835          * look for an unused 2tuple filter index,
3836          * and insert the filter to list.
3837          */
3838         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3839                 if (!(filter_info->twotuple_mask & (1 << i))) {
3840                         filter_info->twotuple_mask |= 1 << i;
3841                         filter->index = i;
3842                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3843                                           filter,
3844                                           entries);
3845                         break;
3846                 }
3847         }
3848         if (i >= E1000_MAX_TTQF_FILTERS) {
3849                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3850                 rte_free(filter);
3851                 return -ENOSYS;
3852         }
3853
3854         igb_inject_2uple_filter(dev, filter);
3855         return 0;
3856 }
3857
3858 int
3859 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3860                         struct e1000_2tuple_filter *filter)
3861 {
3862         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3863         struct e1000_filter_info *filter_info =
3864                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3865
3866         filter_info->twotuple_mask &= ~(1 << filter->index);
3867         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3868         rte_free(filter);
3869
3870         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3871         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3872         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3873         return 0;
3874 }
3875
3876 /*
3877  * igb_remove_2tuple_filter - remove a 2tuple filter
3878  *
3879  * @param
3880  * dev: Pointer to struct rte_eth_dev.
3881  * ntuple_filter: ponter to the filter that will be removed.
3882  *
3883  * @return
3884  *    - On success, zero.
3885  *    - On failure, a negative value.
3886  */
3887 static int
3888 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3889                         struct rte_eth_ntuple_filter *ntuple_filter)
3890 {
3891         struct e1000_filter_info *filter_info =
3892                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3893         struct e1000_2tuple_filter_info filter_2tuple;
3894         struct e1000_2tuple_filter *filter;
3895         int ret;
3896
3897         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3898         ret = ntuple_filter_to_2tuple(ntuple_filter,
3899                                       &filter_2tuple);
3900         if (ret < 0)
3901                 return ret;
3902
3903         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3904                                          &filter_2tuple);
3905         if (filter == NULL) {
3906                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3907                 return -ENOENT;
3908         }
3909
3910         igb_delete_2tuple_filter(dev, filter);
3911
3912         return 0;
3913 }
3914
3915 /* inject a igb flex filter to HW */
3916 static inline void
3917 igb_inject_flex_filter(struct rte_eth_dev *dev,
3918                            struct e1000_flex_filter *filter)
3919 {
3920         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3921         uint32_t wufc, queueing;
3922         uint32_t reg_off;
3923         uint8_t i, j = 0;
3924
3925         wufc = E1000_READ_REG(hw, E1000_WUFC);
3926         if (filter->index < E1000_MAX_FHFT)
3927                 reg_off = E1000_FHFT(filter->index);
3928         else
3929                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3930
3931         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3932                         (E1000_WUFC_FLX0 << filter->index));
3933         queueing = filter->filter_info.len |
3934                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3935                 (filter->filter_info.priority <<
3936                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3937         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3938                         queueing);
3939
3940         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3941                 E1000_WRITE_REG(hw, reg_off,
3942                                 filter->filter_info.dwords[j]);
3943                 reg_off += sizeof(uint32_t);
3944                 E1000_WRITE_REG(hw, reg_off,
3945                                 filter->filter_info.dwords[++j]);
3946                 reg_off += sizeof(uint32_t);
3947                 E1000_WRITE_REG(hw, reg_off,
3948                         (uint32_t)filter->filter_info.mask[i]);
3949                 reg_off += sizeof(uint32_t) * 2;
3950                 ++j;
3951         }
3952 }
3953
3954 static inline struct e1000_flex_filter *
3955 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3956                         struct e1000_flex_filter_info *key)
3957 {
3958         struct e1000_flex_filter *it;
3959
3960         TAILQ_FOREACH(it, filter_list, entries) {
3961                 if (memcmp(key, &it->filter_info,
3962                         sizeof(struct e1000_flex_filter_info)) == 0)
3963                         return it;
3964         }
3965
3966         return NULL;
3967 }
3968
3969 /* remove a flex byte filter
3970  * @param
3971  * dev: Pointer to struct rte_eth_dev.
3972  * filter: the pointer of the filter will be removed.
3973  */
3974 void
3975 igb_remove_flex_filter(struct rte_eth_dev *dev,
3976                         struct e1000_flex_filter *filter)
3977 {
3978         struct e1000_filter_info *filter_info =
3979                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3980         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3981         uint32_t wufc, i;
3982         uint32_t reg_off;
3983
3984         wufc = E1000_READ_REG(hw, E1000_WUFC);
3985         if (filter->index < E1000_MAX_FHFT)
3986                 reg_off = E1000_FHFT(filter->index);
3987         else
3988                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3989
3990         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3991                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3992
3993         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3994                 (~(E1000_WUFC_FLX0 << filter->index)));
3995
3996         filter_info->flex_mask &= ~(1 << filter->index);
3997         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
3998         rte_free(filter);
3999 }
4000
4001 int
4002 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4003                         struct rte_eth_flex_filter *filter,
4004                         bool add)
4005 {
4006         struct e1000_filter_info *filter_info =
4007                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4008         struct e1000_flex_filter *flex_filter, *it;
4009         uint32_t mask;
4010         uint8_t shift, i;
4011
4012         flex_filter = rte_zmalloc("e1000_flex_filter",
4013                         sizeof(struct e1000_flex_filter), 0);
4014         if (flex_filter == NULL)
4015                 return -ENOMEM;
4016
4017         flex_filter->filter_info.len = filter->len;
4018         flex_filter->filter_info.priority = filter->priority;
4019         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4020         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4021                 mask = 0;
4022                 /* reverse bits in flex filter's mask*/
4023                 for (shift = 0; shift < CHAR_BIT; shift++) {
4024                         if (filter->mask[i] & (0x01 << shift))
4025                                 mask |= (0x80 >> shift);
4026                 }
4027                 flex_filter->filter_info.mask[i] = mask;
4028         }
4029
4030         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4031                                 &flex_filter->filter_info);
4032         if (it == NULL && !add) {
4033                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4034                 rte_free(flex_filter);
4035                 return -ENOENT;
4036         }
4037         if (it != NULL && add) {
4038                 PMD_DRV_LOG(ERR, "filter exists.");
4039                 rte_free(flex_filter);
4040                 return -EEXIST;
4041         }
4042
4043         if (add) {
4044                 flex_filter->queue = filter->queue;
4045                 /*
4046                  * look for an unused flex filter index
4047                  * and insert the filter into the list.
4048                  */
4049                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4050                         if (!(filter_info->flex_mask & (1 << i))) {
4051                                 filter_info->flex_mask |= 1 << i;
4052                                 flex_filter->index = i;
4053                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4054                                         flex_filter,
4055                                         entries);
4056                                 break;
4057                         }
4058                 }
4059                 if (i >= E1000_MAX_FLEX_FILTERS) {
4060                         PMD_DRV_LOG(ERR, "flex filters are full.");
4061                         rte_free(flex_filter);
4062                         return -ENOSYS;
4063                 }
4064
4065                 igb_inject_flex_filter(dev, flex_filter);
4066
4067         } else {
4068                 igb_remove_flex_filter(dev, it);
4069                 rte_free(flex_filter);
4070         }
4071
4072         return 0;
4073 }
4074
4075 static int
4076 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4077                         struct rte_eth_flex_filter *filter)
4078 {
4079         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4080         struct e1000_filter_info *filter_info =
4081                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4082         struct e1000_flex_filter flex_filter, *it;
4083         uint32_t wufc, queueing, wufc_en = 0;
4084
4085         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4086         flex_filter.filter_info.len = filter->len;
4087         flex_filter.filter_info.priority = filter->priority;
4088         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4089         memcpy(flex_filter.filter_info.mask, filter->mask,
4090                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
4091
4092         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4093                                 &flex_filter.filter_info);
4094         if (it == NULL) {
4095                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4096                 return -ENOENT;
4097         }
4098
4099         wufc = E1000_READ_REG(hw, E1000_WUFC);
4100         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4101
4102         if ((wufc & wufc_en) == wufc_en) {
4103                 uint32_t reg_off = 0;
4104                 if (it->index < E1000_MAX_FHFT)
4105                         reg_off = E1000_FHFT(it->index);
4106                 else
4107                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4108
4109                 queueing = E1000_READ_REG(hw,
4110                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4111                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4112                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4113                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4114                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4115                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4116                 return 0;
4117         }
4118         return -ENOENT;
4119 }
4120
4121 static int
4122 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4123                         enum rte_filter_op filter_op,
4124                         void *arg)
4125 {
4126         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4127         struct rte_eth_flex_filter *filter;
4128         int ret = 0;
4129
4130         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4131
4132         if (filter_op == RTE_ETH_FILTER_NOP)
4133                 return ret;
4134
4135         if (arg == NULL) {
4136                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4137                             filter_op);
4138                 return -EINVAL;
4139         }
4140
4141         filter = (struct rte_eth_flex_filter *)arg;
4142         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4143             || filter->len % sizeof(uint64_t) != 0) {
4144                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4145                 return -EINVAL;
4146         }
4147         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4148                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4149                 return -EINVAL;
4150         }
4151
4152         switch (filter_op) {
4153         case RTE_ETH_FILTER_ADD:
4154                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4155                 break;
4156         case RTE_ETH_FILTER_DELETE:
4157                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4158                 break;
4159         case RTE_ETH_FILTER_GET:
4160                 ret = eth_igb_get_flex_filter(dev, filter);
4161                 break;
4162         default:
4163                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4164                 ret = -EINVAL;
4165                 break;
4166         }
4167
4168         return ret;
4169 }
4170
4171 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4172 static inline int
4173 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4174                         struct e1000_5tuple_filter_info *filter_info)
4175 {
4176         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4177                 return -EINVAL;
4178         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4179                 return -EINVAL;  /* filter index is out of range. */
4180         if (filter->tcp_flags > TCP_FLAG_ALL)
4181                 return -EINVAL;  /* flags is invalid. */
4182
4183         switch (filter->dst_ip_mask) {
4184         case UINT32_MAX:
4185                 filter_info->dst_ip_mask = 0;
4186                 filter_info->dst_ip = filter->dst_ip;
4187                 break;
4188         case 0:
4189                 filter_info->dst_ip_mask = 1;
4190                 break;
4191         default:
4192                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4193                 return -EINVAL;
4194         }
4195
4196         switch (filter->src_ip_mask) {
4197         case UINT32_MAX:
4198                 filter_info->src_ip_mask = 0;
4199                 filter_info->src_ip = filter->src_ip;
4200                 break;
4201         case 0:
4202                 filter_info->src_ip_mask = 1;
4203                 break;
4204         default:
4205                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4206                 return -EINVAL;
4207         }
4208
4209         switch (filter->dst_port_mask) {
4210         case UINT16_MAX:
4211                 filter_info->dst_port_mask = 0;
4212                 filter_info->dst_port = filter->dst_port;
4213                 break;
4214         case 0:
4215                 filter_info->dst_port_mask = 1;
4216                 break;
4217         default:
4218                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4219                 return -EINVAL;
4220         }
4221
4222         switch (filter->src_port_mask) {
4223         case UINT16_MAX:
4224                 filter_info->src_port_mask = 0;
4225                 filter_info->src_port = filter->src_port;
4226                 break;
4227         case 0:
4228                 filter_info->src_port_mask = 1;
4229                 break;
4230         default:
4231                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4232                 return -EINVAL;
4233         }
4234
4235         switch (filter->proto_mask) {
4236         case UINT8_MAX:
4237                 filter_info->proto_mask = 0;
4238                 filter_info->proto = filter->proto;
4239                 break;
4240         case 0:
4241                 filter_info->proto_mask = 1;
4242                 break;
4243         default:
4244                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4245                 return -EINVAL;
4246         }
4247
4248         filter_info->priority = (uint8_t)filter->priority;
4249         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4250                 filter_info->tcp_flags = filter->tcp_flags;
4251         else
4252                 filter_info->tcp_flags = 0;
4253
4254         return 0;
4255 }
4256
4257 static inline struct e1000_5tuple_filter *
4258 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4259                         struct e1000_5tuple_filter_info *key)
4260 {
4261         struct e1000_5tuple_filter *it;
4262
4263         TAILQ_FOREACH(it, filter_list, entries) {
4264                 if (memcmp(key, &it->filter_info,
4265                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4266                         return it;
4267                 }
4268         }
4269         return NULL;
4270 }
4271
4272 /* inject a igb 5-tuple filter to HW */
4273 static inline void
4274 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4275                            struct e1000_5tuple_filter *filter)
4276 {
4277         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4278         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4279         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4280         uint8_t i;
4281
4282         i = filter->index;
4283         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4284         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4285                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4286         if (filter->filter_info.dst_ip_mask == 0)
4287                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4288         if (filter->filter_info.src_port_mask == 0)
4289                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4290         if (filter->filter_info.proto_mask == 0)
4291                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4292         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4293                 E1000_FTQF_QUEUE_MASK;
4294         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4295         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4296         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4297         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4298
4299         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4300         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4301
4302         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4303         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4304                 imir |= E1000_IMIR_PORT_BP;
4305         else
4306                 imir &= ~E1000_IMIR_PORT_BP;
4307         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4308
4309         /* tcp flags bits setting. */
4310         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4311                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4312                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4313                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4314                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4315                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4316                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4317                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4318                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4319                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4320                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4321                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4322                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4323         } else {
4324                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4325         }
4326         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4327         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4328 }
4329
4330 /*
4331  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4332  *
4333  * @param
4334  * dev: Pointer to struct rte_eth_dev.
4335  * ntuple_filter: ponter to the filter that will be added.
4336  *
4337  * @return
4338  *    - On success, zero.
4339  *    - On failure, a negative value.
4340  */
4341 static int
4342 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4343                         struct rte_eth_ntuple_filter *ntuple_filter)
4344 {
4345         struct e1000_filter_info *filter_info =
4346                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4347         struct e1000_5tuple_filter *filter;
4348         uint8_t i;
4349         int ret;
4350
4351         filter = rte_zmalloc("e1000_5tuple_filter",
4352                         sizeof(struct e1000_5tuple_filter), 0);
4353         if (filter == NULL)
4354                 return -ENOMEM;
4355
4356         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4357                                             &filter->filter_info);
4358         if (ret < 0) {
4359                 rte_free(filter);
4360                 return ret;
4361         }
4362
4363         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4364                                          &filter->filter_info) != NULL) {
4365                 PMD_DRV_LOG(ERR, "filter exists.");
4366                 rte_free(filter);
4367                 return -EEXIST;
4368         }
4369         filter->queue = ntuple_filter->queue;
4370
4371         /*
4372          * look for an unused 5tuple filter index,
4373          * and insert the filter to list.
4374          */
4375         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4376                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4377                         filter_info->fivetuple_mask |= 1 << i;
4378                         filter->index = i;
4379                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4380                                           filter,
4381                                           entries);
4382                         break;
4383                 }
4384         }
4385         if (i >= E1000_MAX_FTQF_FILTERS) {
4386                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4387                 rte_free(filter);
4388                 return -ENOSYS;
4389         }
4390
4391         igb_inject_5tuple_filter_82576(dev, filter);
4392         return 0;
4393 }
4394
4395 int
4396 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4397                                 struct e1000_5tuple_filter *filter)
4398 {
4399         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4400         struct e1000_filter_info *filter_info =
4401                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4402
4403         filter_info->fivetuple_mask &= ~(1 << filter->index);
4404         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4405         rte_free(filter);
4406
4407         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4408                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4409         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4410         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4411         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4412         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4413         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4414         return 0;
4415 }
4416
4417 /*
4418  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4419  *
4420  * @param
4421  * dev: Pointer to struct rte_eth_dev.
4422  * ntuple_filter: ponter to the filter that will be removed.
4423  *
4424  * @return
4425  *    - On success, zero.
4426  *    - On failure, a negative value.
4427  */
4428 static int
4429 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4430                                 struct rte_eth_ntuple_filter *ntuple_filter)
4431 {
4432         struct e1000_filter_info *filter_info =
4433                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4434         struct e1000_5tuple_filter_info filter_5tuple;
4435         struct e1000_5tuple_filter *filter;
4436         int ret;
4437
4438         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4439         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4440                                             &filter_5tuple);
4441         if (ret < 0)
4442                 return ret;
4443
4444         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4445                                          &filter_5tuple);
4446         if (filter == NULL) {
4447                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4448                 return -ENOENT;
4449         }
4450
4451         igb_delete_5tuple_filter_82576(dev, filter);
4452
4453         return 0;
4454 }
4455
4456 static int
4457 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4458 {
4459         uint32_t rctl;
4460         struct e1000_hw *hw;
4461         struct rte_eth_dev_info dev_info;
4462         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4463                                      VLAN_TAG_SIZE);
4464
4465         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4466
4467 #ifdef RTE_LIBRTE_82571_SUPPORT
4468         /* XXX: not bigger than max_rx_pktlen */
4469         if (hw->mac.type == e1000_82571)
4470                 return -ENOTSUP;
4471 #endif
4472         eth_igb_infos_get(dev, &dev_info);
4473
4474         /* check that mtu is within the allowed range */
4475         if ((mtu < ETHER_MIN_MTU) ||
4476             (frame_size > dev_info.max_rx_pktlen))
4477                 return -EINVAL;
4478
4479         /* refuse mtu that requires the support of scattered packets when this
4480          * feature has not been enabled before. */
4481         if (!dev->data->scattered_rx &&
4482             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4483                 return -EINVAL;
4484
4485         rctl = E1000_READ_REG(hw, E1000_RCTL);
4486
4487         /* switch to jumbo mode if needed */
4488         if (frame_size > ETHER_MAX_LEN) {
4489                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4490                 rctl |= E1000_RCTL_LPE;
4491         } else {
4492                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4493                 rctl &= ~E1000_RCTL_LPE;
4494         }
4495         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4496
4497         /* update max frame size */
4498         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4499
4500         E1000_WRITE_REG(hw, E1000_RLPML,
4501                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4502
4503         return 0;
4504 }
4505
4506 /*
4507  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4508  *
4509  * @param
4510  * dev: Pointer to struct rte_eth_dev.
4511  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4512  * add: if true, add filter, if false, remove filter
4513  *
4514  * @return
4515  *    - On success, zero.
4516  *    - On failure, a negative value.
4517  */
4518 int
4519 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4520                         struct rte_eth_ntuple_filter *ntuple_filter,
4521                         bool add)
4522 {
4523         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4524         int ret;
4525
4526         switch (ntuple_filter->flags) {
4527         case RTE_5TUPLE_FLAGS:
4528         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4529                 if (hw->mac.type != e1000_82576)
4530                         return -ENOTSUP;
4531                 if (add)
4532                         ret = igb_add_5tuple_filter_82576(dev,
4533                                                           ntuple_filter);
4534                 else
4535                         ret = igb_remove_5tuple_filter_82576(dev,
4536                                                              ntuple_filter);
4537                 break;
4538         case RTE_2TUPLE_FLAGS:
4539         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4540                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4541                         hw->mac.type != e1000_i210 &&
4542                         hw->mac.type != e1000_i211)
4543                         return -ENOTSUP;
4544                 if (add)
4545                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4546                 else
4547                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4548                 break;
4549         default:
4550                 ret = -EINVAL;
4551                 break;
4552         }
4553
4554         return ret;
4555 }
4556
4557 /*
4558  * igb_get_ntuple_filter - get a ntuple filter
4559  *
4560  * @param
4561  * dev: Pointer to struct rte_eth_dev.
4562  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4563  *
4564  * @return
4565  *    - On success, zero.
4566  *    - On failure, a negative value.
4567  */
4568 static int
4569 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4570                         struct rte_eth_ntuple_filter *ntuple_filter)
4571 {
4572         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4573         struct e1000_filter_info *filter_info =
4574                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4575         struct e1000_5tuple_filter_info filter_5tuple;
4576         struct e1000_2tuple_filter_info filter_2tuple;
4577         struct e1000_5tuple_filter *p_5tuple_filter;
4578         struct e1000_2tuple_filter *p_2tuple_filter;
4579         int ret;
4580
4581         switch (ntuple_filter->flags) {
4582         case RTE_5TUPLE_FLAGS:
4583         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4584                 if (hw->mac.type != e1000_82576)
4585                         return -ENOTSUP;
4586                 memset(&filter_5tuple,
4587                         0,
4588                         sizeof(struct e1000_5tuple_filter_info));
4589                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4590                                                     &filter_5tuple);
4591                 if (ret < 0)
4592                         return ret;
4593                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4594                                         &filter_info->fivetuple_list,
4595                                         &filter_5tuple);
4596                 if (p_5tuple_filter == NULL) {
4597                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4598                         return -ENOENT;
4599                 }
4600                 ntuple_filter->queue = p_5tuple_filter->queue;
4601                 break;
4602         case RTE_2TUPLE_FLAGS:
4603         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4604                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4605                         return -ENOTSUP;
4606                 memset(&filter_2tuple,
4607                         0,
4608                         sizeof(struct e1000_2tuple_filter_info));
4609                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4610                 if (ret < 0)
4611                         return ret;
4612                 p_2tuple_filter = igb_2tuple_filter_lookup(
4613                                         &filter_info->twotuple_list,
4614                                         &filter_2tuple);
4615                 if (p_2tuple_filter == NULL) {
4616                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4617                         return -ENOENT;
4618                 }
4619                 ntuple_filter->queue = p_2tuple_filter->queue;
4620                 break;
4621         default:
4622                 ret = -EINVAL;
4623                 break;
4624         }
4625
4626         return 0;
4627 }
4628
4629 /*
4630  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4631  * @dev: pointer to rte_eth_dev structure
4632  * @filter_op:operation will be taken.
4633  * @arg: a pointer to specific structure corresponding to the filter_op
4634  */
4635 static int
4636 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4637                                 enum rte_filter_op filter_op,
4638                                 void *arg)
4639 {
4640         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4641         int ret;
4642
4643         MAC_TYPE_FILTER_SUP(hw->mac.type);
4644
4645         if (filter_op == RTE_ETH_FILTER_NOP)
4646                 return 0;
4647
4648         if (arg == NULL) {
4649                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4650                             filter_op);
4651                 return -EINVAL;
4652         }
4653
4654         switch (filter_op) {
4655         case RTE_ETH_FILTER_ADD:
4656                 ret = igb_add_del_ntuple_filter(dev,
4657                         (struct rte_eth_ntuple_filter *)arg,
4658                         TRUE);
4659                 break;
4660         case RTE_ETH_FILTER_DELETE:
4661                 ret = igb_add_del_ntuple_filter(dev,
4662                         (struct rte_eth_ntuple_filter *)arg,
4663                         FALSE);
4664                 break;
4665         case RTE_ETH_FILTER_GET:
4666                 ret = igb_get_ntuple_filter(dev,
4667                         (struct rte_eth_ntuple_filter *)arg);
4668                 break;
4669         default:
4670                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4671                 ret = -EINVAL;
4672                 break;
4673         }
4674         return ret;
4675 }
4676
4677 static inline int
4678 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4679                         uint16_t ethertype)
4680 {
4681         int i;
4682
4683         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4684                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4685                     (filter_info->ethertype_mask & (1 << i)))
4686                         return i;
4687         }
4688         return -1;
4689 }
4690
4691 static inline int
4692 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4693                         uint16_t ethertype, uint32_t etqf)
4694 {
4695         int i;
4696
4697         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4698                 if (!(filter_info->ethertype_mask & (1 << i))) {
4699                         filter_info->ethertype_mask |= 1 << i;
4700                         filter_info->ethertype_filters[i].ethertype = ethertype;
4701                         filter_info->ethertype_filters[i].etqf = etqf;
4702                         return i;
4703                 }
4704         }
4705         return -1;
4706 }
4707
4708 int
4709 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4710                         uint8_t idx)
4711 {
4712         if (idx >= E1000_MAX_ETQF_FILTERS)
4713                 return -1;
4714         filter_info->ethertype_mask &= ~(1 << idx);
4715         filter_info->ethertype_filters[idx].ethertype = 0;
4716         filter_info->ethertype_filters[idx].etqf = 0;
4717         return idx;
4718 }
4719
4720
4721 int
4722 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4723                         struct rte_eth_ethertype_filter *filter,
4724                         bool add)
4725 {
4726         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4727         struct e1000_filter_info *filter_info =
4728                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4729         uint32_t etqf = 0;
4730         int ret;
4731
4732         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4733                 filter->ether_type == ETHER_TYPE_IPv6) {
4734                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4735                         " ethertype filter.", filter->ether_type);
4736                 return -EINVAL;
4737         }
4738
4739         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4740                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4741                 return -EINVAL;
4742         }
4743         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4744                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4745                 return -EINVAL;
4746         }
4747
4748         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4749         if (ret >= 0 && add) {
4750                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4751                             filter->ether_type);
4752                 return -EEXIST;
4753         }
4754         if (ret < 0 && !add) {
4755                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4756                             filter->ether_type);
4757                 return -ENOENT;
4758         }
4759
4760         if (add) {
4761                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4762                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4763                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4764                 ret = igb_ethertype_filter_insert(filter_info,
4765                                 filter->ether_type, etqf);
4766                 if (ret < 0) {
4767                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4768                         return -ENOSYS;
4769                 }
4770         } else {
4771                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4772                 if (ret < 0)
4773                         return -ENOSYS;
4774         }
4775         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4776         E1000_WRITE_FLUSH(hw);
4777
4778         return 0;
4779 }
4780
4781 static int
4782 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4783                         struct rte_eth_ethertype_filter *filter)
4784 {
4785         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4786         struct e1000_filter_info *filter_info =
4787                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4788         uint32_t etqf;
4789         int ret;
4790
4791         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4792         if (ret < 0) {
4793                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4794                             filter->ether_type);
4795                 return -ENOENT;
4796         }
4797
4798         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4799         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4800                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4801                 filter->flags = 0;
4802                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4803                                 E1000_ETQF_QUEUE_SHIFT;
4804                 return 0;
4805         }
4806
4807         return -ENOENT;
4808 }
4809
4810 /*
4811  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4812  * @dev: pointer to rte_eth_dev structure
4813  * @filter_op:operation will be taken.
4814  * @arg: a pointer to specific structure corresponding to the filter_op
4815  */
4816 static int
4817 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4818                                 enum rte_filter_op filter_op,
4819                                 void *arg)
4820 {
4821         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4822         int ret;
4823
4824         MAC_TYPE_FILTER_SUP(hw->mac.type);
4825
4826         if (filter_op == RTE_ETH_FILTER_NOP)
4827                 return 0;
4828
4829         if (arg == NULL) {
4830                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4831                             filter_op);
4832                 return -EINVAL;
4833         }
4834
4835         switch (filter_op) {
4836         case RTE_ETH_FILTER_ADD:
4837                 ret = igb_add_del_ethertype_filter(dev,
4838                         (struct rte_eth_ethertype_filter *)arg,
4839                         TRUE);
4840                 break;
4841         case RTE_ETH_FILTER_DELETE:
4842                 ret = igb_add_del_ethertype_filter(dev,
4843                         (struct rte_eth_ethertype_filter *)arg,
4844                         FALSE);
4845                 break;
4846         case RTE_ETH_FILTER_GET:
4847                 ret = igb_get_ethertype_filter(dev,
4848                         (struct rte_eth_ethertype_filter *)arg);
4849                 break;
4850         default:
4851                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4852                 ret = -EINVAL;
4853                 break;
4854         }
4855         return ret;
4856 }
4857
4858 static int
4859 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4860                      enum rte_filter_type filter_type,
4861                      enum rte_filter_op filter_op,
4862                      void *arg)
4863 {
4864         int ret = 0;
4865
4866         switch (filter_type) {
4867         case RTE_ETH_FILTER_NTUPLE:
4868                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4869                 break;
4870         case RTE_ETH_FILTER_ETHERTYPE:
4871                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4872                 break;
4873         case RTE_ETH_FILTER_SYN:
4874                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4875                 break;
4876         case RTE_ETH_FILTER_FLEXIBLE:
4877                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4878                 break;
4879         case RTE_ETH_FILTER_GENERIC:
4880                 if (filter_op != RTE_ETH_FILTER_GET)
4881                         return -EINVAL;
4882                 *(const void **)arg = &igb_flow_ops;
4883                 break;
4884         default:
4885                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4886                                                         filter_type);
4887                 break;
4888         }
4889
4890         return ret;
4891 }
4892
4893 static int
4894 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4895                          struct ether_addr *mc_addr_set,
4896                          uint32_t nb_mc_addr)
4897 {
4898         struct e1000_hw *hw;
4899
4900         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4901         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4902         return 0;
4903 }
4904
4905 static uint64_t
4906 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4907 {
4908         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4909         uint64_t systime_cycles;
4910
4911         switch (hw->mac.type) {
4912         case e1000_i210:
4913         case e1000_i211:
4914                 /*
4915                  * Need to read System Time Residue Register to be able
4916                  * to read the other two registers.
4917                  */
4918                 E1000_READ_REG(hw, E1000_SYSTIMR);
4919                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4920                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4921                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4922                                 * NSEC_PER_SEC;
4923                 break;
4924         case e1000_82580:
4925         case e1000_i350:
4926         case e1000_i354:
4927                 /*
4928                  * Need to read System Time Residue Register to be able
4929                  * to read the other two registers.
4930                  */
4931                 E1000_READ_REG(hw, E1000_SYSTIMR);
4932                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4933                 /* Only the 8 LSB are valid. */
4934                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4935                                 & 0xff) << 32;
4936                 break;
4937         default:
4938                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4939                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4940                                 << 32;
4941                 break;
4942         }
4943
4944         return systime_cycles;
4945 }
4946
4947 static uint64_t
4948 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4949 {
4950         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4951         uint64_t rx_tstamp_cycles;
4952
4953         switch (hw->mac.type) {
4954         case e1000_i210:
4955         case e1000_i211:
4956                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4957                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4958                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4959                                 * NSEC_PER_SEC;
4960                 break;
4961         case e1000_82580:
4962         case e1000_i350:
4963         case e1000_i354:
4964                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4965                 /* Only the 8 LSB are valid. */
4966                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4967                                 & 0xff) << 32;
4968                 break;
4969         default:
4970                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4971                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4972                                 << 32;
4973                 break;
4974         }
4975
4976         return rx_tstamp_cycles;
4977 }
4978
4979 static uint64_t
4980 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4981 {
4982         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4983         uint64_t tx_tstamp_cycles;
4984
4985         switch (hw->mac.type) {
4986         case e1000_i210:
4987         case e1000_i211:
4988                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4989                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4990                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4991                                 * NSEC_PER_SEC;
4992                 break;
4993         case e1000_82580:
4994         case e1000_i350:
4995         case e1000_i354:
4996                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4997                 /* Only the 8 LSB are valid. */
4998                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4999                                 & 0xff) << 32;
5000                 break;
5001         default:
5002                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5003                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5004                                 << 32;
5005                 break;
5006         }
5007
5008         return tx_tstamp_cycles;
5009 }
5010
5011 static void
5012 igb_start_timecounters(struct rte_eth_dev *dev)
5013 {
5014         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5015         struct e1000_adapter *adapter =
5016                 (struct e1000_adapter *)dev->data->dev_private;
5017         uint32_t incval = 1;
5018         uint32_t shift = 0;
5019         uint64_t mask = E1000_CYCLECOUNTER_MASK;
5020
5021         switch (hw->mac.type) {
5022         case e1000_82580:
5023         case e1000_i350:
5024         case e1000_i354:
5025                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5026                 mask = (1ULL << 40) - 1;
5027                 /* fall-through */
5028         case e1000_i210:
5029         case e1000_i211:
5030                 /*
5031                  * Start incrementing the register
5032                  * used to timestamp PTP packets.
5033                  */
5034                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5035                 break;
5036         case e1000_82576:
5037                 incval = E1000_INCVALUE_82576;
5038                 shift = IGB_82576_TSYNC_SHIFT;
5039                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5040                                 E1000_INCPERIOD_82576 | incval);
5041                 break;
5042         default:
5043                 /* Not supported */
5044                 return;
5045         }
5046
5047         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5048         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5049         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5050
5051         adapter->systime_tc.cc_mask = mask;
5052         adapter->systime_tc.cc_shift = shift;
5053         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5054
5055         adapter->rx_tstamp_tc.cc_mask = mask;
5056         adapter->rx_tstamp_tc.cc_shift = shift;
5057         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5058
5059         adapter->tx_tstamp_tc.cc_mask = mask;
5060         adapter->tx_tstamp_tc.cc_shift = shift;
5061         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5062 }
5063
5064 static int
5065 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5066 {
5067         struct e1000_adapter *adapter =
5068                         (struct e1000_adapter *)dev->data->dev_private;
5069
5070         adapter->systime_tc.nsec += delta;
5071         adapter->rx_tstamp_tc.nsec += delta;
5072         adapter->tx_tstamp_tc.nsec += delta;
5073
5074         return 0;
5075 }
5076
5077 static int
5078 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5079 {
5080         uint64_t ns;
5081         struct e1000_adapter *adapter =
5082                         (struct e1000_adapter *)dev->data->dev_private;
5083
5084         ns = rte_timespec_to_ns(ts);
5085
5086         /* Set the timecounters to a new value. */
5087         adapter->systime_tc.nsec = ns;
5088         adapter->rx_tstamp_tc.nsec = ns;
5089         adapter->tx_tstamp_tc.nsec = ns;
5090
5091         return 0;
5092 }
5093
5094 static int
5095 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5096 {
5097         uint64_t ns, systime_cycles;
5098         struct e1000_adapter *adapter =
5099                         (struct e1000_adapter *)dev->data->dev_private;
5100
5101         systime_cycles = igb_read_systime_cyclecounter(dev);
5102         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5103         *ts = rte_ns_to_timespec(ns);
5104
5105         return 0;
5106 }
5107
5108 static int
5109 igb_timesync_enable(struct rte_eth_dev *dev)
5110 {
5111         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5112         uint32_t tsync_ctl;
5113         uint32_t tsauxc;
5114
5115         /* Stop the timesync system time. */
5116         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5117         /* Reset the timesync system time value. */
5118         switch (hw->mac.type) {
5119         case e1000_82580:
5120         case e1000_i350:
5121         case e1000_i354:
5122         case e1000_i210:
5123         case e1000_i211:
5124                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5125                 /* fall-through */
5126         case e1000_82576:
5127                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5128                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5129                 break;
5130         default:
5131                 /* Not supported. */
5132                 return -ENOTSUP;
5133         }
5134
5135         /* Enable system time for it isn't on by default. */
5136         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5137         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5138         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5139
5140         igb_start_timecounters(dev);
5141
5142         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5143         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5144                         (ETHER_TYPE_1588 |
5145                          E1000_ETQF_FILTER_ENABLE |
5146                          E1000_ETQF_1588));
5147
5148         /* Enable timestamping of received PTP packets. */
5149         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5150         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5151         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5152
5153         /* Enable Timestamping of transmitted PTP packets. */
5154         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5155         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5156         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5157
5158         return 0;
5159 }
5160
5161 static int
5162 igb_timesync_disable(struct rte_eth_dev *dev)
5163 {
5164         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5165         uint32_t tsync_ctl;
5166
5167         /* Disable timestamping of transmitted PTP packets. */
5168         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5169         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5170         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5171
5172         /* Disable timestamping of received PTP packets. */
5173         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5174         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5175         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5176
5177         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5178         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5179
5180         /* Stop incrementating the System Time registers. */
5181         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5182
5183         return 0;
5184 }
5185
5186 static int
5187 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5188                                struct timespec *timestamp,
5189                                uint32_t flags __rte_unused)
5190 {
5191         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5192         struct e1000_adapter *adapter =
5193                         (struct e1000_adapter *)dev->data->dev_private;
5194         uint32_t tsync_rxctl;
5195         uint64_t rx_tstamp_cycles;
5196         uint64_t ns;
5197
5198         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5199         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5200                 return -EINVAL;
5201
5202         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5203         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5204         *timestamp = rte_ns_to_timespec(ns);
5205
5206         return  0;
5207 }
5208
5209 static int
5210 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5211                                struct timespec *timestamp)
5212 {
5213         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5214         struct e1000_adapter *adapter =
5215                         (struct e1000_adapter *)dev->data->dev_private;
5216         uint32_t tsync_txctl;
5217         uint64_t tx_tstamp_cycles;
5218         uint64_t ns;
5219
5220         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5221         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5222                 return -EINVAL;
5223
5224         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5225         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5226         *timestamp = rte_ns_to_timespec(ns);
5227
5228         return  0;
5229 }
5230
5231 static int
5232 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5233 {
5234         int count = 0;
5235         int g_ind = 0;
5236         const struct reg_info *reg_group;
5237
5238         while ((reg_group = igb_regs[g_ind++]))
5239                 count += igb_reg_group_count(reg_group);
5240
5241         return count;
5242 }
5243
5244 static int
5245 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5246 {
5247         int count = 0;
5248         int g_ind = 0;
5249         const struct reg_info *reg_group;
5250
5251         while ((reg_group = igbvf_regs[g_ind++]))
5252                 count += igb_reg_group_count(reg_group);
5253
5254         return count;
5255 }
5256
5257 static int
5258 eth_igb_get_regs(struct rte_eth_dev *dev,
5259         struct rte_dev_reg_info *regs)
5260 {
5261         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5262         uint32_t *data = regs->data;
5263         int g_ind = 0;
5264         int count = 0;
5265         const struct reg_info *reg_group;
5266
5267         if (data == NULL) {
5268                 regs->length = eth_igb_get_reg_length(dev);
5269                 regs->width = sizeof(uint32_t);
5270                 return 0;
5271         }
5272
5273         /* Support only full register dump */
5274         if ((regs->length == 0) ||
5275             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5276                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5277                         hw->device_id;
5278                 while ((reg_group = igb_regs[g_ind++]))
5279                         count += igb_read_regs_group(dev, &data[count],
5280                                                         reg_group);
5281                 return 0;
5282         }
5283
5284         return -ENOTSUP;
5285 }
5286
5287 static int
5288 igbvf_get_regs(struct rte_eth_dev *dev,
5289         struct rte_dev_reg_info *regs)
5290 {
5291         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5292         uint32_t *data = regs->data;
5293         int g_ind = 0;
5294         int count = 0;
5295         const struct reg_info *reg_group;
5296
5297         if (data == NULL) {
5298                 regs->length = igbvf_get_reg_length(dev);
5299                 regs->width = sizeof(uint32_t);
5300                 return 0;
5301         }
5302
5303         /* Support only full register dump */
5304         if ((regs->length == 0) ||
5305             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5306                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5307                         hw->device_id;
5308                 while ((reg_group = igbvf_regs[g_ind++]))
5309                         count += igb_read_regs_group(dev, &data[count],
5310                                                         reg_group);
5311                 return 0;
5312         }
5313
5314         return -ENOTSUP;
5315 }
5316
5317 static int
5318 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5319 {
5320         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5321
5322         /* Return unit is byte count */
5323         return hw->nvm.word_size * 2;
5324 }
5325
5326 static int
5327 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5328         struct rte_dev_eeprom_info *in_eeprom)
5329 {
5330         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5331         struct e1000_nvm_info *nvm = &hw->nvm;
5332         uint16_t *data = in_eeprom->data;
5333         int first, length;
5334
5335         first = in_eeprom->offset >> 1;
5336         length = in_eeprom->length >> 1;
5337         if ((first >= hw->nvm.word_size) ||
5338             ((first + length) >= hw->nvm.word_size))
5339                 return -EINVAL;
5340
5341         in_eeprom->magic = hw->vendor_id |
5342                 ((uint32_t)hw->device_id << 16);
5343
5344         if ((nvm->ops.read) == NULL)
5345                 return -ENOTSUP;
5346
5347         return nvm->ops.read(hw, first, length, data);
5348 }
5349
5350 static int
5351 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5352         struct rte_dev_eeprom_info *in_eeprom)
5353 {
5354         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5355         struct e1000_nvm_info *nvm = &hw->nvm;
5356         uint16_t *data = in_eeprom->data;
5357         int first, length;
5358
5359         first = in_eeprom->offset >> 1;
5360         length = in_eeprom->length >> 1;
5361         if ((first >= hw->nvm.word_size) ||
5362             ((first + length) >= hw->nvm.word_size))
5363                 return -EINVAL;
5364
5365         in_eeprom->magic = (uint32_t)hw->vendor_id |
5366                 ((uint32_t)hw->device_id << 16);
5367
5368         if ((nvm->ops.write) == NULL)
5369                 return -ENOTSUP;
5370         return nvm->ops.write(hw,  first, length, data);
5371 }
5372
5373 static int
5374 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5375 {
5376         struct e1000_hw *hw =
5377                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5378         uint32_t mask = 1 << queue_id;
5379
5380         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5381         E1000_WRITE_FLUSH(hw);
5382
5383         return 0;
5384 }
5385
5386 static int
5387 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5388 {
5389         struct e1000_hw *hw =
5390                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5391         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5392         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5393         uint32_t mask = 1 << queue_id;
5394         uint32_t regval;
5395
5396         regval = E1000_READ_REG(hw, E1000_EIMS);
5397         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5398         E1000_WRITE_FLUSH(hw);
5399
5400         rte_intr_enable(intr_handle);
5401
5402         return 0;
5403 }
5404
5405 static void
5406 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5407                    uint8_t index, uint8_t offset)
5408 {
5409         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5410
5411         /* clear bits */
5412         val &= ~((uint32_t)0xFF << offset);
5413
5414         /* write vector and valid bit */
5415         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5416
5417         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5418 }
5419
5420 static void
5421 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5422                            uint8_t queue, uint8_t msix_vector)
5423 {
5424         uint32_t tmp = 0;
5425
5426         if (hw->mac.type == e1000_82575) {
5427                 if (direction == 0)
5428                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5429                 else if (direction == 1)
5430                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5431                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5432         } else if (hw->mac.type == e1000_82576) {
5433                 if ((direction == 0) || (direction == 1))
5434                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5435                                            ((queue & 0x8) << 1) +
5436                                            8 * direction);
5437         } else if ((hw->mac.type == e1000_82580) ||
5438                         (hw->mac.type == e1000_i350) ||
5439                         (hw->mac.type == e1000_i354) ||
5440                         (hw->mac.type == e1000_i210) ||
5441                         (hw->mac.type == e1000_i211)) {
5442                 if ((direction == 0) || (direction == 1))
5443                         eth_igb_write_ivar(hw, msix_vector,
5444                                            queue >> 1,
5445                                            ((queue & 0x1) << 4) +
5446                                            8 * direction);
5447         }
5448 }
5449
5450 /* Sets up the hardware to generate MSI-X interrupts properly
5451  * @hw
5452  *  board private structure
5453  */
5454 static void
5455 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5456 {
5457         int queue_id;
5458         uint32_t tmpval, regval, intr_mask;
5459         struct e1000_hw *hw =
5460                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5461         uint32_t vec = E1000_MISC_VEC_ID;
5462         uint32_t base = E1000_MISC_VEC_ID;
5463         uint32_t misc_shift = 0;
5464         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5465         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5466
5467         /* won't configure msix register if no mapping is done
5468          * between intr vector and event fd
5469          */
5470         if (!rte_intr_dp_is_en(intr_handle))
5471                 return;
5472
5473         if (rte_intr_allow_others(intr_handle)) {
5474                 vec = base = E1000_RX_VEC_START;
5475                 misc_shift = 1;
5476         }
5477
5478         /* set interrupt vector for other causes */
5479         if (hw->mac.type == e1000_82575) {
5480                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5481                 /* enable MSI-X PBA support */
5482                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5483
5484                 /* Auto-Mask interrupts upon ICR read */
5485                 tmpval |= E1000_CTRL_EXT_EIAME;
5486                 tmpval |= E1000_CTRL_EXT_IRCA;
5487
5488                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5489
5490                 /* enable msix_other interrupt */
5491                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5492                 regval = E1000_READ_REG(hw, E1000_EIAC);
5493                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5494                 regval = E1000_READ_REG(hw, E1000_EIAM);
5495                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5496         } else if ((hw->mac.type == e1000_82576) ||
5497                         (hw->mac.type == e1000_82580) ||
5498                         (hw->mac.type == e1000_i350) ||
5499                         (hw->mac.type == e1000_i354) ||
5500                         (hw->mac.type == e1000_i210) ||
5501                         (hw->mac.type == e1000_i211)) {
5502                 /* turn on MSI-X capability first */
5503                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5504                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5505                                         E1000_GPIE_NSICR);
5506                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5507                         misc_shift;
5508                 regval = E1000_READ_REG(hw, E1000_EIAC);
5509                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5510
5511                 /* enable msix_other interrupt */
5512                 regval = E1000_READ_REG(hw, E1000_EIMS);
5513                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5514                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5515                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5516         }
5517
5518         /* use EIAM to auto-mask when MSI-X interrupt
5519          * is asserted, this saves a register write for every interrupt
5520          */
5521         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5522                 misc_shift;
5523         regval = E1000_READ_REG(hw, E1000_EIAM);
5524         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5525
5526         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5527                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5528                 intr_handle->intr_vec[queue_id] = vec;
5529                 if (vec < base + intr_handle->nb_efd - 1)
5530                         vec++;
5531         }
5532
5533         E1000_WRITE_FLUSH(hw);
5534 }
5535
5536 /* restore n-tuple filter */
5537 static inline void
5538 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5539 {
5540         struct e1000_filter_info *filter_info =
5541                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5542         struct e1000_5tuple_filter *p_5tuple;
5543         struct e1000_2tuple_filter *p_2tuple;
5544
5545         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5546                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5547         }
5548
5549         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5550                 igb_inject_2uple_filter(dev, p_2tuple);
5551         }
5552 }
5553
5554 /* restore SYN filter */
5555 static inline void
5556 igb_syn_filter_restore(struct rte_eth_dev *dev)
5557 {
5558         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5559         struct e1000_filter_info *filter_info =
5560                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5561         uint32_t synqf;
5562
5563         synqf = filter_info->syn_info;
5564
5565         if (synqf & E1000_SYN_FILTER_ENABLE) {
5566                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5567                 E1000_WRITE_FLUSH(hw);
5568         }
5569 }
5570
5571 /* restore ethernet type filter */
5572 static inline void
5573 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5574 {
5575         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5576         struct e1000_filter_info *filter_info =
5577                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5578         int i;
5579
5580         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5581                 if (filter_info->ethertype_mask & (1 << i)) {
5582                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5583                                 filter_info->ethertype_filters[i].etqf);
5584                         E1000_WRITE_FLUSH(hw);
5585                 }
5586         }
5587 }
5588
5589 /* restore flex byte filter */
5590 static inline void
5591 igb_flex_filter_restore(struct rte_eth_dev *dev)
5592 {
5593         struct e1000_filter_info *filter_info =
5594                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5595         struct e1000_flex_filter *flex_filter;
5596
5597         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5598                 igb_inject_flex_filter(dev, flex_filter);
5599         }
5600 }
5601
5602 /* restore all types filter */
5603 static int
5604 igb_filter_restore(struct rte_eth_dev *dev)
5605 {
5606         igb_ntuple_filter_restore(dev);
5607         igb_ethertype_filter_restore(dev);
5608         igb_syn_filter_restore(dev);
5609         igb_flex_filter_restore(dev);
5610
5611         return 0;
5612 }
5613
5614 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5615 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5616 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5617 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5618 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5619 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");