drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64
  65 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  66 #define IGB_DEFAULT_RX_HTHRESH      8
  67 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  68
  69 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  70 #define IGB_DEFAULT_TX_HTHRESH      1
  71 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  72
  73 #define IGB_HKEY_MAX_INDEX 10
  74
  75 /* Bit shift and mask */
  76 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  77 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  78 #define IGB_8_BIT_WIDTH  CHAR_BIT
  79 #define IGB_8_BIT_MASK   UINT8_MAX
  80
  81 /* Additional timesync values. */
  82 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  83 #define E1000_ETQF_FILTER_1588       3
  84 #define IGB_82576_TSYNC_SHIFT        16
  85 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  86 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  88
  89 #define E1000_VTIVAR_MISC                0x01740
  90 #define E1000_VTIVAR_MISC_MASK           0xFF
  91 #define E1000_VTIVAR_VALID               0x80
  92 #define E1000_VTIVAR_MISC_MAILBOX        0
  93 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  94
  95 /* External VLAN Enable bit mask */
  96 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  97
  98 /* External VLAN Ether Type bit mask and shift */
  99 #define E1000_VET_VET_EXT            0xFFFF0000
 100 #define E1000_VET_VET_EXT_SHIFT      16
 101
 102 static int  eth_igb_configure(struct rte_eth_dev *dev);
 103 static int  eth_igb_start(struct rte_eth_dev *dev);
 104 static void eth_igb_stop(struct rte_eth_dev *dev);
 105 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 107 static void eth_igb_close(struct rte_eth_dev *dev);
 108 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 110 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 112 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 113                                 int wait_to_complete);
 114 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 115                                 struct rte_eth_stats *rte_stats);
 116 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 117                               struct rte_eth_xstat *xstats, unsigned n);
 118 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 119                                     struct rte_eth_xstat_name *xstats_names,
 120                                     unsigned limit);
 121 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 122 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 123 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 124                               struct rte_eth_dev_info *dev_info);
 125 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 126 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 127                                 struct rte_eth_dev_info *dev_info);
 128 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 129                                 struct rte_eth_fc_conf *fc_conf);
 130 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 131                                 struct rte_eth_fc_conf *fc_conf);
 132 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 133 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 134 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 135 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 136 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 137                                                         void *param);
 138 static int  igb_hardware_init(struct e1000_hw *hw);
 139 static void igb_hw_control_acquire(struct e1000_hw *hw);
 140 static void igb_hw_control_release(struct e1000_hw *hw);
 141 static void igb_init_manageability(struct e1000_hw *hw);
 142 static void igb_release_manageability(struct e1000_hw *hw);
 143
 144 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 145
 146 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 147                 uint16_t vlan_id, int on);
 148 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 149                                  enum rte_vlan_type vlan_type,
 150                                  uint16_t tpid_id);
 151 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 152
 153 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 154 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 155 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 156 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 157 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 158 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 159
 160 static int eth_igb_led_on(struct rte_eth_dev *dev);
 161 static int eth_igb_led_off(struct rte_eth_dev *dev);
 162
 163 static void igb_intr_disable(struct e1000_hw *hw);
 164 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 165 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 166                 struct ether_addr *mac_addr,
 167                 uint32_t index, uint32_t pool);
 168 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 169 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 170                 struct ether_addr *addr);
 171
 172 static void igbvf_intr_disable(struct e1000_hw *hw);
 173 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 174 static int igbvf_dev_start(struct rte_eth_dev *dev);
 175 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 176 static void igbvf_dev_close(struct rte_eth_dev *dev);
 177 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 178 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 179 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 180 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 181 static int eth_igbvf_link_update(struct e1000_hw *hw);
 182 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_stats *rte_stats);
 184 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 185                                 struct rte_eth_xstat *xstats, unsigned n);
 186 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 187                                       struct rte_eth_xstat_name *xstats_names,
 188                                       unsigned limit);
 189 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 190 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 191                 uint16_t vlan_id, int on);
 192 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 193 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 194 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 195                 struct ether_addr *addr);
 196 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 197 static int igbvf_get_regs(struct rte_eth_dev *dev,
 198                 struct rte_dev_reg_info *regs);
 199
 200 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 201                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 202                                    uint16_t reta_size);
 203 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 204                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 205                                   uint16_t reta_size);
 206
 207 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 208                         struct rte_eth_syn_filter *filter,
 209                         bool add);
 210 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 211                         struct rte_eth_syn_filter *filter);
 212 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 213                         enum rte_filter_op filter_op,
 214                         void *arg);
 215 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ntuple_filter *ntuple_filter);
 217 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 218                         struct rte_eth_ntuple_filter *ntuple_filter);
 219 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 220                         struct rte_eth_flex_filter *filter,
 221                         bool add);
 222 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 223                         struct rte_eth_flex_filter *filter);
 224 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 225                         enum rte_filter_op filter_op,
 226                         void *arg);
 227 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 228                         struct rte_eth_ntuple_filter *ntuple_filter);
 229 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 230                         struct rte_eth_ntuple_filter *ntuple_filter);
 231 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 232                         struct rte_eth_ntuple_filter *filter,
 233                         bool add);
 234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 235                         struct rte_eth_ntuple_filter *filter);
 236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 237                                 enum rte_filter_op filter_op,
 238                                 void *arg);
 239 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 240                         struct rte_eth_ethertype_filter *filter,
 241                         bool add);
 242 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 243                                 enum rte_filter_op filter_op,
 244                                 void *arg);
 245 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 246                         struct rte_eth_ethertype_filter *filter);
 247 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 248                      enum rte_filter_type filter_type,
 249                      enum rte_filter_op filter_op,
 250                      void *arg);
 251 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 252 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 253                 struct rte_dev_reg_info *regs);
 254 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 255 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 256                 struct rte_dev_eeprom_info *eeprom);
 257 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 258                 struct rte_dev_eeprom_info *eeprom);
 259 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 260                                     struct ether_addr *mc_addr_set,
 261                                     uint32_t nb_mc_addr);
 262 static int igb_timesync_enable(struct rte_eth_dev *dev);
 263 static int igb_timesync_disable(struct rte_eth_dev *dev);
 264 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 265                                           struct timespec *timestamp,
 266                                           uint32_t flags);
 267 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 268                                           struct timespec *timestamp);
 269 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 270 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 271                                   struct timespec *timestamp);
 272 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 273                                    const struct timespec *timestamp);
 274 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 275                                         uint16_t queue_id);
 276 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 277                                          uint16_t queue_id);
 278 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 279                                        uint8_t queue, uint8_t msix_vector);
 280 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 281                                uint8_t index, uint8_t offset);
 282 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 283 static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
 284                                         void *param);
 285 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 286
 287 /*
 288  * Define VF Stats MACRO for Non "cleared on read" register
 289  */
 290 #define UPDATE_VF_STAT(reg, last, cur)            \
 291 {                                                 \
 292         u32 latest = E1000_READ_REG(hw, reg);     \
 293         cur += (latest - last) & UINT_MAX;        \
 294         last = latest;                            \
 295 }
 296
 297 #define IGB_FC_PAUSE_TIME 0x0680
 298 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 299 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 300
 301 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 302
 303 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 304
 305 /*
 306  * The set of PCI devices this driver supports
 307  */
 308 static const struct rte_pci_id pci_id_igb_map[] = {
 309
 310 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 311 #include "rte_pci_dev_ids.h"
 312
 313 {0},
 314 };
 315
 316 /*
 317  * The set of PCI devices this driver supports (for 82576&I350 VF)
 318  */
 319 static const struct rte_pci_id pci_id_igbvf_map[] = {
 320
 321 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 322 #include "rte_pci_dev_ids.h"
 323
 324 {0},
 325 };
 326
 327 static const struct rte_eth_desc_lim rx_desc_lim = {
 328         .nb_max = E1000_MAX_RING_DESC,
 329         .nb_min = E1000_MIN_RING_DESC,
 330         .nb_align = IGB_RXD_ALIGN,
 331 };
 332
 333 static const struct rte_eth_desc_lim tx_desc_lim = {
 334         .nb_max = E1000_MAX_RING_DESC,
 335         .nb_min = E1000_MIN_RING_DESC,
 336         .nb_align = IGB_RXD_ALIGN,
 337 };
 338
 339 static const struct eth_dev_ops eth_igb_ops = {
 340         .dev_configure        = eth_igb_configure,
 341         .dev_start            = eth_igb_start,
 342         .dev_stop             = eth_igb_stop,
 343         .dev_set_link_up      = eth_igb_dev_set_link_up,
 344         .dev_set_link_down    = eth_igb_dev_set_link_down,
 345         .dev_close            = eth_igb_close,
 346         .promiscuous_enable   = eth_igb_promiscuous_enable,
 347         .promiscuous_disable  = eth_igb_promiscuous_disable,
 348         .allmulticast_enable  = eth_igb_allmulticast_enable,
 349         .allmulticast_disable = eth_igb_allmulticast_disable,
 350         .link_update          = eth_igb_link_update,
 351         .stats_get            = eth_igb_stats_get,
 352         .xstats_get           = eth_igb_xstats_get,
 353         .xstats_get_names     = eth_igb_xstats_get_names,
 354         .stats_reset          = eth_igb_stats_reset,
 355         .xstats_reset         = eth_igb_xstats_reset,
 356         .dev_infos_get        = eth_igb_infos_get,
 357         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 358         .mtu_set              = eth_igb_mtu_set,
 359         .vlan_filter_set      = eth_igb_vlan_filter_set,
 360         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 361         .vlan_offload_set     = eth_igb_vlan_offload_set,
 362         .rx_queue_setup       = eth_igb_rx_queue_setup,
 363         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 364         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 365         .rx_queue_release     = eth_igb_rx_queue_release,
 366         .rx_queue_count       = eth_igb_rx_queue_count,
 367         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 368         .tx_queue_setup       = eth_igb_tx_queue_setup,
 369         .tx_queue_release     = eth_igb_tx_queue_release,
 370         .dev_led_on           = eth_igb_led_on,
 371         .dev_led_off          = eth_igb_led_off,
 372         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 373         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 374         .mac_addr_add         = eth_igb_rar_set,
 375         .mac_addr_remove      = eth_igb_rar_clear,
 376         .mac_addr_set         = eth_igb_default_mac_addr_set,
 377         .reta_update          = eth_igb_rss_reta_update,
 378         .reta_query           = eth_igb_rss_reta_query,
 379         .rss_hash_update      = eth_igb_rss_hash_update,
 380         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 381         .filter_ctrl          = eth_igb_filter_ctrl,
 382         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 383         .rxq_info_get         = igb_rxq_info_get,
 384         .txq_info_get         = igb_txq_info_get,
 385         .timesync_enable      = igb_timesync_enable,
 386         .timesync_disable     = igb_timesync_disable,
 387         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 388         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 389         .get_reg_length       = eth_igb_get_reg_length,
 390         .get_reg              = eth_igb_get_regs,
 391         .get_eeprom_length    = eth_igb_get_eeprom_length,
 392         .get_eeprom           = eth_igb_get_eeprom,
 393         .set_eeprom           = eth_igb_set_eeprom,
 394         .timesync_adjust_time = igb_timesync_adjust_time,
 395         .timesync_read_time   = igb_timesync_read_time,
 396         .timesync_write_time  = igb_timesync_write_time,
 397 };
 398
 399 /*
 400  * dev_ops for virtual function, bare necessities for basic vf
 401  * operation have been implemented
 402  */
 403 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 404         .dev_configure        = igbvf_dev_configure,
 405         .dev_start            = igbvf_dev_start,
 406         .dev_stop             = igbvf_dev_stop,
 407         .dev_close            = igbvf_dev_close,
 408         .promiscuous_enable   = igbvf_promiscuous_enable,
 409         .promiscuous_disable  = igbvf_promiscuous_disable,
 410         .allmulticast_enable  = igbvf_allmulticast_enable,
 411         .allmulticast_disable = igbvf_allmulticast_disable,
 412         .link_update          = eth_igb_link_update,
 413         .stats_get            = eth_igbvf_stats_get,
 414         .xstats_get           = eth_igbvf_xstats_get,
 415         .xstats_get_names     = eth_igbvf_xstats_get_names,
 416         .stats_reset          = eth_igbvf_stats_reset,
 417         .xstats_reset         = eth_igbvf_stats_reset,
 418         .vlan_filter_set      = igbvf_vlan_filter_set,
 419         .dev_infos_get        = eth_igbvf_infos_get,
 420         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 421         .rx_queue_setup       = eth_igb_rx_queue_setup,
 422         .rx_queue_release     = eth_igb_rx_queue_release,
 423         .tx_queue_setup       = eth_igb_tx_queue_setup,
 424         .tx_queue_release     = eth_igb_tx_queue_release,
 425         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 426         .rxq_info_get         = igb_rxq_info_get,
 427         .txq_info_get         = igb_txq_info_get,
 428         .mac_addr_set         = igbvf_default_mac_addr_set,
 429         .get_reg_length       = igbvf_get_reg_length,
 430         .get_reg              = igbvf_get_regs,
 431 };
 432
 433 /* store statistics names and its offset in stats structure */
 434 struct rte_igb_xstats_name_off {
 435         char name[RTE_ETH_XSTATS_NAME_SIZE];
 436         unsigned offset;
 437 };
 438
 439 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 440         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 441         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 442         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 443         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 444         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 445         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 446         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 447                 ecol)},
 448         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 449         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 450         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 451         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 452         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 453         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 454         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 455         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 456         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 457         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 458         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 459                 fcruc)},
 460         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 461         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 462         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 463         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 464         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 465                 prc1023)},
 466         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 467                 prc1522)},
 468         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 469         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 470         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 471         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 472         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 473         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 474         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 475         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 476         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 477         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 478         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 479         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 480         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 481         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 482         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 483         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 484         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 485         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 486                 ptc1023)},
 487         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 488                 ptc1522)},
 489         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 490         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 491         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 492         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 493         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 494         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 495         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 496
 497         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 498 };
 499
 500 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 501                 sizeof(rte_igb_stats_strings[0]))
 502
 503 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 504         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 505         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 506         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 507         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 508         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 509 };
 510
 511 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 512                 sizeof(rte_igbvf_stats_strings[0]))
 513
 514 /**
 515  * Atomically reads the link status information from global
 516  * structure rte_eth_dev.
 517  *
 518  * @param dev
 519  *   - Pointer to the structure rte_eth_dev to read from.
 520  *   - Pointer to the buffer to be saved with the link status.
 521  *
 522  * @return
 523  *   - On success, zero.
 524  *   - On failure, negative value.
 525  */
 526 static inline int
 527 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 528                                 struct rte_eth_link *link)
 529 {
 530         struct rte_eth_link *dst = link;
 531         struct rte_eth_link *src = &(dev->data->dev_link);
 532
 533         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 534                                         *(uint64_t *)src) == 0)
 535                 return -1;
 536
 537         return 0;
 538 }
 539
 540 /**
 541  * Atomically writes the link status information into global
 542  * structure rte_eth_dev.
 543  *
 544  * @param dev
 545  *   - Pointer to the structure rte_eth_dev to read from.
 546  *   - Pointer to the buffer to be saved with the link status.
 547  *
 548  * @return
 549  *   - On success, zero.
 550  *   - On failure, negative value.
 551  */
 552 static inline int
 553 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 554                                 struct rte_eth_link *link)
 555 {
 556         struct rte_eth_link *dst = &(dev->data->dev_link);
 557         struct rte_eth_link *src = link;
 558
 559         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 560                                         *(uint64_t *)src) == 0)
 561                 return -1;
 562
 563         return 0;
 564 }
 565
 566 static inline void
 567 igb_intr_enable(struct rte_eth_dev *dev)
 568 {
 569         struct e1000_interrupt *intr =
 570                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 571         struct e1000_hw *hw =
 572                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 573
 574         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 575         E1000_WRITE_FLUSH(hw);
 576 }
 577
 578 static void
 579 igb_intr_disable(struct e1000_hw *hw)
 580 {
 581         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 582         E1000_WRITE_FLUSH(hw);
 583 }
 584
 585 static inline void
 586 igbvf_intr_enable(struct rte_eth_dev *dev)
 587 {
 588         struct e1000_hw *hw =
 589                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 590
 591         /* only for mailbox */
 592         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 593         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 594         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 595         E1000_WRITE_FLUSH(hw);
 596 }
 597
 598 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 599 static void
 600 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 601 {
 602         uint32_t tmp = 0;
 603
 604         /* mailbox */
 605         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 606         tmp |= E1000_VTIVAR_VALID;
 607         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 608 }
 609
 610 static void
 611 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 612 {
 613         struct e1000_hw *hw =
 614                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 615
 616         /* Configure VF other cause ivar */
 617         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 618 }
 619
 620 static inline int32_t
 621 igb_pf_reset_hw(struct e1000_hw *hw)
 622 {
 623         uint32_t ctrl_ext;
 624         int32_t status;
 625
 626         status = e1000_reset_hw(hw);
 627
 628         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 629         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 630         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 631         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 632         E1000_WRITE_FLUSH(hw);
 633
 634         return status;
 635 }
 636
 637 static void
 638 igb_identify_hardware(struct rte_eth_dev *dev)
 639 {
 640         struct e1000_hw *hw =
 641                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 642
 643         hw->vendor_id = dev->pci_dev->id.vendor_id;
 644         hw->device_id = dev->pci_dev->id.device_id;
 645         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 646         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 647
 648         e1000_set_mac_type(hw);
 649
 650         /* need to check if it is a vf device below */
 651 }
 652
 653 static int
 654 igb_reset_swfw_lock(struct e1000_hw *hw)
 655 {
 656         int ret_val;
 657
 658         /*
 659          * Do mac ops initialization manually here, since we will need
 660          * some function pointers set by this call.
 661          */
 662         ret_val = e1000_init_mac_params(hw);
 663         if (ret_val)
 664                 return ret_val;
 665
 666         /*
 667          * SMBI lock should not fail in this early stage. If this is the case,
 668          * it is due to an improper exit of the application.
 669          * So force the release of the faulty lock.
 670          */
 671         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 672                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 673         }
 674         e1000_put_hw_semaphore_generic(hw);
 675
 676         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 677                 uint16_t mask;
 678
 679                 /*
 680                  * Phy lock should not fail in this early stage. If this is the case,
 681                  * it is due to an improper exit of the application.
 682                  * So force the release of the faulty lock.
 683                  */
 684                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 685                 if (hw->bus.func > E1000_FUNC_1)
 686                         mask <<= 2;
 687                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 688                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 689                                     hw->bus.func);
 690                 }
 691                 hw->mac.ops.release_swfw_sync(hw, mask);
 692
 693                 /*
 694                  * This one is more tricky since it is common to all ports; but
 695                  * swfw_sync retries last long enough (1s) to be almost sure that if
 696                  * lock can not be taken it is due to an improper lock of the
 697                  * semaphore.
 698                  */
 699                 mask = E1000_SWFW_EEP_SM;
 700                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 701                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 702                 }
 703                 hw->mac.ops.release_swfw_sync(hw, mask);
 704         }
 705
 706         return E1000_SUCCESS;
 707 }
 708
 709 static int
 710 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 711 {
 712         int error = 0;
 713         struct rte_pci_device *pci_dev;
 714         struct e1000_hw *hw =
 715                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 716         struct e1000_vfta * shadow_vfta =
 717                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 718         struct e1000_filter_info *filter_info =
 719                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 720         struct e1000_adapter *adapter =
 721                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 722
 723         uint32_t ctrl_ext;
 724
 725         pci_dev = eth_dev->pci_dev;
 726
 727         eth_dev->dev_ops = &eth_igb_ops;
 728         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 729         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 730
 731         /* for secondary processes, we don't initialise any further as primary
 732          * has already done this work. Only check we don't need a different
 733          * RX function */
 734         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 735                 if (eth_dev->data->scattered_rx)
 736                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 737                 return 0;
 738         }
 739
 740         rte_eth_copy_pci_info(eth_dev, pci_dev);
 741
 742         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 743
 744         igb_identify_hardware(eth_dev);
 745         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 746                 error = -EIO;
 747                 goto err_late;
 748         }
 749
 750         e1000_get_bus_info(hw);
 751
 752         /* Reset any pending lock */
 753         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 754                 error = -EIO;
 755                 goto err_late;
 756         }
 757
 758         /* Finish initialization */
 759         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 760                 error = -EIO;
 761                 goto err_late;
 762         }
 763
 764         hw->mac.autoneg = 1;
 765         hw->phy.autoneg_wait_to_complete = 0;
 766         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 767
 768         /* Copper options */
 769         if (hw->phy.media_type == e1000_media_type_copper) {
 770                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 771                 hw->phy.disable_polarity_correction = 0;
 772                 hw->phy.ms_type = e1000_ms_hw_default;
 773         }
 774
 775         /*
 776          * Start from a known state, this is important in reading the nvm
 777          * and mac from that.
 778          */
 779         igb_pf_reset_hw(hw);
 780
 781         /* Make sure we have a good EEPROM before we read from it */
 782         if (e1000_validate_nvm_checksum(hw) < 0) {
 783                 /*
 784                  * Some PCI-E parts fail the first check due to
 785                  * the link being in sleep state, call it again,
 786                  * if it fails a second time its a real issue.
 787                  */
 788                 if (e1000_validate_nvm_checksum(hw) < 0) {
 789                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 790                         error = -EIO;
 791                         goto err_late;
 792                 }
 793         }
 794
 795         /* Read the permanent MAC address out of the EEPROM */
 796         if (e1000_read_mac_addr(hw) != 0) {
 797                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 798                 error = -EIO;
 799                 goto err_late;
 800         }
 801
 802         /* Allocate memory for storing MAC addresses */
 803         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 804                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 805         if (eth_dev->data->mac_addrs == NULL) {
 806                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 807                                                 "store MAC addresses",
 808                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 809                 error = -ENOMEM;
 810                 goto err_late;
 811         }
 812
 813         /* Copy the permanent MAC address */
 814         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 815
 816         /* initialize the vfta */
 817         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 818
 819         /* Now initialize the hardware */
 820         if (igb_hardware_init(hw) != 0) {
 821                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 822                 rte_free(eth_dev->data->mac_addrs);
 823                 eth_dev->data->mac_addrs = NULL;
 824                 error = -ENODEV;
 825                 goto err_late;
 826         }
 827         hw->mac.get_link_status = 1;
 828         adapter->stopped = 0;
 829
 830         /* Indicate SOL/IDER usage */
 831         if (e1000_check_reset_block(hw) < 0) {
 832                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 833                                         "SOL/IDER session");
 834         }
 835
 836         /* initialize PF if max_vfs not zero */
 837         igb_pf_host_init(eth_dev);
 838
 839         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 840         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 841         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 842         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 843         E1000_WRITE_FLUSH(hw);
 844
 845         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 846                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 847                      pci_dev->id.device_id);
 848
 849         rte_intr_callback_register(&pci_dev->intr_handle,
 850                                    eth_igb_interrupt_handler,
 851                                    (void *)eth_dev);
 852
 853         /* enable uio/vfio intr/eventfd mapping */
 854         rte_intr_enable(&pci_dev->intr_handle);
 855
 856         /* enable support intr */
 857         igb_intr_enable(eth_dev);
 858
 859         TAILQ_INIT(&filter_info->flex_list);
 860         filter_info->flex_mask = 0;
 861         TAILQ_INIT(&filter_info->twotuple_list);
 862         filter_info->twotuple_mask = 0;
 863         TAILQ_INIT(&filter_info->fivetuple_list);
 864         filter_info->fivetuple_mask = 0;
 865
 866         return 0;
 867
 868 err_late:
 869         igb_hw_control_release(hw);
 870
 871         return error;
 872 }
 873
 874 static int
 875 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 876 {
 877         struct rte_pci_device *pci_dev;
 878         struct e1000_hw *hw;
 879         struct e1000_adapter *adapter =
 880                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 881
 882         PMD_INIT_FUNC_TRACE();
 883
 884         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 885                 return -EPERM;
 886
 887         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 888         pci_dev = eth_dev->pci_dev;
 889
 890         if (adapter->stopped == 0)
 891                 eth_igb_close(eth_dev);
 892
 893         eth_dev->dev_ops = NULL;
 894         eth_dev->rx_pkt_burst = NULL;
 895         eth_dev->tx_pkt_burst = NULL;
 896
 897         /* Reset any pending lock */
 898         igb_reset_swfw_lock(hw);
 899
 900         rte_free(eth_dev->data->mac_addrs);
 901         eth_dev->data->mac_addrs = NULL;
 902
 903         /* uninitialize PF if max_vfs not zero */
 904         igb_pf_host_uninit(eth_dev);
 905
 906         /* disable uio intr before callback unregister */
 907         rte_intr_disable(&(pci_dev->intr_handle));
 908         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 909                 eth_igb_interrupt_handler, (void *)eth_dev);
 910
 911         return 0;
 912 }
 913
 914 /*
 915  * Virtual Function device init
 916  */
 917 static int
 918 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 919 {
 920         struct rte_pci_device *pci_dev;
 921         struct e1000_adapter *adapter =
 922                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 923         struct e1000_hw *hw =
 924                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 925         int diag;
 926         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 927
 928         PMD_INIT_FUNC_TRACE();
 929
 930         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 931         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 932         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 933
 934         /* for secondary processes, we don't initialise any further as primary
 935          * has already done this work. Only check we don't need a different
 936          * RX function */
 937         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 938                 if (eth_dev->data->scattered_rx)
 939                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 940                 return 0;
 941         }
 942
 943         pci_dev = eth_dev->pci_dev;
 944
 945         rte_eth_copy_pci_info(eth_dev, pci_dev);
 946
 947         hw->device_id = pci_dev->id.device_id;
 948         hw->vendor_id = pci_dev->id.vendor_id;
 949         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 950         adapter->stopped = 0;
 951
 952         /* Initialize the shared code (base driver) */
 953         diag = e1000_setup_init_funcs(hw, TRUE);
 954         if (diag != 0) {
 955                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 956                         diag);
 957                 return -EIO;
 958         }
 959
 960         /* init_mailbox_params */
 961         hw->mbx.ops.init_params(hw);
 962
 963         /* Disable the interrupts for VF */
 964         igbvf_intr_disable(hw);
 965
 966         diag = hw->mac.ops.reset_hw(hw);
 967
 968         /* Allocate memory for storing MAC addresses */
 969         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 970                 hw->mac.rar_entry_count, 0);
 971         if (eth_dev->data->mac_addrs == NULL) {
 972                 PMD_INIT_LOG(ERR,
 973                         "Failed to allocate %d bytes needed to store MAC "
 974                         "addresses",
 975                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 976                 return -ENOMEM;
 977         }
 978
 979         /* Generate a random MAC address, if none was assigned by PF. */
 980         if (is_zero_ether_addr(perm_addr)) {
 981                 eth_random_addr(perm_addr->addr_bytes);
 982                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
 983                 if (diag) {
 984                         rte_free(eth_dev->data->mac_addrs);
 985                         eth_dev->data->mac_addrs = NULL;
 986                         return diag;
 987                 }
 988                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
 989                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
 990                              "%02x:%02x:%02x:%02x:%02x:%02x",
 991                              perm_addr->addr_bytes[0],
 992                              perm_addr->addr_bytes[1],
 993                              perm_addr->addr_bytes[2],
 994                              perm_addr->addr_bytes[3],
 995                              perm_addr->addr_bytes[4],
 996                              perm_addr->addr_bytes[5]);
 997         }
 998
 999         /* Copy the permanent MAC address */
1000         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1001                         &eth_dev->data->mac_addrs[0]);
1002
1003         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1004                      "mac.type=%s",
1005                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1006                      pci_dev->id.device_id, "igb_mac_82576_vf");
1007
1008         rte_intr_callback_register(&pci_dev->intr_handle,
1009                                    eth_igbvf_interrupt_handler,
1010                                    (void *)eth_dev);
1011
1012         return 0;
1013 }
1014
1015 static int
1016 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1017 {
1018         struct e1000_adapter *adapter =
1019                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1020         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1021
1022         PMD_INIT_FUNC_TRACE();
1023
1024         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1025                 return -EPERM;
1026
1027         if (adapter->stopped == 0)
1028                 igbvf_dev_close(eth_dev);
1029
1030         eth_dev->dev_ops = NULL;
1031         eth_dev->rx_pkt_burst = NULL;
1032         eth_dev->tx_pkt_burst = NULL;
1033
1034         rte_free(eth_dev->data->mac_addrs);
1035         eth_dev->data->mac_addrs = NULL;
1036
1037         /* disable uio intr before callback unregister */
1038         rte_intr_disable(&pci_dev->intr_handle);
1039         rte_intr_callback_unregister(&pci_dev->intr_handle,
1040                                      eth_igbvf_interrupt_handler,
1041                                      (void *)eth_dev);
1042
1043         return 0;
1044 }
1045
1046 static struct eth_driver rte_igb_pmd = {
1047         .pci_drv = {
1048                 .name = "rte_igb_pmd",
1049                 .id_table = pci_id_igb_map,
1050                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1051                         RTE_PCI_DRV_DETACHABLE,
1052         },
1053         .eth_dev_init = eth_igb_dev_init,
1054         .eth_dev_uninit = eth_igb_dev_uninit,
1055         .dev_private_size = sizeof(struct e1000_adapter),
1056 };
1057
1058 /*
1059  * virtual function driver struct
1060  */
1061 static struct eth_driver rte_igbvf_pmd = {
1062         .pci_drv = {
1063                 .name = "rte_igbvf_pmd",
1064                 .id_table = pci_id_igbvf_map,
1065                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1066         },
1067         .eth_dev_init = eth_igbvf_dev_init,
1068         .eth_dev_uninit = eth_igbvf_dev_uninit,
1069         .dev_private_size = sizeof(struct e1000_adapter),
1070 };
1071
1072 static int
1073 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1074 {
1075         rte_eth_driver_register(&rte_igb_pmd);
1076         return 0;
1077 }
1078
1079 static void
1080 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1081 {
1082         struct e1000_hw *hw =
1083                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1084         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1085         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1086         rctl |= E1000_RCTL_VFE;
1087         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1088 }
1089
1090 /*
1091  * VF Driver initialization routine.
1092  * Invoked one at EAL init time.
1093  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
1094  */
1095 static int
1096 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1097 {
1098         PMD_INIT_FUNC_TRACE();
1099
1100         rte_eth_driver_register(&rte_igbvf_pmd);
1101         return 0;
1102 }
1103
1104 static int
1105 igb_check_mq_mode(struct rte_eth_dev *dev)
1106 {
1107         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1108         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1109         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1110         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1111
1112         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1113             tx_mq_mode == ETH_MQ_TX_DCB ||
1114             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1115                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1116                 return -EINVAL;
1117         }
1118         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1119                 /* Check multi-queue mode.
1120                  * To no break software we accept ETH_MQ_RX_NONE as this might
1121                  * be used to turn off VLAN filter.
1122                  */
1123
1124                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1125                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1126                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1127                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1128                 } else {
1129                         /* Only support one queue on VFs.
1130                          * RSS together with SRIOV is not supported.
1131                          */
1132                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1133                                         " wrong mq_mode rx %d.",
1134                                         rx_mq_mode);
1135                         return -EINVAL;
1136                 }
1137                 /* TX mode is not used here, so mode might be ignored.*/
1138                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1139                         /* SRIOV only works in VMDq enable mode */
1140                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1141                                         " TX mode %d is not supported. "
1142                                         " Driver will behave as %d mode.",
1143                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1144                 }
1145
1146                 /* check valid queue number */
1147                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1148                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1149                                         " only support one queue on VFs.");
1150                         return -EINVAL;
1151                 }
1152         } else {
1153                 /* To no break software that set invalid mode, only display
1154                  * warning if invalid mode is used.
1155                  */
1156                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1157                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1158                     rx_mq_mode != ETH_MQ_RX_RSS) {
1159                         /* RSS together with VMDq not supported*/
1160                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1161                                      rx_mq_mode);
1162                         return -EINVAL;
1163                 }
1164
1165                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1166                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1167                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1168                                         " Due to txmode is meaningless in this"
1169                                         " driver, just ignore.",
1170                                         tx_mq_mode);
1171                 }
1172         }
1173         return 0;
1174 }
1175
1176 static int
1177 eth_igb_configure(struct rte_eth_dev *dev)
1178 {
1179         struct e1000_interrupt *intr =
1180                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1181         int ret;
1182
1183         PMD_INIT_FUNC_TRACE();
1184
1185         /* multipe queue mode checking */
1186         ret  = igb_check_mq_mode(dev);
1187         if (ret != 0) {
1188                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1189                             ret);
1190                 return ret;
1191         }
1192
1193         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1194         PMD_INIT_FUNC_TRACE();
1195
1196         return 0;
1197 }
1198
1199 static int
1200 eth_igb_start(struct rte_eth_dev *dev)
1201 {
1202         struct e1000_hw *hw =
1203                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1204         struct e1000_adapter *adapter =
1205                 E1000_DEV_PRIVATE(dev->data->dev_private);
1206         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1207         int ret, mask;
1208         uint32_t intr_vector = 0;
1209         uint32_t ctrl_ext;
1210         uint32_t *speeds;
1211         int num_speeds;
1212         bool autoneg;
1213
1214         PMD_INIT_FUNC_TRACE();
1215
1216         /* disable uio/vfio intr/eventfd mapping */
1217         rte_intr_disable(intr_handle);
1218
1219         /* Power up the phy. Needed to make the link go Up */
1220         eth_igb_dev_set_link_up(dev);
1221
1222         /*
1223          * Packet Buffer Allocation (PBA)
1224          * Writing PBA sets the receive portion of the buffer
1225          * the remainder is used for the transmit buffer.
1226          */
1227         if (hw->mac.type == e1000_82575) {
1228                 uint32_t pba;
1229
1230                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1231                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1232         }
1233
1234         /* Put the address into the Receive Address Array */
1235         e1000_rar_set(hw, hw->mac.addr, 0);
1236
1237         /* Initialize the hardware */
1238         if (igb_hardware_init(hw)) {
1239                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1240                 return -EIO;
1241         }
1242         adapter->stopped = 0;
1243
1244         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1245
1246         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1247         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1248         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1249         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1250         E1000_WRITE_FLUSH(hw);
1251
1252         /* configure PF module if SRIOV enabled */
1253         igb_pf_host_configure(dev);
1254
1255         /* check and configure queue intr-vector mapping */
1256         if ((rte_intr_cap_multiple(intr_handle) ||
1257              !RTE_ETH_DEV_SRIOV(dev).active) &&
1258             dev->data->dev_conf.intr_conf.rxq != 0) {
1259                 intr_vector = dev->data->nb_rx_queues;
1260                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1261                         return -1;
1262         }
1263
1264         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1265                 intr_handle->intr_vec =
1266                         rte_zmalloc("intr_vec",
1267                                     dev->data->nb_rx_queues * sizeof(int), 0);
1268                 if (intr_handle->intr_vec == NULL) {
1269                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1270                                      " intr_vec\n", dev->data->nb_rx_queues);
1271                         return -ENOMEM;
1272                 }
1273         }
1274
1275         /* confiugre msix for rx interrupt */
1276         eth_igb_configure_msix_intr(dev);
1277
1278         /* Configure for OS presence */
1279         igb_init_manageability(hw);
1280
1281         eth_igb_tx_init(dev);
1282
1283         /* This can fail when allocating mbufs for descriptor rings */
1284         ret = eth_igb_rx_init(dev);
1285         if (ret) {
1286                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1287                 igb_dev_clear_queues(dev);
1288                 return ret;
1289         }
1290
1291         e1000_clear_hw_cntrs_base_generic(hw);
1292
1293         /*
1294          * VLAN Offload Settings
1295          */
1296         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1297                         ETH_VLAN_EXTEND_MASK;
1298         eth_igb_vlan_offload_set(dev, mask);
1299
1300         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1301                 /* Enable VLAN filter since VMDq always use VLAN filter */
1302                 igb_vmdq_vlan_hw_filter_enable(dev);
1303         }
1304
1305         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1306                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1307                 (hw->mac.type == e1000_i211)) {
1308                 /* Configure EITR with the maximum possible value (0xFFFF) */
1309                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1310         }
1311
1312         /* Setup link speed and duplex */
1313         speeds = &dev->data->dev_conf.link_speeds;
1314         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1315                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1316         } else {
1317                 num_speeds = 0;
1318                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1319
1320                 /* Reset */
1321                 hw->phy.autoneg_advertised = 0;
1322
1323                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1324                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1325                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1326                         num_speeds = -1;
1327                         goto error_invalid_config;
1328                 }
1329                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1330                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1331                         num_speeds++;
1332                 }
1333                 if (*speeds & ETH_LINK_SPEED_10M) {
1334                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1335                         num_speeds++;
1336                 }
1337                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1338                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1339                         num_speeds++;
1340                 }
1341                 if (*speeds & ETH_LINK_SPEED_100M) {
1342                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1343                         num_speeds++;
1344                 }
1345                 if (*speeds & ETH_LINK_SPEED_1G) {
1346                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1347                         num_speeds++;
1348                 }
1349                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1350                         goto error_invalid_config;
1351         }
1352
1353         e1000_setup_link(hw);
1354
1355         if (rte_intr_allow_others(intr_handle)) {
1356                 /* check if lsc interrupt is enabled */
1357                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1358                         eth_igb_lsc_interrupt_setup(dev);
1359         } else {
1360                 rte_intr_callback_unregister(intr_handle,
1361                                              eth_igb_interrupt_handler,
1362                                              (void *)dev);
1363                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1364                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1365                                      " no intr multiplex\n");
1366         }
1367
1368         /* check if rxq interrupt is enabled */
1369         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1370             rte_intr_dp_is_en(intr_handle))
1371                 eth_igb_rxq_interrupt_setup(dev);
1372
1373         /* enable uio/vfio intr/eventfd mapping */
1374         rte_intr_enable(intr_handle);
1375
1376         /* resume enabled intr since hw reset */
1377         igb_intr_enable(dev);
1378
1379         PMD_INIT_LOG(DEBUG, "<<");
1380
1381         return 0;
1382
1383 error_invalid_config:
1384         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1385                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1386         igb_dev_clear_queues(dev);
1387         return -EINVAL;
1388 }
1389
1390 /*********************************************************************
1391  *
1392  *  This routine disables all traffic on the adapter by issuing a
1393  *  global reset on the MAC.
1394  *
1395  **********************************************************************/
1396 static void
1397 eth_igb_stop(struct rte_eth_dev *dev)
1398 {
1399         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1400         struct e1000_filter_info *filter_info =
1401                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1402         struct rte_eth_link link;
1403         struct e1000_flex_filter *p_flex;
1404         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1405         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1406         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1407
1408         igb_intr_disable(hw);
1409
1410         /* disable intr eventfd mapping */
1411         rte_intr_disable(intr_handle);
1412
1413         igb_pf_reset_hw(hw);
1414         E1000_WRITE_REG(hw, E1000_WUC, 0);
1415
1416         /* Set bit for Go Link disconnect */
1417         if (hw->mac.type >= e1000_82580) {
1418                 uint32_t phpm_reg;
1419
1420                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1421                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1422                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1423         }
1424
1425         /* Power down the phy. Needed to make the link go Down */
1426         eth_igb_dev_set_link_down(dev);
1427
1428         igb_dev_clear_queues(dev);
1429
1430         /* clear the recorded link status */
1431         memset(&link, 0, sizeof(link));
1432         rte_igb_dev_atomic_write_link_status(dev, &link);
1433
1434         /* Remove all flex filters of the device */
1435         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1436                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1437                 rte_free(p_flex);
1438         }
1439         filter_info->flex_mask = 0;
1440
1441         /* Remove all ntuple filters of the device */
1442         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1443              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1444                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1445                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1446                              p_5tuple, entries);
1447                 rte_free(p_5tuple);
1448         }
1449         filter_info->fivetuple_mask = 0;
1450         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1451              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1452                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1453                 TAILQ_REMOVE(&filter_info->twotuple_list,
1454                              p_2tuple, entries);
1455                 rte_free(p_2tuple);
1456         }
1457         filter_info->twotuple_mask = 0;
1458
1459         if (!rte_intr_allow_others(intr_handle))
1460                 /* resume to the default handler */
1461                 rte_intr_callback_register(intr_handle,
1462                                            eth_igb_interrupt_handler,
1463                                            (void *)dev);
1464
1465         /* Clean datapath event and queue/vec mapping */
1466         rte_intr_efd_disable(intr_handle);
1467         if (intr_handle->intr_vec != NULL) {
1468                 rte_free(intr_handle->intr_vec);
1469                 intr_handle->intr_vec = NULL;
1470         }
1471 }
1472
1473 static int
1474 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1475 {
1476         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1477
1478         if (hw->phy.media_type == e1000_media_type_copper)
1479                 e1000_power_up_phy(hw);
1480         else
1481                 e1000_power_up_fiber_serdes_link(hw);
1482
1483         return 0;
1484 }
1485
1486 static int
1487 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1488 {
1489         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1490
1491         if (hw->phy.media_type == e1000_media_type_copper)
1492                 e1000_power_down_phy(hw);
1493         else
1494                 e1000_shutdown_fiber_serdes_link(hw);
1495
1496         return 0;
1497 }
1498
1499 static void
1500 eth_igb_close(struct rte_eth_dev *dev)
1501 {
1502         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1503         struct e1000_adapter *adapter =
1504                 E1000_DEV_PRIVATE(dev->data->dev_private);
1505         struct rte_eth_link link;
1506         struct rte_pci_device *pci_dev;
1507
1508         eth_igb_stop(dev);
1509         adapter->stopped = 1;
1510
1511         e1000_phy_hw_reset(hw);
1512         igb_release_manageability(hw);
1513         igb_hw_control_release(hw);
1514
1515         /* Clear bit for Go Link disconnect */
1516         if (hw->mac.type >= e1000_82580) {
1517                 uint32_t phpm_reg;
1518
1519                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1520                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1521                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1522         }
1523
1524         igb_dev_free_queues(dev);
1525
1526         pci_dev = dev->pci_dev;
1527         if (pci_dev->intr_handle.intr_vec) {
1528                 rte_free(pci_dev->intr_handle.intr_vec);
1529                 pci_dev->intr_handle.intr_vec = NULL;
1530         }
1531
1532         memset(&link, 0, sizeof(link));
1533         rte_igb_dev_atomic_write_link_status(dev, &link);
1534 }
1535
1536 static int
1537 igb_get_rx_buffer_size(struct e1000_hw *hw)
1538 {
1539         uint32_t rx_buf_size;
1540         if (hw->mac.type == e1000_82576) {
1541                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1542         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1543                 /* PBS needs to be translated according to a lookup table */
1544                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1545                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1546                 rx_buf_size = (rx_buf_size << 10);
1547         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1548                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1549         } else {
1550                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1551         }
1552
1553         return rx_buf_size;
1554 }
1555
1556 /*********************************************************************
1557  *
1558  *  Initialize the hardware
1559  *
1560  **********************************************************************/
1561 static int
1562 igb_hardware_init(struct e1000_hw *hw)
1563 {
1564         uint32_t rx_buf_size;
1565         int diag;
1566
1567         /* Let the firmware know the OS is in control */
1568         igb_hw_control_acquire(hw);
1569
1570         /*
1571          * These parameters control the automatic generation (Tx) and
1572          * response (Rx) to Ethernet PAUSE frames.
1573          * - High water mark should allow for at least two standard size (1518)
1574          *   frames to be received after sending an XOFF.
1575          * - Low water mark works best when it is very near the high water mark.
1576          *   This allows the receiver to restart by sending XON when it has
1577          *   drained a bit. Here we use an arbitrary value of 1500 which will
1578          *   restart after one full frame is pulled from the buffer. There
1579          *   could be several smaller frames in the buffer and if so they will
1580          *   not trigger the XON until their total number reduces the buffer
1581          *   by 1500.
1582          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1583          */
1584         rx_buf_size = igb_get_rx_buffer_size(hw);
1585
1586         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1587         hw->fc.low_water = hw->fc.high_water - 1500;
1588         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1589         hw->fc.send_xon = 1;
1590
1591         /* Set Flow control, use the tunable location if sane */
1592         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1593                 hw->fc.requested_mode = igb_fc_setting;
1594         else
1595                 hw->fc.requested_mode = e1000_fc_none;
1596
1597         /* Issue a global reset */
1598         igb_pf_reset_hw(hw);
1599         E1000_WRITE_REG(hw, E1000_WUC, 0);
1600
1601         diag = e1000_init_hw(hw);
1602         if (diag < 0)
1603                 return diag;
1604
1605         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1606         e1000_get_phy_info(hw);
1607         e1000_check_for_link(hw);
1608
1609         return 0;
1610 }
1611
1612 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1613 static void
1614 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1615 {
1616         int pause_frames;
1617
1618         uint64_t old_gprc  = stats->gprc;
1619         uint64_t old_gptc  = stats->gptc;
1620         uint64_t old_tpr   = stats->tpr;
1621         uint64_t old_tpt   = stats->tpt;
1622         uint64_t old_rpthc = stats->rpthc;
1623         uint64_t old_hgptc = stats->hgptc;
1624
1625         if(hw->phy.media_type == e1000_media_type_copper ||
1626             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1627                 stats->symerrs +=
1628                     E1000_READ_REG(hw,E1000_SYMERRS);
1629                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1630         }
1631
1632         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1633         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1634         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1635         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1636
1637         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1638         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1639         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1640         stats->dc += E1000_READ_REG(hw, E1000_DC);
1641         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1642         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1643         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1644         /*
1645         ** For watchdog management we need to know if we have been
1646         ** paused during the last interval, so capture that here.
1647         */
1648         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1649         stats->xoffrxc += pause_frames;
1650         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1651         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1652         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1653         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1654         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1655         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1656         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1657         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1658         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1659         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1660         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1661         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1662
1663         /* For the 64-bit byte counters the low dword must be read first. */
1664         /* Both registers clear on the read of the high dword */
1665
1666         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1667         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1668         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1669         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1670         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1671         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1672         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1673
1674         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1675         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1676         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1677         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1678         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1679
1680         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1681         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1682
1683         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1684         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1685         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1686         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1687         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1688         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1689
1690         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1691         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1692         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1693         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1694         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1695         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1696         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1697         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1698
1699         /* Interrupt Counts */
1700
1701         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1702         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1703         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1704         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1705         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1706         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1707         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1708         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1709         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1710
1711         /* Host to Card Statistics */
1712
1713         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1714         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1715         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1716         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1717         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1718         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1719         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1720         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1721         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1722         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1723         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1724         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1725         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1726         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1727         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1728         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1729
1730         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1731         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1732         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1733         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1734         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1735         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1736 }
1737
1738 static void
1739 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1740 {
1741         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1742         struct e1000_hw_stats *stats =
1743                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1744
1745         igb_read_stats_registers(hw, stats);
1746
1747         if (rte_stats == NULL)
1748                 return;
1749
1750         /* Rx Errors */
1751         rte_stats->imissed = stats->mpc;
1752         rte_stats->ierrors = stats->crcerrs +
1753                              stats->rlec + stats->ruc + stats->roc +
1754                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1755
1756         /* Tx Errors */
1757         rte_stats->oerrors = stats->ecol + stats->latecol;
1758
1759         rte_stats->ipackets = stats->gprc;
1760         rte_stats->opackets = stats->gptc;
1761         rte_stats->ibytes   = stats->gorc;
1762         rte_stats->obytes   = stats->gotc;
1763 }
1764
1765 static void
1766 eth_igb_stats_reset(struct rte_eth_dev *dev)
1767 {
1768         struct e1000_hw_stats *hw_stats =
1769                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1770
1771         /* HW registers are cleared on read */
1772         eth_igb_stats_get(dev, NULL);
1773
1774         /* Reset software totals */
1775         memset(hw_stats, 0, sizeof(*hw_stats));
1776 }
1777
1778 static void
1779 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1780 {
1781         struct e1000_hw_stats *stats =
1782                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1783
1784         /* HW registers are cleared on read */
1785         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1786
1787         /* Reset software totals */
1788         memset(stats, 0, sizeof(*stats));
1789 }
1790
1791 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1792         struct rte_eth_xstat_name *xstats_names,
1793         __rte_unused unsigned limit)
1794 {
1795         unsigned i;
1796
1797         if (xstats_names == NULL)
1798                 return IGB_NB_XSTATS;
1799
1800         /* Note: limit checked in rte_eth_xstats_names() */
1801
1802         for (i = 0; i < IGB_NB_XSTATS; i++) {
1803                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1804                          "%s", rte_igb_stats_strings[i].name);
1805                 xstats_names[i].id = i;
1806         }
1807
1808         return IGB_NB_XSTATS;
1809 }
1810
1811 static int
1812 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1813                    unsigned n)
1814 {
1815         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1816         struct e1000_hw_stats *hw_stats =
1817                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1818         unsigned i;
1819
1820         if (n < IGB_NB_XSTATS)
1821                 return IGB_NB_XSTATS;
1822
1823         igb_read_stats_registers(hw, hw_stats);
1824
1825         /* If this is a reset xstats is NULL, and we have cleared the
1826          * registers by reading them.
1827          */
1828         if (!xstats)
1829                 return 0;
1830
1831         /* Extended stats */
1832         for (i = 0; i < IGB_NB_XSTATS; i++) {
1833                 xstats[i].id = i;
1834                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1835                         rte_igb_stats_strings[i].offset);
1836         }
1837
1838         return IGB_NB_XSTATS;
1839 }
1840
1841 static void
1842 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1843 {
1844         /* Good Rx packets, include VF loopback */
1845         UPDATE_VF_STAT(E1000_VFGPRC,
1846             hw_stats->last_gprc, hw_stats->gprc);
1847
1848         /* Good Rx octets, include VF loopback */
1849         UPDATE_VF_STAT(E1000_VFGORC,
1850             hw_stats->last_gorc, hw_stats->gorc);
1851
1852         /* Good Tx packets, include VF loopback */
1853         UPDATE_VF_STAT(E1000_VFGPTC,
1854             hw_stats->last_gptc, hw_stats->gptc);
1855
1856         /* Good Tx octets, include VF loopback */
1857         UPDATE_VF_STAT(E1000_VFGOTC,
1858             hw_stats->last_gotc, hw_stats->gotc);
1859
1860         /* Rx Multicst packets */
1861         UPDATE_VF_STAT(E1000_VFMPRC,
1862             hw_stats->last_mprc, hw_stats->mprc);
1863
1864         /* Good Rx loopback packets */
1865         UPDATE_VF_STAT(E1000_VFGPRLBC,
1866             hw_stats->last_gprlbc, hw_stats->gprlbc);
1867
1868         /* Good Rx loopback octets */
1869         UPDATE_VF_STAT(E1000_VFGORLBC,
1870             hw_stats->last_gorlbc, hw_stats->gorlbc);
1871
1872         /* Good Tx loopback packets */
1873         UPDATE_VF_STAT(E1000_VFGPTLBC,
1874             hw_stats->last_gptlbc, hw_stats->gptlbc);
1875
1876         /* Good Tx loopback octets */
1877         UPDATE_VF_STAT(E1000_VFGOTLBC,
1878             hw_stats->last_gotlbc, hw_stats->gotlbc);
1879 }
1880
1881 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1882                                      struct rte_eth_xstat_name *xstats_names,
1883                                      __rte_unused unsigned limit)
1884 {
1885         unsigned i;
1886
1887         if (xstats_names != NULL)
1888                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1889                         snprintf(xstats_names[i].name,
1890                                 sizeof(xstats_names[i].name), "%s",
1891                                 rte_igbvf_stats_strings[i].name);
1892                         xstats_names[i].id = i;
1893                 }
1894         return IGBVF_NB_XSTATS;
1895 }
1896
1897 static int
1898 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1899                      unsigned n)
1900 {
1901         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1902         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1903                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1904         unsigned i;
1905
1906         if (n < IGBVF_NB_XSTATS)
1907                 return IGBVF_NB_XSTATS;
1908
1909         igbvf_read_stats_registers(hw, hw_stats);
1910
1911         if (!xstats)
1912                 return 0;
1913
1914         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1915                 xstats[i].id = i;
1916                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1917                         rte_igbvf_stats_strings[i].offset);
1918         }
1919
1920         return IGBVF_NB_XSTATS;
1921 }
1922
1923 static void
1924 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1925 {
1926         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1927         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1928                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1929
1930         igbvf_read_stats_registers(hw, hw_stats);
1931
1932         if (rte_stats == NULL)
1933                 return;
1934
1935         rte_stats->ipackets = hw_stats->gprc;
1936         rte_stats->ibytes = hw_stats->gorc;
1937         rte_stats->opackets = hw_stats->gptc;
1938         rte_stats->obytes = hw_stats->gotc;
1939 }
1940
1941 static void
1942 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1943 {
1944         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1945                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1946
1947         /* Sync HW register to the last stats */
1948         eth_igbvf_stats_get(dev, NULL);
1949
1950         /* reset HW current stats*/
1951         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1952                offsetof(struct e1000_vf_stats, gprc));
1953 }
1954
1955 static void
1956 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1957 {
1958         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1959
1960         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1961         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1962         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1963         dev_info->rx_offload_capa =
1964                 DEV_RX_OFFLOAD_VLAN_STRIP |
1965                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1966                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1967                 DEV_RX_OFFLOAD_TCP_CKSUM;
1968         dev_info->tx_offload_capa =
1969                 DEV_TX_OFFLOAD_VLAN_INSERT |
1970                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1971                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1972                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1973                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1974                 DEV_TX_OFFLOAD_TCP_TSO;
1975
1976         switch (hw->mac.type) {
1977         case e1000_82575:
1978                 dev_info->max_rx_queues = 4;
1979                 dev_info->max_tx_queues = 4;
1980                 dev_info->max_vmdq_pools = 0;
1981                 break;
1982
1983         case e1000_82576:
1984                 dev_info->max_rx_queues = 16;
1985                 dev_info->max_tx_queues = 16;
1986                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1987                 dev_info->vmdq_queue_num = 16;
1988                 break;
1989
1990         case e1000_82580:
1991                 dev_info->max_rx_queues = 8;
1992                 dev_info->max_tx_queues = 8;
1993                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1994                 dev_info->vmdq_queue_num = 8;
1995                 break;
1996
1997         case e1000_i350:
1998                 dev_info->max_rx_queues = 8;
1999                 dev_info->max_tx_queues = 8;
2000                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2001                 dev_info->vmdq_queue_num = 8;
2002                 break;
2003
2004         case e1000_i354:
2005                 dev_info->max_rx_queues = 8;
2006                 dev_info->max_tx_queues = 8;
2007                 break;
2008
2009         case e1000_i210:
2010                 dev_info->max_rx_queues = 4;
2011                 dev_info->max_tx_queues = 4;
2012                 dev_info->max_vmdq_pools = 0;
2013                 break;
2014
2015         case e1000_i211:
2016                 dev_info->max_rx_queues = 2;
2017                 dev_info->max_tx_queues = 2;
2018                 dev_info->max_vmdq_pools = 0;
2019                 break;
2020
2021         default:
2022                 /* Should not happen */
2023                 break;
2024         }
2025         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2026         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2027         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2028
2029         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2030                 .rx_thresh = {
2031                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2032                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2033                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2034                 },
2035                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2036                 .rx_drop_en = 0,
2037         };
2038
2039         dev_info->default_txconf = (struct rte_eth_txconf) {
2040                 .tx_thresh = {
2041                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2042                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2043                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2044                 },
2045                 .txq_flags = 0,
2046         };
2047
2048         dev_info->rx_desc_lim = rx_desc_lim;
2049         dev_info->tx_desc_lim = tx_desc_lim;
2050
2051         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2052                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2053                         ETH_LINK_SPEED_1G;
2054 }
2055
2056 static const uint32_t *
2057 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2058 {
2059         static const uint32_t ptypes[] = {
2060                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2061                 RTE_PTYPE_L2_ETHER,
2062                 RTE_PTYPE_L3_IPV4,
2063                 RTE_PTYPE_L3_IPV4_EXT,
2064                 RTE_PTYPE_L3_IPV6,
2065                 RTE_PTYPE_L3_IPV6_EXT,
2066                 RTE_PTYPE_L4_TCP,
2067                 RTE_PTYPE_L4_UDP,
2068                 RTE_PTYPE_L4_SCTP,
2069                 RTE_PTYPE_TUNNEL_IP,
2070                 RTE_PTYPE_INNER_L3_IPV6,
2071                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2072                 RTE_PTYPE_INNER_L4_TCP,
2073                 RTE_PTYPE_INNER_L4_UDP,
2074                 RTE_PTYPE_UNKNOWN
2075         };
2076
2077         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2078             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2079                 return ptypes;
2080         return NULL;
2081 }
2082
2083 static void
2084 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2085 {
2086         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2087
2088         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2089         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2090         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2091         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2092                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2093                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2094                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2095         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2096                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2097                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2098                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2099                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2100                                 DEV_TX_OFFLOAD_TCP_TSO;
2101         switch (hw->mac.type) {
2102         case e1000_vfadapt:
2103                 dev_info->max_rx_queues = 2;
2104                 dev_info->max_tx_queues = 2;
2105                 break;
2106         case e1000_vfadapt_i350:
2107                 dev_info->max_rx_queues = 1;
2108                 dev_info->max_tx_queues = 1;
2109                 break;
2110         default:
2111                 /* Should not happen */
2112                 break;
2113         }
2114
2115         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2116                 .rx_thresh = {
2117                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2118                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2119                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2120                 },
2121                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2122                 .rx_drop_en = 0,
2123         };
2124
2125         dev_info->default_txconf = (struct rte_eth_txconf) {
2126                 .tx_thresh = {
2127                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2128                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2129                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2130                 },
2131                 .txq_flags = 0,
2132         };
2133
2134         dev_info->rx_desc_lim = rx_desc_lim;
2135         dev_info->tx_desc_lim = tx_desc_lim;
2136 }
2137
2138 /* return 0 means link status changed, -1 means not changed */
2139 static int
2140 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2141 {
2142         struct e1000_hw *hw =
2143                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2144         struct rte_eth_link link, old;
2145         int link_check, count;
2146
2147         link_check = 0;
2148         hw->mac.get_link_status = 1;
2149
2150         /* possible wait-to-complete in up to 9 seconds */
2151         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2152                 /* Read the real link status */
2153                 switch (hw->phy.media_type) {
2154                 case e1000_media_type_copper:
2155                         /* Do the work to read phy */
2156                         e1000_check_for_link(hw);
2157                         link_check = !hw->mac.get_link_status;
2158                         break;
2159
2160                 case e1000_media_type_fiber:
2161                         e1000_check_for_link(hw);
2162                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2163                                       E1000_STATUS_LU);
2164                         break;
2165
2166                 case e1000_media_type_internal_serdes:
2167                         e1000_check_for_link(hw);
2168                         link_check = hw->mac.serdes_has_link;
2169                         break;
2170
2171                 /* VF device is type_unknown */
2172                 case e1000_media_type_unknown:
2173                         eth_igbvf_link_update(hw);
2174                         link_check = !hw->mac.get_link_status;
2175                         break;
2176
2177                 default:
2178                         break;
2179                 }
2180                 if (link_check || wait_to_complete == 0)
2181                         break;
2182                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2183         }
2184         memset(&link, 0, sizeof(link));
2185         rte_igb_dev_atomic_read_link_status(dev, &link);
2186         old = link;
2187
2188         /* Now we check if a transition has happened */
2189         if (link_check) {
2190                 uint16_t duplex, speed;
2191                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2192                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2193                                 ETH_LINK_FULL_DUPLEX :
2194                                 ETH_LINK_HALF_DUPLEX;
2195                 link.link_speed = speed;
2196                 link.link_status = ETH_LINK_UP;
2197                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2198                                 ETH_LINK_SPEED_FIXED);
2199         } else if (!link_check) {
2200                 link.link_speed = 0;
2201                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2202                 link.link_status = ETH_LINK_DOWN;
2203                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2204         }
2205         rte_igb_dev_atomic_write_link_status(dev, &link);
2206
2207         /* not changed */
2208         if (old.link_status == link.link_status)
2209                 return -1;
2210
2211         /* changed */
2212         return 0;
2213 }
2214
2215 /*
2216  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2217  * For ASF and Pass Through versions of f/w this means
2218  * that the driver is loaded.
2219  */
2220 static void
2221 igb_hw_control_acquire(struct e1000_hw *hw)
2222 {
2223         uint32_t ctrl_ext;
2224
2225         /* Let firmware know the driver has taken over */
2226         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2227         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2228 }
2229
2230 /*
2231  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2232  * For ASF and Pass Through versions of f/w this means that the
2233  * driver is no longer loaded.
2234  */
2235 static void
2236 igb_hw_control_release(struct e1000_hw *hw)
2237 {
2238         uint32_t ctrl_ext;
2239
2240         /* Let firmware taken over control of h/w */
2241         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2242         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2243                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2244 }
2245
2246 /*
2247  * Bit of a misnomer, what this really means is
2248  * to enable OS management of the system... aka
2249  * to disable special hardware management features.
2250  */
2251 static void
2252 igb_init_manageability(struct e1000_hw *hw)
2253 {
2254         if (e1000_enable_mng_pass_thru(hw)) {
2255                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2256                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2257
2258                 /* disable hardware interception of ARP */
2259                 manc &= ~(E1000_MANC_ARP_EN);
2260
2261                 /* enable receiving management packets to the host */
2262                 manc |= E1000_MANC_EN_MNG2HOST;
2263                 manc2h |= 1 << 5;  /* Mng Port 623 */
2264                 manc2h |= 1 << 6;  /* Mng Port 664 */
2265                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2266                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2267         }
2268 }
2269
2270 static void
2271 igb_release_manageability(struct e1000_hw *hw)
2272 {
2273         if (e1000_enable_mng_pass_thru(hw)) {
2274                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2275
2276                 manc |= E1000_MANC_ARP_EN;
2277                 manc &= ~E1000_MANC_EN_MNG2HOST;
2278
2279                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2280         }
2281 }
2282
2283 static void
2284 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2285 {
2286         struct e1000_hw *hw =
2287                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2288         uint32_t rctl;
2289
2290         rctl = E1000_READ_REG(hw, E1000_RCTL);
2291         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2292         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2293 }
2294
2295 static void
2296 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2297 {
2298         struct e1000_hw *hw =
2299                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2300         uint32_t rctl;
2301
2302         rctl = E1000_READ_REG(hw, E1000_RCTL);
2303         rctl &= (~E1000_RCTL_UPE);
2304         if (dev->data->all_multicast == 1)
2305                 rctl |= E1000_RCTL_MPE;
2306         else
2307                 rctl &= (~E1000_RCTL_MPE);
2308         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2309 }
2310
2311 static void
2312 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2313 {
2314         struct e1000_hw *hw =
2315                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2316         uint32_t rctl;
2317
2318         rctl = E1000_READ_REG(hw, E1000_RCTL);
2319         rctl |= E1000_RCTL_MPE;
2320         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2321 }
2322
2323 static void
2324 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2325 {
2326         struct e1000_hw *hw =
2327                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2328         uint32_t rctl;
2329
2330         if (dev->data->promiscuous == 1)
2331                 return; /* must remain in all_multicast mode */
2332         rctl = E1000_READ_REG(hw, E1000_RCTL);
2333         rctl &= (~E1000_RCTL_MPE);
2334         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2335 }
2336
2337 static int
2338 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2339 {
2340         struct e1000_hw *hw =
2341                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2342         struct e1000_vfta * shadow_vfta =
2343                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2344         uint32_t vfta;
2345         uint32_t vid_idx;
2346         uint32_t vid_bit;
2347
2348         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2349                               E1000_VFTA_ENTRY_MASK);
2350         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2351         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2352         if (on)
2353                 vfta |= vid_bit;
2354         else
2355                 vfta &= ~vid_bit;
2356         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2357
2358         /* update local VFTA copy */
2359         shadow_vfta->vfta[vid_idx] = vfta;
2360
2361         return 0;
2362 }
2363
2364 static int
2365 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2366                       enum rte_vlan_type vlan_type,
2367                       uint16_t tpid)
2368 {
2369         struct e1000_hw *hw =
2370                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2371         uint32_t reg, qinq;
2372
2373         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2374         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2375
2376         /* only outer TPID of double VLAN can be configured*/
2377         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2378                 reg = E1000_READ_REG(hw, E1000_VET);
2379                 reg = (reg & (~E1000_VET_VET_EXT)) |
2380                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2381                 E1000_WRITE_REG(hw, E1000_VET, reg);
2382
2383                 return 0;
2384         }
2385
2386         /* all other TPID values are read-only*/
2387         PMD_DRV_LOG(ERR, "Not supported");
2388
2389         return -ENOTSUP;
2390 }
2391
2392 static void
2393 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2394 {
2395         struct e1000_hw *hw =
2396                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2397         uint32_t reg;
2398
2399         /* Filter Table Disable */
2400         reg = E1000_READ_REG(hw, E1000_RCTL);
2401         reg &= ~E1000_RCTL_CFIEN;
2402         reg &= ~E1000_RCTL_VFE;
2403         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2404 }
2405
2406 static void
2407 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2408 {
2409         struct e1000_hw *hw =
2410                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2411         struct e1000_vfta * shadow_vfta =
2412                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2413         uint32_t reg;
2414         int i;
2415
2416         /* Filter Table Enable, CFI not used for packet acceptance */
2417         reg = E1000_READ_REG(hw, E1000_RCTL);
2418         reg &= ~E1000_RCTL_CFIEN;
2419         reg |= E1000_RCTL_VFE;
2420         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2421
2422         /* restore VFTA table */
2423         for (i = 0; i < IGB_VFTA_SIZE; i++)
2424                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2425 }
2426
2427 static void
2428 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2429 {
2430         struct e1000_hw *hw =
2431                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2432         uint32_t reg;
2433
2434         /* VLAN Mode Disable */
2435         reg = E1000_READ_REG(hw, E1000_CTRL);
2436         reg &= ~E1000_CTRL_VME;
2437         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2438 }
2439
2440 static void
2441 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2442 {
2443         struct e1000_hw *hw =
2444                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2445         uint32_t reg;
2446
2447         /* VLAN Mode Enable */
2448         reg = E1000_READ_REG(hw, E1000_CTRL);
2449         reg |= E1000_CTRL_VME;
2450         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2451 }
2452
2453 static void
2454 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2455 {
2456         struct e1000_hw *hw =
2457                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2458         uint32_t reg;
2459
2460         /* CTRL_EXT: Extended VLAN */
2461         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2462         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2463         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2464
2465         /* Update maximum packet length */
2466         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2467                 E1000_WRITE_REG(hw, E1000_RLPML,
2468                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2469                                                 VLAN_TAG_SIZE);
2470 }
2471
2472 static void
2473 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2474 {
2475         struct e1000_hw *hw =
2476                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2477         uint32_t reg;
2478
2479         /* CTRL_EXT: Extended VLAN */
2480         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2481         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2482         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2483
2484         /* Update maximum packet length */
2485         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2486                 E1000_WRITE_REG(hw, E1000_RLPML,
2487                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2488                                                 2 * VLAN_TAG_SIZE);
2489 }
2490
2491 static void
2492 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2493 {
2494         if(mask & ETH_VLAN_STRIP_MASK){
2495                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2496                         igb_vlan_hw_strip_enable(dev);
2497                 else
2498                         igb_vlan_hw_strip_disable(dev);
2499         }
2500
2501         if(mask & ETH_VLAN_FILTER_MASK){
2502                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2503                         igb_vlan_hw_filter_enable(dev);
2504                 else
2505                         igb_vlan_hw_filter_disable(dev);
2506         }
2507
2508         if(mask & ETH_VLAN_EXTEND_MASK){
2509                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2510                         igb_vlan_hw_extend_enable(dev);
2511                 else
2512                         igb_vlan_hw_extend_disable(dev);
2513         }
2514 }
2515
2516
2517 /**
2518  * It enables the interrupt mask and then enable the interrupt.
2519  *
2520  * @param dev
2521  *  Pointer to struct rte_eth_dev.
2522  *
2523  * @return
2524  *  - On success, zero.
2525  *  - On failure, a negative value.
2526  */
2527 static int
2528 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2529 {
2530         struct e1000_interrupt *intr =
2531                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2532
2533         intr->mask |= E1000_ICR_LSC;
2534
2535         return 0;
2536 }
2537
2538 /* It clears the interrupt causes and enables the interrupt.
2539  * It will be called once only during nic initialized.
2540  *
2541  * @param dev
2542  *  Pointer to struct rte_eth_dev.
2543  *
2544  * @return
2545  *  - On success, zero.
2546  *  - On failure, a negative value.
2547  */
2548 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2549 {
2550         uint32_t mask, regval;
2551         struct e1000_hw *hw =
2552                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2553         struct rte_eth_dev_info dev_info;
2554
2555         memset(&dev_info, 0, sizeof(dev_info));
2556         eth_igb_infos_get(dev, &dev_info);
2557
2558         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2559         regval = E1000_READ_REG(hw, E1000_EIMS);
2560         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2561
2562         return 0;
2563 }
2564
2565 /*
2566  * It reads ICR and gets interrupt causes, check it and set a bit flag
2567  * to update link status.
2568  *
2569  * @param dev
2570  *  Pointer to struct rte_eth_dev.
2571  *
2572  * @return
2573  *  - On success, zero.
2574  *  - On failure, a negative value.
2575  */
2576 static int
2577 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2578 {
2579         uint32_t icr;
2580         struct e1000_hw *hw =
2581                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2582         struct e1000_interrupt *intr =
2583                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2584
2585         igb_intr_disable(hw);
2586
2587         /* read-on-clear nic registers here */
2588         icr = E1000_READ_REG(hw, E1000_ICR);
2589
2590         intr->flags = 0;
2591         if (icr & E1000_ICR_LSC) {
2592                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2593         }
2594
2595         if (icr & E1000_ICR_VMMB)
2596                 intr->flags |= E1000_FLAG_MAILBOX;
2597
2598         return 0;
2599 }
2600
2601 /*
2602  * It executes link_update after knowing an interrupt is prsent.
2603  *
2604  * @param dev
2605  *  Pointer to struct rte_eth_dev.
2606  *
2607  * @return
2608  *  - On success, zero.
2609  *  - On failure, a negative value.
2610  */
2611 static int
2612 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2613 {
2614         struct e1000_hw *hw =
2615                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616         struct e1000_interrupt *intr =
2617                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2618         uint32_t tctl, rctl;
2619         struct rte_eth_link link;
2620         int ret;
2621
2622         if (intr->flags & E1000_FLAG_MAILBOX) {
2623                 igb_pf_mbx_process(dev);
2624                 intr->flags &= ~E1000_FLAG_MAILBOX;
2625         }
2626
2627         igb_intr_enable(dev);
2628         rte_intr_enable(&(dev->pci_dev->intr_handle));
2629
2630         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2631                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2632
2633                 /* set get_link_status to check register later */
2634                 hw->mac.get_link_status = 1;
2635                 ret = eth_igb_link_update(dev, 0);
2636
2637                 /* check if link has changed */
2638                 if (ret < 0)
2639                         return 0;
2640
2641                 memset(&link, 0, sizeof(link));
2642                 rte_igb_dev_atomic_read_link_status(dev, &link);
2643                 if (link.link_status) {
2644                         PMD_INIT_LOG(INFO,
2645                                      " Port %d: Link Up - speed %u Mbps - %s",
2646                                      dev->data->port_id,
2647                                      (unsigned)link.link_speed,
2648                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2649                                      "full-duplex" : "half-duplex");
2650                 } else {
2651                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2652                                      dev->data->port_id);
2653                 }
2654
2655                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2656                              dev->pci_dev->addr.domain,
2657                              dev->pci_dev->addr.bus,
2658                              dev->pci_dev->addr.devid,
2659                              dev->pci_dev->addr.function);
2660                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2661                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2662                 if (link.link_status) {
2663                         /* enable Tx/Rx */
2664                         tctl |= E1000_TCTL_EN;
2665                         rctl |= E1000_RCTL_EN;
2666                 } else {
2667                         /* disable Tx/Rx */
2668                         tctl &= ~E1000_TCTL_EN;
2669                         rctl &= ~E1000_RCTL_EN;
2670                 }
2671                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2672                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2673                 E1000_WRITE_FLUSH(hw);
2674                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2675         }
2676
2677         return 0;
2678 }
2679
2680 /**
2681  * Interrupt handler which shall be registered at first.
2682  *
2683  * @param handle
2684  *  Pointer to interrupt handle.
2685  * @param param
2686  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2687  *
2688  * @return
2689  *  void
2690  */
2691 static void
2692 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2693                                                         void *param)
2694 {
2695         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2696
2697         eth_igb_interrupt_get_status(dev);
2698         eth_igb_interrupt_action(dev);
2699 }
2700
2701 static int
2702 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2703 {
2704         uint32_t eicr;
2705         struct e1000_hw *hw =
2706                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2707         struct e1000_interrupt *intr =
2708                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2709
2710         igbvf_intr_disable(hw);
2711
2712         /* read-on-clear nic registers here */
2713         eicr = E1000_READ_REG(hw, E1000_EICR);
2714         intr->flags = 0;
2715
2716         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2717                 intr->flags |= E1000_FLAG_MAILBOX;
2718
2719         return 0;
2720 }
2721
2722 void igbvf_mbx_process(struct rte_eth_dev *dev)
2723 {
2724         struct e1000_hw *hw =
2725                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2726         struct e1000_mbx_info *mbx = &hw->mbx;
2727         u32 in_msg = 0;
2728
2729         if (mbx->ops.read(hw, &in_msg, 1, 0))
2730                 return;
2731
2732         /* PF reset VF event */
2733         if (in_msg == E1000_PF_CONTROL_MSG)
2734                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
2735 }
2736
2737 static int
2738 eth_igbvf_interrupt_action(struct rte_eth_dev *dev)
2739 {
2740         struct e1000_interrupt *intr =
2741                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2742
2743         if (intr->flags & E1000_FLAG_MAILBOX) {
2744                 igbvf_mbx_process(dev);
2745                 intr->flags &= ~E1000_FLAG_MAILBOX;
2746         }
2747
2748         igbvf_intr_enable(dev);
2749         rte_intr_enable(&dev->pci_dev->intr_handle);
2750
2751         return 0;
2752 }
2753
2754 static void
2755 eth_igbvf_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2756                             void *param)
2757 {
2758         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2759
2760         eth_igbvf_interrupt_get_status(dev);
2761         eth_igbvf_interrupt_action(dev);
2762 }
2763
2764 static int
2765 eth_igb_led_on(struct rte_eth_dev *dev)
2766 {
2767         struct e1000_hw *hw;
2768
2769         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2770         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2771 }
2772
2773 static int
2774 eth_igb_led_off(struct rte_eth_dev *dev)
2775 {
2776         struct e1000_hw *hw;
2777
2778         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2779         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2780 }
2781
2782 static int
2783 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2784 {
2785         struct e1000_hw *hw;
2786         uint32_t ctrl;
2787         int tx_pause;
2788         int rx_pause;
2789
2790         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2791         fc_conf->pause_time = hw->fc.pause_time;
2792         fc_conf->high_water = hw->fc.high_water;
2793         fc_conf->low_water = hw->fc.low_water;
2794         fc_conf->send_xon = hw->fc.send_xon;
2795         fc_conf->autoneg = hw->mac.autoneg;
2796
2797         /*
2798          * Return rx_pause and tx_pause status according to actual setting of
2799          * the TFCE and RFCE bits in the CTRL register.
2800          */
2801         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2802         if (ctrl & E1000_CTRL_TFCE)
2803                 tx_pause = 1;
2804         else
2805                 tx_pause = 0;
2806
2807         if (ctrl & E1000_CTRL_RFCE)
2808                 rx_pause = 1;
2809         else
2810                 rx_pause = 0;
2811
2812         if (rx_pause && tx_pause)
2813                 fc_conf->mode = RTE_FC_FULL;
2814         else if (rx_pause)
2815                 fc_conf->mode = RTE_FC_RX_PAUSE;
2816         else if (tx_pause)
2817                 fc_conf->mode = RTE_FC_TX_PAUSE;
2818         else
2819                 fc_conf->mode = RTE_FC_NONE;
2820
2821         return 0;
2822 }
2823
2824 static int
2825 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2826 {
2827         struct e1000_hw *hw;
2828         int err;
2829         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2830                 e1000_fc_none,
2831                 e1000_fc_rx_pause,
2832                 e1000_fc_tx_pause,
2833                 e1000_fc_full
2834         };
2835         uint32_t rx_buf_size;
2836         uint32_t max_high_water;
2837         uint32_t rctl;
2838
2839         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2840         if (fc_conf->autoneg != hw->mac.autoneg)
2841                 return -ENOTSUP;
2842         rx_buf_size = igb_get_rx_buffer_size(hw);
2843         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2844
2845         /* At least reserve one Ethernet frame for watermark */
2846         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2847         if ((fc_conf->high_water > max_high_water) ||
2848             (fc_conf->high_water < fc_conf->low_water)) {
2849                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2850                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2851                 return -EINVAL;
2852         }
2853
2854         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2855         hw->fc.pause_time     = fc_conf->pause_time;
2856         hw->fc.high_water     = fc_conf->high_water;
2857         hw->fc.low_water      = fc_conf->low_water;
2858         hw->fc.send_xon       = fc_conf->send_xon;
2859
2860         err = e1000_setup_link_generic(hw);
2861         if (err == E1000_SUCCESS) {
2862
2863                 /* check if we want to forward MAC frames - driver doesn't have native
2864                  * capability to do that, so we'll write the registers ourselves */
2865
2866                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2867
2868                 /* set or clear MFLCN.PMCF bit depending on configuration */
2869                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2870                         rctl |= E1000_RCTL_PMCF;
2871                 else
2872                         rctl &= ~E1000_RCTL_PMCF;
2873
2874                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2875                 E1000_WRITE_FLUSH(hw);
2876
2877                 return 0;
2878         }
2879
2880         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2881         return -EIO;
2882 }
2883
2884 #define E1000_RAH_POOLSEL_SHIFT      (18)
2885 static void
2886 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2887                 uint32_t index, __rte_unused uint32_t pool)
2888 {
2889         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2890         uint32_t rah;
2891
2892         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2893         rah = E1000_READ_REG(hw, E1000_RAH(index));
2894         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2895         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2896 }
2897
2898 static void
2899 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2900 {
2901         uint8_t addr[ETHER_ADDR_LEN];
2902         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2903
2904         memset(addr, 0, sizeof(addr));
2905
2906         e1000_rar_set(hw, addr, index);
2907 }
2908
2909 static void
2910 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2911                                 struct ether_addr *addr)
2912 {
2913         eth_igb_rar_clear(dev, 0);
2914
2915         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2916 }
2917 /*
2918  * Virtual Function operations
2919  */
2920 static void
2921 igbvf_intr_disable(struct e1000_hw *hw)
2922 {
2923         PMD_INIT_FUNC_TRACE();
2924
2925         /* Clear interrupt mask to stop from interrupts being generated */
2926         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2927
2928         E1000_WRITE_FLUSH(hw);
2929 }
2930
2931 static void
2932 igbvf_stop_adapter(struct rte_eth_dev *dev)
2933 {
2934         u32 reg_val;
2935         u16 i;
2936         struct rte_eth_dev_info dev_info;
2937         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2938
2939         memset(&dev_info, 0, sizeof(dev_info));
2940         eth_igbvf_infos_get(dev, &dev_info);
2941
2942         /* Clear interrupt mask to stop from interrupts being generated */
2943         igbvf_intr_disable(hw);
2944
2945         /* Clear any pending interrupts, flush previous writes */
2946         E1000_READ_REG(hw, E1000_EICR);
2947
2948         /* Disable the transmit unit.  Each queue must be disabled. */
2949         for (i = 0; i < dev_info.max_tx_queues; i++)
2950                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2951
2952         /* Disable the receive unit by stopping each queue */
2953         for (i = 0; i < dev_info.max_rx_queues; i++) {
2954                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2955                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2956                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2957                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2958                         ;
2959         }
2960
2961         /* flush all queues disables */
2962         E1000_WRITE_FLUSH(hw);
2963         msec_delay(2);
2964 }
2965
2966 static int eth_igbvf_link_update(struct e1000_hw *hw)
2967 {
2968         struct e1000_mbx_info *mbx = &hw->mbx;
2969         struct e1000_mac_info *mac = &hw->mac;
2970         int ret_val = E1000_SUCCESS;
2971
2972         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2973
2974         /*
2975          * We only want to run this if there has been a rst asserted.
2976          * in this case that could mean a link change, device reset,
2977          * or a virtual function reset
2978          */
2979
2980         /* If we were hit with a reset or timeout drop the link */
2981         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2982                 mac->get_link_status = TRUE;
2983
2984         if (!mac->get_link_status)
2985                 goto out;
2986
2987         /* if link status is down no point in checking to see if pf is up */
2988         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2989                 goto out;
2990
2991         /* if we passed all the tests above then the link is up and we no
2992          * longer need to check for link */
2993         mac->get_link_status = FALSE;
2994
2995 out:
2996         return ret_val;
2997 }
2998
2999
3000 static int
3001 igbvf_dev_configure(struct rte_eth_dev *dev)
3002 {
3003         struct rte_eth_conf* conf = &dev->data->dev_conf;
3004
3005         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3006                      dev->data->port_id);
3007
3008         /*
3009          * VF has no ability to enable/disable HW CRC
3010          * Keep the persistent behavior the same as Host PF
3011          */
3012 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3013         if (!conf->rxmode.hw_strip_crc) {
3014                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3015                 conf->rxmode.hw_strip_crc = 1;
3016         }
3017 #else
3018         if (conf->rxmode.hw_strip_crc) {
3019                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3020                 conf->rxmode.hw_strip_crc = 0;
3021         }
3022 #endif
3023
3024         return 0;
3025 }
3026
3027 static int
3028 igbvf_dev_start(struct rte_eth_dev *dev)
3029 {
3030         struct e1000_hw *hw =
3031                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3032         struct e1000_adapter *adapter =
3033                 E1000_DEV_PRIVATE(dev->data->dev_private);
3034         int ret;
3035         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3036         uint32_t intr_vector = 0;
3037
3038         PMD_INIT_FUNC_TRACE();
3039
3040         hw->mac.ops.reset_hw(hw);
3041         adapter->stopped = 0;
3042
3043         /* Set all vfta */
3044         igbvf_set_vfta_all(dev,1);
3045
3046         eth_igbvf_tx_init(dev);
3047
3048         /* This can fail when allocating mbufs for descriptor rings */
3049         ret = eth_igbvf_rx_init(dev);
3050         if (ret) {
3051                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3052                 igb_dev_clear_queues(dev);
3053                 return ret;
3054         }
3055
3056         /* check and configure queue intr-vector mapping */
3057         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3058                 intr_vector = dev->data->nb_rx_queues;
3059                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3060                 if (ret)
3061                         return ret;
3062         }
3063
3064         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3065                 intr_handle->intr_vec =
3066                         rte_zmalloc("intr_vec",
3067                                     dev->data->nb_rx_queues * sizeof(int), 0);
3068                 if (!intr_handle->intr_vec) {
3069                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3070                                      " intr_vec\n", dev->data->nb_rx_queues);
3071                         return -ENOMEM;
3072                 }
3073         }
3074
3075         eth_igbvf_configure_msix_intr(dev);
3076
3077         /* enable uio/vfio intr/eventfd mapping */
3078         rte_intr_enable(intr_handle);
3079
3080         /* resume enabled intr since hw reset */
3081         igbvf_intr_enable(dev);
3082
3083         return 0;
3084 }
3085
3086 static void
3087 igbvf_dev_stop(struct rte_eth_dev *dev)
3088 {
3089         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3090
3091         PMD_INIT_FUNC_TRACE();
3092
3093         igbvf_stop_adapter(dev);
3094
3095         /*
3096           * Clear what we set, but we still keep shadow_vfta to
3097           * restore after device starts
3098           */
3099         igbvf_set_vfta_all(dev,0);
3100
3101         igb_dev_clear_queues(dev);
3102
3103         /* disable intr eventfd mapping */
3104         rte_intr_disable(intr_handle);
3105
3106         /* Clean datapath event and queue/vec mapping */
3107         rte_intr_efd_disable(intr_handle);
3108         if (intr_handle->intr_vec) {
3109                 rte_free(intr_handle->intr_vec);
3110                 intr_handle->intr_vec = NULL;
3111         }
3112 }
3113
3114 static void
3115 igbvf_dev_close(struct rte_eth_dev *dev)
3116 {
3117         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3118         struct e1000_adapter *adapter =
3119                 E1000_DEV_PRIVATE(dev->data->dev_private);
3120         struct ether_addr addr;
3121
3122         PMD_INIT_FUNC_TRACE();
3123
3124         e1000_reset_hw(hw);
3125
3126         igbvf_dev_stop(dev);
3127         adapter->stopped = 1;
3128         igb_dev_free_queues(dev);
3129
3130         /**
3131          * reprogram the RAR with a zero mac address,
3132          * to ensure that the VF traffic goes to the PF
3133          * after stop, close and detach of the VF.
3134          **/
3135
3136         memset(&addr, 0, sizeof(addr));
3137         igbvf_default_mac_addr_set(dev, &addr);
3138 }
3139
3140 static void
3141 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3142 {
3143         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3144
3145         /* Set both unicast and multicast promisc */
3146         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3147 }
3148
3149 static void
3150 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3151 {
3152         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3153
3154         /* If in allmulticast mode leave multicast promisc */
3155         if (dev->data->all_multicast == 1)
3156                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3157         else
3158                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3159 }
3160
3161 static void
3162 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3163 {
3164         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3165
3166         /* In promiscuous mode multicast promisc already set */
3167         if (dev->data->promiscuous == 0)
3168                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3169 }
3170
3171 static void
3172 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3173 {
3174         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3175
3176         /* In promiscuous mode leave multicast promisc enabled */
3177         if (dev->data->promiscuous == 0)
3178                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3179 }
3180
3181 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3182 {
3183         struct e1000_mbx_info *mbx = &hw->mbx;
3184         uint32_t msgbuf[2];
3185         s32 err;
3186
3187         /* After set vlan, vlan strip will also be enabled in igb driver*/
3188         msgbuf[0] = E1000_VF_SET_VLAN;
3189         msgbuf[1] = vid;
3190         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3191         if (on)
3192                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3193
3194         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3195         if (err)
3196                 goto mbx_err;
3197
3198         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3199         if (err)
3200                 goto mbx_err;
3201
3202         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3203         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3204                 err = -EINVAL;
3205
3206 mbx_err:
3207         return err;
3208 }
3209
3210 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3211 {
3212         struct e1000_hw *hw =
3213                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3214         struct e1000_vfta * shadow_vfta =
3215                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3216         int i = 0, j = 0, vfta = 0, mask = 1;
3217
3218         for (i = 0; i < IGB_VFTA_SIZE; i++){
3219                 vfta = shadow_vfta->vfta[i];
3220                 if(vfta){
3221                         mask = 1;
3222                         for (j = 0; j < 32; j++){
3223                                 if(vfta & mask)
3224                                         igbvf_set_vfta(hw,
3225                                                 (uint16_t)((i<<5)+j), on);
3226                                 mask<<=1;
3227                         }
3228                 }
3229         }
3230
3231 }
3232
3233 static int
3234 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3235 {
3236         struct e1000_hw *hw =
3237                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3238         struct e1000_vfta * shadow_vfta =
3239                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3240         uint32_t vid_idx = 0;
3241         uint32_t vid_bit = 0;
3242         int ret = 0;
3243
3244         PMD_INIT_FUNC_TRACE();
3245
3246         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3247         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3248         if(ret){
3249                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3250                 return ret;
3251         }
3252         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3253         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3254
3255         /*Save what we set and retore it after device reset*/
3256         if (on)
3257                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3258         else
3259                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3260
3261         return 0;
3262 }
3263
3264 static void
3265 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3266 {
3267         struct e1000_hw *hw =
3268                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3269
3270         /* index is not used by rar_set() */
3271         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3272 }
3273
3274
3275 static int
3276 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3277                         struct rte_eth_rss_reta_entry64 *reta_conf,
3278                         uint16_t reta_size)
3279 {
3280         uint8_t i, j, mask;
3281         uint32_t reta, r;
3282         uint16_t idx, shift;
3283         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3284
3285         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3286                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3287                         "(%d) doesn't match the number hardware can supported "
3288                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3289                 return -EINVAL;
3290         }
3291
3292         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3293                 idx = i / RTE_RETA_GROUP_SIZE;
3294                 shift = i % RTE_RETA_GROUP_SIZE;
3295                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3296                                                 IGB_4_BIT_MASK);
3297                 if (!mask)
3298                         continue;
3299                 if (mask == IGB_4_BIT_MASK)
3300                         r = 0;
3301                 else
3302                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3303                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3304                         if (mask & (0x1 << j))
3305                                 reta |= reta_conf[idx].reta[shift + j] <<
3306                                                         (CHAR_BIT * j);
3307                         else
3308                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3309                 }
3310                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3311         }
3312
3313         return 0;
3314 }
3315
3316 static int
3317 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3318                        struct rte_eth_rss_reta_entry64 *reta_conf,
3319                        uint16_t reta_size)
3320 {
3321         uint8_t i, j, mask;
3322         uint32_t reta;
3323         uint16_t idx, shift;
3324         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3325
3326         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3327                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3328                         "(%d) doesn't match the number hardware can supported "
3329                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3330                 return -EINVAL;
3331         }
3332
3333         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3334                 idx = i / RTE_RETA_GROUP_SIZE;
3335                 shift = i % RTE_RETA_GROUP_SIZE;
3336                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3337                                                 IGB_4_BIT_MASK);
3338                 if (!mask)
3339                         continue;
3340                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3341                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3342                         if (mask & (0x1 << j))
3343                                 reta_conf[idx].reta[shift + j] =
3344                                         ((reta >> (CHAR_BIT * j)) &
3345                                                 IGB_8_BIT_MASK);
3346                 }
3347         }
3348
3349         return 0;
3350 }
3351
3352 #define MAC_TYPE_FILTER_SUP(type)    do {\
3353         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3354                 (type) != e1000_82576)\
3355                 return -ENOTSUP;\
3356 } while (0)
3357
3358 static int
3359 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3360                         struct rte_eth_syn_filter *filter,
3361                         bool add)
3362 {
3363         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3364         uint32_t synqf, rfctl;
3365
3366         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3367                 return -EINVAL;
3368
3369         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3370
3371         if (add) {
3372                 if (synqf & E1000_SYN_FILTER_ENABLE)
3373                         return -EINVAL;
3374
3375                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3376                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3377
3378                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3379                 if (filter->hig_pri)
3380                         rfctl |= E1000_RFCTL_SYNQFP;
3381                 else
3382                         rfctl &= ~E1000_RFCTL_SYNQFP;
3383
3384                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3385         } else {
3386                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3387                         return -ENOENT;
3388                 synqf = 0;
3389         }
3390
3391         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3392         E1000_WRITE_FLUSH(hw);
3393         return 0;
3394 }
3395
3396 static int
3397 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3398                         struct rte_eth_syn_filter *filter)
3399 {
3400         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3401         uint32_t synqf, rfctl;
3402
3403         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3404         if (synqf & E1000_SYN_FILTER_ENABLE) {
3405                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3406                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3407                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3408                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3409                 return 0;
3410         }
3411
3412         return -ENOENT;
3413 }
3414
3415 static int
3416 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3417                         enum rte_filter_op filter_op,
3418                         void *arg)
3419 {
3420         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3421         int ret;
3422
3423         MAC_TYPE_FILTER_SUP(hw->mac.type);
3424
3425         if (filter_op == RTE_ETH_FILTER_NOP)
3426                 return 0;
3427
3428         if (arg == NULL) {
3429                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3430                             filter_op);
3431                 return -EINVAL;
3432         }
3433
3434         switch (filter_op) {
3435         case RTE_ETH_FILTER_ADD:
3436                 ret = eth_igb_syn_filter_set(dev,
3437                                 (struct rte_eth_syn_filter *)arg,
3438                                 TRUE);
3439                 break;
3440         case RTE_ETH_FILTER_DELETE:
3441                 ret = eth_igb_syn_filter_set(dev,
3442                                 (struct rte_eth_syn_filter *)arg,
3443                                 FALSE);
3444                 break;
3445         case RTE_ETH_FILTER_GET:
3446                 ret = eth_igb_syn_filter_get(dev,
3447                                 (struct rte_eth_syn_filter *)arg);
3448                 break;
3449         default:
3450                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3451                 ret = -EINVAL;
3452                 break;
3453         }
3454
3455         return ret;
3456 }
3457
3458 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3459         if ((type) != e1000_82580 && (type) != e1000_i350)\
3460                 return -ENOSYS; \
3461 } while (0)
3462
3463 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3464 static inline int
3465 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3466                         struct e1000_2tuple_filter_info *filter_info)
3467 {
3468         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3469                 return -EINVAL;
3470         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3471                 return -EINVAL;  /* filter index is out of range. */
3472         if (filter->tcp_flags > TCP_FLAG_ALL)
3473                 return -EINVAL;  /* flags is invalid. */
3474
3475         switch (filter->dst_port_mask) {
3476         case UINT16_MAX:
3477                 filter_info->dst_port_mask = 0;
3478                 filter_info->dst_port = filter->dst_port;
3479                 break;
3480         case 0:
3481                 filter_info->dst_port_mask = 1;
3482                 break;
3483         default:
3484                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3485                 return -EINVAL;
3486         }
3487
3488         switch (filter->proto_mask) {
3489         case UINT8_MAX:
3490                 filter_info->proto_mask = 0;
3491                 filter_info->proto = filter->proto;
3492                 break;
3493         case 0:
3494                 filter_info->proto_mask = 1;
3495                 break;
3496         default:
3497                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3498                 return -EINVAL;
3499         }
3500
3501         filter_info->priority = (uint8_t)filter->priority;
3502         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3503                 filter_info->tcp_flags = filter->tcp_flags;
3504         else
3505                 filter_info->tcp_flags = 0;
3506
3507         return 0;
3508 }
3509
3510 static inline struct e1000_2tuple_filter *
3511 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3512                         struct e1000_2tuple_filter_info *key)
3513 {
3514         struct e1000_2tuple_filter *it;
3515
3516         TAILQ_FOREACH(it, filter_list, entries) {
3517                 if (memcmp(key, &it->filter_info,
3518                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3519                         return it;
3520                 }
3521         }
3522         return NULL;
3523 }
3524
3525 /*
3526  * igb_add_2tuple_filter - add a 2tuple filter
3527  *
3528  * @param
3529  * dev: Pointer to struct rte_eth_dev.
3530  * ntuple_filter: ponter to the filter that will be added.
3531  *
3532  * @return
3533  *    - On success, zero.
3534  *    - On failure, a negative value.
3535  */
3536 static int
3537 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3538                         struct rte_eth_ntuple_filter *ntuple_filter)
3539 {
3540         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3541         struct e1000_filter_info *filter_info =
3542                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3543         struct e1000_2tuple_filter *filter;
3544         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3545         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3546         int i, ret;
3547
3548         filter = rte_zmalloc("e1000_2tuple_filter",
3549                         sizeof(struct e1000_2tuple_filter), 0);
3550         if (filter == NULL)
3551                 return -ENOMEM;
3552
3553         ret = ntuple_filter_to_2tuple(ntuple_filter,
3554                                       &filter->filter_info);
3555         if (ret < 0) {
3556                 rte_free(filter);
3557                 return ret;
3558         }
3559         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3560                                          &filter->filter_info) != NULL) {
3561                 PMD_DRV_LOG(ERR, "filter exists.");
3562                 rte_free(filter);
3563                 return -EEXIST;
3564         }
3565         filter->queue = ntuple_filter->queue;
3566
3567         /*
3568          * look for an unused 2tuple filter index,
3569          * and insert the filter to list.
3570          */
3571         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3572                 if (!(filter_info->twotuple_mask & (1 << i))) {
3573                         filter_info->twotuple_mask |= 1 << i;
3574                         filter->index = i;
3575                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3576                                           filter,
3577                                           entries);
3578                         break;
3579                 }
3580         }
3581         if (i >= E1000_MAX_TTQF_FILTERS) {
3582                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3583                 rte_free(filter);
3584                 return -ENOSYS;
3585         }
3586
3587         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3588         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3589                 imir |= E1000_IMIR_PORT_BP;
3590         else
3591                 imir &= ~E1000_IMIR_PORT_BP;
3592
3593         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3594
3595         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3596         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3597         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3598         if (filter->filter_info.proto_mask == 0)
3599                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3600
3601         /* tcp flags bits setting. */
3602         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3603                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3604                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3605                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3606                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3607                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3608                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3609                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3610                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3611                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3612                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3613                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3614                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3615         } else
3616                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3617         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3618         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3619         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3620         return 0;
3621 }
3622
3623 /*
3624  * igb_remove_2tuple_filter - remove a 2tuple filter
3625  *
3626  * @param
3627  * dev: Pointer to struct rte_eth_dev.
3628  * ntuple_filter: ponter to the filter that will be removed.
3629  *
3630  * @return
3631  *    - On success, zero.
3632  *    - On failure, a negative value.
3633  */
3634 static int
3635 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3636                         struct rte_eth_ntuple_filter *ntuple_filter)
3637 {
3638         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3639         struct e1000_filter_info *filter_info =
3640                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3641         struct e1000_2tuple_filter_info filter_2tuple;
3642         struct e1000_2tuple_filter *filter;
3643         int ret;
3644
3645         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3646         ret = ntuple_filter_to_2tuple(ntuple_filter,
3647                                       &filter_2tuple);
3648         if (ret < 0)
3649                 return ret;
3650
3651         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3652                                          &filter_2tuple);
3653         if (filter == NULL) {
3654                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3655                 return -ENOENT;
3656         }
3657
3658         filter_info->twotuple_mask &= ~(1 << filter->index);
3659         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3660         rte_free(filter);
3661
3662         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3663         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3664         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3665         return 0;
3666 }
3667
3668 static inline struct e1000_flex_filter *
3669 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3670                         struct e1000_flex_filter_info *key)
3671 {
3672         struct e1000_flex_filter *it;
3673
3674         TAILQ_FOREACH(it, filter_list, entries) {
3675                 if (memcmp(key, &it->filter_info,
3676                         sizeof(struct e1000_flex_filter_info)) == 0)
3677                         return it;
3678         }
3679
3680         return NULL;
3681 }
3682
3683 static int
3684 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3685                         struct rte_eth_flex_filter *filter,
3686                         bool add)
3687 {
3688         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3689         struct e1000_filter_info *filter_info =
3690                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3691         struct e1000_flex_filter *flex_filter, *it;
3692         uint32_t wufc, queueing, mask;
3693         uint32_t reg_off;
3694         uint8_t shift, i, j = 0;
3695
3696         flex_filter = rte_zmalloc("e1000_flex_filter",
3697                         sizeof(struct e1000_flex_filter), 0);
3698         if (flex_filter == NULL)
3699                 return -ENOMEM;
3700
3701         flex_filter->filter_info.len = filter->len;
3702         flex_filter->filter_info.priority = filter->priority;
3703         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3704         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3705                 mask = 0;
3706                 /* reverse bits in flex filter's mask*/
3707                 for (shift = 0; shift < CHAR_BIT; shift++) {
3708                         if (filter->mask[i] & (0x01 << shift))
3709                                 mask |= (0x80 >> shift);
3710                 }
3711                 flex_filter->filter_info.mask[i] = mask;
3712         }
3713
3714         wufc = E1000_READ_REG(hw, E1000_WUFC);
3715         if (flex_filter->index < E1000_MAX_FHFT)
3716                 reg_off = E1000_FHFT(flex_filter->index);
3717         else
3718                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3719
3720         if (add) {
3721                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3722                                 &flex_filter->filter_info) != NULL) {
3723                         PMD_DRV_LOG(ERR, "filter exists.");
3724                         rte_free(flex_filter);
3725                         return -EEXIST;
3726                 }
3727                 flex_filter->queue = filter->queue;
3728                 /*
3729                  * look for an unused flex filter index
3730                  * and insert the filter into the list.
3731                  */
3732                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3733                         if (!(filter_info->flex_mask & (1 << i))) {
3734                                 filter_info->flex_mask |= 1 << i;
3735                                 flex_filter->index = i;
3736                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3737                                         flex_filter,
3738                                         entries);
3739                                 break;
3740                         }
3741                 }
3742                 if (i >= E1000_MAX_FLEX_FILTERS) {
3743                         PMD_DRV_LOG(ERR, "flex filters are full.");
3744                         rte_free(flex_filter);
3745                         return -ENOSYS;
3746                 }
3747
3748                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3749                                 (E1000_WUFC_FLX0 << flex_filter->index));
3750                 queueing = filter->len |
3751                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3752                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3753                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3754                                 queueing);
3755                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3756                         E1000_WRITE_REG(hw, reg_off,
3757                                         flex_filter->filter_info.dwords[j]);
3758                         reg_off += sizeof(uint32_t);
3759                         E1000_WRITE_REG(hw, reg_off,
3760                                         flex_filter->filter_info.dwords[++j]);
3761                         reg_off += sizeof(uint32_t);
3762                         E1000_WRITE_REG(hw, reg_off,
3763                                 (uint32_t)flex_filter->filter_info.mask[i]);
3764                         reg_off += sizeof(uint32_t) * 2;
3765                         ++j;
3766                 }
3767         } else {
3768                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3769                                 &flex_filter->filter_info);
3770                 if (it == NULL) {
3771                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3772                         rte_free(flex_filter);
3773                         return -ENOENT;
3774                 }
3775
3776                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3777                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3778                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3779                         (~(E1000_WUFC_FLX0 << it->index)));
3780
3781                 filter_info->flex_mask &= ~(1 << it->index);
3782                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3783                 rte_free(it);
3784                 rte_free(flex_filter);
3785         }
3786
3787         return 0;
3788 }
3789
3790 static int
3791 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3792                         struct rte_eth_flex_filter *filter)
3793 {
3794         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3795         struct e1000_filter_info *filter_info =
3796                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3797         struct e1000_flex_filter flex_filter, *it;
3798         uint32_t wufc, queueing, wufc_en = 0;
3799
3800         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3801         flex_filter.filter_info.len = filter->len;
3802         flex_filter.filter_info.priority = filter->priority;
3803         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3804         memcpy(flex_filter.filter_info.mask, filter->mask,
3805                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3806
3807         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3808                                 &flex_filter.filter_info);
3809         if (it == NULL) {
3810                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3811                 return -ENOENT;
3812         }
3813
3814         wufc = E1000_READ_REG(hw, E1000_WUFC);
3815         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3816
3817         if ((wufc & wufc_en) == wufc_en) {
3818                 uint32_t reg_off = 0;
3819                 if (it->index < E1000_MAX_FHFT)
3820                         reg_off = E1000_FHFT(it->index);
3821                 else
3822                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3823
3824                 queueing = E1000_READ_REG(hw,
3825                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3826                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3827                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3828                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3829                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3830                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3831                 return 0;
3832         }
3833         return -ENOENT;
3834 }
3835
3836 static int
3837 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3838                         enum rte_filter_op filter_op,
3839                         void *arg)
3840 {
3841         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3842         struct rte_eth_flex_filter *filter;
3843         int ret = 0;
3844
3845         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3846
3847         if (filter_op == RTE_ETH_FILTER_NOP)
3848                 return ret;
3849
3850         if (arg == NULL) {
3851                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3852                             filter_op);
3853                 return -EINVAL;
3854         }
3855
3856         filter = (struct rte_eth_flex_filter *)arg;
3857         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3858             || filter->len % sizeof(uint64_t) != 0) {
3859                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3860                 return -EINVAL;
3861         }
3862         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3863                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3864                 return -EINVAL;
3865         }
3866
3867         switch (filter_op) {
3868         case RTE_ETH_FILTER_ADD:
3869                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3870                 break;
3871         case RTE_ETH_FILTER_DELETE:
3872                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3873                 break;
3874         case RTE_ETH_FILTER_GET:
3875                 ret = eth_igb_get_flex_filter(dev, filter);
3876                 break;
3877         default:
3878                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3879                 ret = -EINVAL;
3880                 break;
3881         }
3882
3883         return ret;
3884 }
3885
3886 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3887 static inline int
3888 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3889                         struct e1000_5tuple_filter_info *filter_info)
3890 {
3891         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3892                 return -EINVAL;
3893         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3894                 return -EINVAL;  /* filter index is out of range. */
3895         if (filter->tcp_flags > TCP_FLAG_ALL)
3896                 return -EINVAL;  /* flags is invalid. */
3897
3898         switch (filter->dst_ip_mask) {
3899         case UINT32_MAX:
3900                 filter_info->dst_ip_mask = 0;
3901                 filter_info->dst_ip = filter->dst_ip;
3902                 break;
3903         case 0:
3904                 filter_info->dst_ip_mask = 1;
3905                 break;
3906         default:
3907                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3908                 return -EINVAL;
3909         }
3910
3911         switch (filter->src_ip_mask) {
3912         case UINT32_MAX:
3913                 filter_info->src_ip_mask = 0;
3914                 filter_info->src_ip = filter->src_ip;
3915                 break;
3916         case 0:
3917                 filter_info->src_ip_mask = 1;
3918                 break;
3919         default:
3920                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3921                 return -EINVAL;
3922         }
3923
3924         switch (filter->dst_port_mask) {
3925         case UINT16_MAX:
3926                 filter_info->dst_port_mask = 0;
3927                 filter_info->dst_port = filter->dst_port;
3928                 break;
3929         case 0:
3930                 filter_info->dst_port_mask = 1;
3931                 break;
3932         default:
3933                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3934                 return -EINVAL;
3935         }
3936
3937         switch (filter->src_port_mask) {
3938         case UINT16_MAX:
3939                 filter_info->src_port_mask = 0;
3940                 filter_info->src_port = filter->src_port;
3941                 break;
3942         case 0:
3943                 filter_info->src_port_mask = 1;
3944                 break;
3945         default:
3946                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3947                 return -EINVAL;
3948         }
3949
3950         switch (filter->proto_mask) {
3951         case UINT8_MAX:
3952                 filter_info->proto_mask = 0;
3953                 filter_info->proto = filter->proto;
3954                 break;
3955         case 0:
3956                 filter_info->proto_mask = 1;
3957                 break;
3958         default:
3959                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3960                 return -EINVAL;
3961         }
3962
3963         filter_info->priority = (uint8_t)filter->priority;
3964         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3965                 filter_info->tcp_flags = filter->tcp_flags;
3966         else
3967                 filter_info->tcp_flags = 0;
3968
3969         return 0;
3970 }
3971
3972 static inline struct e1000_5tuple_filter *
3973 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3974                         struct e1000_5tuple_filter_info *key)
3975 {
3976         struct e1000_5tuple_filter *it;
3977
3978         TAILQ_FOREACH(it, filter_list, entries) {
3979                 if (memcmp(key, &it->filter_info,
3980                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3981                         return it;
3982                 }
3983         }
3984         return NULL;
3985 }
3986
3987 /*
3988  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3989  *
3990  * @param
3991  * dev: Pointer to struct rte_eth_dev.
3992  * ntuple_filter: ponter to the filter that will be added.
3993  *
3994  * @return
3995  *    - On success, zero.
3996  *    - On failure, a negative value.
3997  */
3998 static int
3999 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4000                         struct rte_eth_ntuple_filter *ntuple_filter)
4001 {
4002         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4003         struct e1000_filter_info *filter_info =
4004                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4005         struct e1000_5tuple_filter *filter;
4006         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4007         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4008         uint8_t i;
4009         int ret;
4010
4011         filter = rte_zmalloc("e1000_5tuple_filter",
4012                         sizeof(struct e1000_5tuple_filter), 0);
4013         if (filter == NULL)
4014                 return -ENOMEM;
4015
4016         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4017                                             &filter->filter_info);
4018         if (ret < 0) {
4019                 rte_free(filter);
4020                 return ret;
4021         }
4022
4023         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4024                                          &filter->filter_info) != NULL) {
4025                 PMD_DRV_LOG(ERR, "filter exists.");
4026                 rte_free(filter);
4027                 return -EEXIST;
4028         }
4029         filter->queue = ntuple_filter->queue;
4030
4031         /*
4032          * look for an unused 5tuple filter index,
4033          * and insert the filter to list.
4034          */
4035         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4036                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4037                         filter_info->fivetuple_mask |= 1 << i;
4038                         filter->index = i;
4039                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4040                                           filter,
4041                                           entries);
4042                         break;
4043                 }
4044         }
4045         if (i >= E1000_MAX_FTQF_FILTERS) {
4046                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4047                 rte_free(filter);
4048                 return -ENOSYS;
4049         }
4050
4051         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4052         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4053                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4054         if (filter->filter_info.dst_ip_mask == 0)
4055                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4056         if (filter->filter_info.src_port_mask == 0)
4057                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4058         if (filter->filter_info.proto_mask == 0)
4059                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4060         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4061                 E1000_FTQF_QUEUE_MASK;
4062         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4063         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4064         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4065         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4066
4067         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4068         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4069
4070         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4071         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4072                 imir |= E1000_IMIR_PORT_BP;
4073         else
4074                 imir &= ~E1000_IMIR_PORT_BP;
4075         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4076
4077         /* tcp flags bits setting. */
4078         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4079                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4080                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4081                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4082                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4083                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4084                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4085                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4086                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4087                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4088                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4089                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4090                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4091         } else
4092                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4093         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4094         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4095         return 0;
4096 }
4097
4098 /*
4099  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4100  *
4101  * @param
4102  * dev: Pointer to struct rte_eth_dev.
4103  * ntuple_filter: ponter to the filter that will be removed.
4104  *
4105  * @return
4106  *    - On success, zero.
4107  *    - On failure, a negative value.
4108  */
4109 static int
4110 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4111                                 struct rte_eth_ntuple_filter *ntuple_filter)
4112 {
4113         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4114         struct e1000_filter_info *filter_info =
4115                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4116         struct e1000_5tuple_filter_info filter_5tuple;
4117         struct e1000_5tuple_filter *filter;
4118         int ret;
4119
4120         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4121         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4122                                             &filter_5tuple);
4123         if (ret < 0)
4124                 return ret;
4125
4126         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4127                                          &filter_5tuple);
4128         if (filter == NULL) {
4129                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4130                 return -ENOENT;
4131         }
4132
4133         filter_info->fivetuple_mask &= ~(1 << filter->index);
4134         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4135         rte_free(filter);
4136
4137         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4138                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4139         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4140         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4141         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4142         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4143         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4144         return 0;
4145 }
4146
4147 static int
4148 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4149 {
4150         uint32_t rctl;
4151         struct e1000_hw *hw;
4152         struct rte_eth_dev_info dev_info;
4153         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4154                                      VLAN_TAG_SIZE);
4155
4156         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4157
4158 #ifdef RTE_LIBRTE_82571_SUPPORT
4159         /* XXX: not bigger than max_rx_pktlen */
4160         if (hw->mac.type == e1000_82571)
4161                 return -ENOTSUP;
4162 #endif
4163         eth_igb_infos_get(dev, &dev_info);
4164
4165         /* check that mtu is within the allowed range */
4166         if ((mtu < ETHER_MIN_MTU) ||
4167             (frame_size > dev_info.max_rx_pktlen))
4168                 return -EINVAL;
4169
4170         /* refuse mtu that requires the support of scattered packets when this
4171          * feature has not been enabled before. */
4172         if (!dev->data->scattered_rx &&
4173             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4174                 return -EINVAL;
4175
4176         rctl = E1000_READ_REG(hw, E1000_RCTL);
4177
4178         /* switch to jumbo mode if needed */
4179         if (frame_size > ETHER_MAX_LEN) {
4180                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4181                 rctl |= E1000_RCTL_LPE;
4182         } else {
4183                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4184                 rctl &= ~E1000_RCTL_LPE;
4185         }
4186         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4187
4188         /* update max frame size */
4189         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4190
4191         E1000_WRITE_REG(hw, E1000_RLPML,
4192                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4193
4194         return 0;
4195 }
4196
4197 /*
4198  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4199  *
4200  * @param
4201  * dev: Pointer to struct rte_eth_dev.
4202  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4203  * add: if true, add filter, if false, remove filter
4204  *
4205  * @return
4206  *    - On success, zero.
4207  *    - On failure, a negative value.
4208  */
4209 static int
4210 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4211                         struct rte_eth_ntuple_filter *ntuple_filter,
4212                         bool add)
4213 {
4214         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4215         int ret;
4216
4217         switch (ntuple_filter->flags) {
4218         case RTE_5TUPLE_FLAGS:
4219         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4220                 if (hw->mac.type != e1000_82576)
4221                         return -ENOTSUP;
4222                 if (add)
4223                         ret = igb_add_5tuple_filter_82576(dev,
4224                                                           ntuple_filter);
4225                 else
4226                         ret = igb_remove_5tuple_filter_82576(dev,
4227                                                              ntuple_filter);
4228                 break;
4229         case RTE_2TUPLE_FLAGS:
4230         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4231                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4232                         return -ENOTSUP;
4233                 if (add)
4234                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4235                 else
4236                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4237                 break;
4238         default:
4239                 ret = -EINVAL;
4240                 break;
4241         }
4242
4243         return ret;
4244 }
4245
4246 /*
4247  * igb_get_ntuple_filter - get a ntuple filter
4248  *
4249  * @param
4250  * dev: Pointer to struct rte_eth_dev.
4251  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4252  *
4253  * @return
4254  *    - On success, zero.
4255  *    - On failure, a negative value.
4256  */
4257 static int
4258 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4259                         struct rte_eth_ntuple_filter *ntuple_filter)
4260 {
4261         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4262         struct e1000_filter_info *filter_info =
4263                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4264         struct e1000_5tuple_filter_info filter_5tuple;
4265         struct e1000_2tuple_filter_info filter_2tuple;
4266         struct e1000_5tuple_filter *p_5tuple_filter;
4267         struct e1000_2tuple_filter *p_2tuple_filter;
4268         int ret;
4269
4270         switch (ntuple_filter->flags) {
4271         case RTE_5TUPLE_FLAGS:
4272         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4273                 if (hw->mac.type != e1000_82576)
4274                         return -ENOTSUP;
4275                 memset(&filter_5tuple,
4276                         0,
4277                         sizeof(struct e1000_5tuple_filter_info));
4278                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4279                                                     &filter_5tuple);
4280                 if (ret < 0)
4281                         return ret;
4282                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4283                                         &filter_info->fivetuple_list,
4284                                         &filter_5tuple);
4285                 if (p_5tuple_filter == NULL) {
4286                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4287                         return -ENOENT;
4288                 }
4289                 ntuple_filter->queue = p_5tuple_filter->queue;
4290                 break;
4291         case RTE_2TUPLE_FLAGS:
4292         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4293                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4294                         return -ENOTSUP;
4295                 memset(&filter_2tuple,
4296                         0,
4297                         sizeof(struct e1000_2tuple_filter_info));
4298                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4299                 if (ret < 0)
4300                         return ret;
4301                 p_2tuple_filter = igb_2tuple_filter_lookup(
4302                                         &filter_info->twotuple_list,
4303                                         &filter_2tuple);
4304                 if (p_2tuple_filter == NULL) {
4305                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4306                         return -ENOENT;
4307                 }
4308                 ntuple_filter->queue = p_2tuple_filter->queue;
4309                 break;
4310         default:
4311                 ret = -EINVAL;
4312                 break;
4313         }
4314
4315         return 0;
4316 }
4317
4318 /*
4319  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4320  * @dev: pointer to rte_eth_dev structure
4321  * @filter_op:operation will be taken.
4322  * @arg: a pointer to specific structure corresponding to the filter_op
4323  */
4324 static int
4325 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4326                                 enum rte_filter_op filter_op,
4327                                 void *arg)
4328 {
4329         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4330         int ret;
4331
4332         MAC_TYPE_FILTER_SUP(hw->mac.type);
4333
4334         if (filter_op == RTE_ETH_FILTER_NOP)
4335                 return 0;
4336
4337         if (arg == NULL) {
4338                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4339                             filter_op);
4340                 return -EINVAL;
4341         }
4342
4343         switch (filter_op) {
4344         case RTE_ETH_FILTER_ADD:
4345                 ret = igb_add_del_ntuple_filter(dev,
4346                         (struct rte_eth_ntuple_filter *)arg,
4347                         TRUE);
4348                 break;
4349         case RTE_ETH_FILTER_DELETE:
4350                 ret = igb_add_del_ntuple_filter(dev,
4351                         (struct rte_eth_ntuple_filter *)arg,
4352                         FALSE);
4353                 break;
4354         case RTE_ETH_FILTER_GET:
4355                 ret = igb_get_ntuple_filter(dev,
4356                         (struct rte_eth_ntuple_filter *)arg);
4357                 break;
4358         default:
4359                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4360                 ret = -EINVAL;
4361                 break;
4362         }
4363         return ret;
4364 }
4365
4366 static inline int
4367 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4368                         uint16_t ethertype)
4369 {
4370         int i;
4371
4372         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4373                 if (filter_info->ethertype_filters[i] == ethertype &&
4374                     (filter_info->ethertype_mask & (1 << i)))
4375                         return i;
4376         }
4377         return -1;
4378 }
4379
4380 static inline int
4381 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4382                         uint16_t ethertype)
4383 {
4384         int i;
4385
4386         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4387                 if (!(filter_info->ethertype_mask & (1 << i))) {
4388                         filter_info->ethertype_mask |= 1 << i;
4389                         filter_info->ethertype_filters[i] = ethertype;
4390                         return i;
4391                 }
4392         }
4393         return -1;
4394 }
4395
4396 static inline int
4397 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4398                         uint8_t idx)
4399 {
4400         if (idx >= E1000_MAX_ETQF_FILTERS)
4401                 return -1;
4402         filter_info->ethertype_mask &= ~(1 << idx);
4403         filter_info->ethertype_filters[idx] = 0;
4404         return idx;
4405 }
4406
4407
4408 static int
4409 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4410                         struct rte_eth_ethertype_filter *filter,
4411                         bool add)
4412 {
4413         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4414         struct e1000_filter_info *filter_info =
4415                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4416         uint32_t etqf = 0;
4417         int ret;
4418
4419         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4420                 filter->ether_type == ETHER_TYPE_IPv6) {
4421                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4422                         " ethertype filter.", filter->ether_type);
4423                 return -EINVAL;
4424         }
4425
4426         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4427                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4428                 return -EINVAL;
4429         }
4430         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4431                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4432                 return -EINVAL;
4433         }
4434
4435         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4436         if (ret >= 0 && add) {
4437                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4438                             filter->ether_type);
4439                 return -EEXIST;
4440         }
4441         if (ret < 0 && !add) {
4442                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4443                             filter->ether_type);
4444                 return -ENOENT;
4445         }
4446
4447         if (add) {
4448                 ret = igb_ethertype_filter_insert(filter_info,
4449                         filter->ether_type);
4450                 if (ret < 0) {
4451                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4452                         return -ENOSYS;
4453                 }
4454
4455                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4456                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4457                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4458         } else {
4459                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4460                 if (ret < 0)
4461                         return -ENOSYS;
4462         }
4463         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4464         E1000_WRITE_FLUSH(hw);
4465
4466         return 0;
4467 }
4468
4469 static int
4470 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4471                         struct rte_eth_ethertype_filter *filter)
4472 {
4473         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4474         struct e1000_filter_info *filter_info =
4475                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4476         uint32_t etqf;
4477         int ret;
4478
4479         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4480         if (ret < 0) {
4481                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4482                             filter->ether_type);
4483                 return -ENOENT;
4484         }
4485
4486         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4487         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4488                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4489                 filter->flags = 0;
4490                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4491                                 E1000_ETQF_QUEUE_SHIFT;
4492                 return 0;
4493         }
4494
4495         return -ENOENT;
4496 }
4497
4498 /*
4499  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4500  * @dev: pointer to rte_eth_dev structure
4501  * @filter_op:operation will be taken.
4502  * @arg: a pointer to specific structure corresponding to the filter_op
4503  */
4504 static int
4505 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4506                                 enum rte_filter_op filter_op,
4507                                 void *arg)
4508 {
4509         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4510         int ret;
4511
4512         MAC_TYPE_FILTER_SUP(hw->mac.type);
4513
4514         if (filter_op == RTE_ETH_FILTER_NOP)
4515                 return 0;
4516
4517         if (arg == NULL) {
4518                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4519                             filter_op);
4520                 return -EINVAL;
4521         }
4522
4523         switch (filter_op) {
4524         case RTE_ETH_FILTER_ADD:
4525                 ret = igb_add_del_ethertype_filter(dev,
4526                         (struct rte_eth_ethertype_filter *)arg,
4527                         TRUE);
4528                 break;
4529         case RTE_ETH_FILTER_DELETE:
4530                 ret = igb_add_del_ethertype_filter(dev,
4531                         (struct rte_eth_ethertype_filter *)arg,
4532                         FALSE);
4533                 break;
4534         case RTE_ETH_FILTER_GET:
4535                 ret = igb_get_ethertype_filter(dev,
4536                         (struct rte_eth_ethertype_filter *)arg);
4537                 break;
4538         default:
4539                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4540                 ret = -EINVAL;
4541                 break;
4542         }
4543         return ret;
4544 }
4545
4546 static int
4547 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4548                      enum rte_filter_type filter_type,
4549                      enum rte_filter_op filter_op,
4550                      void *arg)
4551 {
4552         int ret = -EINVAL;
4553
4554         switch (filter_type) {
4555         case RTE_ETH_FILTER_NTUPLE:
4556                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4557                 break;
4558         case RTE_ETH_FILTER_ETHERTYPE:
4559                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4560                 break;
4561         case RTE_ETH_FILTER_SYN:
4562                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4563                 break;
4564         case RTE_ETH_FILTER_FLEXIBLE:
4565                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4566                 break;
4567         default:
4568                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4569                                                         filter_type);
4570                 break;
4571         }
4572
4573         return ret;
4574 }
4575
4576 static int
4577 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4578                          struct ether_addr *mc_addr_set,
4579                          uint32_t nb_mc_addr)
4580 {
4581         struct e1000_hw *hw;
4582
4583         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4584         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4585         return 0;
4586 }
4587
4588 static uint64_t
4589 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4590 {
4591         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4592         uint64_t systime_cycles;
4593
4594         switch (hw->mac.type) {
4595         case e1000_i210:
4596         case e1000_i211:
4597                 /*
4598                  * Need to read System Time Residue Register to be able
4599                  * to read the other two registers.
4600                  */
4601                 E1000_READ_REG(hw, E1000_SYSTIMR);
4602                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4603                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4604                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4605                                 * NSEC_PER_SEC;
4606                 break;
4607         case e1000_82580:
4608         case e1000_i350:
4609         case e1000_i354:
4610                 /*
4611                  * Need to read System Time Residue Register to be able
4612                  * to read the other two registers.
4613                  */
4614                 E1000_READ_REG(hw, E1000_SYSTIMR);
4615                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4616                 /* Only the 8 LSB are valid. */
4617                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4618                                 & 0xff) << 32;
4619                 break;
4620         default:
4621                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4622                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4623                                 << 32;
4624                 break;
4625         }
4626
4627         return systime_cycles;
4628 }
4629
4630 static uint64_t
4631 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4632 {
4633         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4634         uint64_t rx_tstamp_cycles;
4635
4636         switch (hw->mac.type) {
4637         case e1000_i210:
4638         case e1000_i211:
4639                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4640                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4641                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4642                                 * NSEC_PER_SEC;
4643                 break;
4644         case e1000_82580:
4645         case e1000_i350:
4646         case e1000_i354:
4647                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4648                 /* Only the 8 LSB are valid. */
4649                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4650                                 & 0xff) << 32;
4651                 break;
4652         default:
4653                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4654                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4655                                 << 32;
4656                 break;
4657         }
4658
4659         return rx_tstamp_cycles;
4660 }
4661
4662 static uint64_t
4663 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4664 {
4665         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4666         uint64_t tx_tstamp_cycles;
4667
4668         switch (hw->mac.type) {
4669         case e1000_i210:
4670         case e1000_i211:
4671                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4672                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4673                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4674                                 * NSEC_PER_SEC;
4675                 break;
4676         case e1000_82580:
4677         case e1000_i350:
4678         case e1000_i354:
4679                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4680                 /* Only the 8 LSB are valid. */
4681                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4682                                 & 0xff) << 32;
4683                 break;
4684         default:
4685                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4686                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4687                                 << 32;
4688                 break;
4689         }
4690
4691         return tx_tstamp_cycles;
4692 }
4693
4694 static void
4695 igb_start_timecounters(struct rte_eth_dev *dev)
4696 {
4697         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4698         struct e1000_adapter *adapter =
4699                 (struct e1000_adapter *)dev->data->dev_private;
4700         uint32_t incval = 1;
4701         uint32_t shift = 0;
4702         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4703
4704         switch (hw->mac.type) {
4705         case e1000_82580:
4706         case e1000_i350:
4707         case e1000_i354:
4708                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4709                 mask = (1ULL << 40) - 1;
4710                 /* fall-through */
4711         case e1000_i210:
4712         case e1000_i211:
4713                 /*
4714                  * Start incrementing the register
4715                  * used to timestamp PTP packets.
4716                  */
4717                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4718                 break;
4719         case e1000_82576:
4720                 incval = E1000_INCVALUE_82576;
4721                 shift = IGB_82576_TSYNC_SHIFT;
4722                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4723                                 E1000_INCPERIOD_82576 | incval);
4724                 break;
4725         default:
4726                 /* Not supported */
4727                 return;
4728         }
4729
4730         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4731         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4732         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4733
4734         adapter->systime_tc.cc_mask = mask;
4735         adapter->systime_tc.cc_shift = shift;
4736         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4737
4738         adapter->rx_tstamp_tc.cc_mask = mask;
4739         adapter->rx_tstamp_tc.cc_shift = shift;
4740         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4741
4742         adapter->tx_tstamp_tc.cc_mask = mask;
4743         adapter->tx_tstamp_tc.cc_shift = shift;
4744         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4745 }
4746
4747 static int
4748 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4749 {
4750         struct e1000_adapter *adapter =
4751                         (struct e1000_adapter *)dev->data->dev_private;
4752
4753         adapter->systime_tc.nsec += delta;
4754         adapter->rx_tstamp_tc.nsec += delta;
4755         adapter->tx_tstamp_tc.nsec += delta;
4756
4757         return 0;
4758 }
4759
4760 static int
4761 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4762 {
4763         uint64_t ns;
4764         struct e1000_adapter *adapter =
4765                         (struct e1000_adapter *)dev->data->dev_private;
4766
4767         ns = rte_timespec_to_ns(ts);
4768
4769         /* Set the timecounters to a new value. */
4770         adapter->systime_tc.nsec = ns;
4771         adapter->rx_tstamp_tc.nsec = ns;
4772         adapter->tx_tstamp_tc.nsec = ns;
4773
4774         return 0;
4775 }
4776
4777 static int
4778 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4779 {
4780         uint64_t ns, systime_cycles;
4781         struct e1000_adapter *adapter =
4782                         (struct e1000_adapter *)dev->data->dev_private;
4783
4784         systime_cycles = igb_read_systime_cyclecounter(dev);
4785         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4786         *ts = rte_ns_to_timespec(ns);
4787
4788         return 0;
4789 }
4790
4791 static int
4792 igb_timesync_enable(struct rte_eth_dev *dev)
4793 {
4794         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4795         uint32_t tsync_ctl;
4796         uint32_t tsauxc;
4797
4798         /* Stop the timesync system time. */
4799         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4800         /* Reset the timesync system time value. */
4801         switch (hw->mac.type) {
4802         case e1000_82580:
4803         case e1000_i350:
4804         case e1000_i354:
4805         case e1000_i210:
4806         case e1000_i211:
4807                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4808                 /* fall-through */
4809         case e1000_82576:
4810                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4811                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4812                 break;
4813         default:
4814                 /* Not supported. */
4815                 return -ENOTSUP;
4816         }
4817
4818         /* Enable system time for it isn't on by default. */
4819         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4820         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4821         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4822
4823         igb_start_timecounters(dev);
4824
4825         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4826         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4827                         (ETHER_TYPE_1588 |
4828                          E1000_ETQF_FILTER_ENABLE |
4829                          E1000_ETQF_1588));
4830
4831         /* Enable timestamping of received PTP packets. */
4832         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4833         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4834         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4835
4836         /* Enable Timestamping of transmitted PTP packets. */
4837         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4838         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4839         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4840
4841         return 0;
4842 }
4843
4844 static int
4845 igb_timesync_disable(struct rte_eth_dev *dev)
4846 {
4847         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4848         uint32_t tsync_ctl;
4849
4850         /* Disable timestamping of transmitted PTP packets. */
4851         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4852         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4853         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4854
4855         /* Disable timestamping of received PTP packets. */
4856         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4857         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4858         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4859
4860         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4861         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4862
4863         /* Stop incrementating the System Time registers. */
4864         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4865
4866         return 0;
4867 }
4868
4869 static int
4870 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4871                                struct timespec *timestamp,
4872                                uint32_t flags __rte_unused)
4873 {
4874         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4875         struct e1000_adapter *adapter =
4876                         (struct e1000_adapter *)dev->data->dev_private;
4877         uint32_t tsync_rxctl;
4878         uint64_t rx_tstamp_cycles;
4879         uint64_t ns;
4880
4881         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4882         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4883                 return -EINVAL;
4884
4885         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4886         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4887         *timestamp = rte_ns_to_timespec(ns);
4888
4889         return  0;
4890 }
4891
4892 static int
4893 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4894                                struct timespec *timestamp)
4895 {
4896         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4897         struct e1000_adapter *adapter =
4898                         (struct e1000_adapter *)dev->data->dev_private;
4899         uint32_t tsync_txctl;
4900         uint64_t tx_tstamp_cycles;
4901         uint64_t ns;
4902
4903         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4904         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4905                 return -EINVAL;
4906
4907         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4908         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4909         *timestamp = rte_ns_to_timespec(ns);
4910
4911         return  0;
4912 }
4913
4914 static int
4915 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4916 {
4917         int count = 0;
4918         int g_ind = 0;
4919         const struct reg_info *reg_group;
4920
4921         while ((reg_group = igb_regs[g_ind++]))
4922                 count += igb_reg_group_count(reg_group);
4923
4924         return count;
4925 }
4926
4927 static int
4928 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4929 {
4930         int count = 0;
4931         int g_ind = 0;
4932         const struct reg_info *reg_group;
4933
4934         while ((reg_group = igbvf_regs[g_ind++]))
4935                 count += igb_reg_group_count(reg_group);
4936
4937         return count;
4938 }
4939
4940 static int
4941 eth_igb_get_regs(struct rte_eth_dev *dev,
4942         struct rte_dev_reg_info *regs)
4943 {
4944         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4945         uint32_t *data = regs->data;
4946         int g_ind = 0;
4947         int count = 0;
4948         const struct reg_info *reg_group;
4949
4950         /* Support only full register dump */
4951         if ((regs->length == 0) ||
4952             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4953                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4954                         hw->device_id;
4955                 while ((reg_group = igb_regs[g_ind++]))
4956                         count += igb_read_regs_group(dev, &data[count],
4957                                                         reg_group);
4958                 return 0;
4959         }
4960
4961         return -ENOTSUP;
4962 }
4963
4964 static int
4965 igbvf_get_regs(struct rte_eth_dev *dev,
4966         struct rte_dev_reg_info *regs)
4967 {
4968         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4969         uint32_t *data = regs->data;
4970         int g_ind = 0;
4971         int count = 0;
4972         const struct reg_info *reg_group;
4973
4974         /* Support only full register dump */
4975         if ((regs->length == 0) ||
4976             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4977                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4978                         hw->device_id;
4979                 while ((reg_group = igbvf_regs[g_ind++]))
4980                         count += igb_read_regs_group(dev, &data[count],
4981                                                         reg_group);
4982                 return 0;
4983         }
4984
4985         return -ENOTSUP;
4986 }
4987
4988 static int
4989 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4990 {
4991         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4992
4993         /* Return unit is byte count */
4994         return hw->nvm.word_size * 2;
4995 }
4996
4997 static int
4998 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4999         struct rte_dev_eeprom_info *in_eeprom)
5000 {
5001         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5002         struct e1000_nvm_info *nvm = &hw->nvm;
5003         uint16_t *data = in_eeprom->data;
5004         int first, length;
5005
5006         first = in_eeprom->offset >> 1;
5007         length = in_eeprom->length >> 1;
5008         if ((first >= hw->nvm.word_size) ||
5009             ((first + length) >= hw->nvm.word_size))
5010                 return -EINVAL;
5011
5012         in_eeprom->magic = hw->vendor_id |
5013                 ((uint32_t)hw->device_id << 16);
5014
5015         if ((nvm->ops.read) == NULL)
5016                 return -ENOTSUP;
5017
5018         return nvm->ops.read(hw, first, length, data);
5019 }
5020
5021 static int
5022 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5023         struct rte_dev_eeprom_info *in_eeprom)
5024 {
5025         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5026         struct e1000_nvm_info *nvm = &hw->nvm;
5027         uint16_t *data = in_eeprom->data;
5028         int first, length;
5029
5030         first = in_eeprom->offset >> 1;
5031         length = in_eeprom->length >> 1;
5032         if ((first >= hw->nvm.word_size) ||
5033             ((first + length) >= hw->nvm.word_size))
5034                 return -EINVAL;
5035
5036         in_eeprom->magic = (uint32_t)hw->vendor_id |
5037                 ((uint32_t)hw->device_id << 16);
5038
5039         if ((nvm->ops.write) == NULL)
5040                 return -ENOTSUP;
5041         return nvm->ops.write(hw,  first, length, data);
5042 }
5043
5044 static struct rte_driver pmd_igb_drv = {
5045         .type = PMD_PDEV,
5046         .init = rte_igb_pmd_init,
5047 };
5048
5049 static struct rte_driver pmd_igbvf_drv = {
5050         .type = PMD_PDEV,
5051         .init = rte_igbvf_pmd_init,
5052 };
5053
5054 static int
5055 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5056 {
5057         struct e1000_hw *hw =
5058                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5059         uint32_t mask = 1 << queue_id;
5060
5061         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5062         E1000_WRITE_FLUSH(hw);
5063
5064         return 0;
5065 }
5066
5067 static int
5068 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5069 {
5070         struct e1000_hw *hw =
5071                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5072         uint32_t mask = 1 << queue_id;
5073         uint32_t regval;
5074
5075         regval = E1000_READ_REG(hw, E1000_EIMS);
5076         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5077         E1000_WRITE_FLUSH(hw);
5078
5079         rte_intr_enable(&dev->pci_dev->intr_handle);
5080
5081         return 0;
5082 }
5083
5084 static void
5085 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5086                    uint8_t index, uint8_t offset)
5087 {
5088         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5089
5090         /* clear bits */
5091         val &= ~((uint32_t)0xFF << offset);
5092
5093         /* write vector and valid bit */
5094         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5095
5096         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5097 }
5098
5099 static void
5100 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5101                            uint8_t queue, uint8_t msix_vector)
5102 {
5103         uint32_t tmp = 0;
5104
5105         if (hw->mac.type == e1000_82575) {
5106                 if (direction == 0)
5107                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5108                 else if (direction == 1)
5109                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5110                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5111         } else if (hw->mac.type == e1000_82576) {
5112                 if ((direction == 0) || (direction == 1))
5113                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5114                                            ((queue & 0x8) << 1) +
5115                                            8 * direction);
5116         } else if ((hw->mac.type == e1000_82580) ||
5117                         (hw->mac.type == e1000_i350) ||
5118                         (hw->mac.type == e1000_i354) ||
5119                         (hw->mac.type == e1000_i210) ||
5120                         (hw->mac.type == e1000_i211)) {
5121                 if ((direction == 0) || (direction == 1))
5122                         eth_igb_write_ivar(hw, msix_vector,
5123                                            queue >> 1,
5124                                            ((queue & 0x1) << 4) +
5125                                            8 * direction);
5126         }
5127 }
5128
5129 /* Sets up the hardware to generate MSI-X interrupts properly
5130  * @hw
5131  *  board private structure
5132  */
5133 static void
5134 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5135 {
5136         int queue_id;
5137         uint32_t tmpval, regval, intr_mask;
5138         struct e1000_hw *hw =
5139                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5140         uint32_t vec = E1000_MISC_VEC_ID;
5141         uint32_t base = E1000_MISC_VEC_ID;
5142         uint32_t misc_shift = 0;
5143
5144         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5145
5146         /* won't configure msix register if no mapping is done
5147          * between intr vector and event fd
5148          */
5149         if (!rte_intr_dp_is_en(intr_handle))
5150                 return;
5151
5152         if (rte_intr_allow_others(intr_handle)) {
5153                 vec = base = E1000_RX_VEC_START;
5154                 misc_shift = 1;
5155         }
5156
5157         /* set interrupt vector for other causes */
5158         if (hw->mac.type == e1000_82575) {
5159                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5160                 /* enable MSI-X PBA support */
5161                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5162
5163                 /* Auto-Mask interrupts upon ICR read */
5164                 tmpval |= E1000_CTRL_EXT_EIAME;
5165                 tmpval |= E1000_CTRL_EXT_IRCA;
5166
5167                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5168
5169                 /* enable msix_other interrupt */
5170                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5171                 regval = E1000_READ_REG(hw, E1000_EIAC);
5172                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5173                 regval = E1000_READ_REG(hw, E1000_EIAM);
5174                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5175         } else if ((hw->mac.type == e1000_82576) ||
5176                         (hw->mac.type == e1000_82580) ||
5177                         (hw->mac.type == e1000_i350) ||
5178                         (hw->mac.type == e1000_i354) ||
5179                         (hw->mac.type == e1000_i210) ||
5180                         (hw->mac.type == e1000_i211)) {
5181                 /* turn on MSI-X capability first */
5182                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5183                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5184                                         E1000_GPIE_NSICR);
5185                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5186                         misc_shift;
5187                 regval = E1000_READ_REG(hw, E1000_EIAC);
5188                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5189
5190                 /* enable msix_other interrupt */
5191                 regval = E1000_READ_REG(hw, E1000_EIMS);
5192                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5193                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5194                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5195         }
5196
5197         /* use EIAM to auto-mask when MSI-X interrupt
5198          * is asserted, this saves a register write for every interrupt
5199          */
5200         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5201                 misc_shift;
5202         regval = E1000_READ_REG(hw, E1000_EIAM);
5203         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5204
5205         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5206                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5207                 intr_handle->intr_vec[queue_id] = vec;
5208                 if (vec < base + intr_handle->nb_efd - 1)
5209                         vec++;
5210         }
5211
5212         E1000_WRITE_FLUSH(hw);
5213 }
5214
5215 PMD_REGISTER_DRIVER(pmd_igb_drv);
5216 PMD_REGISTER_DRIVER(pmd_igbvf_drv);