drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64
  65 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  66 #define IGB_DEFAULT_RX_HTHRESH      8
  67 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  68
  69 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  70 #define IGB_DEFAULT_TX_HTHRESH      1
  71 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  72
  73 #define IGB_HKEY_MAX_INDEX 10
  74
  75 /* Bit shift and mask */
  76 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  77 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  78 #define IGB_8_BIT_WIDTH  CHAR_BIT
  79 #define IGB_8_BIT_MASK   UINT8_MAX
  80
  81 /* Additional timesync values. */
  82 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  83 #define E1000_ETQF_FILTER_1588       3
  84 #define IGB_82576_TSYNC_SHIFT        16
  85 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  86 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  88
  89 #define E1000_VTIVAR_MISC                0x01740
  90 #define E1000_VTIVAR_MISC_MASK           0xFF
  91 #define E1000_VTIVAR_VALID               0x80
  92 #define E1000_VTIVAR_MISC_MAILBOX        0
  93 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  94
  95 /* External VLAN Enable bit mask */
  96 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  97
  98 /* External VLAN Ether Type bit mask and shift */
  99 #define E1000_VET_VET_EXT            0xFFFF0000
 100 #define E1000_VET_VET_EXT_SHIFT      16
 101
 102 static int  eth_igb_configure(struct rte_eth_dev *dev);
 103 static int  eth_igb_start(struct rte_eth_dev *dev);
 104 static void eth_igb_stop(struct rte_eth_dev *dev);
 105 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 107 static void eth_igb_close(struct rte_eth_dev *dev);
 108 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 110 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 112 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 113                                 int wait_to_complete);
 114 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 115                                 struct rte_eth_stats *rte_stats);
 116 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 117                               struct rte_eth_xstat *xstats, unsigned n);
 118 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 119                                     struct rte_eth_xstat_name *xstats_names,
 120                                     unsigned limit);
 121 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 122 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 123 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 124                               struct rte_eth_dev_info *dev_info);
 125 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 126 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 127                                 struct rte_eth_dev_info *dev_info);
 128 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 129                                 struct rte_eth_fc_conf *fc_conf);
 130 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 131                                 struct rte_eth_fc_conf *fc_conf);
 132 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 133 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 134 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 135 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 136                                     struct rte_intr_handle *handle);
 137 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 138                                                         void *param);
 139 static int  igb_hardware_init(struct e1000_hw *hw);
 140 static void igb_hw_control_acquire(struct e1000_hw *hw);
 141 static void igb_hw_control_release(struct e1000_hw *hw);
 142 static void igb_init_manageability(struct e1000_hw *hw);
 143 static void igb_release_manageability(struct e1000_hw *hw);
 144
 145 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 146
 147 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 148                 uint16_t vlan_id, int on);
 149 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 150                                  enum rte_vlan_type vlan_type,
 151                                  uint16_t tpid_id);
 152 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 153
 154 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 155 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 156 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 157 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 158 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 159 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 160
 161 static int eth_igb_led_on(struct rte_eth_dev *dev);
 162 static int eth_igb_led_off(struct rte_eth_dev *dev);
 163
 164 static void igb_intr_disable(struct e1000_hw *hw);
 165 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 166 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 167                 struct ether_addr *mac_addr,
 168                 uint32_t index, uint32_t pool);
 169 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 170 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 171                 struct ether_addr *addr);
 172
 173 static void igbvf_intr_disable(struct e1000_hw *hw);
 174 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 175 static int igbvf_dev_start(struct rte_eth_dev *dev);
 176 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 177 static void igbvf_dev_close(struct rte_eth_dev *dev);
 178 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 179 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 180 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 181 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 182 static int eth_igbvf_link_update(struct e1000_hw *hw);
 183 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 184                                 struct rte_eth_stats *rte_stats);
 185 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 186                                 struct rte_eth_xstat *xstats, unsigned n);
 187 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 188                                       struct rte_eth_xstat_name *xstats_names,
 189                                       unsigned limit);
 190 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 191 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 192                 uint16_t vlan_id, int on);
 193 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 194 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 195 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 196                 struct ether_addr *addr);
 197 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 198 static int igbvf_get_regs(struct rte_eth_dev *dev,
 199                 struct rte_dev_reg_info *regs);
 200
 201 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 202                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 203                                    uint16_t reta_size);
 204 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 205                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 206                                   uint16_t reta_size);
 207
 208 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 209                         struct rte_eth_syn_filter *filter,
 210                         bool add);
 211 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 212                         struct rte_eth_syn_filter *filter);
 213 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 214                         enum rte_filter_op filter_op,
 215                         void *arg);
 216 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 217                         struct rte_eth_ntuple_filter *ntuple_filter);
 218 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 219                         struct rte_eth_ntuple_filter *ntuple_filter);
 220 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 221                         struct rte_eth_flex_filter *filter,
 222                         bool add);
 223 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 224                         struct rte_eth_flex_filter *filter);
 225 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 226                         enum rte_filter_op filter_op,
 227                         void *arg);
 228 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 229                         struct rte_eth_ntuple_filter *ntuple_filter);
 230 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 231                         struct rte_eth_ntuple_filter *ntuple_filter);
 232 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 233                         struct rte_eth_ntuple_filter *filter,
 234                         bool add);
 235 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 236                         struct rte_eth_ntuple_filter *filter);
 237 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 238                                 enum rte_filter_op filter_op,
 239                                 void *arg);
 240 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 241                         struct rte_eth_ethertype_filter *filter,
 242                         bool add);
 243 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 244                                 enum rte_filter_op filter_op,
 245                                 void *arg);
 246 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 247                         struct rte_eth_ethertype_filter *filter);
 248 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 249                      enum rte_filter_type filter_type,
 250                      enum rte_filter_op filter_op,
 251                      void *arg);
 252 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 253 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 254                 struct rte_dev_reg_info *regs);
 255 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 256 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 257                 struct rte_dev_eeprom_info *eeprom);
 258 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 259                 struct rte_dev_eeprom_info *eeprom);
 260 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 261                                     struct ether_addr *mc_addr_set,
 262                                     uint32_t nb_mc_addr);
 263 static int igb_timesync_enable(struct rte_eth_dev *dev);
 264 static int igb_timesync_disable(struct rte_eth_dev *dev);
 265 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 266                                           struct timespec *timestamp,
 267                                           uint32_t flags);
 268 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 269                                           struct timespec *timestamp);
 270 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 271 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 272                                   struct timespec *timestamp);
 273 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 274                                    const struct timespec *timestamp);
 275 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 276                                         uint16_t queue_id);
 277 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 278                                          uint16_t queue_id);
 279 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 280                                        uint8_t queue, uint8_t msix_vector);
 281 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 282                                uint8_t index, uint8_t offset);
 283 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 284 static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
 285                                         void *param);
 286 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 287
 288 /*
 289  * Define VF Stats MACRO for Non "cleared on read" register
 290  */
 291 #define UPDATE_VF_STAT(reg, last, cur)            \
 292 {                                                 \
 293         u32 latest = E1000_READ_REG(hw, reg);     \
 294         cur += (latest - last) & UINT_MAX;        \
 295         last = latest;                            \
 296 }
 297
 298 #define IGB_FC_PAUSE_TIME 0x0680
 299 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 300 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 301
 302 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 303
 304 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 305
 306 /*
 307  * The set of PCI devices this driver supports
 308  */
 309 static const struct rte_pci_id pci_id_igb_map[] = {
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 318
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 322
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 329
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 347         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 348         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 349         { .vendor_id = 0, /* sentinel */ },
 350 };
 351
 352 /*
 353  * The set of PCI devices this driver supports (for 82576&I350 VF)
 354  */
 355 static const struct rte_pci_id pci_id_igbvf_map[] = {
 356         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 357         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 358         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 359         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 360         { .vendor_id = 0, /* sentinel */ },
 361 };
 362
 363 static const struct rte_eth_desc_lim rx_desc_lim = {
 364         .nb_max = E1000_MAX_RING_DESC,
 365         .nb_min = E1000_MIN_RING_DESC,
 366         .nb_align = IGB_RXD_ALIGN,
 367 };
 368
 369 static const struct rte_eth_desc_lim tx_desc_lim = {
 370         .nb_max = E1000_MAX_RING_DESC,
 371         .nb_min = E1000_MIN_RING_DESC,
 372         .nb_align = IGB_RXD_ALIGN,
 373         .nb_seg_max = IGB_TX_MAX_SEG,
 374         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 375 };
 376
 377 static const struct eth_dev_ops eth_igb_ops = {
 378         .dev_configure        = eth_igb_configure,
 379         .dev_start            = eth_igb_start,
 380         .dev_stop             = eth_igb_stop,
 381         .dev_set_link_up      = eth_igb_dev_set_link_up,
 382         .dev_set_link_down    = eth_igb_dev_set_link_down,
 383         .dev_close            = eth_igb_close,
 384         .promiscuous_enable   = eth_igb_promiscuous_enable,
 385         .promiscuous_disable  = eth_igb_promiscuous_disable,
 386         .allmulticast_enable  = eth_igb_allmulticast_enable,
 387         .allmulticast_disable = eth_igb_allmulticast_disable,
 388         .link_update          = eth_igb_link_update,
 389         .stats_get            = eth_igb_stats_get,
 390         .xstats_get           = eth_igb_xstats_get,
 391         .xstats_get_names     = eth_igb_xstats_get_names,
 392         .stats_reset          = eth_igb_stats_reset,
 393         .xstats_reset         = eth_igb_xstats_reset,
 394         .dev_infos_get        = eth_igb_infos_get,
 395         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 396         .mtu_set              = eth_igb_mtu_set,
 397         .vlan_filter_set      = eth_igb_vlan_filter_set,
 398         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 399         .vlan_offload_set     = eth_igb_vlan_offload_set,
 400         .rx_queue_setup       = eth_igb_rx_queue_setup,
 401         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 402         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 403         .rx_queue_release     = eth_igb_rx_queue_release,
 404         .rx_queue_count       = eth_igb_rx_queue_count,
 405         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 406         .tx_queue_setup       = eth_igb_tx_queue_setup,
 407         .tx_queue_release     = eth_igb_tx_queue_release,
 408         .dev_led_on           = eth_igb_led_on,
 409         .dev_led_off          = eth_igb_led_off,
 410         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 411         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 412         .mac_addr_add         = eth_igb_rar_set,
 413         .mac_addr_remove      = eth_igb_rar_clear,
 414         .mac_addr_set         = eth_igb_default_mac_addr_set,
 415         .reta_update          = eth_igb_rss_reta_update,
 416         .reta_query           = eth_igb_rss_reta_query,
 417         .rss_hash_update      = eth_igb_rss_hash_update,
 418         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 419         .filter_ctrl          = eth_igb_filter_ctrl,
 420         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 421         .rxq_info_get         = igb_rxq_info_get,
 422         .txq_info_get         = igb_txq_info_get,
 423         .timesync_enable      = igb_timesync_enable,
 424         .timesync_disable     = igb_timesync_disable,
 425         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 426         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 427         .get_reg              = eth_igb_get_regs,
 428         .get_eeprom_length    = eth_igb_get_eeprom_length,
 429         .get_eeprom           = eth_igb_get_eeprom,
 430         .set_eeprom           = eth_igb_set_eeprom,
 431         .timesync_adjust_time = igb_timesync_adjust_time,
 432         .timesync_read_time   = igb_timesync_read_time,
 433         .timesync_write_time  = igb_timesync_write_time,
 434 };
 435
 436 /*
 437  * dev_ops for virtual function, bare necessities for basic vf
 438  * operation have been implemented
 439  */
 440 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 441         .dev_configure        = igbvf_dev_configure,
 442         .dev_start            = igbvf_dev_start,
 443         .dev_stop             = igbvf_dev_stop,
 444         .dev_close            = igbvf_dev_close,
 445         .promiscuous_enable   = igbvf_promiscuous_enable,
 446         .promiscuous_disable  = igbvf_promiscuous_disable,
 447         .allmulticast_enable  = igbvf_allmulticast_enable,
 448         .allmulticast_disable = igbvf_allmulticast_disable,
 449         .link_update          = eth_igb_link_update,
 450         .stats_get            = eth_igbvf_stats_get,
 451         .xstats_get           = eth_igbvf_xstats_get,
 452         .xstats_get_names     = eth_igbvf_xstats_get_names,
 453         .stats_reset          = eth_igbvf_stats_reset,
 454         .xstats_reset         = eth_igbvf_stats_reset,
 455         .vlan_filter_set      = igbvf_vlan_filter_set,
 456         .dev_infos_get        = eth_igbvf_infos_get,
 457         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 458         .rx_queue_setup       = eth_igb_rx_queue_setup,
 459         .rx_queue_release     = eth_igb_rx_queue_release,
 460         .tx_queue_setup       = eth_igb_tx_queue_setup,
 461         .tx_queue_release     = eth_igb_tx_queue_release,
 462         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 463         .rxq_info_get         = igb_rxq_info_get,
 464         .txq_info_get         = igb_txq_info_get,
 465         .mac_addr_set         = igbvf_default_mac_addr_set,
 466         .get_reg              = igbvf_get_regs,
 467 };
 468
 469 /* store statistics names and its offset in stats structure */
 470 struct rte_igb_xstats_name_off {
 471         char name[RTE_ETH_XSTATS_NAME_SIZE];
 472         unsigned offset;
 473 };
 474
 475 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 476         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 477         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 478         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 479         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 480         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 481         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 482         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 483                 ecol)},
 484         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 485         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 486         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 487         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 488         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 489         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 490         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 491         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 492         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 493         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 494         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 495                 fcruc)},
 496         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 497         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 498         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 499         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 500         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 501                 prc1023)},
 502         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 503                 prc1522)},
 504         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 505         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 506         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 507         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 508         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 509         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 510         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 511         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 512         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 513         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 514         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 515         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 516         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 517         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 518         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 519         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 520         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 521         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 522                 ptc1023)},
 523         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 524                 ptc1522)},
 525         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 526         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 527         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 528         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 529         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 530         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 531         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 532
 533         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 534 };
 535
 536 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 537                 sizeof(rte_igb_stats_strings[0]))
 538
 539 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 540         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 541         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 542         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 543         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 544         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 545 };
 546
 547 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 548                 sizeof(rte_igbvf_stats_strings[0]))
 549
 550 /**
 551  * Atomically reads the link status information from global
 552  * structure rte_eth_dev.
 553  *
 554  * @param dev
 555  *   - Pointer to the structure rte_eth_dev to read from.
 556  *   - Pointer to the buffer to be saved with the link status.
 557  *
 558  * @return
 559  *   - On success, zero.
 560  *   - On failure, negative value.
 561  */
 562 static inline int
 563 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 564                                 struct rte_eth_link *link)
 565 {
 566         struct rte_eth_link *dst = link;
 567         struct rte_eth_link *src = &(dev->data->dev_link);
 568
 569         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 570                                         *(uint64_t *)src) == 0)
 571                 return -1;
 572
 573         return 0;
 574 }
 575
 576 /**
 577  * Atomically writes the link status information into global
 578  * structure rte_eth_dev.
 579  *
 580  * @param dev
 581  *   - Pointer to the structure rte_eth_dev to read from.
 582  *   - Pointer to the buffer to be saved with the link status.
 583  *
 584  * @return
 585  *   - On success, zero.
 586  *   - On failure, negative value.
 587  */
 588 static inline int
 589 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 590                                 struct rte_eth_link *link)
 591 {
 592         struct rte_eth_link *dst = &(dev->data->dev_link);
 593         struct rte_eth_link *src = link;
 594
 595         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 596                                         *(uint64_t *)src) == 0)
 597                 return -1;
 598
 599         return 0;
 600 }
 601
 602 static inline void
 603 igb_intr_enable(struct rte_eth_dev *dev)
 604 {
 605         struct e1000_interrupt *intr =
 606                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 607         struct e1000_hw *hw =
 608                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 609
 610         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 611         E1000_WRITE_FLUSH(hw);
 612 }
 613
 614 static void
 615 igb_intr_disable(struct e1000_hw *hw)
 616 {
 617         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 618         E1000_WRITE_FLUSH(hw);
 619 }
 620
 621 static inline void
 622 igbvf_intr_enable(struct rte_eth_dev *dev)
 623 {
 624         struct e1000_hw *hw =
 625                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 626
 627         /* only for mailbox */
 628         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 629         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 630         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 631         E1000_WRITE_FLUSH(hw);
 632 }
 633
 634 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 635 static void
 636 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 637 {
 638         uint32_t tmp = 0;
 639
 640         /* mailbox */
 641         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 642         tmp |= E1000_VTIVAR_VALID;
 643         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 644 }
 645
 646 static void
 647 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 648 {
 649         struct e1000_hw *hw =
 650                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 651
 652         /* Configure VF other cause ivar */
 653         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 654 }
 655
 656 static inline int32_t
 657 igb_pf_reset_hw(struct e1000_hw *hw)
 658 {
 659         uint32_t ctrl_ext;
 660         int32_t status;
 661
 662         status = e1000_reset_hw(hw);
 663
 664         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 665         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 666         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 667         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 668         E1000_WRITE_FLUSH(hw);
 669
 670         return status;
 671 }
 672
 673 static void
 674 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 675 {
 676         struct e1000_hw *hw =
 677                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 678
 679
 680         hw->vendor_id = pci_dev->id.vendor_id;
 681         hw->device_id = pci_dev->id.device_id;
 682         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 683         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 684
 685         e1000_set_mac_type(hw);
 686
 687         /* need to check if it is a vf device below */
 688 }
 689
 690 static int
 691 igb_reset_swfw_lock(struct e1000_hw *hw)
 692 {
 693         int ret_val;
 694
 695         /*
 696          * Do mac ops initialization manually here, since we will need
 697          * some function pointers set by this call.
 698          */
 699         ret_val = e1000_init_mac_params(hw);
 700         if (ret_val)
 701                 return ret_val;
 702
 703         /*
 704          * SMBI lock should not fail in this early stage. If this is the case,
 705          * it is due to an improper exit of the application.
 706          * So force the release of the faulty lock.
 707          */
 708         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 709                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 710         }
 711         e1000_put_hw_semaphore_generic(hw);
 712
 713         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 714                 uint16_t mask;
 715
 716                 /*
 717                  * Phy lock should not fail in this early stage. If this is the case,
 718                  * it is due to an improper exit of the application.
 719                  * So force the release of the faulty lock.
 720                  */
 721                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 722                 if (hw->bus.func > E1000_FUNC_1)
 723                         mask <<= 2;
 724                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 725                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 726                                     hw->bus.func);
 727                 }
 728                 hw->mac.ops.release_swfw_sync(hw, mask);
 729
 730                 /*
 731                  * This one is more tricky since it is common to all ports; but
 732                  * swfw_sync retries last long enough (1s) to be almost sure that if
 733                  * lock can not be taken it is due to an improper lock of the
 734                  * semaphore.
 735                  */
 736                 mask = E1000_SWFW_EEP_SM;
 737                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 738                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 739                 }
 740                 hw->mac.ops.release_swfw_sync(hw, mask);
 741         }
 742
 743         return E1000_SUCCESS;
 744 }
 745
 746 static int
 747 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 748 {
 749         int error = 0;
 750         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
 751         struct e1000_hw *hw =
 752                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 753         struct e1000_vfta * shadow_vfta =
 754                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 755         struct e1000_filter_info *filter_info =
 756                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 757         struct e1000_adapter *adapter =
 758                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 759
 760         uint32_t ctrl_ext;
 761
 762         eth_dev->dev_ops = &eth_igb_ops;
 763         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 764         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 765         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 766
 767         /* for secondary processes, we don't initialise any further as primary
 768          * has already done this work. Only check we don't need a different
 769          * RX function */
 770         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 771                 if (eth_dev->data->scattered_rx)
 772                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 773                 return 0;
 774         }
 775
 776         rte_eth_copy_pci_info(eth_dev, pci_dev);
 777         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
 778
 779         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 780
 781         igb_identify_hardware(eth_dev, pci_dev);
 782         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 783                 error = -EIO;
 784                 goto err_late;
 785         }
 786
 787         e1000_get_bus_info(hw);
 788
 789         /* Reset any pending lock */
 790         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 791                 error = -EIO;
 792                 goto err_late;
 793         }
 794
 795         /* Finish initialization */
 796         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 797                 error = -EIO;
 798                 goto err_late;
 799         }
 800
 801         hw->mac.autoneg = 1;
 802         hw->phy.autoneg_wait_to_complete = 0;
 803         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 804
 805         /* Copper options */
 806         if (hw->phy.media_type == e1000_media_type_copper) {
 807                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 808                 hw->phy.disable_polarity_correction = 0;
 809                 hw->phy.ms_type = e1000_ms_hw_default;
 810         }
 811
 812         /*
 813          * Start from a known state, this is important in reading the nvm
 814          * and mac from that.
 815          */
 816         igb_pf_reset_hw(hw);
 817
 818         /* Make sure we have a good EEPROM before we read from it */
 819         if (e1000_validate_nvm_checksum(hw) < 0) {
 820                 /*
 821                  * Some PCI-E parts fail the first check due to
 822                  * the link being in sleep state, call it again,
 823                  * if it fails a second time its a real issue.
 824                  */
 825                 if (e1000_validate_nvm_checksum(hw) < 0) {
 826                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 827                         error = -EIO;
 828                         goto err_late;
 829                 }
 830         }
 831
 832         /* Read the permanent MAC address out of the EEPROM */
 833         if (e1000_read_mac_addr(hw) != 0) {
 834                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 835                 error = -EIO;
 836                 goto err_late;
 837         }
 838
 839         /* Allocate memory for storing MAC addresses */
 840         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 841                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 842         if (eth_dev->data->mac_addrs == NULL) {
 843                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 844                                                 "store MAC addresses",
 845                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 846                 error = -ENOMEM;
 847                 goto err_late;
 848         }
 849
 850         /* Copy the permanent MAC address */
 851         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 852
 853         /* initialize the vfta */
 854         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 855
 856         /* Now initialize the hardware */
 857         if (igb_hardware_init(hw) != 0) {
 858                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 859                 rte_free(eth_dev->data->mac_addrs);
 860                 eth_dev->data->mac_addrs = NULL;
 861                 error = -ENODEV;
 862                 goto err_late;
 863         }
 864         hw->mac.get_link_status = 1;
 865         adapter->stopped = 0;
 866
 867         /* Indicate SOL/IDER usage */
 868         if (e1000_check_reset_block(hw) < 0) {
 869                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 870                                         "SOL/IDER session");
 871         }
 872
 873         /* initialize PF if max_vfs not zero */
 874         igb_pf_host_init(eth_dev);
 875
 876         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 877         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 878         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 879         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 880         E1000_WRITE_FLUSH(hw);
 881
 882         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 883                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 884                      pci_dev->id.device_id);
 885
 886         rte_intr_callback_register(&pci_dev->intr_handle,
 887                                    eth_igb_interrupt_handler,
 888                                    (void *)eth_dev);
 889
 890         /* enable uio/vfio intr/eventfd mapping */
 891         rte_intr_enable(&pci_dev->intr_handle);
 892
 893         /* enable support intr */
 894         igb_intr_enable(eth_dev);
 895
 896         TAILQ_INIT(&filter_info->flex_list);
 897         filter_info->flex_mask = 0;
 898         TAILQ_INIT(&filter_info->twotuple_list);
 899         filter_info->twotuple_mask = 0;
 900         TAILQ_INIT(&filter_info->fivetuple_list);
 901         filter_info->fivetuple_mask = 0;
 902
 903         return 0;
 904
 905 err_late:
 906         igb_hw_control_release(hw);
 907
 908         return error;
 909 }
 910
 911 static int
 912 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 913 {
 914         struct rte_pci_device *pci_dev;
 915         struct rte_intr_handle *intr_handle;
 916         struct e1000_hw *hw;
 917         struct e1000_adapter *adapter =
 918                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 919
 920         PMD_INIT_FUNC_TRACE();
 921
 922         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 923                 return -EPERM;
 924
 925         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 926         pci_dev = E1000_DEV_TO_PCI(eth_dev);
 927         intr_handle = &pci_dev->intr_handle;
 928
 929         if (adapter->stopped == 0)
 930                 eth_igb_close(eth_dev);
 931
 932         eth_dev->dev_ops = NULL;
 933         eth_dev->rx_pkt_burst = NULL;
 934         eth_dev->tx_pkt_burst = NULL;
 935
 936         /* Reset any pending lock */
 937         igb_reset_swfw_lock(hw);
 938
 939         rte_free(eth_dev->data->mac_addrs);
 940         eth_dev->data->mac_addrs = NULL;
 941
 942         /* uninitialize PF if max_vfs not zero */
 943         igb_pf_host_uninit(eth_dev);
 944
 945         /* disable uio intr before callback unregister */
 946         rte_intr_disable(intr_handle);
 947         rte_intr_callback_unregister(intr_handle,
 948                                      eth_igb_interrupt_handler, eth_dev);
 949
 950         return 0;
 951 }
 952
 953 /*
 954  * Virtual Function device init
 955  */
 956 static int
 957 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 958 {
 959         struct rte_pci_device *pci_dev;
 960         struct rte_intr_handle *intr_handle;
 961         struct e1000_adapter *adapter =
 962                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 963         struct e1000_hw *hw =
 964                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 965         int diag;
 966         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 967
 968         PMD_INIT_FUNC_TRACE();
 969
 970         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 971         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 972         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 973         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 974
 975         /* for secondary processes, we don't initialise any further as primary
 976          * has already done this work. Only check we don't need a different
 977          * RX function */
 978         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 979                 if (eth_dev->data->scattered_rx)
 980                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 981                 return 0;
 982         }
 983
 984         pci_dev = E1000_DEV_TO_PCI(eth_dev);
 985         rte_eth_copy_pci_info(eth_dev, pci_dev);
 986         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
 987
 988         hw->device_id = pci_dev->id.device_id;
 989         hw->vendor_id = pci_dev->id.vendor_id;
 990         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 991         adapter->stopped = 0;
 992
 993         /* Initialize the shared code (base driver) */
 994         diag = e1000_setup_init_funcs(hw, TRUE);
 995         if (diag != 0) {
 996                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 997                         diag);
 998                 return -EIO;
 999         }
1000
1001         /* init_mailbox_params */
1002         hw->mbx.ops.init_params(hw);
1003
1004         /* Disable the interrupts for VF */
1005         igbvf_intr_disable(hw);
1006
1007         diag = hw->mac.ops.reset_hw(hw);
1008
1009         /* Allocate memory for storing MAC addresses */
1010         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1011                 hw->mac.rar_entry_count, 0);
1012         if (eth_dev->data->mac_addrs == NULL) {
1013                 PMD_INIT_LOG(ERR,
1014                         "Failed to allocate %d bytes needed to store MAC "
1015                         "addresses",
1016                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1017                 return -ENOMEM;
1018         }
1019
1020         /* Generate a random MAC address, if none was assigned by PF. */
1021         if (is_zero_ether_addr(perm_addr)) {
1022                 eth_random_addr(perm_addr->addr_bytes);
1023                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1024                 if (diag) {
1025                         rte_free(eth_dev->data->mac_addrs);
1026                         eth_dev->data->mac_addrs = NULL;
1027                         return diag;
1028                 }
1029                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1030                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1031                              "%02x:%02x:%02x:%02x:%02x:%02x",
1032                              perm_addr->addr_bytes[0],
1033                              perm_addr->addr_bytes[1],
1034                              perm_addr->addr_bytes[2],
1035                              perm_addr->addr_bytes[3],
1036                              perm_addr->addr_bytes[4],
1037                              perm_addr->addr_bytes[5]);
1038         }
1039
1040         /* Copy the permanent MAC address */
1041         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1042                         &eth_dev->data->mac_addrs[0]);
1043
1044         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1045                      "mac.type=%s",
1046                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1047                      pci_dev->id.device_id, "igb_mac_82576_vf");
1048
1049         intr_handle = &pci_dev->intr_handle;
1050         rte_intr_callback_register(intr_handle,
1051                                    eth_igbvf_interrupt_handler, eth_dev);
1052
1053         return 0;
1054 }
1055
1056 static int
1057 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1058 {
1059         struct e1000_adapter *adapter =
1060                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1061         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
1062
1063         PMD_INIT_FUNC_TRACE();
1064
1065         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1066                 return -EPERM;
1067
1068         if (adapter->stopped == 0)
1069                 igbvf_dev_close(eth_dev);
1070
1071         eth_dev->dev_ops = NULL;
1072         eth_dev->rx_pkt_burst = NULL;
1073         eth_dev->tx_pkt_burst = NULL;
1074
1075         rte_free(eth_dev->data->mac_addrs);
1076         eth_dev->data->mac_addrs = NULL;
1077
1078         /* disable uio intr before callback unregister */
1079         rte_intr_disable(&pci_dev->intr_handle);
1080         rte_intr_callback_unregister(&pci_dev->intr_handle,
1081                                      eth_igbvf_interrupt_handler,
1082                                      (void *)eth_dev);
1083
1084         return 0;
1085 }
1086
1087 static struct eth_driver rte_igb_pmd = {
1088         .pci_drv = {
1089                 .id_table = pci_id_igb_map,
1090                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1091                 .probe = rte_eth_dev_pci_probe,
1092                 .remove = rte_eth_dev_pci_remove,
1093         },
1094         .eth_dev_init = eth_igb_dev_init,
1095         .eth_dev_uninit = eth_igb_dev_uninit,
1096         .dev_private_size = sizeof(struct e1000_adapter),
1097 };
1098
1099 /*
1100  * virtual function driver struct
1101  */
1102 static struct eth_driver rte_igbvf_pmd = {
1103         .pci_drv = {
1104                 .id_table = pci_id_igbvf_map,
1105                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1106                 .probe = rte_eth_dev_pci_probe,
1107                 .remove = rte_eth_dev_pci_remove,
1108         },
1109         .eth_dev_init = eth_igbvf_dev_init,
1110         .eth_dev_uninit = eth_igbvf_dev_uninit,
1111         .dev_private_size = sizeof(struct e1000_adapter),
1112 };
1113
1114 static void
1115 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1116 {
1117         struct e1000_hw *hw =
1118                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1119         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1120         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1121         rctl |= E1000_RCTL_VFE;
1122         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1123 }
1124
1125 static int
1126 igb_check_mq_mode(struct rte_eth_dev *dev)
1127 {
1128         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1129         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1130         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1131         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1132
1133         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1134             tx_mq_mode == ETH_MQ_TX_DCB ||
1135             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1136                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1137                 return -EINVAL;
1138         }
1139         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1140                 /* Check multi-queue mode.
1141                  * To no break software we accept ETH_MQ_RX_NONE as this might
1142                  * be used to turn off VLAN filter.
1143                  */
1144
1145                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1146                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1147                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1148                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1149                 } else {
1150                         /* Only support one queue on VFs.
1151                          * RSS together with SRIOV is not supported.
1152                          */
1153                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1154                                         " wrong mq_mode rx %d.",
1155                                         rx_mq_mode);
1156                         return -EINVAL;
1157                 }
1158                 /* TX mode is not used here, so mode might be ignored.*/
1159                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1160                         /* SRIOV only works in VMDq enable mode */
1161                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1162                                         " TX mode %d is not supported. "
1163                                         " Driver will behave as %d mode.",
1164                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1165                 }
1166
1167                 /* check valid queue number */
1168                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1169                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1170                                         " only support one queue on VFs.");
1171                         return -EINVAL;
1172                 }
1173         } else {
1174                 /* To no break software that set invalid mode, only display
1175                  * warning if invalid mode is used.
1176                  */
1177                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1178                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1179                     rx_mq_mode != ETH_MQ_RX_RSS) {
1180                         /* RSS together with VMDq not supported*/
1181                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1182                                      rx_mq_mode);
1183                         return -EINVAL;
1184                 }
1185
1186                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1187                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1188                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1189                                         " Due to txmode is meaningless in this"
1190                                         " driver, just ignore.",
1191                                         tx_mq_mode);
1192                 }
1193         }
1194         return 0;
1195 }
1196
1197 static int
1198 eth_igb_configure(struct rte_eth_dev *dev)
1199 {
1200         struct e1000_interrupt *intr =
1201                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1202         int ret;
1203
1204         PMD_INIT_FUNC_TRACE();
1205
1206         /* multipe queue mode checking */
1207         ret  = igb_check_mq_mode(dev);
1208         if (ret != 0) {
1209                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1210                             ret);
1211                 return ret;
1212         }
1213
1214         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1215         PMD_INIT_FUNC_TRACE();
1216
1217         return 0;
1218 }
1219
1220 static int
1221 eth_igb_start(struct rte_eth_dev *dev)
1222 {
1223         struct e1000_hw *hw =
1224                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1225         struct e1000_adapter *adapter =
1226                 E1000_DEV_PRIVATE(dev->data->dev_private);
1227         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1228         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1229         int ret, mask;
1230         uint32_t intr_vector = 0;
1231         uint32_t ctrl_ext;
1232         uint32_t *speeds;
1233         int num_speeds;
1234         bool autoneg;
1235
1236         PMD_INIT_FUNC_TRACE();
1237
1238         /* disable uio/vfio intr/eventfd mapping */
1239         rte_intr_disable(intr_handle);
1240
1241         /* Power up the phy. Needed to make the link go Up */
1242         eth_igb_dev_set_link_up(dev);
1243
1244         /*
1245          * Packet Buffer Allocation (PBA)
1246          * Writing PBA sets the receive portion of the buffer
1247          * the remainder is used for the transmit buffer.
1248          */
1249         if (hw->mac.type == e1000_82575) {
1250                 uint32_t pba;
1251
1252                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1253                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1254         }
1255
1256         /* Put the address into the Receive Address Array */
1257         e1000_rar_set(hw, hw->mac.addr, 0);
1258
1259         /* Initialize the hardware */
1260         if (igb_hardware_init(hw)) {
1261                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1262                 return -EIO;
1263         }
1264         adapter->stopped = 0;
1265
1266         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1267
1268         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1269         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1270         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1271         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1272         E1000_WRITE_FLUSH(hw);
1273
1274         /* configure PF module if SRIOV enabled */
1275         igb_pf_host_configure(dev);
1276
1277         /* check and configure queue intr-vector mapping */
1278         if ((rte_intr_cap_multiple(intr_handle) ||
1279              !RTE_ETH_DEV_SRIOV(dev).active) &&
1280             dev->data->dev_conf.intr_conf.rxq != 0) {
1281                 intr_vector = dev->data->nb_rx_queues;
1282                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1283                         return -1;
1284         }
1285
1286         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1287                 intr_handle->intr_vec =
1288                         rte_zmalloc("intr_vec",
1289                                     dev->data->nb_rx_queues * sizeof(int), 0);
1290                 if (intr_handle->intr_vec == NULL) {
1291                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1292                                      " intr_vec\n", dev->data->nb_rx_queues);
1293                         return -ENOMEM;
1294                 }
1295         }
1296
1297         /* confiugre msix for rx interrupt */
1298         eth_igb_configure_msix_intr(dev);
1299
1300         /* Configure for OS presence */
1301         igb_init_manageability(hw);
1302
1303         eth_igb_tx_init(dev);
1304
1305         /* This can fail when allocating mbufs for descriptor rings */
1306         ret = eth_igb_rx_init(dev);
1307         if (ret) {
1308                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1309                 igb_dev_clear_queues(dev);
1310                 return ret;
1311         }
1312
1313         e1000_clear_hw_cntrs_base_generic(hw);
1314
1315         /*
1316          * VLAN Offload Settings
1317          */
1318         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1319                         ETH_VLAN_EXTEND_MASK;
1320         eth_igb_vlan_offload_set(dev, mask);
1321
1322         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1323                 /* Enable VLAN filter since VMDq always use VLAN filter */
1324                 igb_vmdq_vlan_hw_filter_enable(dev);
1325         }
1326
1327         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1328                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1329                 (hw->mac.type == e1000_i211)) {
1330                 /* Configure EITR with the maximum possible value (0xFFFF) */
1331                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1332         }
1333
1334         /* Setup link speed and duplex */
1335         speeds = &dev->data->dev_conf.link_speeds;
1336         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1337                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1338                 hw->mac.autoneg = 1;
1339         } else {
1340                 num_speeds = 0;
1341                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1342
1343                 /* Reset */
1344                 hw->phy.autoneg_advertised = 0;
1345
1346                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1347                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1348                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1349                         num_speeds = -1;
1350                         goto error_invalid_config;
1351                 }
1352                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1353                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1354                         num_speeds++;
1355                 }
1356                 if (*speeds & ETH_LINK_SPEED_10M) {
1357                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1358                         num_speeds++;
1359                 }
1360                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1361                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1362                         num_speeds++;
1363                 }
1364                 if (*speeds & ETH_LINK_SPEED_100M) {
1365                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1366                         num_speeds++;
1367                 }
1368                 if (*speeds & ETH_LINK_SPEED_1G) {
1369                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1370                         num_speeds++;
1371                 }
1372                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1373                         goto error_invalid_config;
1374
1375                 /* Set/reset the mac.autoneg based on the link speed,
1376                  * fixed or not
1377                  */
1378                 if (!autoneg) {
1379                         hw->mac.autoneg = 0;
1380                         hw->mac.forced_speed_duplex =
1381                                         hw->phy.autoneg_advertised;
1382                 } else {
1383                         hw->mac.autoneg = 1;
1384                 }
1385         }
1386
1387         e1000_setup_link(hw);
1388
1389         if (rte_intr_allow_others(intr_handle)) {
1390                 /* check if lsc interrupt is enabled */
1391                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1392                         eth_igb_lsc_interrupt_setup(dev);
1393         } else {
1394                 rte_intr_callback_unregister(intr_handle,
1395                                              eth_igb_interrupt_handler,
1396                                              (void *)dev);
1397                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1398                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1399                                      " no intr multiplex\n");
1400         }
1401
1402         /* check if rxq interrupt is enabled */
1403         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1404             rte_intr_dp_is_en(intr_handle))
1405                 eth_igb_rxq_interrupt_setup(dev);
1406
1407         /* enable uio/vfio intr/eventfd mapping */
1408         rte_intr_enable(intr_handle);
1409
1410         /* resume enabled intr since hw reset */
1411         igb_intr_enable(dev);
1412
1413         PMD_INIT_LOG(DEBUG, "<<");
1414
1415         return 0;
1416
1417 error_invalid_config:
1418         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1419                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1420         igb_dev_clear_queues(dev);
1421         return -EINVAL;
1422 }
1423
1424 /*********************************************************************
1425  *
1426  *  This routine disables all traffic on the adapter by issuing a
1427  *  global reset on the MAC.
1428  *
1429  **********************************************************************/
1430 static void
1431 eth_igb_stop(struct rte_eth_dev *dev)
1432 {
1433         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1434         struct e1000_filter_info *filter_info =
1435                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1436         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1437         struct rte_eth_link link;
1438         struct e1000_flex_filter *p_flex;
1439         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1440         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1441         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1442
1443         igb_intr_disable(hw);
1444
1445         /* disable intr eventfd mapping */
1446         rte_intr_disable(intr_handle);
1447
1448         igb_pf_reset_hw(hw);
1449         E1000_WRITE_REG(hw, E1000_WUC, 0);
1450
1451         /* Set bit for Go Link disconnect */
1452         if (hw->mac.type >= e1000_82580) {
1453                 uint32_t phpm_reg;
1454
1455                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1456                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1457                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1458         }
1459
1460         /* Power down the phy. Needed to make the link go Down */
1461         eth_igb_dev_set_link_down(dev);
1462
1463         igb_dev_clear_queues(dev);
1464
1465         /* clear the recorded link status */
1466         memset(&link, 0, sizeof(link));
1467         rte_igb_dev_atomic_write_link_status(dev, &link);
1468
1469         /* Remove all flex filters of the device */
1470         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1471                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1472                 rte_free(p_flex);
1473         }
1474         filter_info->flex_mask = 0;
1475
1476         /* Remove all ntuple filters of the device */
1477         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1478              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1479                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1480                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1481                              p_5tuple, entries);
1482                 rte_free(p_5tuple);
1483         }
1484         filter_info->fivetuple_mask = 0;
1485         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1486              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1487                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1488                 TAILQ_REMOVE(&filter_info->twotuple_list,
1489                              p_2tuple, entries);
1490                 rte_free(p_2tuple);
1491         }
1492         filter_info->twotuple_mask = 0;
1493
1494         if (!rte_intr_allow_others(intr_handle))
1495                 /* resume to the default handler */
1496                 rte_intr_callback_register(intr_handle,
1497                                            eth_igb_interrupt_handler,
1498                                            (void *)dev);
1499
1500         /* Clean datapath event and queue/vec mapping */
1501         rte_intr_efd_disable(intr_handle);
1502         if (intr_handle->intr_vec != NULL) {
1503                 rte_free(intr_handle->intr_vec);
1504                 intr_handle->intr_vec = NULL;
1505         }
1506 }
1507
1508 static int
1509 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1510 {
1511         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1512
1513         if (hw->phy.media_type == e1000_media_type_copper)
1514                 e1000_power_up_phy(hw);
1515         else
1516                 e1000_power_up_fiber_serdes_link(hw);
1517
1518         return 0;
1519 }
1520
1521 static int
1522 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1523 {
1524         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1525
1526         if (hw->phy.media_type == e1000_media_type_copper)
1527                 e1000_power_down_phy(hw);
1528         else
1529                 e1000_shutdown_fiber_serdes_link(hw);
1530
1531         return 0;
1532 }
1533
1534 static void
1535 eth_igb_close(struct rte_eth_dev *dev)
1536 {
1537         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1538         struct e1000_adapter *adapter =
1539                 E1000_DEV_PRIVATE(dev->data->dev_private);
1540         struct rte_eth_link link;
1541         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1542         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1543
1544         eth_igb_stop(dev);
1545         adapter->stopped = 1;
1546
1547         e1000_phy_hw_reset(hw);
1548         igb_release_manageability(hw);
1549         igb_hw_control_release(hw);
1550
1551         /* Clear bit for Go Link disconnect */
1552         if (hw->mac.type >= e1000_82580) {
1553                 uint32_t phpm_reg;
1554
1555                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1556                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1557                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1558         }
1559
1560         igb_dev_free_queues(dev);
1561
1562         if (intr_handle->intr_vec) {
1563                 rte_free(intr_handle->intr_vec);
1564                 intr_handle->intr_vec = NULL;
1565         }
1566
1567         memset(&link, 0, sizeof(link));
1568         rte_igb_dev_atomic_write_link_status(dev, &link);
1569 }
1570
1571 static int
1572 igb_get_rx_buffer_size(struct e1000_hw *hw)
1573 {
1574         uint32_t rx_buf_size;
1575         if (hw->mac.type == e1000_82576) {
1576                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1577         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1578                 /* PBS needs to be translated according to a lookup table */
1579                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1580                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1581                 rx_buf_size = (rx_buf_size << 10);
1582         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1583                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1584         } else {
1585                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1586         }
1587
1588         return rx_buf_size;
1589 }
1590
1591 /*********************************************************************
1592  *
1593  *  Initialize the hardware
1594  *
1595  **********************************************************************/
1596 static int
1597 igb_hardware_init(struct e1000_hw *hw)
1598 {
1599         uint32_t rx_buf_size;
1600         int diag;
1601
1602         /* Let the firmware know the OS is in control */
1603         igb_hw_control_acquire(hw);
1604
1605         /*
1606          * These parameters control the automatic generation (Tx) and
1607          * response (Rx) to Ethernet PAUSE frames.
1608          * - High water mark should allow for at least two standard size (1518)
1609          *   frames to be received after sending an XOFF.
1610          * - Low water mark works best when it is very near the high water mark.
1611          *   This allows the receiver to restart by sending XON when it has
1612          *   drained a bit. Here we use an arbitrary value of 1500 which will
1613          *   restart after one full frame is pulled from the buffer. There
1614          *   could be several smaller frames in the buffer and if so they will
1615          *   not trigger the XON until their total number reduces the buffer
1616          *   by 1500.
1617          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1618          */
1619         rx_buf_size = igb_get_rx_buffer_size(hw);
1620
1621         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1622         hw->fc.low_water = hw->fc.high_water - 1500;
1623         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1624         hw->fc.send_xon = 1;
1625
1626         /* Set Flow control, use the tunable location if sane */
1627         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1628                 hw->fc.requested_mode = igb_fc_setting;
1629         else
1630                 hw->fc.requested_mode = e1000_fc_none;
1631
1632         /* Issue a global reset */
1633         igb_pf_reset_hw(hw);
1634         E1000_WRITE_REG(hw, E1000_WUC, 0);
1635
1636         diag = e1000_init_hw(hw);
1637         if (diag < 0)
1638                 return diag;
1639
1640         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1641         e1000_get_phy_info(hw);
1642         e1000_check_for_link(hw);
1643
1644         return 0;
1645 }
1646
1647 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1648 static void
1649 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1650 {
1651         int pause_frames;
1652
1653         uint64_t old_gprc  = stats->gprc;
1654         uint64_t old_gptc  = stats->gptc;
1655         uint64_t old_tpr   = stats->tpr;
1656         uint64_t old_tpt   = stats->tpt;
1657         uint64_t old_rpthc = stats->rpthc;
1658         uint64_t old_hgptc = stats->hgptc;
1659
1660         if(hw->phy.media_type == e1000_media_type_copper ||
1661             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1662                 stats->symerrs +=
1663                     E1000_READ_REG(hw,E1000_SYMERRS);
1664                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1665         }
1666
1667         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1668         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1669         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1670         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1671
1672         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1673         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1674         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1675         stats->dc += E1000_READ_REG(hw, E1000_DC);
1676         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1677         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1678         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1679         /*
1680         ** For watchdog management we need to know if we have been
1681         ** paused during the last interval, so capture that here.
1682         */
1683         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1684         stats->xoffrxc += pause_frames;
1685         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1686         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1687         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1688         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1689         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1690         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1691         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1692         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1693         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1694         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1695         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1696         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1697
1698         /* For the 64-bit byte counters the low dword must be read first. */
1699         /* Both registers clear on the read of the high dword */
1700
1701         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1702         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1703         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1704         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1705         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1706         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1707         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1708
1709         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1710         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1711         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1712         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1713         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1714
1715         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1716         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1717
1718         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1719         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1720         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1721         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1722         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1723         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1724
1725         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1726         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1727         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1728         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1729         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1730         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1731         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1732         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1733
1734         /* Interrupt Counts */
1735
1736         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1737         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1738         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1739         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1740         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1741         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1742         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1743         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1744         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1745
1746         /* Host to Card Statistics */
1747
1748         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1749         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1750         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1751         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1752         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1753         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1754         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1755         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1756         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1757         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1758         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1759         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1760         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1761         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1762         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1763         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1764
1765         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1766         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1767         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1768         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1769         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1770         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1771 }
1772
1773 static void
1774 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1775 {
1776         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1777         struct e1000_hw_stats *stats =
1778                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1779
1780         igb_read_stats_registers(hw, stats);
1781
1782         if (rte_stats == NULL)
1783                 return;
1784
1785         /* Rx Errors */
1786         rte_stats->imissed = stats->mpc;
1787         rte_stats->ierrors = stats->crcerrs +
1788                              stats->rlec + stats->ruc + stats->roc +
1789                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1790
1791         /* Tx Errors */
1792         rte_stats->oerrors = stats->ecol + stats->latecol;
1793
1794         rte_stats->ipackets = stats->gprc;
1795         rte_stats->opackets = stats->gptc;
1796         rte_stats->ibytes   = stats->gorc;
1797         rte_stats->obytes   = stats->gotc;
1798 }
1799
1800 static void
1801 eth_igb_stats_reset(struct rte_eth_dev *dev)
1802 {
1803         struct e1000_hw_stats *hw_stats =
1804                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1805
1806         /* HW registers are cleared on read */
1807         eth_igb_stats_get(dev, NULL);
1808
1809         /* Reset software totals */
1810         memset(hw_stats, 0, sizeof(*hw_stats));
1811 }
1812
1813 static void
1814 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1815 {
1816         struct e1000_hw_stats *stats =
1817                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1818
1819         /* HW registers are cleared on read */
1820         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1821
1822         /* Reset software totals */
1823         memset(stats, 0, sizeof(*stats));
1824 }
1825
1826 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1827         struct rte_eth_xstat_name *xstats_names,
1828         __rte_unused unsigned limit)
1829 {
1830         unsigned i;
1831
1832         if (xstats_names == NULL)
1833                 return IGB_NB_XSTATS;
1834
1835         /* Note: limit checked in rte_eth_xstats_names() */
1836
1837         for (i = 0; i < IGB_NB_XSTATS; i++) {
1838                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1839                          "%s", rte_igb_stats_strings[i].name);
1840         }
1841
1842         return IGB_NB_XSTATS;
1843 }
1844
1845 static int
1846 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1847                    unsigned n)
1848 {
1849         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1850         struct e1000_hw_stats *hw_stats =
1851                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1852         unsigned i;
1853
1854         if (n < IGB_NB_XSTATS)
1855                 return IGB_NB_XSTATS;
1856
1857         igb_read_stats_registers(hw, hw_stats);
1858
1859         /* If this is a reset xstats is NULL, and we have cleared the
1860          * registers by reading them.
1861          */
1862         if (!xstats)
1863                 return 0;
1864
1865         /* Extended stats */
1866         for (i = 0; i < IGB_NB_XSTATS; i++) {
1867                 xstats[i].id = i;
1868                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1869                         rte_igb_stats_strings[i].offset);
1870         }
1871
1872         return IGB_NB_XSTATS;
1873 }
1874
1875 static void
1876 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1877 {
1878         /* Good Rx packets, include VF loopback */
1879         UPDATE_VF_STAT(E1000_VFGPRC,
1880             hw_stats->last_gprc, hw_stats->gprc);
1881
1882         /* Good Rx octets, include VF loopback */
1883         UPDATE_VF_STAT(E1000_VFGORC,
1884             hw_stats->last_gorc, hw_stats->gorc);
1885
1886         /* Good Tx packets, include VF loopback */
1887         UPDATE_VF_STAT(E1000_VFGPTC,
1888             hw_stats->last_gptc, hw_stats->gptc);
1889
1890         /* Good Tx octets, include VF loopback */
1891         UPDATE_VF_STAT(E1000_VFGOTC,
1892             hw_stats->last_gotc, hw_stats->gotc);
1893
1894         /* Rx Multicst packets */
1895         UPDATE_VF_STAT(E1000_VFMPRC,
1896             hw_stats->last_mprc, hw_stats->mprc);
1897
1898         /* Good Rx loopback packets */
1899         UPDATE_VF_STAT(E1000_VFGPRLBC,
1900             hw_stats->last_gprlbc, hw_stats->gprlbc);
1901
1902         /* Good Rx loopback octets */
1903         UPDATE_VF_STAT(E1000_VFGORLBC,
1904             hw_stats->last_gorlbc, hw_stats->gorlbc);
1905
1906         /* Good Tx loopback packets */
1907         UPDATE_VF_STAT(E1000_VFGPTLBC,
1908             hw_stats->last_gptlbc, hw_stats->gptlbc);
1909
1910         /* Good Tx loopback octets */
1911         UPDATE_VF_STAT(E1000_VFGOTLBC,
1912             hw_stats->last_gotlbc, hw_stats->gotlbc);
1913 }
1914
1915 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1916                                      struct rte_eth_xstat_name *xstats_names,
1917                                      __rte_unused unsigned limit)
1918 {
1919         unsigned i;
1920
1921         if (xstats_names != NULL)
1922                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1923                         snprintf(xstats_names[i].name,
1924                                 sizeof(xstats_names[i].name), "%s",
1925                                 rte_igbvf_stats_strings[i].name);
1926                 }
1927         return IGBVF_NB_XSTATS;
1928 }
1929
1930 static int
1931 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1932                      unsigned n)
1933 {
1934         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1935         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1936                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1937         unsigned i;
1938
1939         if (n < IGBVF_NB_XSTATS)
1940                 return IGBVF_NB_XSTATS;
1941
1942         igbvf_read_stats_registers(hw, hw_stats);
1943
1944         if (!xstats)
1945                 return 0;
1946
1947         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1948                 xstats[i].id = i;
1949                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1950                         rte_igbvf_stats_strings[i].offset);
1951         }
1952
1953         return IGBVF_NB_XSTATS;
1954 }
1955
1956 static void
1957 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1958 {
1959         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1960         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1961                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1962
1963         igbvf_read_stats_registers(hw, hw_stats);
1964
1965         if (rte_stats == NULL)
1966                 return;
1967
1968         rte_stats->ipackets = hw_stats->gprc;
1969         rte_stats->ibytes = hw_stats->gorc;
1970         rte_stats->opackets = hw_stats->gptc;
1971         rte_stats->obytes = hw_stats->gotc;
1972 }
1973
1974 static void
1975 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1976 {
1977         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1978                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1979
1980         /* Sync HW register to the last stats */
1981         eth_igbvf_stats_get(dev, NULL);
1982
1983         /* reset HW current stats*/
1984         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1985                offsetof(struct e1000_vf_stats, gprc));
1986 }
1987
1988 static void
1989 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1990 {
1991         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1992
1993         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1994         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1995         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1996         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1997         dev_info->rx_offload_capa =
1998                 DEV_RX_OFFLOAD_VLAN_STRIP |
1999                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2000                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2001                 DEV_RX_OFFLOAD_TCP_CKSUM;
2002         dev_info->tx_offload_capa =
2003                 DEV_TX_OFFLOAD_VLAN_INSERT |
2004                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2005                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2006                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2007                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2008                 DEV_TX_OFFLOAD_TCP_TSO;
2009
2010         switch (hw->mac.type) {
2011         case e1000_82575:
2012                 dev_info->max_rx_queues = 4;
2013                 dev_info->max_tx_queues = 4;
2014                 dev_info->max_vmdq_pools = 0;
2015                 break;
2016
2017         case e1000_82576:
2018                 dev_info->max_rx_queues = 16;
2019                 dev_info->max_tx_queues = 16;
2020                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2021                 dev_info->vmdq_queue_num = 16;
2022                 break;
2023
2024         case e1000_82580:
2025                 dev_info->max_rx_queues = 8;
2026                 dev_info->max_tx_queues = 8;
2027                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2028                 dev_info->vmdq_queue_num = 8;
2029                 break;
2030
2031         case e1000_i350:
2032                 dev_info->max_rx_queues = 8;
2033                 dev_info->max_tx_queues = 8;
2034                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2035                 dev_info->vmdq_queue_num = 8;
2036                 break;
2037
2038         case e1000_i354:
2039                 dev_info->max_rx_queues = 8;
2040                 dev_info->max_tx_queues = 8;
2041                 break;
2042
2043         case e1000_i210:
2044                 dev_info->max_rx_queues = 4;
2045                 dev_info->max_tx_queues = 4;
2046                 dev_info->max_vmdq_pools = 0;
2047                 break;
2048
2049         case e1000_i211:
2050                 dev_info->max_rx_queues = 2;
2051                 dev_info->max_tx_queues = 2;
2052                 dev_info->max_vmdq_pools = 0;
2053                 break;
2054
2055         default:
2056                 /* Should not happen */
2057                 break;
2058         }
2059         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2060         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2061         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2062
2063         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2064                 .rx_thresh = {
2065                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2066                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2067                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2068                 },
2069                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2070                 .rx_drop_en = 0,
2071         };
2072
2073         dev_info->default_txconf = (struct rte_eth_txconf) {
2074                 .tx_thresh = {
2075                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2076                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2077                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2078                 },
2079                 .txq_flags = 0,
2080         };
2081
2082         dev_info->rx_desc_lim = rx_desc_lim;
2083         dev_info->tx_desc_lim = tx_desc_lim;
2084
2085         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2086                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2087                         ETH_LINK_SPEED_1G;
2088 }
2089
2090 static const uint32_t *
2091 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2092 {
2093         static const uint32_t ptypes[] = {
2094                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2095                 RTE_PTYPE_L2_ETHER,
2096                 RTE_PTYPE_L3_IPV4,
2097                 RTE_PTYPE_L3_IPV4_EXT,
2098                 RTE_PTYPE_L3_IPV6,
2099                 RTE_PTYPE_L3_IPV6_EXT,
2100                 RTE_PTYPE_L4_TCP,
2101                 RTE_PTYPE_L4_UDP,
2102                 RTE_PTYPE_L4_SCTP,
2103                 RTE_PTYPE_TUNNEL_IP,
2104                 RTE_PTYPE_INNER_L3_IPV6,
2105                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2106                 RTE_PTYPE_INNER_L4_TCP,
2107                 RTE_PTYPE_INNER_L4_UDP,
2108                 RTE_PTYPE_UNKNOWN
2109         };
2110
2111         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2112             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2113                 return ptypes;
2114         return NULL;
2115 }
2116
2117 static void
2118 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2119 {
2120         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2121
2122         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2123         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2124         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2125         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2126         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2127                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2128                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2129                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2130         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2131                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2132                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2133                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2134                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2135                                 DEV_TX_OFFLOAD_TCP_TSO;
2136         switch (hw->mac.type) {
2137         case e1000_vfadapt:
2138                 dev_info->max_rx_queues = 2;
2139                 dev_info->max_tx_queues = 2;
2140                 break;
2141         case e1000_vfadapt_i350:
2142                 dev_info->max_rx_queues = 1;
2143                 dev_info->max_tx_queues = 1;
2144                 break;
2145         default:
2146                 /* Should not happen */
2147                 break;
2148         }
2149
2150         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2151                 .rx_thresh = {
2152                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2153                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2154                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2155                 },
2156                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2157                 .rx_drop_en = 0,
2158         };
2159
2160         dev_info->default_txconf = (struct rte_eth_txconf) {
2161                 .tx_thresh = {
2162                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2163                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2164                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2165                 },
2166                 .txq_flags = 0,
2167         };
2168
2169         dev_info->rx_desc_lim = rx_desc_lim;
2170         dev_info->tx_desc_lim = tx_desc_lim;
2171 }
2172
2173 /* return 0 means link status changed, -1 means not changed */
2174 static int
2175 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2176 {
2177         struct e1000_hw *hw =
2178                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2179         struct rte_eth_link link, old;
2180         int link_check, count;
2181
2182         link_check = 0;
2183         hw->mac.get_link_status = 1;
2184
2185         /* possible wait-to-complete in up to 9 seconds */
2186         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2187                 /* Read the real link status */
2188                 switch (hw->phy.media_type) {
2189                 case e1000_media_type_copper:
2190                         /* Do the work to read phy */
2191                         e1000_check_for_link(hw);
2192                         link_check = !hw->mac.get_link_status;
2193                         break;
2194
2195                 case e1000_media_type_fiber:
2196                         e1000_check_for_link(hw);
2197                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2198                                       E1000_STATUS_LU);
2199                         break;
2200
2201                 case e1000_media_type_internal_serdes:
2202                         e1000_check_for_link(hw);
2203                         link_check = hw->mac.serdes_has_link;
2204                         break;
2205
2206                 /* VF device is type_unknown */
2207                 case e1000_media_type_unknown:
2208                         eth_igbvf_link_update(hw);
2209                         link_check = !hw->mac.get_link_status;
2210                         break;
2211
2212                 default:
2213                         break;
2214                 }
2215                 if (link_check || wait_to_complete == 0)
2216                         break;
2217                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2218         }
2219         memset(&link, 0, sizeof(link));
2220         rte_igb_dev_atomic_read_link_status(dev, &link);
2221         old = link;
2222
2223         /* Now we check if a transition has happened */
2224         if (link_check) {
2225                 uint16_t duplex, speed;
2226                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2227                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2228                                 ETH_LINK_FULL_DUPLEX :
2229                                 ETH_LINK_HALF_DUPLEX;
2230                 link.link_speed = speed;
2231                 link.link_status = ETH_LINK_UP;
2232                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2233                                 ETH_LINK_SPEED_FIXED);
2234         } else if (!link_check) {
2235                 link.link_speed = 0;
2236                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2237                 link.link_status = ETH_LINK_DOWN;
2238                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2239         }
2240         rte_igb_dev_atomic_write_link_status(dev, &link);
2241
2242         /* not changed */
2243         if (old.link_status == link.link_status)
2244                 return -1;
2245
2246         /* changed */
2247         return 0;
2248 }
2249
2250 /*
2251  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2252  * For ASF and Pass Through versions of f/w this means
2253  * that the driver is loaded.
2254  */
2255 static void
2256 igb_hw_control_acquire(struct e1000_hw *hw)
2257 {
2258         uint32_t ctrl_ext;
2259
2260         /* Let firmware know the driver has taken over */
2261         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2262         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2263 }
2264
2265 /*
2266  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2267  * For ASF and Pass Through versions of f/w this means that the
2268  * driver is no longer loaded.
2269  */
2270 static void
2271 igb_hw_control_release(struct e1000_hw *hw)
2272 {
2273         uint32_t ctrl_ext;
2274
2275         /* Let firmware taken over control of h/w */
2276         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2277         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2278                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2279 }
2280
2281 /*
2282  * Bit of a misnomer, what this really means is
2283  * to enable OS management of the system... aka
2284  * to disable special hardware management features.
2285  */
2286 static void
2287 igb_init_manageability(struct e1000_hw *hw)
2288 {
2289         if (e1000_enable_mng_pass_thru(hw)) {
2290                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2291                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2292
2293                 /* disable hardware interception of ARP */
2294                 manc &= ~(E1000_MANC_ARP_EN);
2295
2296                 /* enable receiving management packets to the host */
2297                 manc |= E1000_MANC_EN_MNG2HOST;
2298                 manc2h |= 1 << 5;  /* Mng Port 623 */
2299                 manc2h |= 1 << 6;  /* Mng Port 664 */
2300                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2301                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2302         }
2303 }
2304
2305 static void
2306 igb_release_manageability(struct e1000_hw *hw)
2307 {
2308         if (e1000_enable_mng_pass_thru(hw)) {
2309                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2310
2311                 manc |= E1000_MANC_ARP_EN;
2312                 manc &= ~E1000_MANC_EN_MNG2HOST;
2313
2314                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2315         }
2316 }
2317
2318 static void
2319 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2320 {
2321         struct e1000_hw *hw =
2322                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2323         uint32_t rctl;
2324
2325         rctl = E1000_READ_REG(hw, E1000_RCTL);
2326         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2327         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2328 }
2329
2330 static void
2331 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2332 {
2333         struct e1000_hw *hw =
2334                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2335         uint32_t rctl;
2336
2337         rctl = E1000_READ_REG(hw, E1000_RCTL);
2338         rctl &= (~E1000_RCTL_UPE);
2339         if (dev->data->all_multicast == 1)
2340                 rctl |= E1000_RCTL_MPE;
2341         else
2342                 rctl &= (~E1000_RCTL_MPE);
2343         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2344 }
2345
2346 static void
2347 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2348 {
2349         struct e1000_hw *hw =
2350                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2351         uint32_t rctl;
2352
2353         rctl = E1000_READ_REG(hw, E1000_RCTL);
2354         rctl |= E1000_RCTL_MPE;
2355         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2356 }
2357
2358 static void
2359 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2360 {
2361         struct e1000_hw *hw =
2362                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2363         uint32_t rctl;
2364
2365         if (dev->data->promiscuous == 1)
2366                 return; /* must remain in all_multicast mode */
2367         rctl = E1000_READ_REG(hw, E1000_RCTL);
2368         rctl &= (~E1000_RCTL_MPE);
2369         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2370 }
2371
2372 static int
2373 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2374 {
2375         struct e1000_hw *hw =
2376                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2377         struct e1000_vfta * shadow_vfta =
2378                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2379         uint32_t vfta;
2380         uint32_t vid_idx;
2381         uint32_t vid_bit;
2382
2383         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2384                               E1000_VFTA_ENTRY_MASK);
2385         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2386         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2387         if (on)
2388                 vfta |= vid_bit;
2389         else
2390                 vfta &= ~vid_bit;
2391         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2392
2393         /* update local VFTA copy */
2394         shadow_vfta->vfta[vid_idx] = vfta;
2395
2396         return 0;
2397 }
2398
2399 static int
2400 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2401                       enum rte_vlan_type vlan_type,
2402                       uint16_t tpid)
2403 {
2404         struct e1000_hw *hw =
2405                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2406         uint32_t reg, qinq;
2407
2408         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2409         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2410
2411         /* only outer TPID of double VLAN can be configured*/
2412         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2413                 reg = E1000_READ_REG(hw, E1000_VET);
2414                 reg = (reg & (~E1000_VET_VET_EXT)) |
2415                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2416                 E1000_WRITE_REG(hw, E1000_VET, reg);
2417
2418                 return 0;
2419         }
2420
2421         /* all other TPID values are read-only*/
2422         PMD_DRV_LOG(ERR, "Not supported");
2423
2424         return -ENOTSUP;
2425 }
2426
2427 static void
2428 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2429 {
2430         struct e1000_hw *hw =
2431                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2432         uint32_t reg;
2433
2434         /* Filter Table Disable */
2435         reg = E1000_READ_REG(hw, E1000_RCTL);
2436         reg &= ~E1000_RCTL_CFIEN;
2437         reg &= ~E1000_RCTL_VFE;
2438         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2439 }
2440
2441 static void
2442 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2443 {
2444         struct e1000_hw *hw =
2445                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2446         struct e1000_vfta * shadow_vfta =
2447                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2448         uint32_t reg;
2449         int i;
2450
2451         /* Filter Table Enable, CFI not used for packet acceptance */
2452         reg = E1000_READ_REG(hw, E1000_RCTL);
2453         reg &= ~E1000_RCTL_CFIEN;
2454         reg |= E1000_RCTL_VFE;
2455         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2456
2457         /* restore VFTA table */
2458         for (i = 0; i < IGB_VFTA_SIZE; i++)
2459                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2460 }
2461
2462 static void
2463 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2464 {
2465         struct e1000_hw *hw =
2466                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2467         uint32_t reg;
2468
2469         /* VLAN Mode Disable */
2470         reg = E1000_READ_REG(hw, E1000_CTRL);
2471         reg &= ~E1000_CTRL_VME;
2472         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2473 }
2474
2475 static void
2476 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2477 {
2478         struct e1000_hw *hw =
2479                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2480         uint32_t reg;
2481
2482         /* VLAN Mode Enable */
2483         reg = E1000_READ_REG(hw, E1000_CTRL);
2484         reg |= E1000_CTRL_VME;
2485         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2486 }
2487
2488 static void
2489 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2490 {
2491         struct e1000_hw *hw =
2492                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2493         uint32_t reg;
2494
2495         /* CTRL_EXT: Extended VLAN */
2496         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2497         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2498         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2499
2500         /* Update maximum packet length */
2501         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2502                 E1000_WRITE_REG(hw, E1000_RLPML,
2503                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2504                                                 VLAN_TAG_SIZE);
2505 }
2506
2507 static void
2508 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2509 {
2510         struct e1000_hw *hw =
2511                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2512         uint32_t reg;
2513
2514         /* CTRL_EXT: Extended VLAN */
2515         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2516         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2517         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2518
2519         /* Update maximum packet length */
2520         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2521                 E1000_WRITE_REG(hw, E1000_RLPML,
2522                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2523                                                 2 * VLAN_TAG_SIZE);
2524 }
2525
2526 static void
2527 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2528 {
2529         if(mask & ETH_VLAN_STRIP_MASK){
2530                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2531                         igb_vlan_hw_strip_enable(dev);
2532                 else
2533                         igb_vlan_hw_strip_disable(dev);
2534         }
2535
2536         if(mask & ETH_VLAN_FILTER_MASK){
2537                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2538                         igb_vlan_hw_filter_enable(dev);
2539                 else
2540                         igb_vlan_hw_filter_disable(dev);
2541         }
2542
2543         if(mask & ETH_VLAN_EXTEND_MASK){
2544                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2545                         igb_vlan_hw_extend_enable(dev);
2546                 else
2547                         igb_vlan_hw_extend_disable(dev);
2548         }
2549 }
2550
2551
2552 /**
2553  * It enables the interrupt mask and then enable the interrupt.
2554  *
2555  * @param dev
2556  *  Pointer to struct rte_eth_dev.
2557  *
2558  * @return
2559  *  - On success, zero.
2560  *  - On failure, a negative value.
2561  */
2562 static int
2563 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2564 {
2565         struct e1000_interrupt *intr =
2566                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2567
2568         intr->mask |= E1000_ICR_LSC;
2569
2570         return 0;
2571 }
2572
2573 /* It clears the interrupt causes and enables the interrupt.
2574  * It will be called once only during nic initialized.
2575  *
2576  * @param dev
2577  *  Pointer to struct rte_eth_dev.
2578  *
2579  * @return
2580  *  - On success, zero.
2581  *  - On failure, a negative value.
2582  */
2583 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2584 {
2585         uint32_t mask, regval;
2586         struct e1000_hw *hw =
2587                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2588         struct rte_eth_dev_info dev_info;
2589
2590         memset(&dev_info, 0, sizeof(dev_info));
2591         eth_igb_infos_get(dev, &dev_info);
2592
2593         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2594         regval = E1000_READ_REG(hw, E1000_EIMS);
2595         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2596
2597         return 0;
2598 }
2599
2600 /*
2601  * It reads ICR and gets interrupt causes, check it and set a bit flag
2602  * to update link status.
2603  *
2604  * @param dev
2605  *  Pointer to struct rte_eth_dev.
2606  *
2607  * @return
2608  *  - On success, zero.
2609  *  - On failure, a negative value.
2610  */
2611 static int
2612 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2613 {
2614         uint32_t icr;
2615         struct e1000_hw *hw =
2616                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2617         struct e1000_interrupt *intr =
2618                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2619
2620         igb_intr_disable(hw);
2621
2622         /* read-on-clear nic registers here */
2623         icr = E1000_READ_REG(hw, E1000_ICR);
2624
2625         intr->flags = 0;
2626         if (icr & E1000_ICR_LSC) {
2627                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2628         }
2629
2630         if (icr & E1000_ICR_VMMB)
2631                 intr->flags |= E1000_FLAG_MAILBOX;
2632
2633         return 0;
2634 }
2635
2636 /*
2637  * It executes link_update after knowing an interrupt is prsent.
2638  *
2639  * @param dev
2640  *  Pointer to struct rte_eth_dev.
2641  *
2642  * @return
2643  *  - On success, zero.
2644  *  - On failure, a negative value.
2645  */
2646 static int
2647 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2648                          struct rte_intr_handle *intr_handle)
2649 {
2650         struct e1000_hw *hw =
2651                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2652         struct e1000_interrupt *intr =
2653                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2654         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
2655         uint32_t tctl, rctl;
2656         struct rte_eth_link link;
2657         int ret;
2658
2659         if (intr->flags & E1000_FLAG_MAILBOX) {
2660                 igb_pf_mbx_process(dev);
2661                 intr->flags &= ~E1000_FLAG_MAILBOX;
2662         }
2663
2664         igb_intr_enable(dev);
2665         rte_intr_enable(intr_handle);
2666
2667         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2668                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2669
2670                 /* set get_link_status to check register later */
2671                 hw->mac.get_link_status = 1;
2672                 ret = eth_igb_link_update(dev, 0);
2673
2674                 /* check if link has changed */
2675                 if (ret < 0)
2676                         return 0;
2677
2678                 memset(&link, 0, sizeof(link));
2679                 rte_igb_dev_atomic_read_link_status(dev, &link);
2680                 if (link.link_status) {
2681                         PMD_INIT_LOG(INFO,
2682                                      " Port %d: Link Up - speed %u Mbps - %s",
2683                                      dev->data->port_id,
2684                                      (unsigned)link.link_speed,
2685                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2686                                      "full-duplex" : "half-duplex");
2687                 } else {
2688                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2689                                      dev->data->port_id);
2690                 }
2691
2692                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2693                              pci_dev->addr.domain,
2694                              pci_dev->addr.bus,
2695                              pci_dev->addr.devid,
2696                              pci_dev->addr.function);
2697                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2698                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2699                 if (link.link_status) {
2700                         /* enable Tx/Rx */
2701                         tctl |= E1000_TCTL_EN;
2702                         rctl |= E1000_RCTL_EN;
2703                 } else {
2704                         /* disable Tx/Rx */
2705                         tctl &= ~E1000_TCTL_EN;
2706                         rctl &= ~E1000_RCTL_EN;
2707                 }
2708                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2709                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2710                 E1000_WRITE_FLUSH(hw);
2711                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2712         }
2713
2714         return 0;
2715 }
2716
2717 /**
2718  * Interrupt handler which shall be registered at first.
2719  *
2720  * @param handle
2721  *  Pointer to interrupt handle.
2722  * @param param
2723  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2724  *
2725  * @return
2726  *  void
2727  */
2728 static void
2729 eth_igb_interrupt_handler(struct rte_intr_handle *handle, void *param)
2730 {
2731         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2732
2733         eth_igb_interrupt_get_status(dev);
2734         eth_igb_interrupt_action(dev, handle);
2735 }
2736
2737 static int
2738 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2739 {
2740         uint32_t eicr;
2741         struct e1000_hw *hw =
2742                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2743         struct e1000_interrupt *intr =
2744                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2745
2746         igbvf_intr_disable(hw);
2747
2748         /* read-on-clear nic registers here */
2749         eicr = E1000_READ_REG(hw, E1000_EICR);
2750         intr->flags = 0;
2751
2752         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2753                 intr->flags |= E1000_FLAG_MAILBOX;
2754
2755         return 0;
2756 }
2757
2758 void igbvf_mbx_process(struct rte_eth_dev *dev)
2759 {
2760         struct e1000_hw *hw =
2761                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2762         struct e1000_mbx_info *mbx = &hw->mbx;
2763         u32 in_msg = 0;
2764
2765         if (mbx->ops.read(hw, &in_msg, 1, 0))
2766                 return;
2767
2768         /* PF reset VF event */
2769         if (in_msg == E1000_PF_CONTROL_MSG)
2770                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2771 }
2772
2773 static int
2774 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2775 {
2776         struct e1000_interrupt *intr =
2777                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2778
2779         if (intr->flags & E1000_FLAG_MAILBOX) {
2780                 igbvf_mbx_process(dev);
2781                 intr->flags &= ~E1000_FLAG_MAILBOX;
2782         }
2783
2784         igbvf_intr_enable(dev);
2785         rte_intr_enable(intr_handle);
2786
2787         return 0;
2788 }
2789
2790 static void
2791 eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
2792                             void *param)
2793 {
2794         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2795
2796         eth_igbvf_interrupt_get_status(dev);
2797         eth_igbvf_interrupt_action(dev, handle);
2798 }
2799
2800 static int
2801 eth_igb_led_on(struct rte_eth_dev *dev)
2802 {
2803         struct e1000_hw *hw;
2804
2805         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2806         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2807 }
2808
2809 static int
2810 eth_igb_led_off(struct rte_eth_dev *dev)
2811 {
2812         struct e1000_hw *hw;
2813
2814         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2815         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2816 }
2817
2818 static int
2819 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2820 {
2821         struct e1000_hw *hw;
2822         uint32_t ctrl;
2823         int tx_pause;
2824         int rx_pause;
2825
2826         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2827         fc_conf->pause_time = hw->fc.pause_time;
2828         fc_conf->high_water = hw->fc.high_water;
2829         fc_conf->low_water = hw->fc.low_water;
2830         fc_conf->send_xon = hw->fc.send_xon;
2831         fc_conf->autoneg = hw->mac.autoneg;
2832
2833         /*
2834          * Return rx_pause and tx_pause status according to actual setting of
2835          * the TFCE and RFCE bits in the CTRL register.
2836          */
2837         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2838         if (ctrl & E1000_CTRL_TFCE)
2839                 tx_pause = 1;
2840         else
2841                 tx_pause = 0;
2842
2843         if (ctrl & E1000_CTRL_RFCE)
2844                 rx_pause = 1;
2845         else
2846                 rx_pause = 0;
2847
2848         if (rx_pause && tx_pause)
2849                 fc_conf->mode = RTE_FC_FULL;
2850         else if (rx_pause)
2851                 fc_conf->mode = RTE_FC_RX_PAUSE;
2852         else if (tx_pause)
2853                 fc_conf->mode = RTE_FC_TX_PAUSE;
2854         else
2855                 fc_conf->mode = RTE_FC_NONE;
2856
2857         return 0;
2858 }
2859
2860 static int
2861 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2862 {
2863         struct e1000_hw *hw;
2864         int err;
2865         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2866                 e1000_fc_none,
2867                 e1000_fc_rx_pause,
2868                 e1000_fc_tx_pause,
2869                 e1000_fc_full
2870         };
2871         uint32_t rx_buf_size;
2872         uint32_t max_high_water;
2873         uint32_t rctl;
2874
2875         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876         if (fc_conf->autoneg != hw->mac.autoneg)
2877                 return -ENOTSUP;
2878         rx_buf_size = igb_get_rx_buffer_size(hw);
2879         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2880
2881         /* At least reserve one Ethernet frame for watermark */
2882         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2883         if ((fc_conf->high_water > max_high_water) ||
2884             (fc_conf->high_water < fc_conf->low_water)) {
2885                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2886                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2887                 return -EINVAL;
2888         }
2889
2890         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2891         hw->fc.pause_time     = fc_conf->pause_time;
2892         hw->fc.high_water     = fc_conf->high_water;
2893         hw->fc.low_water      = fc_conf->low_water;
2894         hw->fc.send_xon       = fc_conf->send_xon;
2895
2896         err = e1000_setup_link_generic(hw);
2897         if (err == E1000_SUCCESS) {
2898
2899                 /* check if we want to forward MAC frames - driver doesn't have native
2900                  * capability to do that, so we'll write the registers ourselves */
2901
2902                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2903
2904                 /* set or clear MFLCN.PMCF bit depending on configuration */
2905                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2906                         rctl |= E1000_RCTL_PMCF;
2907                 else
2908                         rctl &= ~E1000_RCTL_PMCF;
2909
2910                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2911                 E1000_WRITE_FLUSH(hw);
2912
2913                 return 0;
2914         }
2915
2916         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2917         return -EIO;
2918 }
2919
2920 #define E1000_RAH_POOLSEL_SHIFT      (18)
2921 static void
2922 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2923                 uint32_t index, __rte_unused uint32_t pool)
2924 {
2925         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2926         uint32_t rah;
2927
2928         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2929         rah = E1000_READ_REG(hw, E1000_RAH(index));
2930         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2931         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2932 }
2933
2934 static void
2935 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2936 {
2937         uint8_t addr[ETHER_ADDR_LEN];
2938         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2939
2940         memset(addr, 0, sizeof(addr));
2941
2942         e1000_rar_set(hw, addr, index);
2943 }
2944
2945 static void
2946 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2947                                 struct ether_addr *addr)
2948 {
2949         eth_igb_rar_clear(dev, 0);
2950
2951         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2952 }
2953 /*
2954  * Virtual Function operations
2955  */
2956 static void
2957 igbvf_intr_disable(struct e1000_hw *hw)
2958 {
2959         PMD_INIT_FUNC_TRACE();
2960
2961         /* Clear interrupt mask to stop from interrupts being generated */
2962         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2963
2964         E1000_WRITE_FLUSH(hw);
2965 }
2966
2967 static void
2968 igbvf_stop_adapter(struct rte_eth_dev *dev)
2969 {
2970         u32 reg_val;
2971         u16 i;
2972         struct rte_eth_dev_info dev_info;
2973         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2974
2975         memset(&dev_info, 0, sizeof(dev_info));
2976         eth_igbvf_infos_get(dev, &dev_info);
2977
2978         /* Clear interrupt mask to stop from interrupts being generated */
2979         igbvf_intr_disable(hw);
2980
2981         /* Clear any pending interrupts, flush previous writes */
2982         E1000_READ_REG(hw, E1000_EICR);
2983
2984         /* Disable the transmit unit.  Each queue must be disabled. */
2985         for (i = 0; i < dev_info.max_tx_queues; i++)
2986                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2987
2988         /* Disable the receive unit by stopping each queue */
2989         for (i = 0; i < dev_info.max_rx_queues; i++) {
2990                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2991                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2992                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2993                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2994                         ;
2995         }
2996
2997         /* flush all queues disables */
2998         E1000_WRITE_FLUSH(hw);
2999         msec_delay(2);
3000 }
3001
3002 static int eth_igbvf_link_update(struct e1000_hw *hw)
3003 {
3004         struct e1000_mbx_info *mbx = &hw->mbx;
3005         struct e1000_mac_info *mac = &hw->mac;
3006         int ret_val = E1000_SUCCESS;
3007
3008         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3009
3010         /*
3011          * We only want to run this if there has been a rst asserted.
3012          * in this case that could mean a link change, device reset,
3013          * or a virtual function reset
3014          */
3015
3016         /* If we were hit with a reset or timeout drop the link */
3017         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3018                 mac->get_link_status = TRUE;
3019
3020         if (!mac->get_link_status)
3021                 goto out;
3022
3023         /* if link status is down no point in checking to see if pf is up */
3024         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3025                 goto out;
3026
3027         /* if we passed all the tests above then the link is up and we no
3028          * longer need to check for link */
3029         mac->get_link_status = FALSE;
3030
3031 out:
3032         return ret_val;
3033 }
3034
3035
3036 static int
3037 igbvf_dev_configure(struct rte_eth_dev *dev)
3038 {
3039         struct rte_eth_conf* conf = &dev->data->dev_conf;
3040
3041         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3042                      dev->data->port_id);
3043
3044         /*
3045          * VF has no ability to enable/disable HW CRC
3046          * Keep the persistent behavior the same as Host PF
3047          */
3048 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3049         if (!conf->rxmode.hw_strip_crc) {
3050                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3051                 conf->rxmode.hw_strip_crc = 1;
3052         }
3053 #else
3054         if (conf->rxmode.hw_strip_crc) {
3055                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3056                 conf->rxmode.hw_strip_crc = 0;
3057         }
3058 #endif
3059
3060         return 0;
3061 }
3062
3063 static int
3064 igbvf_dev_start(struct rte_eth_dev *dev)
3065 {
3066         struct e1000_hw *hw =
3067                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068         struct e1000_adapter *adapter =
3069                 E1000_DEV_PRIVATE(dev->data->dev_private);
3070         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3071         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3072         int ret;
3073         uint32_t intr_vector = 0;
3074
3075         PMD_INIT_FUNC_TRACE();
3076
3077         hw->mac.ops.reset_hw(hw);
3078         adapter->stopped = 0;
3079
3080         /* Set all vfta */
3081         igbvf_set_vfta_all(dev,1);
3082
3083         eth_igbvf_tx_init(dev);
3084
3085         /* This can fail when allocating mbufs for descriptor rings */
3086         ret = eth_igbvf_rx_init(dev);
3087         if (ret) {
3088                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3089                 igb_dev_clear_queues(dev);
3090                 return ret;
3091         }
3092
3093         /* check and configure queue intr-vector mapping */
3094         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3095                 intr_vector = dev->data->nb_rx_queues;
3096                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3097                 if (ret)
3098                         return ret;
3099         }
3100
3101         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3102                 intr_handle->intr_vec =
3103                         rte_zmalloc("intr_vec",
3104                                     dev->data->nb_rx_queues * sizeof(int), 0);
3105                 if (!intr_handle->intr_vec) {
3106                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3107                                      " intr_vec\n", dev->data->nb_rx_queues);
3108                         return -ENOMEM;
3109                 }
3110         }
3111
3112         eth_igbvf_configure_msix_intr(dev);
3113
3114         /* enable uio/vfio intr/eventfd mapping */
3115         rte_intr_enable(intr_handle);
3116
3117         /* resume enabled intr since hw reset */
3118         igbvf_intr_enable(dev);
3119
3120         return 0;
3121 }
3122
3123 static void
3124 igbvf_dev_stop(struct rte_eth_dev *dev)
3125 {
3126         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3127         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3128
3129         PMD_INIT_FUNC_TRACE();
3130
3131         igbvf_stop_adapter(dev);
3132
3133         /*
3134           * Clear what we set, but we still keep shadow_vfta to
3135           * restore after device starts
3136           */
3137         igbvf_set_vfta_all(dev,0);
3138
3139         igb_dev_clear_queues(dev);
3140
3141         /* disable intr eventfd mapping */
3142         rte_intr_disable(intr_handle);
3143
3144         /* Clean datapath event and queue/vec mapping */
3145         rte_intr_efd_disable(intr_handle);
3146         if (intr_handle->intr_vec) {
3147                 rte_free(intr_handle->intr_vec);
3148                 intr_handle->intr_vec = NULL;
3149         }
3150 }
3151
3152 static void
3153 igbvf_dev_close(struct rte_eth_dev *dev)
3154 {
3155         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3156         struct e1000_adapter *adapter =
3157                 E1000_DEV_PRIVATE(dev->data->dev_private);
3158         struct ether_addr addr;
3159
3160         PMD_INIT_FUNC_TRACE();
3161
3162         e1000_reset_hw(hw);
3163
3164         igbvf_dev_stop(dev);
3165         adapter->stopped = 1;
3166         igb_dev_free_queues(dev);
3167
3168         /**
3169          * reprogram the RAR with a zero mac address,
3170          * to ensure that the VF traffic goes to the PF
3171          * after stop, close and detach of the VF.
3172          **/
3173
3174         memset(&addr, 0, sizeof(addr));
3175         igbvf_default_mac_addr_set(dev, &addr);
3176 }
3177
3178 static void
3179 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3180 {
3181         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3182
3183         /* Set both unicast and multicast promisc */
3184         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3185 }
3186
3187 static void
3188 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3189 {
3190         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3191
3192         /* If in allmulticast mode leave multicast promisc */
3193         if (dev->data->all_multicast == 1)
3194                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3195         else
3196                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3197 }
3198
3199 static void
3200 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3201 {
3202         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3203
3204         /* In promiscuous mode multicast promisc already set */
3205         if (dev->data->promiscuous == 0)
3206                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3207 }
3208
3209 static void
3210 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3211 {
3212         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3213
3214         /* In promiscuous mode leave multicast promisc enabled */
3215         if (dev->data->promiscuous == 0)
3216                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3217 }
3218
3219 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3220 {
3221         struct e1000_mbx_info *mbx = &hw->mbx;
3222         uint32_t msgbuf[2];
3223         s32 err;
3224
3225         /* After set vlan, vlan strip will also be enabled in igb driver*/
3226         msgbuf[0] = E1000_VF_SET_VLAN;
3227         msgbuf[1] = vid;
3228         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3229         if (on)
3230                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3231
3232         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3233         if (err)
3234                 goto mbx_err;
3235
3236         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3237         if (err)
3238                 goto mbx_err;
3239
3240         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3241         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3242                 err = -EINVAL;
3243
3244 mbx_err:
3245         return err;
3246 }
3247
3248 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3249 {
3250         struct e1000_hw *hw =
3251                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3252         struct e1000_vfta * shadow_vfta =
3253                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3254         int i = 0, j = 0, vfta = 0, mask = 1;
3255
3256         for (i = 0; i < IGB_VFTA_SIZE; i++){
3257                 vfta = shadow_vfta->vfta[i];
3258                 if(vfta){
3259                         mask = 1;
3260                         for (j = 0; j < 32; j++){
3261                                 if(vfta & mask)
3262                                         igbvf_set_vfta(hw,
3263                                                 (uint16_t)((i<<5)+j), on);
3264                                 mask<<=1;
3265                         }
3266                 }
3267         }
3268
3269 }
3270
3271 static int
3272 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3273 {
3274         struct e1000_hw *hw =
3275                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3276         struct e1000_vfta * shadow_vfta =
3277                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3278         uint32_t vid_idx = 0;
3279         uint32_t vid_bit = 0;
3280         int ret = 0;
3281
3282         PMD_INIT_FUNC_TRACE();
3283
3284         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3285         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3286         if(ret){
3287                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3288                 return ret;
3289         }
3290         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3291         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3292
3293         /*Save what we set and retore it after device reset*/
3294         if (on)
3295                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3296         else
3297                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3298
3299         return 0;
3300 }
3301
3302 static void
3303 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3304 {
3305         struct e1000_hw *hw =
3306                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3307
3308         /* index is not used by rar_set() */
3309         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3310 }
3311
3312
3313 static int
3314 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3315                         struct rte_eth_rss_reta_entry64 *reta_conf,
3316                         uint16_t reta_size)
3317 {
3318         uint8_t i, j, mask;
3319         uint32_t reta, r;
3320         uint16_t idx, shift;
3321         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3322
3323         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3324                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3325                         "(%d) doesn't match the number hardware can supported "
3326                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3327                 return -EINVAL;
3328         }
3329
3330         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3331                 idx = i / RTE_RETA_GROUP_SIZE;
3332                 shift = i % RTE_RETA_GROUP_SIZE;
3333                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3334                                                 IGB_4_BIT_MASK);
3335                 if (!mask)
3336                         continue;
3337                 if (mask == IGB_4_BIT_MASK)
3338                         r = 0;
3339                 else
3340                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3341                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3342                         if (mask & (0x1 << j))
3343                                 reta |= reta_conf[idx].reta[shift + j] <<
3344                                                         (CHAR_BIT * j);
3345                         else
3346                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3347                 }
3348                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3349         }
3350
3351         return 0;
3352 }
3353
3354 static int
3355 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3356                        struct rte_eth_rss_reta_entry64 *reta_conf,
3357                        uint16_t reta_size)
3358 {
3359         uint8_t i, j, mask;
3360         uint32_t reta;
3361         uint16_t idx, shift;
3362         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3363
3364         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3365                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3366                         "(%d) doesn't match the number hardware can supported "
3367                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3368                 return -EINVAL;
3369         }
3370
3371         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3372                 idx = i / RTE_RETA_GROUP_SIZE;
3373                 shift = i % RTE_RETA_GROUP_SIZE;
3374                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3375                                                 IGB_4_BIT_MASK);
3376                 if (!mask)
3377                         continue;
3378                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3379                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3380                         if (mask & (0x1 << j))
3381                                 reta_conf[idx].reta[shift + j] =
3382                                         ((reta >> (CHAR_BIT * j)) &
3383                                                 IGB_8_BIT_MASK);
3384                 }
3385         }
3386
3387         return 0;
3388 }
3389
3390 #define MAC_TYPE_FILTER_SUP(type)    do {\
3391         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3392                 (type) != e1000_82576)\
3393                 return -ENOTSUP;\
3394 } while (0)
3395
3396 static int
3397 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3398                         struct rte_eth_syn_filter *filter,
3399                         bool add)
3400 {
3401         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3402         uint32_t synqf, rfctl;
3403
3404         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3405                 return -EINVAL;
3406
3407         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3408
3409         if (add) {
3410                 if (synqf & E1000_SYN_FILTER_ENABLE)
3411                         return -EINVAL;
3412
3413                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3414                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3415
3416                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3417                 if (filter->hig_pri)
3418                         rfctl |= E1000_RFCTL_SYNQFP;
3419                 else
3420                         rfctl &= ~E1000_RFCTL_SYNQFP;
3421
3422                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3423         } else {
3424                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3425                         return -ENOENT;
3426                 synqf = 0;
3427         }
3428
3429         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3430         E1000_WRITE_FLUSH(hw);
3431         return 0;
3432 }
3433
3434 static int
3435 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3436                         struct rte_eth_syn_filter *filter)
3437 {
3438         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3439         uint32_t synqf, rfctl;
3440
3441         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3442         if (synqf & E1000_SYN_FILTER_ENABLE) {
3443                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3444                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3445                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3446                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3447                 return 0;
3448         }
3449
3450         return -ENOENT;
3451 }
3452
3453 static int
3454 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3455                         enum rte_filter_op filter_op,
3456                         void *arg)
3457 {
3458         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3459         int ret;
3460
3461         MAC_TYPE_FILTER_SUP(hw->mac.type);
3462
3463         if (filter_op == RTE_ETH_FILTER_NOP)
3464                 return 0;
3465
3466         if (arg == NULL) {
3467                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3468                             filter_op);
3469                 return -EINVAL;
3470         }
3471
3472         switch (filter_op) {
3473         case RTE_ETH_FILTER_ADD:
3474                 ret = eth_igb_syn_filter_set(dev,
3475                                 (struct rte_eth_syn_filter *)arg,
3476                                 TRUE);
3477                 break;
3478         case RTE_ETH_FILTER_DELETE:
3479                 ret = eth_igb_syn_filter_set(dev,
3480                                 (struct rte_eth_syn_filter *)arg,
3481                                 FALSE);
3482                 break;
3483         case RTE_ETH_FILTER_GET:
3484                 ret = eth_igb_syn_filter_get(dev,
3485                                 (struct rte_eth_syn_filter *)arg);
3486                 break;
3487         default:
3488                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3489                 ret = -EINVAL;
3490                 break;
3491         }
3492
3493         return ret;
3494 }
3495
3496 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3497         if ((type) != e1000_82580 && (type) != e1000_i350)\
3498                 return -ENOSYS; \
3499 } while (0)
3500
3501 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3502 static inline int
3503 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3504                         struct e1000_2tuple_filter_info *filter_info)
3505 {
3506         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3507                 return -EINVAL;
3508         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3509                 return -EINVAL;  /* filter index is out of range. */
3510         if (filter->tcp_flags > TCP_FLAG_ALL)
3511                 return -EINVAL;  /* flags is invalid. */
3512
3513         switch (filter->dst_port_mask) {
3514         case UINT16_MAX:
3515                 filter_info->dst_port_mask = 0;
3516                 filter_info->dst_port = filter->dst_port;
3517                 break;
3518         case 0:
3519                 filter_info->dst_port_mask = 1;
3520                 break;
3521         default:
3522                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3523                 return -EINVAL;
3524         }
3525
3526         switch (filter->proto_mask) {
3527         case UINT8_MAX:
3528                 filter_info->proto_mask = 0;
3529                 filter_info->proto = filter->proto;
3530                 break;
3531         case 0:
3532                 filter_info->proto_mask = 1;
3533                 break;
3534         default:
3535                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3536                 return -EINVAL;
3537         }
3538
3539         filter_info->priority = (uint8_t)filter->priority;
3540         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3541                 filter_info->tcp_flags = filter->tcp_flags;
3542         else
3543                 filter_info->tcp_flags = 0;
3544
3545         return 0;
3546 }
3547
3548 static inline struct e1000_2tuple_filter *
3549 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3550                         struct e1000_2tuple_filter_info *key)
3551 {
3552         struct e1000_2tuple_filter *it;
3553
3554         TAILQ_FOREACH(it, filter_list, entries) {
3555                 if (memcmp(key, &it->filter_info,
3556                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3557                         return it;
3558                 }
3559         }
3560         return NULL;
3561 }
3562
3563 /*
3564  * igb_add_2tuple_filter - add a 2tuple filter
3565  *
3566  * @param
3567  * dev: Pointer to struct rte_eth_dev.
3568  * ntuple_filter: ponter to the filter that will be added.
3569  *
3570  * @return
3571  *    - On success, zero.
3572  *    - On failure, a negative value.
3573  */
3574 static int
3575 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3576                         struct rte_eth_ntuple_filter *ntuple_filter)
3577 {
3578         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3579         struct e1000_filter_info *filter_info =
3580                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3581         struct e1000_2tuple_filter *filter;
3582         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3583         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3584         int i, ret;
3585
3586         filter = rte_zmalloc("e1000_2tuple_filter",
3587                         sizeof(struct e1000_2tuple_filter), 0);
3588         if (filter == NULL)
3589                 return -ENOMEM;
3590
3591         ret = ntuple_filter_to_2tuple(ntuple_filter,
3592                                       &filter->filter_info);
3593         if (ret < 0) {
3594                 rte_free(filter);
3595                 return ret;
3596         }
3597         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3598                                          &filter->filter_info) != NULL) {
3599                 PMD_DRV_LOG(ERR, "filter exists.");
3600                 rte_free(filter);
3601                 return -EEXIST;
3602         }
3603         filter->queue = ntuple_filter->queue;
3604
3605         /*
3606          * look for an unused 2tuple filter index,
3607          * and insert the filter to list.
3608          */
3609         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3610                 if (!(filter_info->twotuple_mask & (1 << i))) {
3611                         filter_info->twotuple_mask |= 1 << i;
3612                         filter->index = i;
3613                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3614                                           filter,
3615                                           entries);
3616                         break;
3617                 }
3618         }
3619         if (i >= E1000_MAX_TTQF_FILTERS) {
3620                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3621                 rte_free(filter);
3622                 return -ENOSYS;
3623         }
3624
3625         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3626         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3627                 imir |= E1000_IMIR_PORT_BP;
3628         else
3629                 imir &= ~E1000_IMIR_PORT_BP;
3630
3631         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3632
3633         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3634         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3635         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3636         if (filter->filter_info.proto_mask == 0)
3637                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3638
3639         /* tcp flags bits setting. */
3640         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3641                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3642                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3643                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3644                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3645                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3646                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3647                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3648                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3649                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3650                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3651                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3652                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3653         } else
3654                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3655         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3656         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3657         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3658         return 0;
3659 }
3660
3661 /*
3662  * igb_remove_2tuple_filter - remove a 2tuple filter
3663  *
3664  * @param
3665  * dev: Pointer to struct rte_eth_dev.
3666  * ntuple_filter: ponter to the filter that will be removed.
3667  *
3668  * @return
3669  *    - On success, zero.
3670  *    - On failure, a negative value.
3671  */
3672 static int
3673 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3674                         struct rte_eth_ntuple_filter *ntuple_filter)
3675 {
3676         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3677         struct e1000_filter_info *filter_info =
3678                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3679         struct e1000_2tuple_filter_info filter_2tuple;
3680         struct e1000_2tuple_filter *filter;
3681         int ret;
3682
3683         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3684         ret = ntuple_filter_to_2tuple(ntuple_filter,
3685                                       &filter_2tuple);
3686         if (ret < 0)
3687                 return ret;
3688
3689         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3690                                          &filter_2tuple);
3691         if (filter == NULL) {
3692                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3693                 return -ENOENT;
3694         }
3695
3696         filter_info->twotuple_mask &= ~(1 << filter->index);
3697         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3698         rte_free(filter);
3699
3700         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3701         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3702         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3703         return 0;
3704 }
3705
3706 static inline struct e1000_flex_filter *
3707 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3708                         struct e1000_flex_filter_info *key)
3709 {
3710         struct e1000_flex_filter *it;
3711
3712         TAILQ_FOREACH(it, filter_list, entries) {
3713                 if (memcmp(key, &it->filter_info,
3714                         sizeof(struct e1000_flex_filter_info)) == 0)
3715                         return it;
3716         }
3717
3718         return NULL;
3719 }
3720
3721 static int
3722 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3723                         struct rte_eth_flex_filter *filter,
3724                         bool add)
3725 {
3726         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3727         struct e1000_filter_info *filter_info =
3728                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3729         struct e1000_flex_filter *flex_filter, *it;
3730         uint32_t wufc, queueing, mask;
3731         uint32_t reg_off;
3732         uint8_t shift, i, j = 0;
3733
3734         flex_filter = rte_zmalloc("e1000_flex_filter",
3735                         sizeof(struct e1000_flex_filter), 0);
3736         if (flex_filter == NULL)
3737                 return -ENOMEM;
3738
3739         flex_filter->filter_info.len = filter->len;
3740         flex_filter->filter_info.priority = filter->priority;
3741         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3742         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3743                 mask = 0;
3744                 /* reverse bits in flex filter's mask*/
3745                 for (shift = 0; shift < CHAR_BIT; shift++) {
3746                         if (filter->mask[i] & (0x01 << shift))
3747                                 mask |= (0x80 >> shift);
3748                 }
3749                 flex_filter->filter_info.mask[i] = mask;
3750         }
3751
3752         wufc = E1000_READ_REG(hw, E1000_WUFC);
3753         if (flex_filter->index < E1000_MAX_FHFT)
3754                 reg_off = E1000_FHFT(flex_filter->index);
3755         else
3756                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3757
3758         if (add) {
3759                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3760                                 &flex_filter->filter_info) != NULL) {
3761                         PMD_DRV_LOG(ERR, "filter exists.");
3762                         rte_free(flex_filter);
3763                         return -EEXIST;
3764                 }
3765                 flex_filter->queue = filter->queue;
3766                 /*
3767                  * look for an unused flex filter index
3768                  * and insert the filter into the list.
3769                  */
3770                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3771                         if (!(filter_info->flex_mask & (1 << i))) {
3772                                 filter_info->flex_mask |= 1 << i;
3773                                 flex_filter->index = i;
3774                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3775                                         flex_filter,
3776                                         entries);
3777                                 break;
3778                         }
3779                 }
3780                 if (i >= E1000_MAX_FLEX_FILTERS) {
3781                         PMD_DRV_LOG(ERR, "flex filters are full.");
3782                         rte_free(flex_filter);
3783                         return -ENOSYS;
3784                 }
3785
3786                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3787                                 (E1000_WUFC_FLX0 << flex_filter->index));
3788                 queueing = filter->len |
3789                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3790                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3791                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3792                                 queueing);
3793                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3794                         E1000_WRITE_REG(hw, reg_off,
3795                                         flex_filter->filter_info.dwords[j]);
3796                         reg_off += sizeof(uint32_t);
3797                         E1000_WRITE_REG(hw, reg_off,
3798                                         flex_filter->filter_info.dwords[++j]);
3799                         reg_off += sizeof(uint32_t);
3800                         E1000_WRITE_REG(hw, reg_off,
3801                                 (uint32_t)flex_filter->filter_info.mask[i]);
3802                         reg_off += sizeof(uint32_t) * 2;
3803                         ++j;
3804                 }
3805         } else {
3806                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3807                                 &flex_filter->filter_info);
3808                 if (it == NULL) {
3809                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3810                         rte_free(flex_filter);
3811                         return -ENOENT;
3812                 }
3813
3814                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3815                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3816                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3817                         (~(E1000_WUFC_FLX0 << it->index)));
3818
3819                 filter_info->flex_mask &= ~(1 << it->index);
3820                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3821                 rte_free(it);
3822                 rte_free(flex_filter);
3823         }
3824
3825         return 0;
3826 }
3827
3828 static int
3829 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3830                         struct rte_eth_flex_filter *filter)
3831 {
3832         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3833         struct e1000_filter_info *filter_info =
3834                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3835         struct e1000_flex_filter flex_filter, *it;
3836         uint32_t wufc, queueing, wufc_en = 0;
3837
3838         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3839         flex_filter.filter_info.len = filter->len;
3840         flex_filter.filter_info.priority = filter->priority;
3841         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3842         memcpy(flex_filter.filter_info.mask, filter->mask,
3843                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3844
3845         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3846                                 &flex_filter.filter_info);
3847         if (it == NULL) {
3848                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3849                 return -ENOENT;
3850         }
3851
3852         wufc = E1000_READ_REG(hw, E1000_WUFC);
3853         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3854
3855         if ((wufc & wufc_en) == wufc_en) {
3856                 uint32_t reg_off = 0;
3857                 if (it->index < E1000_MAX_FHFT)
3858                         reg_off = E1000_FHFT(it->index);
3859                 else
3860                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3861
3862                 queueing = E1000_READ_REG(hw,
3863                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3864                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3865                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3866                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3867                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3868                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3869                 return 0;
3870         }
3871         return -ENOENT;
3872 }
3873
3874 static int
3875 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3876                         enum rte_filter_op filter_op,
3877                         void *arg)
3878 {
3879         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3880         struct rte_eth_flex_filter *filter;
3881         int ret = 0;
3882
3883         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3884
3885         if (filter_op == RTE_ETH_FILTER_NOP)
3886                 return ret;
3887
3888         if (arg == NULL) {
3889                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3890                             filter_op);
3891                 return -EINVAL;
3892         }
3893
3894         filter = (struct rte_eth_flex_filter *)arg;
3895         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3896             || filter->len % sizeof(uint64_t) != 0) {
3897                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3898                 return -EINVAL;
3899         }
3900         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3901                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3902                 return -EINVAL;
3903         }
3904
3905         switch (filter_op) {
3906         case RTE_ETH_FILTER_ADD:
3907                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3908                 break;
3909         case RTE_ETH_FILTER_DELETE:
3910                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3911                 break;
3912         case RTE_ETH_FILTER_GET:
3913                 ret = eth_igb_get_flex_filter(dev, filter);
3914                 break;
3915         default:
3916                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3917                 ret = -EINVAL;
3918                 break;
3919         }
3920
3921         return ret;
3922 }
3923
3924 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3925 static inline int
3926 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3927                         struct e1000_5tuple_filter_info *filter_info)
3928 {
3929         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3930                 return -EINVAL;
3931         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3932                 return -EINVAL;  /* filter index is out of range. */
3933         if (filter->tcp_flags > TCP_FLAG_ALL)
3934                 return -EINVAL;  /* flags is invalid. */
3935
3936         switch (filter->dst_ip_mask) {
3937         case UINT32_MAX:
3938                 filter_info->dst_ip_mask = 0;
3939                 filter_info->dst_ip = filter->dst_ip;
3940                 break;
3941         case 0:
3942                 filter_info->dst_ip_mask = 1;
3943                 break;
3944         default:
3945                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3946                 return -EINVAL;
3947         }
3948
3949         switch (filter->src_ip_mask) {
3950         case UINT32_MAX:
3951                 filter_info->src_ip_mask = 0;
3952                 filter_info->src_ip = filter->src_ip;
3953                 break;
3954         case 0:
3955                 filter_info->src_ip_mask = 1;
3956                 break;
3957         default:
3958                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3959                 return -EINVAL;
3960         }
3961
3962         switch (filter->dst_port_mask) {
3963         case UINT16_MAX:
3964                 filter_info->dst_port_mask = 0;
3965                 filter_info->dst_port = filter->dst_port;
3966                 break;
3967         case 0:
3968                 filter_info->dst_port_mask = 1;
3969                 break;
3970         default:
3971                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3972                 return -EINVAL;
3973         }
3974
3975         switch (filter->src_port_mask) {
3976         case UINT16_MAX:
3977                 filter_info->src_port_mask = 0;
3978                 filter_info->src_port = filter->src_port;
3979                 break;
3980         case 0:
3981                 filter_info->src_port_mask = 1;
3982                 break;
3983         default:
3984                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3985                 return -EINVAL;
3986         }
3987
3988         switch (filter->proto_mask) {
3989         case UINT8_MAX:
3990                 filter_info->proto_mask = 0;
3991                 filter_info->proto = filter->proto;
3992                 break;
3993         case 0:
3994                 filter_info->proto_mask = 1;
3995                 break;
3996         default:
3997                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3998                 return -EINVAL;
3999         }
4000
4001         filter_info->priority = (uint8_t)filter->priority;
4002         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4003                 filter_info->tcp_flags = filter->tcp_flags;
4004         else
4005                 filter_info->tcp_flags = 0;
4006
4007         return 0;
4008 }
4009
4010 static inline struct e1000_5tuple_filter *
4011 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4012                         struct e1000_5tuple_filter_info *key)
4013 {
4014         struct e1000_5tuple_filter *it;
4015
4016         TAILQ_FOREACH(it, filter_list, entries) {
4017                 if (memcmp(key, &it->filter_info,
4018                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4019                         return it;
4020                 }
4021         }
4022         return NULL;
4023 }
4024
4025 /*
4026  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4027  *
4028  * @param
4029  * dev: Pointer to struct rte_eth_dev.
4030  * ntuple_filter: ponter to the filter that will be added.
4031  *
4032  * @return
4033  *    - On success, zero.
4034  *    - On failure, a negative value.
4035  */
4036 static int
4037 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4038                         struct rte_eth_ntuple_filter *ntuple_filter)
4039 {
4040         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4041         struct e1000_filter_info *filter_info =
4042                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4043         struct e1000_5tuple_filter *filter;
4044         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4045         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4046         uint8_t i;
4047         int ret;
4048
4049         filter = rte_zmalloc("e1000_5tuple_filter",
4050                         sizeof(struct e1000_5tuple_filter), 0);
4051         if (filter == NULL)
4052                 return -ENOMEM;
4053
4054         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4055                                             &filter->filter_info);
4056         if (ret < 0) {
4057                 rte_free(filter);
4058                 return ret;
4059         }
4060
4061         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4062                                          &filter->filter_info) != NULL) {
4063                 PMD_DRV_LOG(ERR, "filter exists.");
4064                 rte_free(filter);
4065                 return -EEXIST;
4066         }
4067         filter->queue = ntuple_filter->queue;
4068
4069         /*
4070          * look for an unused 5tuple filter index,
4071          * and insert the filter to list.
4072          */
4073         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4074                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4075                         filter_info->fivetuple_mask |= 1 << i;
4076                         filter->index = i;
4077                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4078                                           filter,
4079                                           entries);
4080                         break;
4081                 }
4082         }
4083         if (i >= E1000_MAX_FTQF_FILTERS) {
4084                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4085                 rte_free(filter);
4086                 return -ENOSYS;
4087         }
4088
4089         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4090         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4091                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4092         if (filter->filter_info.dst_ip_mask == 0)
4093                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4094         if (filter->filter_info.src_port_mask == 0)
4095                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4096         if (filter->filter_info.proto_mask == 0)
4097                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4098         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4099                 E1000_FTQF_QUEUE_MASK;
4100         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4101         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4102         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4103         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4104
4105         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4106         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4107
4108         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4109         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4110                 imir |= E1000_IMIR_PORT_BP;
4111         else
4112                 imir &= ~E1000_IMIR_PORT_BP;
4113         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4114
4115         /* tcp flags bits setting. */
4116         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4117                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4118                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4119                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4120                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4121                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4122                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4123                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4124                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4125                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4126                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4127                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4128                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4129         } else
4130                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4131         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4132         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4133         return 0;
4134 }
4135
4136 /*
4137  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4138  *
4139  * @param
4140  * dev: Pointer to struct rte_eth_dev.
4141  * ntuple_filter: ponter to the filter that will be removed.
4142  *
4143  * @return
4144  *    - On success, zero.
4145  *    - On failure, a negative value.
4146  */
4147 static int
4148 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4149                                 struct rte_eth_ntuple_filter *ntuple_filter)
4150 {
4151         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4152         struct e1000_filter_info *filter_info =
4153                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4154         struct e1000_5tuple_filter_info filter_5tuple;
4155         struct e1000_5tuple_filter *filter;
4156         int ret;
4157
4158         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4159         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4160                                             &filter_5tuple);
4161         if (ret < 0)
4162                 return ret;
4163
4164         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4165                                          &filter_5tuple);
4166         if (filter == NULL) {
4167                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4168                 return -ENOENT;
4169         }
4170
4171         filter_info->fivetuple_mask &= ~(1 << filter->index);
4172         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4173         rte_free(filter);
4174
4175         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4176                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4177         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4178         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4179         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4180         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4181         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4182         return 0;
4183 }
4184
4185 static int
4186 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4187 {
4188         uint32_t rctl;
4189         struct e1000_hw *hw;
4190         struct rte_eth_dev_info dev_info;
4191         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4192                                      VLAN_TAG_SIZE);
4193
4194         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4195
4196 #ifdef RTE_LIBRTE_82571_SUPPORT
4197         /* XXX: not bigger than max_rx_pktlen */
4198         if (hw->mac.type == e1000_82571)
4199                 return -ENOTSUP;
4200 #endif
4201         eth_igb_infos_get(dev, &dev_info);
4202
4203         /* check that mtu is within the allowed range */
4204         if ((mtu < ETHER_MIN_MTU) ||
4205             (frame_size > dev_info.max_rx_pktlen))
4206                 return -EINVAL;
4207
4208         /* refuse mtu that requires the support of scattered packets when this
4209          * feature has not been enabled before. */
4210         if (!dev->data->scattered_rx &&
4211             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4212                 return -EINVAL;
4213
4214         rctl = E1000_READ_REG(hw, E1000_RCTL);
4215
4216         /* switch to jumbo mode if needed */
4217         if (frame_size > ETHER_MAX_LEN) {
4218                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4219                 rctl |= E1000_RCTL_LPE;
4220         } else {
4221                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4222                 rctl &= ~E1000_RCTL_LPE;
4223         }
4224         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4225
4226         /* update max frame size */
4227         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4228
4229         E1000_WRITE_REG(hw, E1000_RLPML,
4230                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4231
4232         return 0;
4233 }
4234
4235 /*
4236  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4237  *
4238  * @param
4239  * dev: Pointer to struct rte_eth_dev.
4240  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4241  * add: if true, add filter, if false, remove filter
4242  *
4243  * @return
4244  *    - On success, zero.
4245  *    - On failure, a negative value.
4246  */
4247 static int
4248 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4249                         struct rte_eth_ntuple_filter *ntuple_filter,
4250                         bool add)
4251 {
4252         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4253         int ret;
4254
4255         switch (ntuple_filter->flags) {
4256         case RTE_5TUPLE_FLAGS:
4257         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4258                 if (hw->mac.type != e1000_82576)
4259                         return -ENOTSUP;
4260                 if (add)
4261                         ret = igb_add_5tuple_filter_82576(dev,
4262                                                           ntuple_filter);
4263                 else
4264                         ret = igb_remove_5tuple_filter_82576(dev,
4265                                                              ntuple_filter);
4266                 break;
4267         case RTE_2TUPLE_FLAGS:
4268         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4269                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4270                         return -ENOTSUP;
4271                 if (add)
4272                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4273                 else
4274                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4275                 break;
4276         default:
4277                 ret = -EINVAL;
4278                 break;
4279         }
4280
4281         return ret;
4282 }
4283
4284 /*
4285  * igb_get_ntuple_filter - get a ntuple filter
4286  *
4287  * @param
4288  * dev: Pointer to struct rte_eth_dev.
4289  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4290  *
4291  * @return
4292  *    - On success, zero.
4293  *    - On failure, a negative value.
4294  */
4295 static int
4296 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4297                         struct rte_eth_ntuple_filter *ntuple_filter)
4298 {
4299         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4300         struct e1000_filter_info *filter_info =
4301                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4302         struct e1000_5tuple_filter_info filter_5tuple;
4303         struct e1000_2tuple_filter_info filter_2tuple;
4304         struct e1000_5tuple_filter *p_5tuple_filter;
4305         struct e1000_2tuple_filter *p_2tuple_filter;
4306         int ret;
4307
4308         switch (ntuple_filter->flags) {
4309         case RTE_5TUPLE_FLAGS:
4310         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4311                 if (hw->mac.type != e1000_82576)
4312                         return -ENOTSUP;
4313                 memset(&filter_5tuple,
4314                         0,
4315                         sizeof(struct e1000_5tuple_filter_info));
4316                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4317                                                     &filter_5tuple);
4318                 if (ret < 0)
4319                         return ret;
4320                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4321                                         &filter_info->fivetuple_list,
4322                                         &filter_5tuple);
4323                 if (p_5tuple_filter == NULL) {
4324                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4325                         return -ENOENT;
4326                 }
4327                 ntuple_filter->queue = p_5tuple_filter->queue;
4328                 break;
4329         case RTE_2TUPLE_FLAGS:
4330         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4331                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4332                         return -ENOTSUP;
4333                 memset(&filter_2tuple,
4334                         0,
4335                         sizeof(struct e1000_2tuple_filter_info));
4336                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4337                 if (ret < 0)
4338                         return ret;
4339                 p_2tuple_filter = igb_2tuple_filter_lookup(
4340                                         &filter_info->twotuple_list,
4341                                         &filter_2tuple);
4342                 if (p_2tuple_filter == NULL) {
4343                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4344                         return -ENOENT;
4345                 }
4346                 ntuple_filter->queue = p_2tuple_filter->queue;
4347                 break;
4348         default:
4349                 ret = -EINVAL;
4350                 break;
4351         }
4352
4353         return 0;
4354 }
4355
4356 /*
4357  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4358  * @dev: pointer to rte_eth_dev structure
4359  * @filter_op:operation will be taken.
4360  * @arg: a pointer to specific structure corresponding to the filter_op
4361  */
4362 static int
4363 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4364                                 enum rte_filter_op filter_op,
4365                                 void *arg)
4366 {
4367         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4368         int ret;
4369
4370         MAC_TYPE_FILTER_SUP(hw->mac.type);
4371
4372         if (filter_op == RTE_ETH_FILTER_NOP)
4373                 return 0;
4374
4375         if (arg == NULL) {
4376                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4377                             filter_op);
4378                 return -EINVAL;
4379         }
4380
4381         switch (filter_op) {
4382         case RTE_ETH_FILTER_ADD:
4383                 ret = igb_add_del_ntuple_filter(dev,
4384                         (struct rte_eth_ntuple_filter *)arg,
4385                         TRUE);
4386                 break;
4387         case RTE_ETH_FILTER_DELETE:
4388                 ret = igb_add_del_ntuple_filter(dev,
4389                         (struct rte_eth_ntuple_filter *)arg,
4390                         FALSE);
4391                 break;
4392         case RTE_ETH_FILTER_GET:
4393                 ret = igb_get_ntuple_filter(dev,
4394                         (struct rte_eth_ntuple_filter *)arg);
4395                 break;
4396         default:
4397                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4398                 ret = -EINVAL;
4399                 break;
4400         }
4401         return ret;
4402 }
4403
4404 static inline int
4405 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4406                         uint16_t ethertype)
4407 {
4408         int i;
4409
4410         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4411                 if (filter_info->ethertype_filters[i] == ethertype &&
4412                     (filter_info->ethertype_mask & (1 << i)))
4413                         return i;
4414         }
4415         return -1;
4416 }
4417
4418 static inline int
4419 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4420                         uint16_t ethertype)
4421 {
4422         int i;
4423
4424         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4425                 if (!(filter_info->ethertype_mask & (1 << i))) {
4426                         filter_info->ethertype_mask |= 1 << i;
4427                         filter_info->ethertype_filters[i] = ethertype;
4428                         return i;
4429                 }
4430         }
4431         return -1;
4432 }
4433
4434 static inline int
4435 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4436                         uint8_t idx)
4437 {
4438         if (idx >= E1000_MAX_ETQF_FILTERS)
4439                 return -1;
4440         filter_info->ethertype_mask &= ~(1 << idx);
4441         filter_info->ethertype_filters[idx] = 0;
4442         return idx;
4443 }
4444
4445
4446 static int
4447 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4448                         struct rte_eth_ethertype_filter *filter,
4449                         bool add)
4450 {
4451         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4452         struct e1000_filter_info *filter_info =
4453                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4454         uint32_t etqf = 0;
4455         int ret;
4456
4457         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4458                 filter->ether_type == ETHER_TYPE_IPv6) {
4459                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4460                         " ethertype filter.", filter->ether_type);
4461                 return -EINVAL;
4462         }
4463
4464         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4465                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4466                 return -EINVAL;
4467         }
4468         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4469                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4470                 return -EINVAL;
4471         }
4472
4473         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4474         if (ret >= 0 && add) {
4475                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4476                             filter->ether_type);
4477                 return -EEXIST;
4478         }
4479         if (ret < 0 && !add) {
4480                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4481                             filter->ether_type);
4482                 return -ENOENT;
4483         }
4484
4485         if (add) {
4486                 ret = igb_ethertype_filter_insert(filter_info,
4487                         filter->ether_type);
4488                 if (ret < 0) {
4489                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4490                         return -ENOSYS;
4491                 }
4492
4493                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4494                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4495                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4496         } else {
4497                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4498                 if (ret < 0)
4499                         return -ENOSYS;
4500         }
4501         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4502         E1000_WRITE_FLUSH(hw);
4503
4504         return 0;
4505 }
4506
4507 static int
4508 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4509                         struct rte_eth_ethertype_filter *filter)
4510 {
4511         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4512         struct e1000_filter_info *filter_info =
4513                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4514         uint32_t etqf;
4515         int ret;
4516
4517         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4518         if (ret < 0) {
4519                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4520                             filter->ether_type);
4521                 return -ENOENT;
4522         }
4523
4524         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4525         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4526                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4527                 filter->flags = 0;
4528                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4529                                 E1000_ETQF_QUEUE_SHIFT;
4530                 return 0;
4531         }
4532
4533         return -ENOENT;
4534 }
4535
4536 /*
4537  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4538  * @dev: pointer to rte_eth_dev structure
4539  * @filter_op:operation will be taken.
4540  * @arg: a pointer to specific structure corresponding to the filter_op
4541  */
4542 static int
4543 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4544                                 enum rte_filter_op filter_op,
4545                                 void *arg)
4546 {
4547         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4548         int ret;
4549
4550         MAC_TYPE_FILTER_SUP(hw->mac.type);
4551
4552         if (filter_op == RTE_ETH_FILTER_NOP)
4553                 return 0;
4554
4555         if (arg == NULL) {
4556                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4557                             filter_op);
4558                 return -EINVAL;
4559         }
4560
4561         switch (filter_op) {
4562         case RTE_ETH_FILTER_ADD:
4563                 ret = igb_add_del_ethertype_filter(dev,
4564                         (struct rte_eth_ethertype_filter *)arg,
4565                         TRUE);
4566                 break;
4567         case RTE_ETH_FILTER_DELETE:
4568                 ret = igb_add_del_ethertype_filter(dev,
4569                         (struct rte_eth_ethertype_filter *)arg,
4570                         FALSE);
4571                 break;
4572         case RTE_ETH_FILTER_GET:
4573                 ret = igb_get_ethertype_filter(dev,
4574                         (struct rte_eth_ethertype_filter *)arg);
4575                 break;
4576         default:
4577                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4578                 ret = -EINVAL;
4579                 break;
4580         }
4581         return ret;
4582 }
4583
4584 static int
4585 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4586                      enum rte_filter_type filter_type,
4587                      enum rte_filter_op filter_op,
4588                      void *arg)
4589 {
4590         int ret = -EINVAL;
4591
4592         switch (filter_type) {
4593         case RTE_ETH_FILTER_NTUPLE:
4594                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4595                 break;
4596         case RTE_ETH_FILTER_ETHERTYPE:
4597                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4598                 break;
4599         case RTE_ETH_FILTER_SYN:
4600                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4601                 break;
4602         case RTE_ETH_FILTER_FLEXIBLE:
4603                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4604                 break;
4605         default:
4606                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4607                                                         filter_type);
4608                 break;
4609         }
4610
4611         return ret;
4612 }
4613
4614 static int
4615 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4616                          struct ether_addr *mc_addr_set,
4617                          uint32_t nb_mc_addr)
4618 {
4619         struct e1000_hw *hw;
4620
4621         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4622         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4623         return 0;
4624 }
4625
4626 static uint64_t
4627 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4628 {
4629         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4630         uint64_t systime_cycles;
4631
4632         switch (hw->mac.type) {
4633         case e1000_i210:
4634         case e1000_i211:
4635                 /*
4636                  * Need to read System Time Residue Register to be able
4637                  * to read the other two registers.
4638                  */
4639                 E1000_READ_REG(hw, E1000_SYSTIMR);
4640                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4641                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4642                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4643                                 * NSEC_PER_SEC;
4644                 break;
4645         case e1000_82580:
4646         case e1000_i350:
4647         case e1000_i354:
4648                 /*
4649                  * Need to read System Time Residue Register to be able
4650                  * to read the other two registers.
4651                  */
4652                 E1000_READ_REG(hw, E1000_SYSTIMR);
4653                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4654                 /* Only the 8 LSB are valid. */
4655                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4656                                 & 0xff) << 32;
4657                 break;
4658         default:
4659                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4660                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4661                                 << 32;
4662                 break;
4663         }
4664
4665         return systime_cycles;
4666 }
4667
4668 static uint64_t
4669 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4670 {
4671         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4672         uint64_t rx_tstamp_cycles;
4673
4674         switch (hw->mac.type) {
4675         case e1000_i210:
4676         case e1000_i211:
4677                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4678                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4679                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4680                                 * NSEC_PER_SEC;
4681                 break;
4682         case e1000_82580:
4683         case e1000_i350:
4684         case e1000_i354:
4685                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4686                 /* Only the 8 LSB are valid. */
4687                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4688                                 & 0xff) << 32;
4689                 break;
4690         default:
4691                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4692                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4693                                 << 32;
4694                 break;
4695         }
4696
4697         return rx_tstamp_cycles;
4698 }
4699
4700 static uint64_t
4701 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4702 {
4703         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4704         uint64_t tx_tstamp_cycles;
4705
4706         switch (hw->mac.type) {
4707         case e1000_i210:
4708         case e1000_i211:
4709                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4710                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4711                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4712                                 * NSEC_PER_SEC;
4713                 break;
4714         case e1000_82580:
4715         case e1000_i350:
4716         case e1000_i354:
4717                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4718                 /* Only the 8 LSB are valid. */
4719                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4720                                 & 0xff) << 32;
4721                 break;
4722         default:
4723                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4724                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4725                                 << 32;
4726                 break;
4727         }
4728
4729         return tx_tstamp_cycles;
4730 }
4731
4732 static void
4733 igb_start_timecounters(struct rte_eth_dev *dev)
4734 {
4735         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4736         struct e1000_adapter *adapter =
4737                 (struct e1000_adapter *)dev->data->dev_private;
4738         uint32_t incval = 1;
4739         uint32_t shift = 0;
4740         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4741
4742         switch (hw->mac.type) {
4743         case e1000_82580:
4744         case e1000_i350:
4745         case e1000_i354:
4746                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4747                 mask = (1ULL << 40) - 1;
4748                 /* fall-through */
4749         case e1000_i210:
4750         case e1000_i211:
4751                 /*
4752                  * Start incrementing the register
4753                  * used to timestamp PTP packets.
4754                  */
4755                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4756                 break;
4757         case e1000_82576:
4758                 incval = E1000_INCVALUE_82576;
4759                 shift = IGB_82576_TSYNC_SHIFT;
4760                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4761                                 E1000_INCPERIOD_82576 | incval);
4762                 break;
4763         default:
4764                 /* Not supported */
4765                 return;
4766         }
4767
4768         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4769         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4770         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4771
4772         adapter->systime_tc.cc_mask = mask;
4773         adapter->systime_tc.cc_shift = shift;
4774         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4775
4776         adapter->rx_tstamp_tc.cc_mask = mask;
4777         adapter->rx_tstamp_tc.cc_shift = shift;
4778         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4779
4780         adapter->tx_tstamp_tc.cc_mask = mask;
4781         adapter->tx_tstamp_tc.cc_shift = shift;
4782         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4783 }
4784
4785 static int
4786 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4787 {
4788         struct e1000_adapter *adapter =
4789                         (struct e1000_adapter *)dev->data->dev_private;
4790
4791         adapter->systime_tc.nsec += delta;
4792         adapter->rx_tstamp_tc.nsec += delta;
4793         adapter->tx_tstamp_tc.nsec += delta;
4794
4795         return 0;
4796 }
4797
4798 static int
4799 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4800 {
4801         uint64_t ns;
4802         struct e1000_adapter *adapter =
4803                         (struct e1000_adapter *)dev->data->dev_private;
4804
4805         ns = rte_timespec_to_ns(ts);
4806
4807         /* Set the timecounters to a new value. */
4808         adapter->systime_tc.nsec = ns;
4809         adapter->rx_tstamp_tc.nsec = ns;
4810         adapter->tx_tstamp_tc.nsec = ns;
4811
4812         return 0;
4813 }
4814
4815 static int
4816 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4817 {
4818         uint64_t ns, systime_cycles;
4819         struct e1000_adapter *adapter =
4820                         (struct e1000_adapter *)dev->data->dev_private;
4821
4822         systime_cycles = igb_read_systime_cyclecounter(dev);
4823         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4824         *ts = rte_ns_to_timespec(ns);
4825
4826         return 0;
4827 }
4828
4829 static int
4830 igb_timesync_enable(struct rte_eth_dev *dev)
4831 {
4832         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4833         uint32_t tsync_ctl;
4834         uint32_t tsauxc;
4835
4836         /* Stop the timesync system time. */
4837         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4838         /* Reset the timesync system time value. */
4839         switch (hw->mac.type) {
4840         case e1000_82580:
4841         case e1000_i350:
4842         case e1000_i354:
4843         case e1000_i210:
4844         case e1000_i211:
4845                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4846                 /* fall-through */
4847         case e1000_82576:
4848                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4849                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4850                 break;
4851         default:
4852                 /* Not supported. */
4853                 return -ENOTSUP;
4854         }
4855
4856         /* Enable system time for it isn't on by default. */
4857         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4858         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4859         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4860
4861         igb_start_timecounters(dev);
4862
4863         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4864         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4865                         (ETHER_TYPE_1588 |
4866                          E1000_ETQF_FILTER_ENABLE |
4867                          E1000_ETQF_1588));
4868
4869         /* Enable timestamping of received PTP packets. */
4870         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4871         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4872         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4873
4874         /* Enable Timestamping of transmitted PTP packets. */
4875         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4876         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4877         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4878
4879         return 0;
4880 }
4881
4882 static int
4883 igb_timesync_disable(struct rte_eth_dev *dev)
4884 {
4885         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4886         uint32_t tsync_ctl;
4887
4888         /* Disable timestamping of transmitted PTP packets. */
4889         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4890         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4891         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4892
4893         /* Disable timestamping of received PTP packets. */
4894         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4895         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4896         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4897
4898         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4899         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4900
4901         /* Stop incrementating the System Time registers. */
4902         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4903
4904         return 0;
4905 }
4906
4907 static int
4908 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4909                                struct timespec *timestamp,
4910                                uint32_t flags __rte_unused)
4911 {
4912         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4913         struct e1000_adapter *adapter =
4914                         (struct e1000_adapter *)dev->data->dev_private;
4915         uint32_t tsync_rxctl;
4916         uint64_t rx_tstamp_cycles;
4917         uint64_t ns;
4918
4919         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4920         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4921                 return -EINVAL;
4922
4923         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4924         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4925         *timestamp = rte_ns_to_timespec(ns);
4926
4927         return  0;
4928 }
4929
4930 static int
4931 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4932                                struct timespec *timestamp)
4933 {
4934         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4935         struct e1000_adapter *adapter =
4936                         (struct e1000_adapter *)dev->data->dev_private;
4937         uint32_t tsync_txctl;
4938         uint64_t tx_tstamp_cycles;
4939         uint64_t ns;
4940
4941         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4942         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4943                 return -EINVAL;
4944
4945         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4946         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4947         *timestamp = rte_ns_to_timespec(ns);
4948
4949         return  0;
4950 }
4951
4952 static int
4953 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4954 {
4955         int count = 0;
4956         int g_ind = 0;
4957         const struct reg_info *reg_group;
4958
4959         while ((reg_group = igb_regs[g_ind++]))
4960                 count += igb_reg_group_count(reg_group);
4961
4962         return count;
4963 }
4964
4965 static int
4966 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4967 {
4968         int count = 0;
4969         int g_ind = 0;
4970         const struct reg_info *reg_group;
4971
4972         while ((reg_group = igbvf_regs[g_ind++]))
4973                 count += igb_reg_group_count(reg_group);
4974
4975         return count;
4976 }
4977
4978 static int
4979 eth_igb_get_regs(struct rte_eth_dev *dev,
4980         struct rte_dev_reg_info *regs)
4981 {
4982         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4983         uint32_t *data = regs->data;
4984         int g_ind = 0;
4985         int count = 0;
4986         const struct reg_info *reg_group;
4987
4988         if (data == NULL) {
4989                 regs->length = eth_igb_get_reg_length(dev);
4990                 regs->width = sizeof(uint32_t);
4991                 return 0;
4992         }
4993
4994         /* Support only full register dump */
4995         if ((regs->length == 0) ||
4996             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4997                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4998                         hw->device_id;
4999                 while ((reg_group = igb_regs[g_ind++]))
5000                         count += igb_read_regs_group(dev, &data[count],
5001                                                         reg_group);
5002                 return 0;
5003         }
5004
5005         return -ENOTSUP;
5006 }
5007
5008 static int
5009 igbvf_get_regs(struct rte_eth_dev *dev,
5010         struct rte_dev_reg_info *regs)
5011 {
5012         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5013         uint32_t *data = regs->data;
5014         int g_ind = 0;
5015         int count = 0;
5016         const struct reg_info *reg_group;
5017
5018         if (data == NULL) {
5019                 regs->length = igbvf_get_reg_length(dev);
5020                 regs->width = sizeof(uint32_t);
5021                 return 0;
5022         }
5023
5024         /* Support only full register dump */
5025         if ((regs->length == 0) ||
5026             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5027                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5028                         hw->device_id;
5029                 while ((reg_group = igbvf_regs[g_ind++]))
5030                         count += igb_read_regs_group(dev, &data[count],
5031                                                         reg_group);
5032                 return 0;
5033         }
5034
5035         return -ENOTSUP;
5036 }
5037
5038 static int
5039 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5040 {
5041         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5042
5043         /* Return unit is byte count */
5044         return hw->nvm.word_size * 2;
5045 }
5046
5047 static int
5048 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5049         struct rte_dev_eeprom_info *in_eeprom)
5050 {
5051         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5052         struct e1000_nvm_info *nvm = &hw->nvm;
5053         uint16_t *data = in_eeprom->data;
5054         int first, length;
5055
5056         first = in_eeprom->offset >> 1;
5057         length = in_eeprom->length >> 1;
5058         if ((first >= hw->nvm.word_size) ||
5059             ((first + length) >= hw->nvm.word_size))
5060                 return -EINVAL;
5061
5062         in_eeprom->magic = hw->vendor_id |
5063                 ((uint32_t)hw->device_id << 16);
5064
5065         if ((nvm->ops.read) == NULL)
5066                 return -ENOTSUP;
5067
5068         return nvm->ops.read(hw, first, length, data);
5069 }
5070
5071 static int
5072 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5073         struct rte_dev_eeprom_info *in_eeprom)
5074 {
5075         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5076         struct e1000_nvm_info *nvm = &hw->nvm;
5077         uint16_t *data = in_eeprom->data;
5078         int first, length;
5079
5080         first = in_eeprom->offset >> 1;
5081         length = in_eeprom->length >> 1;
5082         if ((first >= hw->nvm.word_size) ||
5083             ((first + length) >= hw->nvm.word_size))
5084                 return -EINVAL;
5085
5086         in_eeprom->magic = (uint32_t)hw->vendor_id |
5087                 ((uint32_t)hw->device_id << 16);
5088
5089         if ((nvm->ops.write) == NULL)
5090                 return -ENOTSUP;
5091         return nvm->ops.write(hw,  first, length, data);
5092 }
5093
5094 static int
5095 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5096 {
5097         struct e1000_hw *hw =
5098                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5099         uint32_t mask = 1 << queue_id;
5100
5101         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5102         E1000_WRITE_FLUSH(hw);
5103
5104         return 0;
5105 }
5106
5107 static int
5108 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5109 {
5110         struct e1000_hw *hw =
5111                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5112         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5113         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5114         uint32_t mask = 1 << queue_id;
5115         uint32_t regval;
5116
5117         regval = E1000_READ_REG(hw, E1000_EIMS);
5118         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5119         E1000_WRITE_FLUSH(hw);
5120
5121         rte_intr_enable(intr_handle);
5122
5123         return 0;
5124 }
5125
5126 static void
5127 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5128                    uint8_t index, uint8_t offset)
5129 {
5130         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5131
5132         /* clear bits */
5133         val &= ~((uint32_t)0xFF << offset);
5134
5135         /* write vector and valid bit */
5136         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5137
5138         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5139 }
5140
5141 static void
5142 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5143                            uint8_t queue, uint8_t msix_vector)
5144 {
5145         uint32_t tmp = 0;
5146
5147         if (hw->mac.type == e1000_82575) {
5148                 if (direction == 0)
5149                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5150                 else if (direction == 1)
5151                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5152                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5153         } else if (hw->mac.type == e1000_82576) {
5154                 if ((direction == 0) || (direction == 1))
5155                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5156                                            ((queue & 0x8) << 1) +
5157                                            8 * direction);
5158         } else if ((hw->mac.type == e1000_82580) ||
5159                         (hw->mac.type == e1000_i350) ||
5160                         (hw->mac.type == e1000_i354) ||
5161                         (hw->mac.type == e1000_i210) ||
5162                         (hw->mac.type == e1000_i211)) {
5163                 if ((direction == 0) || (direction == 1))
5164                         eth_igb_write_ivar(hw, msix_vector,
5165                                            queue >> 1,
5166                                            ((queue & 0x1) << 4) +
5167                                            8 * direction);
5168         }
5169 }
5170
5171 /* Sets up the hardware to generate MSI-X interrupts properly
5172  * @hw
5173  *  board private structure
5174  */
5175 static void
5176 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5177 {
5178         int queue_id;
5179         uint32_t tmpval, regval, intr_mask;
5180         struct e1000_hw *hw =
5181                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5182         uint32_t vec = E1000_MISC_VEC_ID;
5183         uint32_t base = E1000_MISC_VEC_ID;
5184         uint32_t misc_shift = 0;
5185         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5186         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5187
5188         /* won't configure msix register if no mapping is done
5189          * between intr vector and event fd
5190          */
5191         if (!rte_intr_dp_is_en(intr_handle))
5192                 return;
5193
5194         if (rte_intr_allow_others(intr_handle)) {
5195                 vec = base = E1000_RX_VEC_START;
5196                 misc_shift = 1;
5197         }
5198
5199         /* set interrupt vector for other causes */
5200         if (hw->mac.type == e1000_82575) {
5201                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5202                 /* enable MSI-X PBA support */
5203                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5204
5205                 /* Auto-Mask interrupts upon ICR read */
5206                 tmpval |= E1000_CTRL_EXT_EIAME;
5207                 tmpval |= E1000_CTRL_EXT_IRCA;
5208
5209                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5210
5211                 /* enable msix_other interrupt */
5212                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5213                 regval = E1000_READ_REG(hw, E1000_EIAC);
5214                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5215                 regval = E1000_READ_REG(hw, E1000_EIAM);
5216                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5217         } else if ((hw->mac.type == e1000_82576) ||
5218                         (hw->mac.type == e1000_82580) ||
5219                         (hw->mac.type == e1000_i350) ||
5220                         (hw->mac.type == e1000_i354) ||
5221                         (hw->mac.type == e1000_i210) ||
5222                         (hw->mac.type == e1000_i211)) {
5223                 /* turn on MSI-X capability first */
5224                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5225                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5226                                         E1000_GPIE_NSICR);
5227                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5228                         misc_shift;
5229                 regval = E1000_READ_REG(hw, E1000_EIAC);
5230                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5231
5232                 /* enable msix_other interrupt */
5233                 regval = E1000_READ_REG(hw, E1000_EIMS);
5234                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5235                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5236                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5237         }
5238
5239         /* use EIAM to auto-mask when MSI-X interrupt
5240          * is asserted, this saves a register write for every interrupt
5241          */
5242         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5243                 misc_shift;
5244         regval = E1000_READ_REG(hw, E1000_EIAM);
5245         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5246
5247         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5248                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5249                 intr_handle->intr_vec[queue_id] = vec;
5250                 if (vec < base + intr_handle->nb_efd - 1)
5251                         vec++;
5252         }
5253
5254         E1000_WRITE_FLUSH(hw);
5255 }
5256
5257 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd.pci_drv);
5258 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5259 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio");
5260 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd.pci_drv);
5261 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5262 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio");