drivers/net/fm10k/fm10k_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2013-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <rte_ethdev.h>
  35 #include <rte_ethdev_pci.h>
  36 #include <rte_malloc.h>
  37 #include <rte_memzone.h>
  38 #include <rte_string_fns.h>
  39 #include <rte_dev.h>
  40 #include <rte_spinlock.h>
  41 #include <rte_kvargs.h>
  42
  43 #include "fm10k.h"
  44 #include "base/fm10k_api.h"
  45
  46 /* Default delay to acquire mailbox lock */
  47 #define FM10K_MBXLOCK_DELAY_US 20
  48 #define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL
  49
  50 #define MAIN_VSI_POOL_NUMBER 0
  51
  52 /* Max try times to acquire switch status */
  53 #define MAX_QUERY_SWITCH_STATE_TIMES 10
  54 /* Wait interval to get switch status */
  55 #define WAIT_SWITCH_MSG_US    100000
  56 /* A period of quiescence for switch */
  57 #define FM10K_SWITCH_QUIESCE_US 10000
  58 /* Number of chars per uint32 type */
  59 #define CHARS_PER_UINT32 (sizeof(uint32_t))
  60 #define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)
  61
  62 /* default 1:1 map from queue ID to interrupt vector ID */
  63 #define Q2V(pci_dev, queue_id) ((pci_dev)->intr_handle.intr_vec[queue_id])
  64
  65 /* First 64 Logical ports for PF/VMDQ, second 64 for Flow director */
  66 #define MAX_LPORT_NUM    128
  67 #define GLORT_FD_Q_BASE  0x40
  68 #define GLORT_PF_MASK    0xFFC0
  69 #define GLORT_FD_MASK    GLORT_PF_MASK
  70 #define GLORT_FD_INDEX   GLORT_FD_Q_BASE
  71
  72 static void fm10k_close_mbx_service(struct fm10k_hw *hw);
  73 static void fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev);
  74 static void fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev);
  75 static void fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev);
  76 static void fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev);
  77 static inline int fm10k_glort_valid(struct fm10k_hw *hw);
  78 static int
  79 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
  80 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
  81         const u8 *mac, bool add, uint32_t pool);
  82 static void fm10k_tx_queue_release(void *queue);
  83 static void fm10k_rx_queue_release(void *queue);
  84 static void fm10k_set_rx_function(struct rte_eth_dev *dev);
  85 static void fm10k_set_tx_function(struct rte_eth_dev *dev);
  86 static int fm10k_check_ftag(struct rte_devargs *devargs);
  87
  88 struct fm10k_xstats_name_off {
  89         char name[RTE_ETH_XSTATS_NAME_SIZE];
  90         unsigned offset;
  91 };
  92
  93 struct fm10k_xstats_name_off fm10k_hw_stats_strings[] = {
  94         {"completion_timeout_count", offsetof(struct fm10k_hw_stats, timeout)},
  95         {"unsupported_requests_count", offsetof(struct fm10k_hw_stats, ur)},
  96         {"completer_abort_count", offsetof(struct fm10k_hw_stats, ca)},
  97         {"unsupported_message_count", offsetof(struct fm10k_hw_stats, um)},
  98         {"checksum_error_count", offsetof(struct fm10k_hw_stats, xec)},
  99         {"vlan_dropped", offsetof(struct fm10k_hw_stats, vlan_drop)},
 100         {"loopback_dropped", offsetof(struct fm10k_hw_stats, loopback_drop)},
 101         {"rx_mbuf_allocation_errors", offsetof(struct fm10k_hw_stats,
 102                 nodesc_drop)},
 103 };
 104
 105 #define FM10K_NB_HW_XSTATS (sizeof(fm10k_hw_stats_strings) / \
 106                 sizeof(fm10k_hw_stats_strings[0]))
 107
 108 struct fm10k_xstats_name_off fm10k_hw_stats_rx_q_strings[] = {
 109         {"packets", offsetof(struct fm10k_hw_stats_q, rx_packets)},
 110         {"bytes", offsetof(struct fm10k_hw_stats_q, rx_bytes)},
 111         {"dropped", offsetof(struct fm10k_hw_stats_q, rx_drops)},
 112 };
 113
 114 #define FM10K_NB_RX_Q_XSTATS (sizeof(fm10k_hw_stats_rx_q_strings) / \
 115                 sizeof(fm10k_hw_stats_rx_q_strings[0]))
 116
 117 struct fm10k_xstats_name_off fm10k_hw_stats_tx_q_strings[] = {
 118         {"packets", offsetof(struct fm10k_hw_stats_q, tx_packets)},
 119         {"bytes", offsetof(struct fm10k_hw_stats_q, tx_bytes)},
 120 };
 121
 122 #define FM10K_NB_TX_Q_XSTATS (sizeof(fm10k_hw_stats_tx_q_strings) / \
 123                 sizeof(fm10k_hw_stats_tx_q_strings[0]))
 124
 125 #define FM10K_NB_XSTATS (FM10K_NB_HW_XSTATS + FM10K_MAX_QUEUES_PF * \
 126                 (FM10K_NB_RX_Q_XSTATS + FM10K_NB_TX_Q_XSTATS))
 127 static int
 128 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 129
 130 static void
 131 fm10k_mbx_initlock(struct fm10k_hw *hw)
 132 {
 133         rte_spinlock_init(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 134 }
 135
 136 static void
 137 fm10k_mbx_lock(struct fm10k_hw *hw)
 138 {
 139         while (!rte_spinlock_trylock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back)))
 140                 rte_delay_us(FM10K_MBXLOCK_DELAY_US);
 141 }
 142
 143 static void
 144 fm10k_mbx_unlock(struct fm10k_hw *hw)
 145 {
 146         rte_spinlock_unlock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 147 }
 148
 149 /* Stubs needed for linkage when vPMD is disabled */
 150 int __attribute__((weak))
 151 fm10k_rx_vec_condition_check(__rte_unused struct rte_eth_dev *dev)
 152 {
 153         return -1;
 154 }
 155
 156 uint16_t __attribute__((weak))
 157 fm10k_recv_pkts_vec(
 158         __rte_unused void *rx_queue,
 159         __rte_unused struct rte_mbuf **rx_pkts,
 160         __rte_unused uint16_t nb_pkts)
 161 {
 162         return 0;
 163 }
 164
 165 uint16_t __attribute__((weak))
 166 fm10k_recv_scattered_pkts_vec(
 167                 __rte_unused void *rx_queue,
 168                 __rte_unused struct rte_mbuf **rx_pkts,
 169                 __rte_unused uint16_t nb_pkts)
 170 {
 171         return 0;
 172 }
 173
 174 int __attribute__((weak))
 175 fm10k_rxq_vec_setup(__rte_unused struct fm10k_rx_queue *rxq)
 176
 177 {
 178         return -1;
 179 }
 180
 181 void __attribute__((weak))
 182 fm10k_rx_queue_release_mbufs_vec(
 183                 __rte_unused struct fm10k_rx_queue *rxq)
 184 {
 185         return;
 186 }
 187
 188 void __attribute__((weak))
 189 fm10k_txq_vec_setup(__rte_unused struct fm10k_tx_queue *txq)
 190 {
 191         return;
 192 }
 193
 194 int __attribute__((weak))
 195 fm10k_tx_vec_condition_check(__rte_unused struct fm10k_tx_queue *txq)
 196 {
 197         return -1;
 198 }
 199
 200 uint16_t __attribute__((weak))
 201 fm10k_xmit_fixed_burst_vec(__rte_unused void *tx_queue,
 202                            __rte_unused struct rte_mbuf **tx_pkts,
 203                            __rte_unused uint16_t nb_pkts)
 204 {
 205         return 0;
 206 }
 207
 208 /*
 209  * reset queue to initial state, allocate software buffers used when starting
 210  * device.
 211  * return 0 on success
 212  * return -ENOMEM if buffers cannot be allocated
 213  * return -EINVAL if buffers do not satisfy alignment condition
 214  */
 215 static inline int
 216 rx_queue_reset(struct fm10k_rx_queue *q)
 217 {
 218         static const union fm10k_rx_desc zero = {{0} };
 219         uint64_t dma_addr;
 220         int i, diag;
 221         PMD_INIT_FUNC_TRACE();
 222
 223         diag = rte_mempool_get_bulk(q->mp, (void **)q->sw_ring, q->nb_desc);
 224         if (diag != 0)
 225                 return -ENOMEM;
 226
 227         for (i = 0; i < q->nb_desc; ++i) {
 228                 fm10k_pktmbuf_reset(q->sw_ring[i], q->port_id);
 229                 if (!fm10k_addr_alignment_valid(q->sw_ring[i])) {
 230                         rte_mempool_put_bulk(q->mp, (void **)q->sw_ring,
 231                                                 q->nb_desc);
 232                         return -EINVAL;
 233                 }
 234                 dma_addr = MBUF_DMA_ADDR_DEFAULT(q->sw_ring[i]);
 235                 q->hw_ring[i].q.pkt_addr = dma_addr;
 236                 q->hw_ring[i].q.hdr_addr = dma_addr;
 237         }
 238
 239         /* initialize extra software ring entries. Space for these extra
 240          * entries is always allocated.
 241          */
 242         memset(&q->fake_mbuf, 0x0, sizeof(q->fake_mbuf));
 243         for (i = 0; i < q->nb_fake_desc; ++i) {
 244                 q->sw_ring[q->nb_desc + i] = &q->fake_mbuf;
 245                 q->hw_ring[q->nb_desc + i] = zero;
 246         }
 247
 248         q->next_dd = 0;
 249         q->next_alloc = 0;
 250         q->next_trigger = q->alloc_thresh - 1;
 251         FM10K_PCI_REG_WRITE(q->tail_ptr, q->nb_desc - 1);
 252         q->rxrearm_start = 0;
 253         q->rxrearm_nb = 0;
 254
 255         return 0;
 256 }
 257
 258 /*
 259  * clean queue, descriptor rings, free software buffers used when stopping
 260  * device.
 261  */
 262 static inline void
 263 rx_queue_clean(struct fm10k_rx_queue *q)
 264 {
 265         union fm10k_rx_desc zero = {.q = {0, 0, 0, 0} };
 266         uint32_t i;
 267         PMD_INIT_FUNC_TRACE();
 268
 269         /* zero descriptor rings */
 270         for (i = 0; i < q->nb_desc; ++i)
 271                 q->hw_ring[i] = zero;
 272
 273         /* zero faked descriptors */
 274         for (i = 0; i < q->nb_fake_desc; ++i)
 275                 q->hw_ring[q->nb_desc + i] = zero;
 276
 277         /* vPMD driver has a different way of releasing mbufs. */
 278         if (q->rx_using_sse) {
 279                 fm10k_rx_queue_release_mbufs_vec(q);
 280                 return;
 281         }
 282
 283         /* free software buffers */
 284         for (i = 0; i < q->nb_desc; ++i) {
 285                 if (q->sw_ring[i]) {
 286                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 287                         q->sw_ring[i] = NULL;
 288                 }
 289         }
 290 }
 291
 292 /*
 293  * free all queue memory used when releasing the queue (i.e. configure)
 294  */
 295 static inline void
 296 rx_queue_free(struct fm10k_rx_queue *q)
 297 {
 298         PMD_INIT_FUNC_TRACE();
 299         if (q) {
 300                 PMD_INIT_LOG(DEBUG, "Freeing rx queue %p", q);
 301                 rx_queue_clean(q);
 302                 if (q->sw_ring) {
 303                         rte_free(q->sw_ring);
 304                         q->sw_ring = NULL;
 305                 }
 306                 rte_free(q);
 307                 q = NULL;
 308         }
 309 }
 310
 311 /*
 312  * disable RX queue, wait unitl HW finished necessary flush operation
 313  */
 314 static inline int
 315 rx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 316 {
 317         uint32_t reg, i;
 318
 319         reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 320         FM10K_WRITE_REG(hw, FM10K_RXQCTL(qnum),
 321                         reg & ~FM10K_RXQCTL_ENABLE);
 322
 323         /* Wait 100us at most */
 324         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 325                 rte_delay_us(1);
 326                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 327                 if (!(reg & FM10K_RXQCTL_ENABLE))
 328                         break;
 329         }
 330
 331         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 332                 return -1;
 333
 334         return 0;
 335 }
 336
 337 /*
 338  * reset queue to initial state, allocate software buffers used when starting
 339  * device
 340  */
 341 static inline void
 342 tx_queue_reset(struct fm10k_tx_queue *q)
 343 {
 344         PMD_INIT_FUNC_TRACE();
 345         q->last_free = 0;
 346         q->next_free = 0;
 347         q->nb_used = 0;
 348         q->nb_free = q->nb_desc - 1;
 349         fifo_reset(&q->rs_tracker, (q->nb_desc + 1) / q->rs_thresh);
 350         FM10K_PCI_REG_WRITE(q->tail_ptr, 0);
 351 }
 352
 353 /*
 354  * clean queue, descriptor rings, free software buffers used when stopping
 355  * device
 356  */
 357 static inline void
 358 tx_queue_clean(struct fm10k_tx_queue *q)
 359 {
 360         struct fm10k_tx_desc zero = {0, 0, 0, 0, 0, 0};
 361         uint32_t i;
 362         PMD_INIT_FUNC_TRACE();
 363
 364         /* zero descriptor rings */
 365         for (i = 0; i < q->nb_desc; ++i)
 366                 q->hw_ring[i] = zero;
 367
 368         /* free software buffers */
 369         for (i = 0; i < q->nb_desc; ++i) {
 370                 if (q->sw_ring[i]) {
 371                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 372                         q->sw_ring[i] = NULL;
 373                 }
 374         }
 375 }
 376
 377 /*
 378  * free all queue memory used when releasing the queue (i.e. configure)
 379  */
 380 static inline void
 381 tx_queue_free(struct fm10k_tx_queue *q)
 382 {
 383         PMD_INIT_FUNC_TRACE();
 384         if (q) {
 385                 PMD_INIT_LOG(DEBUG, "Freeing tx queue %p", q);
 386                 tx_queue_clean(q);
 387                 if (q->rs_tracker.list) {
 388                         rte_free(q->rs_tracker.list);
 389                         q->rs_tracker.list = NULL;
 390                 }
 391                 if (q->sw_ring) {
 392                         rte_free(q->sw_ring);
 393                         q->sw_ring = NULL;
 394                 }
 395                 rte_free(q);
 396                 q = NULL;
 397         }
 398 }
 399
 400 /*
 401  * disable TX queue, wait unitl HW finished necessary flush operation
 402  */
 403 static inline int
 404 tx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 405 {
 406         uint32_t reg, i;
 407
 408         reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 409         FM10K_WRITE_REG(hw, FM10K_TXDCTL(qnum),
 410                         reg & ~FM10K_TXDCTL_ENABLE);
 411
 412         /* Wait 100us at most */
 413         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 414                 rte_delay_us(1);
 415                 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 416                 if (!(reg & FM10K_TXDCTL_ENABLE))
 417                         break;
 418         }
 419
 420         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 421                 return -1;
 422
 423         return 0;
 424 }
 425
 426 static int
 427 fm10k_check_mq_mode(struct rte_eth_dev *dev)
 428 {
 429         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 430         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 431         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 432         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 433
 434         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 435
 436         if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
 437                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
 438                 return -EINVAL;
 439         }
 440
 441         if (!(rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG))
 442                 return 0;
 443
 444         if (hw->mac.type == fm10k_mac_vf) {
 445                 PMD_INIT_LOG(ERR, "VMDQ mode is not supported in VF.");
 446                 return -EINVAL;
 447         }
 448
 449         /* Check VMDQ queue pool number */
 450         if (vmdq_conf->nb_queue_pools >
 451                         sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT ||
 452                         vmdq_conf->nb_queue_pools > nb_rx_q) {
 453                 PMD_INIT_LOG(ERR, "Too many of queue pools: %d",
 454                         vmdq_conf->nb_queue_pools);
 455                 return -EINVAL;
 456         }
 457
 458         return 0;
 459 }
 460
 461 static const struct fm10k_txq_ops def_txq_ops = {
 462         .reset = tx_queue_reset,
 463 };
 464
 465 static int
 466 fm10k_dev_configure(struct rte_eth_dev *dev)
 467 {
 468         int ret;
 469
 470         PMD_INIT_FUNC_TRACE();
 471
 472         if (dev->data->dev_conf.rxmode.hw_strip_crc == 0)
 473                 PMD_INIT_LOG(WARNING, "fm10k always strip CRC");
 474         /* multipe queue mode checking */
 475         ret  = fm10k_check_mq_mode(dev);
 476         if (ret != 0) {
 477                 PMD_DRV_LOG(ERR, "fm10k_check_mq_mode fails with %d.",
 478                             ret);
 479                 return ret;
 480         }
 481
 482         return 0;
 483 }
 484
 485 /* fls = find last set bit = 32 minus the number of leading zeros */
 486 #ifndef fls
 487 #define fls(x) (((x) == 0) ? 0 : (32 - __builtin_clz((x))))
 488 #endif
 489
 490 static void
 491 fm10k_dev_vmdq_rx_configure(struct rte_eth_dev *dev)
 492 {
 493         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 494         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 495         uint32_t i;
 496
 497         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 498
 499         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
 500                 if (!vmdq_conf->pool_map[i].pools)
 501                         continue;
 502                 fm10k_mbx_lock(hw);
 503                 fm10k_update_vlan(hw, vmdq_conf->pool_map[i].vlan_id, 0, true);
 504                 fm10k_mbx_unlock(hw);
 505         }
 506 }
 507
 508 static void
 509 fm10k_dev_pf_main_vsi_reset(struct rte_eth_dev *dev)
 510 {
 511         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 512
 513         /* Add default mac address */
 514         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
 515                 MAIN_VSI_POOL_NUMBER);
 516 }
 517
 518 static void
 519 fm10k_dev_rss_configure(struct rte_eth_dev *dev)
 520 {
 521         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 522         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 523         uint32_t mrqc, *key, i, reta, j;
 524         uint64_t hf;
 525
 526 #define RSS_KEY_SIZE 40
 527         static uint8_t rss_intel_key[RSS_KEY_SIZE] = {
 528                 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
 529                 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
 530                 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
 531                 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
 532                 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
 533         };
 534
 535         if (dev->data->nb_rx_queues == 1 ||
 536             dev_conf->rxmode.mq_mode != ETH_MQ_RX_RSS ||
 537             dev_conf->rx_adv_conf.rss_conf.rss_hf == 0) {
 538                 FM10K_WRITE_REG(hw, FM10K_MRQC(0), 0);
 539                 return;
 540         }
 541
 542         /* random key is rss_intel_key (default) or user provided (rss_key) */
 543         if (dev_conf->rx_adv_conf.rss_conf.rss_key == NULL)
 544                 key = (uint32_t *)rss_intel_key;
 545         else
 546                 key = (uint32_t *)dev_conf->rx_adv_conf.rss_conf.rss_key;
 547
 548         /* Now fill our hash function seeds, 4 bytes at a time */
 549         for (i = 0; i < RSS_KEY_SIZE / sizeof(*key); ++i)
 550                 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
 551
 552         /*
 553          * Fill in redirection table
 554          * The byte-swap is needed because NIC registers are in
 555          * little-endian order.
 556          */
 557         reta = 0;
 558         for (i = 0, j = 0; i < FM10K_MAX_RSS_INDICES; i++, j++) {
 559                 if (j == dev->data->nb_rx_queues)
 560                         j = 0;
 561                 reta = (reta << CHAR_BIT) | j;
 562                 if ((i & 3) == 3)
 563                         FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2),
 564                                         rte_bswap32(reta));
 565         }
 566
 567         /*
 568          * Generate RSS hash based on packet types, TCP/UDP
 569          * port numbers and/or IPv4/v6 src and dst addresses
 570          */
 571         hf = dev_conf->rx_adv_conf.rss_conf.rss_hf;
 572         mrqc = 0;
 573         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
 574         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
 575         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
 576         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
 577         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
 578         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
 579         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
 580         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
 581         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
 582
 583         if (mrqc == 0) {
 584                 PMD_INIT_LOG(ERR, "Specified RSS mode 0x%"PRIx64"is not"
 585                         "supported", hf);
 586                 return;
 587         }
 588
 589         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
 590 }
 591
 592 static void
 593 fm10k_dev_logic_port_update(struct rte_eth_dev *dev, uint16_t nb_lport_new)
 594 {
 595         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 596         uint32_t i;
 597
 598         for (i = 0; i < nb_lport_new; i++) {
 599                 /* Set unicast mode by default. App can change
 600                  * to other mode in other API func.
 601                  */
 602                 fm10k_mbx_lock(hw);
 603                 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map + i,
 604                         FM10K_XCAST_MODE_NONE);
 605                 fm10k_mbx_unlock(hw);
 606         }
 607 }
 608
 609 static void
 610 fm10k_dev_mq_rx_configure(struct rte_eth_dev *dev)
 611 {
 612         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 613         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 614         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 615         struct fm10k_macvlan_filter_info *macvlan;
 616         uint16_t nb_queue_pools = 0; /* pool number in configuration */
 617         uint16_t nb_lport_new;
 618
 619         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 620         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 621
 622         fm10k_dev_rss_configure(dev);
 623
 624         /* only PF supports VMDQ */
 625         if (hw->mac.type != fm10k_mac_pf)
 626                 return;
 627
 628         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
 629                 nb_queue_pools = vmdq_conf->nb_queue_pools;
 630
 631         /* no pool number change, no need to update logic port and VLAN/MAC */
 632         if (macvlan->nb_queue_pools == nb_queue_pools)
 633                 return;
 634
 635         nb_lport_new = nb_queue_pools ? nb_queue_pools : 1;
 636         fm10k_dev_logic_port_update(dev, nb_lport_new);
 637
 638         /* reset MAC/VLAN as it's based on VMDQ or PF main VSI */
 639         memset(dev->data->mac_addrs, 0,
 640                 ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM);
 641         ether_addr_copy((const struct ether_addr *)hw->mac.addr,
 642                 &dev->data->mac_addrs[0]);
 643         memset(macvlan, 0, sizeof(*macvlan));
 644         macvlan->nb_queue_pools = nb_queue_pools;
 645
 646         if (nb_queue_pools)
 647                 fm10k_dev_vmdq_rx_configure(dev);
 648         else
 649                 fm10k_dev_pf_main_vsi_reset(dev);
 650 }
 651
 652 static int
 653 fm10k_dev_tx_init(struct rte_eth_dev *dev)
 654 {
 655         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 656         int i, ret;
 657         struct fm10k_tx_queue *txq;
 658         uint64_t base_addr;
 659         uint32_t size;
 660
 661         /* Disable TXINT to avoid possible interrupt */
 662         for (i = 0; i < hw->mac.max_queues; i++)
 663                 FM10K_WRITE_REG(hw, FM10K_TXINT(i),
 664                                 3 << FM10K_TXINT_TIMER_SHIFT);
 665
 666         /* Setup TX queue */
 667         for (i = 0; i < dev->data->nb_tx_queues; ++i) {
 668                 txq = dev->data->tx_queues[i];
 669                 base_addr = txq->hw_ring_phys_addr;
 670                 size = txq->nb_desc * sizeof(struct fm10k_tx_desc);
 671
 672                 /* disable queue to avoid issues while updating state */
 673                 ret = tx_queue_disable(hw, i);
 674                 if (ret) {
 675                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 676                         return -1;
 677                 }
 678                 /* Enable use of FTAG bit in TX descriptor, PFVTCTL
 679                  * register is read-only for VF.
 680                  */
 681                 if (fm10k_check_ftag(dev->device->devargs)) {
 682                         if (hw->mac.type == fm10k_mac_pf) {
 683                                 FM10K_WRITE_REG(hw, FM10K_PFVTCTL(i),
 684                                                 FM10K_PFVTCTL_FTAG_DESC_ENABLE);
 685                                 PMD_INIT_LOG(DEBUG, "FTAG mode is enabled");
 686                         } else {
 687                                 PMD_INIT_LOG(ERR, "VF FTAG is not supported.");
 688                                 return -ENOTSUP;
 689                         }
 690                 }
 691
 692                 /* set location and size for descriptor ring */
 693                 FM10K_WRITE_REG(hw, FM10K_TDBAL(i),
 694                                 base_addr & UINT64_LOWER_32BITS_MASK);
 695                 FM10K_WRITE_REG(hw, FM10K_TDBAH(i),
 696                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 697                 FM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);
 698
 699                 /* assign default SGLORT for each TX queue by PF */
 700                 if (hw->mac.type == fm10k_mac_pf)
 701                         FM10K_WRITE_REG(hw, FM10K_TX_SGLORT(i), hw->mac.dglort_map);
 702         }
 703
 704         /* set up vector or scalar TX function as appropriate */
 705         fm10k_set_tx_function(dev);
 706
 707         return 0;
 708 }
 709
 710 static int
 711 fm10k_dev_rx_init(struct rte_eth_dev *dev)
 712 {
 713         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 714         struct fm10k_macvlan_filter_info *macvlan;
 715         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
 716         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
 717         int i, ret;
 718         struct fm10k_rx_queue *rxq;
 719         uint64_t base_addr;
 720         uint32_t size;
 721         uint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
 722         uint32_t logic_port = hw->mac.dglort_map;
 723         uint16_t buf_size;
 724         uint16_t queue_stride = 0;
 725
 726         /* enable RXINT for interrupt mode */
 727         i = 0;
 728         if (rte_intr_dp_is_en(intr_handle)) {
 729                 for (; i < dev->data->nb_rx_queues; i++) {
 730                         FM10K_WRITE_REG(hw, FM10K_RXINT(i), Q2V(pdev, i));
 731                         if (hw->mac.type == fm10k_mac_pf)
 732                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, i)),
 733                                         FM10K_ITR_AUTOMASK |
 734                                         FM10K_ITR_MASK_CLEAR);
 735                         else
 736                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, i)),
 737                                         FM10K_ITR_AUTOMASK |
 738                                         FM10K_ITR_MASK_CLEAR);
 739                 }
 740         }
 741         /* Disable other RXINT to avoid possible interrupt */
 742         for (; i < hw->mac.max_queues; i++)
 743                 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
 744                         3 << FM10K_RXINT_TIMER_SHIFT);
 745
 746         /* Setup RX queues */
 747         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 748                 rxq = dev->data->rx_queues[i];
 749                 base_addr = rxq->hw_ring_phys_addr;
 750                 size = rxq->nb_desc * sizeof(union fm10k_rx_desc);
 751
 752                 /* disable queue to avoid issues while updating state */
 753                 ret = rx_queue_disable(hw, i);
 754                 if (ret) {
 755                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 756                         return -1;
 757                 }
 758
 759                 /* Setup the Base and Length of the Rx Descriptor Ring */
 760                 FM10K_WRITE_REG(hw, FM10K_RDBAL(i),
 761                                 base_addr & UINT64_LOWER_32BITS_MASK);
 762                 FM10K_WRITE_REG(hw, FM10K_RDBAH(i),
 763                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 764                 FM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);
 765
 766                 /* Configure the Rx buffer size for one buff without split */
 767                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 768                         RTE_PKTMBUF_HEADROOM);
 769                 /* As RX buffer is aligned to 512B within mbuf, some bytes are
 770                  * reserved for this purpose, and the worst case could be 511B.
 771                  * But SRR reg assumes all buffers have the same size. In order
 772                  * to fill the gap, we'll have to consider the worst case and
 773                  * assume 512B is reserved. If we don't do so, it's possible
 774                  * for HW to overwrite data to next mbuf.
 775                  */
 776                 buf_size -= FM10K_RX_DATABUF_ALIGN;
 777
 778                 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i),
 779                                 (buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT) |
 780                                 FM10K_SRRCTL_LOOPBACK_SUPPRESS);
 781
 782                 /* It adds dual VLAN length for supporting dual VLAN */
 783                 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
 784                                 2 * FM10K_VLAN_TAG_SIZE) > buf_size ||
 785                         dev->data->dev_conf.rxmode.enable_scatter) {
 786                         uint32_t reg;
 787                         dev->data->scattered_rx = 1;
 788                         reg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));
 789                         reg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;
 790                         FM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);
 791                 }
 792
 793                 /* Enable drop on empty, it's RO for VF */
 794                 if (hw->mac.type == fm10k_mac_pf && rxq->drop_en)
 795                         rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
 796
 797                 FM10K_WRITE_REG(hw, FM10K_RXDCTL(i), rxdctl);
 798                 FM10K_WRITE_FLUSH(hw);
 799         }
 800
 801         /* Configure VMDQ/RSS if applicable */
 802         fm10k_dev_mq_rx_configure(dev);
 803
 804         /* Decide the best RX function */
 805         fm10k_set_rx_function(dev);
 806
 807         /* update RX_SGLORT for loopback suppress*/
 808         if (hw->mac.type != fm10k_mac_pf)
 809                 return 0;
 810         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 811         if (macvlan->nb_queue_pools)
 812                 queue_stride = dev->data->nb_rx_queues / macvlan->nb_queue_pools;
 813         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 814                 if (i && queue_stride && !(i % queue_stride))
 815                         logic_port++;
 816                 FM10K_WRITE_REG(hw, FM10K_RX_SGLORT(i), logic_port);
 817         }
 818
 819         return 0;
 820 }
 821
 822 static int
 823 fm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 824 {
 825         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 826         int err = -1;
 827         uint32_t reg;
 828         struct fm10k_rx_queue *rxq;
 829
 830         PMD_INIT_FUNC_TRACE();
 831
 832         if (rx_queue_id < dev->data->nb_rx_queues) {
 833                 rxq = dev->data->rx_queues[rx_queue_id];
 834                 err = rx_queue_reset(rxq);
 835                 if (err == -ENOMEM) {
 836                         PMD_INIT_LOG(ERR, "Failed to alloc memory : %d", err);
 837                         return err;
 838                 } else if (err == -EINVAL) {
 839                         PMD_INIT_LOG(ERR, "Invalid buffer address alignment :"
 840                                 " %d", err);
 841                         return err;
 842                 }
 843
 844                 /* Setup the HW Rx Head and Tail Descriptor Pointers
 845                  * Note: this must be done AFTER the queue is enabled on real
 846                  * hardware, but BEFORE the queue is enabled when using the
 847                  * emulation platform. Do it in both places for now and remove
 848                  * this comment and the following two register writes when the
 849                  * emulation platform is no longer being used.
 850                  */
 851                 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 852                 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 853
 854                 /* Set PF ownership flag for PF devices */
 855                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));
 856                 if (hw->mac.type == fm10k_mac_pf)
 857                         reg |= FM10K_RXQCTL_PF;
 858                 reg |= FM10K_RXQCTL_ENABLE;
 859                 /* enable RX queue */
 860                 FM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);
 861                 FM10K_WRITE_FLUSH(hw);
 862
 863                 /* Setup the HW Rx Head and Tail Descriptor Pointers
 864                  * Note: this must be done AFTER the queue is enabled
 865                  */
 866                 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 867                 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 868                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 869         }
 870
 871         return err;
 872 }
 873
 874 static int
 875 fm10k_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 876 {
 877         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 878
 879         PMD_INIT_FUNC_TRACE();
 880
 881         if (rx_queue_id < dev->data->nb_rx_queues) {
 882                 /* Disable RX queue */
 883                 rx_queue_disable(hw, rx_queue_id);
 884
 885                 /* Free mbuf and clean HW ring */
 886                 rx_queue_clean(dev->data->rx_queues[rx_queue_id]);
 887                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 888         }
 889
 890         return 0;
 891 }
 892
 893 static int
 894 fm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 895 {
 896         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 897         /** @todo - this should be defined in the shared code */
 898 #define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY       0x00010000
 899         uint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;
 900         int err = 0;
 901
 902         PMD_INIT_FUNC_TRACE();
 903
 904         if (tx_queue_id < dev->data->nb_tx_queues) {
 905                 struct fm10k_tx_queue *q = dev->data->tx_queues[tx_queue_id];
 906
 907                 q->ops->reset(q);
 908
 909                 /* reset head and tail pointers */
 910                 FM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);
 911                 FM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);
 912
 913                 /* enable TX queue */
 914                 FM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),
 915                                         FM10K_TXDCTL_ENABLE | txdctl);
 916                 FM10K_WRITE_FLUSH(hw);
 917                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 918         } else
 919                 err = -1;
 920
 921         return err;
 922 }
 923
 924 static int
 925 fm10k_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 926 {
 927         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 928
 929         PMD_INIT_FUNC_TRACE();
 930
 931         if (tx_queue_id < dev->data->nb_tx_queues) {
 932                 tx_queue_disable(hw, tx_queue_id);
 933                 tx_queue_clean(dev->data->tx_queues[tx_queue_id]);
 934                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 935         }
 936
 937         return 0;
 938 }
 939
 940 static inline int fm10k_glort_valid(struct fm10k_hw *hw)
 941 {
 942         return ((hw->mac.dglort_map & FM10K_DGLORTMAP_NONE)
 943                 != FM10K_DGLORTMAP_NONE);
 944 }
 945
 946 static void
 947 fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev)
 948 {
 949         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 950         int status;
 951
 952         PMD_INIT_FUNC_TRACE();
 953
 954         /* Return if it didn't acquire valid glort range */
 955         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
 956                 return;
 957
 958         fm10k_mbx_lock(hw);
 959         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 960                                 FM10K_XCAST_MODE_PROMISC);
 961         fm10k_mbx_unlock(hw);
 962
 963         if (status != FM10K_SUCCESS)
 964                 PMD_INIT_LOG(ERR, "Failed to enable promiscuous mode");
 965 }
 966
 967 static void
 968 fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev)
 969 {
 970         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 971         uint8_t mode;
 972         int status;
 973
 974         PMD_INIT_FUNC_TRACE();
 975
 976         /* Return if it didn't acquire valid glort range */
 977         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
 978                 return;
 979
 980         if (dev->data->all_multicast == 1)
 981                 mode = FM10K_XCAST_MODE_ALLMULTI;
 982         else
 983                 mode = FM10K_XCAST_MODE_NONE;
 984
 985         fm10k_mbx_lock(hw);
 986         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 987                                 mode);
 988         fm10k_mbx_unlock(hw);
 989
 990         if (status != FM10K_SUCCESS)
 991                 PMD_INIT_LOG(ERR, "Failed to disable promiscuous mode");
 992 }
 993
 994 static void
 995 fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev)
 996 {
 997         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 998         int status;
 999
1000         PMD_INIT_FUNC_TRACE();
1001
1002         /* Return if it didn't acquire valid glort range */
1003         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1004                 return;
1005
1006         /* If promiscuous mode is enabled, it doesn't make sense to enable
1007          * allmulticast and disable promiscuous since fm10k only can select
1008          * one of the modes.
1009          */
1010         if (dev->data->promiscuous) {
1011                 PMD_INIT_LOG(INFO, "Promiscuous mode is enabled, "\
1012                         "needn't enable allmulticast");
1013                 return;
1014         }
1015
1016         fm10k_mbx_lock(hw);
1017         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1018                                 FM10K_XCAST_MODE_ALLMULTI);
1019         fm10k_mbx_unlock(hw);
1020
1021         if (status != FM10K_SUCCESS)
1022                 PMD_INIT_LOG(ERR, "Failed to enable allmulticast mode");
1023 }
1024
1025 static void
1026 fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev)
1027 {
1028         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1029         int status;
1030
1031         PMD_INIT_FUNC_TRACE();
1032
1033         /* Return if it didn't acquire valid glort range */
1034         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1035                 return;
1036
1037         if (dev->data->promiscuous) {
1038                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode "\
1039                         "since promisc mode is enabled");
1040                 return;
1041         }
1042
1043         fm10k_mbx_lock(hw);
1044         /* Change mode to unicast mode */
1045         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1046                                 FM10K_XCAST_MODE_NONE);
1047         fm10k_mbx_unlock(hw);
1048
1049         if (status != FM10K_SUCCESS)
1050                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode");
1051 }
1052
1053 static void
1054 fm10k_dev_dglort_map_configure(struct rte_eth_dev *dev)
1055 {
1056         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1057         uint32_t dglortdec, pool_len, rss_len, i, dglortmask;
1058         uint16_t nb_queue_pools;
1059         struct fm10k_macvlan_filter_info *macvlan;
1060
1061         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1062         nb_queue_pools = macvlan->nb_queue_pools;
1063         pool_len = nb_queue_pools ? fls(nb_queue_pools - 1) : 0;
1064         rss_len = fls(dev->data->nb_rx_queues - 1) - pool_len;
1065
1066         /* GLORT 0x0-0x3F are used by PF and VMDQ,  0x40-0x7F used by FD */
1067         dglortdec = (rss_len << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | pool_len;
1068         dglortmask = (GLORT_PF_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1069                         hw->mac.dglort_map;
1070         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(0), dglortmask);
1071         /* Configure VMDQ/RSS DGlort Decoder */
1072         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(0), dglortdec);
1073
1074         /* Flow Director configurations, only queue number is valid. */
1075         dglortdec = fls(dev->data->nb_rx_queues - 1);
1076         dglortmask = (GLORT_FD_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1077                         (hw->mac.dglort_map + GLORT_FD_Q_BASE);
1078         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(1), dglortmask);
1079         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(1), dglortdec);
1080
1081         /* Invalidate all other GLORT entries */
1082         for (i = 2; i < FM10K_DGLORT_COUNT; i++)
1083                 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i),
1084                                 FM10K_DGLORTMAP_NONE);
1085 }
1086
1087 #define BSIZEPKT_ROUNDUP ((1 << FM10K_SRRCTL_BSIZEPKT_SHIFT) - 1)
1088 static int
1089 fm10k_dev_start(struct rte_eth_dev *dev)
1090 {
1091         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1092         int i, diag;
1093
1094         PMD_INIT_FUNC_TRACE();
1095
1096         /* stop, init, then start the hw */
1097         diag = fm10k_stop_hw(hw);
1098         if (diag != FM10K_SUCCESS) {
1099                 PMD_INIT_LOG(ERR, "Hardware stop failed: %d", diag);
1100                 return -EIO;
1101         }
1102
1103         diag = fm10k_init_hw(hw);
1104         if (diag != FM10K_SUCCESS) {
1105                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
1106                 return -EIO;
1107         }
1108
1109         diag = fm10k_start_hw(hw);
1110         if (diag != FM10K_SUCCESS) {
1111                 PMD_INIT_LOG(ERR, "Hardware start failed: %d", diag);
1112                 return -EIO;
1113         }
1114
1115         diag = fm10k_dev_tx_init(dev);
1116         if (diag) {
1117                 PMD_INIT_LOG(ERR, "TX init failed: %d", diag);
1118                 return diag;
1119         }
1120
1121         if (fm10k_dev_rxq_interrupt_setup(dev))
1122                 return -EIO;
1123
1124         diag = fm10k_dev_rx_init(dev);
1125         if (diag) {
1126                 PMD_INIT_LOG(ERR, "RX init failed: %d", diag);
1127                 return diag;
1128         }
1129
1130         if (hw->mac.type == fm10k_mac_pf)
1131                 fm10k_dev_dglort_map_configure(dev);
1132
1133         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1134                 struct fm10k_rx_queue *rxq;
1135                 rxq = dev->data->rx_queues[i];
1136
1137                 if (rxq->rx_deferred_start)
1138                         continue;
1139                 diag = fm10k_dev_rx_queue_start(dev, i);
1140                 if (diag != 0) {
1141                         int j;
1142                         for (j = 0; j < i; ++j)
1143                                 rx_queue_clean(dev->data->rx_queues[j]);
1144                         return diag;
1145                 }
1146         }
1147
1148         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1149                 struct fm10k_tx_queue *txq;
1150                 txq = dev->data->tx_queues[i];
1151
1152                 if (txq->tx_deferred_start)
1153                         continue;
1154                 diag = fm10k_dev_tx_queue_start(dev, i);
1155                 if (diag != 0) {
1156                         int j;
1157                         for (j = 0; j < i; ++j)
1158                                 tx_queue_clean(dev->data->tx_queues[j]);
1159                         for (j = 0; j < dev->data->nb_rx_queues; ++j)
1160                                 rx_queue_clean(dev->data->rx_queues[j]);
1161                         return diag;
1162                 }
1163         }
1164
1165         /* Update default vlan when not in VMDQ mode */
1166         if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
1167                 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
1168
1169         return 0;
1170 }
1171
1172 static void
1173 fm10k_dev_stop(struct rte_eth_dev *dev)
1174 {
1175         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1176         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
1177         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
1178         int i;
1179
1180         PMD_INIT_FUNC_TRACE();
1181
1182         if (dev->data->tx_queues)
1183                 for (i = 0; i < dev->data->nb_tx_queues; i++)
1184                         fm10k_dev_tx_queue_stop(dev, i);
1185
1186         if (dev->data->rx_queues)
1187                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1188                         fm10k_dev_rx_queue_stop(dev, i);
1189
1190         /* Disable datapath event */
1191         if (rte_intr_dp_is_en(intr_handle)) {
1192                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1193                         FM10K_WRITE_REG(hw, FM10K_RXINT(i),
1194                                 3 << FM10K_RXINT_TIMER_SHIFT);
1195                         if (hw->mac.type == fm10k_mac_pf)
1196                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, i)),
1197                                         FM10K_ITR_MASK_SET);
1198                         else
1199                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, i)),
1200                                         FM10K_ITR_MASK_SET);
1201                 }
1202         }
1203         /* Clean datapath event and queue/vec mapping */
1204         rte_intr_efd_disable(intr_handle);
1205         rte_free(intr_handle->intr_vec);
1206         intr_handle->intr_vec = NULL;
1207 }
1208
1209 static void
1210 fm10k_dev_queue_release(struct rte_eth_dev *dev)
1211 {
1212         int i;
1213
1214         PMD_INIT_FUNC_TRACE();
1215
1216         if (dev->data->tx_queues) {
1217                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1218                         struct fm10k_tx_queue *txq = dev->data->tx_queues[i];
1219
1220                         tx_queue_free(txq);
1221                 }
1222         }
1223
1224         if (dev->data->rx_queues) {
1225                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1226                         fm10k_rx_queue_release(dev->data->rx_queues[i]);
1227         }
1228 }
1229
1230 static void
1231 fm10k_dev_close(struct rte_eth_dev *dev)
1232 {
1233         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1234
1235         PMD_INIT_FUNC_TRACE();
1236
1237         fm10k_mbx_lock(hw);
1238         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
1239                 MAX_LPORT_NUM, false);
1240         fm10k_mbx_unlock(hw);
1241
1242         /* allow 10ms for device to quiesce */
1243         rte_delay_us(FM10K_SWITCH_QUIESCE_US);
1244
1245         /* Stop mailbox service first */
1246         fm10k_close_mbx_service(hw);
1247         fm10k_dev_stop(dev);
1248         fm10k_dev_queue_release(dev);
1249         fm10k_stop_hw(hw);
1250 }
1251
1252 static int
1253 fm10k_link_update(struct rte_eth_dev *dev,
1254         __rte_unused int wait_to_complete)
1255 {
1256         PMD_INIT_FUNC_TRACE();
1257
1258         /* The host-interface link is always up.  The speed is ~50Gbps per Gen3
1259          * x8 PCIe interface. For now, we leave the speed undefined since there
1260          * is no 50Gbps Ethernet. */
1261         dev->data->dev_link.link_speed  = 0;
1262         dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
1263         dev->data->dev_link.link_status = ETH_LINK_UP;
1264
1265         return 0;
1266 }
1267
1268 static int fm10k_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1269         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
1270 {
1271         unsigned i, q;
1272         unsigned count = 0;
1273
1274         if (xstats_names != NULL) {
1275                 /* Note: limit checked in rte_eth_xstats_names() */
1276
1277                 /* Global stats */
1278                 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1279                         snprintf(xstats_names[count].name,
1280                                 sizeof(xstats_names[count].name),
1281                                 "%s", fm10k_hw_stats_strings[count].name);
1282                         count++;
1283                 }
1284
1285                 /* PF queue stats */
1286                 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1287                         for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1288                                 snprintf(xstats_names[count].name,
1289                                         sizeof(xstats_names[count].name),
1290                                         "rx_q%u_%s", q,
1291                                         fm10k_hw_stats_rx_q_strings[i].name);
1292                                 count++;
1293                         }
1294                         for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1295                                 snprintf(xstats_names[count].name,
1296                                         sizeof(xstats_names[count].name),
1297                                         "tx_q%u_%s", q,
1298                                         fm10k_hw_stats_tx_q_strings[i].name);
1299                                 count++;
1300                         }
1301                 }
1302         }
1303         return FM10K_NB_XSTATS;
1304 }
1305
1306 static int
1307 fm10k_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1308                  unsigned n)
1309 {
1310         struct fm10k_hw_stats *hw_stats =
1311                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1312         unsigned i, q, count = 0;
1313
1314         if (n < FM10K_NB_XSTATS)
1315                 return FM10K_NB_XSTATS;
1316
1317         /* Global stats */
1318         for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1319                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1320                         fm10k_hw_stats_strings[count].offset);
1321                 xstats[count].id = count;
1322                 count++;
1323         }
1324
1325         /* PF queue stats */
1326         for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1327                 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1328                         xstats[count].value =
1329                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1330                                 fm10k_hw_stats_rx_q_strings[i].offset);
1331                         xstats[count].id = count;
1332                         count++;
1333                 }
1334                 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1335                         xstats[count].value =
1336                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1337                                 fm10k_hw_stats_tx_q_strings[i].offset);
1338                         xstats[count].id = count;
1339                         count++;
1340                 }
1341         }
1342
1343         return FM10K_NB_XSTATS;
1344 }
1345
1346 static void
1347 fm10k_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1348 {
1349         uint64_t ipackets, opackets, ibytes, obytes;
1350         struct fm10k_hw *hw =
1351                 FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1352         struct fm10k_hw_stats *hw_stats =
1353                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1354         int i;
1355
1356         PMD_INIT_FUNC_TRACE();
1357
1358         fm10k_update_hw_stats(hw, hw_stats);
1359
1360         ipackets = opackets = ibytes = obytes = 0;
1361         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1362                 (i < hw->mac.max_queues); ++i) {
1363                 stats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;
1364                 stats->q_opackets[i] = hw_stats->q[i].tx_packets.count;
1365                 stats->q_ibytes[i]   = hw_stats->q[i].rx_bytes.count;
1366                 stats->q_obytes[i]   = hw_stats->q[i].tx_bytes.count;
1367                 ipackets += stats->q_ipackets[i];
1368                 opackets += stats->q_opackets[i];
1369                 ibytes   += stats->q_ibytes[i];
1370                 obytes   += stats->q_obytes[i];
1371         }
1372         stats->ipackets = ipackets;
1373         stats->opackets = opackets;
1374         stats->ibytes = ibytes;
1375         stats->obytes = obytes;
1376 }
1377
1378 static void
1379 fm10k_stats_reset(struct rte_eth_dev *dev)
1380 {
1381         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1382         struct fm10k_hw_stats *hw_stats =
1383                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1384
1385         PMD_INIT_FUNC_TRACE();
1386
1387         memset(hw_stats, 0, sizeof(*hw_stats));
1388         fm10k_rebind_hw_stats(hw, hw_stats);
1389 }
1390
1391 static void
1392 fm10k_dev_infos_get(struct rte_eth_dev *dev,
1393         struct rte_eth_dev_info *dev_info)
1394 {
1395         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1396         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
1397
1398         PMD_INIT_FUNC_TRACE();
1399
1400         dev_info->pci_dev            = pdev;
1401         dev_info->min_rx_bufsize     = FM10K_MIN_RX_BUF_SIZE;
1402         dev_info->max_rx_pktlen      = FM10K_MAX_PKT_SIZE;
1403         dev_info->max_rx_queues      = hw->mac.max_queues;
1404         dev_info->max_tx_queues      = hw->mac.max_queues;
1405         dev_info->max_mac_addrs      = FM10K_MAX_MACADDR_NUM;
1406         dev_info->max_hash_mac_addrs = 0;
1407         dev_info->max_vfs            = pdev->max_vfs;
1408         dev_info->vmdq_pool_base     = 0;
1409         dev_info->vmdq_queue_base    = 0;
1410         dev_info->max_vmdq_pools     = ETH_32_POOLS;
1411         dev_info->vmdq_queue_num     = FM10K_MAX_QUEUES_PF;
1412         dev_info->rx_offload_capa =
1413                 DEV_RX_OFFLOAD_VLAN_STRIP |
1414                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1415                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1416                 DEV_RX_OFFLOAD_TCP_CKSUM;
1417         dev_info->tx_offload_capa =
1418                 DEV_TX_OFFLOAD_VLAN_INSERT |
1419                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1420                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1421                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1422                 DEV_TX_OFFLOAD_TCP_TSO;
1423
1424         dev_info->hash_key_size = FM10K_RSSRK_SIZE * sizeof(uint32_t);
1425         dev_info->reta_size = FM10K_MAX_RSS_INDICES;
1426
1427         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1428                 .rx_thresh = {
1429                         .pthresh = FM10K_DEFAULT_RX_PTHRESH,
1430                         .hthresh = FM10K_DEFAULT_RX_HTHRESH,
1431                         .wthresh = FM10K_DEFAULT_RX_WTHRESH,
1432                 },
1433                 .rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(0),
1434                 .rx_drop_en = 0,
1435         };
1436
1437         dev_info->default_txconf = (struct rte_eth_txconf) {
1438                 .tx_thresh = {
1439                         .pthresh = FM10K_DEFAULT_TX_PTHRESH,
1440                         .hthresh = FM10K_DEFAULT_TX_HTHRESH,
1441                         .wthresh = FM10K_DEFAULT_TX_WTHRESH,
1442                 },
1443                 .tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(0),
1444                 .tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(0),
1445                 .txq_flags = FM10K_SIMPLE_TX_FLAG,
1446         };
1447
1448         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1449                 .nb_max = FM10K_MAX_RX_DESC,
1450                 .nb_min = FM10K_MIN_RX_DESC,
1451                 .nb_align = FM10K_MULT_RX_DESC,
1452         };
1453
1454         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1455                 .nb_max = FM10K_MAX_TX_DESC,
1456                 .nb_min = FM10K_MIN_TX_DESC,
1457                 .nb_align = FM10K_MULT_TX_DESC,
1458                 .nb_seg_max = FM10K_TX_MAX_SEG,
1459                 .nb_mtu_seg_max = FM10K_TX_MAX_MTU_SEG,
1460         };
1461
1462         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G |
1463                         ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
1464                         ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1465 }
1466
1467 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
1468 static const uint32_t *
1469 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1470 {
1471         if (dev->rx_pkt_burst == fm10k_recv_pkts ||
1472             dev->rx_pkt_burst == fm10k_recv_scattered_pkts) {
1473                 static uint32_t ptypes[] = {
1474                         /* refers to rx_desc_to_ol_flags() */
1475                         RTE_PTYPE_L2_ETHER,
1476                         RTE_PTYPE_L3_IPV4,
1477                         RTE_PTYPE_L3_IPV4_EXT,
1478                         RTE_PTYPE_L3_IPV6,
1479                         RTE_PTYPE_L3_IPV6_EXT,
1480                         RTE_PTYPE_L4_TCP,
1481                         RTE_PTYPE_L4_UDP,
1482                         RTE_PTYPE_UNKNOWN
1483                 };
1484
1485                 return ptypes;
1486         } else if (dev->rx_pkt_burst == fm10k_recv_pkts_vec ||
1487                    dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec) {
1488                 static uint32_t ptypes_vec[] = {
1489                         /* refers to fm10k_desc_to_pktype_v() */
1490                         RTE_PTYPE_L3_IPV4,
1491                         RTE_PTYPE_L3_IPV4_EXT,
1492                         RTE_PTYPE_L3_IPV6,
1493                         RTE_PTYPE_L3_IPV6_EXT,
1494                         RTE_PTYPE_L4_TCP,
1495                         RTE_PTYPE_L4_UDP,
1496                         RTE_PTYPE_TUNNEL_GENEVE,
1497                         RTE_PTYPE_TUNNEL_NVGRE,
1498                         RTE_PTYPE_TUNNEL_VXLAN,
1499                         RTE_PTYPE_TUNNEL_GRE,
1500                         RTE_PTYPE_UNKNOWN
1501                 };
1502
1503                 return ptypes_vec;
1504         }
1505
1506         return NULL;
1507 }
1508 #else
1509 static const uint32_t *
1510 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1511 {
1512         return NULL;
1513 }
1514 #endif
1515
1516 static int
1517 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1518 {
1519         s32 result;
1520         uint16_t mac_num = 0;
1521         uint32_t vid_idx, vid_bit, mac_index;
1522         struct fm10k_hw *hw;
1523         struct fm10k_macvlan_filter_info *macvlan;
1524         struct rte_eth_dev_data *data = dev->data;
1525
1526         hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1527         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1528
1529         if (macvlan->nb_queue_pools > 0) { /* VMDQ mode */
1530                 PMD_INIT_LOG(ERR, "Cannot change VLAN filter in VMDQ mode");
1531                 return -EINVAL;
1532         }
1533
1534         if (vlan_id > ETH_VLAN_ID_MAX) {
1535                 PMD_INIT_LOG(ERR, "Invalid vlan_id: must be < 4096");
1536                 return -EINVAL;
1537         }
1538
1539         vid_idx = FM10K_VFTA_IDX(vlan_id);
1540         vid_bit = FM10K_VFTA_BIT(vlan_id);
1541         /* this VLAN ID is already in the VLAN filter table, return SUCCESS */
1542         if (on && (macvlan->vfta[vid_idx] & vid_bit))
1543                 return 0;
1544         /* this VLAN ID is NOT in the VLAN filter table, cannot remove */
1545         if (!on && !(macvlan->vfta[vid_idx] & vid_bit)) {
1546                 PMD_INIT_LOG(ERR, "Invalid vlan_id: not existing "
1547                         "in the VLAN filter table");
1548                 return -EINVAL;
1549         }
1550
1551         fm10k_mbx_lock(hw);
1552         result = fm10k_update_vlan(hw, vlan_id, 0, on);
1553         fm10k_mbx_unlock(hw);
1554         if (result != FM10K_SUCCESS) {
1555                 PMD_INIT_LOG(ERR, "VLAN update failed: %d", result);
1556                 return -EIO;
1557         }
1558
1559         for (mac_index = 0; (mac_index < FM10K_MAX_MACADDR_NUM) &&
1560                         (result == FM10K_SUCCESS); mac_index++) {
1561                 if (is_zero_ether_addr(&data->mac_addrs[mac_index]))
1562                         continue;
1563                 if (mac_num > macvlan->mac_num - 1) {
1564                         PMD_INIT_LOG(ERR, "MAC address number "
1565                                         "not match");
1566                         break;
1567                 }
1568                 fm10k_mbx_lock(hw);
1569                 result = fm10k_update_uc_addr(hw, hw->mac.dglort_map,
1570                         data->mac_addrs[mac_index].addr_bytes,
1571                         vlan_id, on, 0);
1572                 fm10k_mbx_unlock(hw);
1573                 mac_num++;
1574         }
1575         if (result != FM10K_SUCCESS) {
1576                 PMD_INIT_LOG(ERR, "MAC address update failed: %d", result);
1577                 return -EIO;
1578         }
1579
1580         if (on) {
1581                 macvlan->vlan_num++;
1582                 macvlan->vfta[vid_idx] |= vid_bit;
1583         } else {
1584                 macvlan->vlan_num--;
1585                 macvlan->vfta[vid_idx] &= ~vid_bit;
1586         }
1587         return 0;
1588 }
1589
1590 static void
1591 fm10k_vlan_offload_set(__rte_unused struct rte_eth_dev *dev, int mask)
1592 {
1593         if (mask & ETH_VLAN_STRIP_MASK) {
1594                 if (!dev->data->dev_conf.rxmode.hw_vlan_strip)
1595                         PMD_INIT_LOG(ERR, "VLAN stripping is "
1596                                         "always on in fm10k");
1597         }
1598
1599         if (mask & ETH_VLAN_EXTEND_MASK) {
1600                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1601                         PMD_INIT_LOG(ERR, "VLAN QinQ is not "
1602                                         "supported in fm10k");
1603         }
1604
1605         if (mask & ETH_VLAN_FILTER_MASK) {
1606                 if (!dev->data->dev_conf.rxmode.hw_vlan_filter)
1607                         PMD_INIT_LOG(ERR, "VLAN filter is always on in fm10k");
1608         }
1609 }
1610
1611 /* Add/Remove a MAC address, and update filters to main VSI */
1612 static void fm10k_MAC_filter_set_main_vsi(struct rte_eth_dev *dev,
1613                 const u8 *mac, bool add, uint32_t pool)
1614 {
1615         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1616         struct fm10k_macvlan_filter_info *macvlan;
1617         uint32_t i, j, k;
1618
1619         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1620
1621         if (pool != MAIN_VSI_POOL_NUMBER) {
1622                 PMD_DRV_LOG(ERR, "VMDQ not enabled, can't set "
1623                         "mac to pool %u", pool);
1624                 return;
1625         }
1626         for (i = 0, j = 0; j < FM10K_VFTA_SIZE; j++) {
1627                 if (!macvlan->vfta[j])
1628                         continue;
1629                 for (k = 0; k < FM10K_UINT32_BIT_SIZE; k++) {
1630                         if (!(macvlan->vfta[j] & (1 << k)))
1631                                 continue;
1632                         if (i + 1 > macvlan->vlan_num) {
1633                                 PMD_INIT_LOG(ERR, "vlan number not match");
1634                                 return;
1635                         }
1636                         fm10k_mbx_lock(hw);
1637                         fm10k_update_uc_addr(hw, hw->mac.dglort_map, mac,
1638                                 j * FM10K_UINT32_BIT_SIZE + k, add, 0);
1639                         fm10k_mbx_unlock(hw);
1640                         i++;
1641                 }
1642         }
1643 }
1644
1645 /* Add/Remove a MAC address, and update filters to VMDQ */
1646 static void fm10k_MAC_filter_set_vmdq(struct rte_eth_dev *dev,
1647                 const u8 *mac, bool add, uint32_t pool)
1648 {
1649         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1650         struct fm10k_macvlan_filter_info *macvlan;
1651         struct rte_eth_vmdq_rx_conf *vmdq_conf;
1652         uint32_t i;
1653
1654         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1655         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1656
1657         if (pool > macvlan->nb_queue_pools) {
1658                 PMD_DRV_LOG(ERR, "Pool number %u invalid."
1659                         " Max pool is %u",
1660                         pool, macvlan->nb_queue_pools);
1661                 return;
1662         }
1663         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
1664                 if (!(vmdq_conf->pool_map[i].pools & (1UL << pool)))
1665                         continue;
1666                 fm10k_mbx_lock(hw);
1667                 fm10k_update_uc_addr(hw, hw->mac.dglort_map + pool, mac,
1668                         vmdq_conf->pool_map[i].vlan_id, add, 0);
1669                 fm10k_mbx_unlock(hw);
1670         }
1671 }
1672
1673 /* Add/Remove a MAC address, and update filters */
1674 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
1675                 const u8 *mac, bool add, uint32_t pool)
1676 {
1677         struct fm10k_macvlan_filter_info *macvlan;
1678
1679         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1680
1681         if (macvlan->nb_queue_pools > 0) /* VMDQ mode */
1682                 fm10k_MAC_filter_set_vmdq(dev, mac, add, pool);
1683         else
1684                 fm10k_MAC_filter_set_main_vsi(dev, mac, add, pool);
1685
1686         if (add)
1687                 macvlan->mac_num++;
1688         else
1689                 macvlan->mac_num--;
1690 }
1691
1692 /* Add a MAC address, and update filters */
1693 static void
1694 fm10k_macaddr_add(struct rte_eth_dev *dev,
1695                 struct ether_addr *mac_addr,
1696                 uint32_t index,
1697                 uint32_t pool)
1698 {
1699         struct fm10k_macvlan_filter_info *macvlan;
1700
1701         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1702         fm10k_MAC_filter_set(dev, mac_addr->addr_bytes, TRUE, pool);
1703         macvlan->mac_vmdq_id[index] = pool;
1704 }
1705
1706 /* Remove a MAC address, and update filters */
1707 static void
1708 fm10k_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1709 {
1710         struct rte_eth_dev_data *data = dev->data;
1711         struct fm10k_macvlan_filter_info *macvlan;
1712
1713         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1714         fm10k_MAC_filter_set(dev, data->mac_addrs[index].addr_bytes,
1715                         FALSE, macvlan->mac_vmdq_id[index]);
1716         macvlan->mac_vmdq_id[index] = 0;
1717 }
1718
1719 static inline int
1720 check_nb_desc(uint16_t min, uint16_t max, uint16_t mult, uint16_t request)
1721 {
1722         if ((request < min) || (request > max) || ((request % mult) != 0))
1723                 return -1;
1724         else
1725                 return 0;
1726 }
1727
1728
1729 static inline int
1730 check_thresh(uint16_t min, uint16_t max, uint16_t div, uint16_t request)
1731 {
1732         if ((request < min) || (request > max) || ((div % request) != 0))
1733                 return -1;
1734         else
1735                 return 0;
1736 }
1737
1738 static inline int
1739 handle_rxconf(struct fm10k_rx_queue *q, const struct rte_eth_rxconf *conf)
1740 {
1741         uint16_t rx_free_thresh;
1742
1743         if (conf->rx_free_thresh == 0)
1744                 rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(q);
1745         else
1746                 rx_free_thresh = conf->rx_free_thresh;
1747
1748         /* make sure the requested threshold satisfies the constraints */
1749         if (check_thresh(FM10K_RX_FREE_THRESH_MIN(q),
1750                         FM10K_RX_FREE_THRESH_MAX(q),
1751                         FM10K_RX_FREE_THRESH_DIV(q),
1752                         rx_free_thresh)) {
1753                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be "
1754                         "less than or equal to %u, "
1755                         "greater than or equal to %u, "
1756                         "and a divisor of %u",
1757                         rx_free_thresh, FM10K_RX_FREE_THRESH_MAX(q),
1758                         FM10K_RX_FREE_THRESH_MIN(q),
1759                         FM10K_RX_FREE_THRESH_DIV(q));
1760                 return -EINVAL;
1761         }
1762
1763         q->alloc_thresh = rx_free_thresh;
1764         q->drop_en = conf->rx_drop_en;
1765         q->rx_deferred_start = conf->rx_deferred_start;
1766
1767         return 0;
1768 }
1769
1770 /*
1771  * Hardware requires specific alignment for Rx packet buffers. At
1772  * least one of the following two conditions must be satisfied.
1773  *  1. Address is 512B aligned
1774  *  2. Address is 8B aligned and buffer does not cross 4K boundary.
1775  *
1776  * As such, the driver may need to adjust the DMA address within the
1777  * buffer by up to 512B.
1778  *
1779  * return 1 if the element size is valid, otherwise return 0.
1780  */
1781 static int
1782 mempool_element_size_valid(struct rte_mempool *mp)
1783 {
1784         uint32_t min_size;
1785
1786         /* elt_size includes mbuf header and headroom */
1787         min_size = mp->elt_size - sizeof(struct rte_mbuf) -
1788                         RTE_PKTMBUF_HEADROOM;
1789
1790         /* account for up to 512B of alignment */
1791         min_size -= FM10K_RX_DATABUF_ALIGN;
1792
1793         /* sanity check for overflow */
1794         if (min_size > mp->elt_size)
1795                 return 0;
1796
1797         /* size is valid */
1798         return 1;
1799 }
1800
1801 static int
1802 fm10k_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1803         uint16_t nb_desc, unsigned int socket_id,
1804         const struct rte_eth_rxconf *conf, struct rte_mempool *mp)
1805 {
1806         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1807         struct fm10k_dev_info *dev_info =
1808                 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
1809         struct fm10k_rx_queue *q;
1810         const struct rte_memzone *mz;
1811
1812         PMD_INIT_FUNC_TRACE();
1813
1814         /* make sure the mempool element size can account for alignment. */
1815         if (!mempool_element_size_valid(mp)) {
1816                 PMD_INIT_LOG(ERR, "Error : Mempool element size is too small");
1817                 return -EINVAL;
1818         }
1819
1820         /* make sure a valid number of descriptors have been requested */
1821         if (check_nb_desc(FM10K_MIN_RX_DESC, FM10K_MAX_RX_DESC,
1822                                 FM10K_MULT_RX_DESC, nb_desc)) {
1823                 PMD_INIT_LOG(ERR, "Number of Rx descriptors (%u) must be "
1824                         "less than or equal to %"PRIu32", "
1825                         "greater than or equal to %u, "
1826                         "and a multiple of %u",
1827                         nb_desc, (uint32_t)FM10K_MAX_RX_DESC, FM10K_MIN_RX_DESC,
1828                         FM10K_MULT_RX_DESC);
1829                 return -EINVAL;
1830         }
1831
1832         /*
1833          * if this queue existed already, free the associated memory. The
1834          * queue cannot be reused in case we need to allocate memory on
1835          * different socket than was previously used.
1836          */
1837         if (dev->data->rx_queues[queue_id] != NULL) {
1838                 rx_queue_free(dev->data->rx_queues[queue_id]);
1839                 dev->data->rx_queues[queue_id] = NULL;
1840         }
1841
1842         /* allocate memory for the queue structure */
1843         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1844                                 socket_id);
1845         if (q == NULL) {
1846                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1847                 return -ENOMEM;
1848         }
1849
1850         /* setup queue */
1851         q->mp = mp;
1852         q->nb_desc = nb_desc;
1853         q->nb_fake_desc = FM10K_MULT_RX_DESC;
1854         q->port_id = dev->data->port_id;
1855         q->queue_id = queue_id;
1856         q->tail_ptr = (volatile uint32_t *)
1857                 &((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];
1858         if (handle_rxconf(q, conf))
1859                 return -EINVAL;
1860
1861         /* allocate memory for the software ring */
1862         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
1863                         (nb_desc + q->nb_fake_desc) * sizeof(struct rte_mbuf *),
1864                         RTE_CACHE_LINE_SIZE, socket_id);
1865         if (q->sw_ring == NULL) {
1866                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
1867                 rte_free(q);
1868                 return -ENOMEM;
1869         }
1870
1871         /*
1872          * allocate memory for the hardware descriptor ring. A memzone large
1873          * enough to hold the maximum ring size is requested to allow for
1874          * resizing in later calls to the queue setup function.
1875          */
1876         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_id,
1877                                       FM10K_MAX_RX_RING_SZ, FM10K_ALIGN_RX_DESC,
1878                                       socket_id);
1879         if (mz == NULL) {
1880                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
1881                 rte_free(q->sw_ring);
1882                 rte_free(q);
1883                 return -ENOMEM;
1884         }
1885         q->hw_ring = mz->addr;
1886         q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1887
1888         /* Check if number of descs satisfied Vector requirement */
1889         if (!rte_is_power_of_2(nb_desc)) {
1890                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
1891                                     "preconditions - canceling the feature for "
1892                                     "the whole port[%d]",
1893                              q->queue_id, q->port_id);
1894                 dev_info->rx_vec_allowed = false;
1895         } else
1896                 fm10k_rxq_vec_setup(q);
1897
1898         dev->data->rx_queues[queue_id] = q;
1899         return 0;
1900 }
1901
1902 static void
1903 fm10k_rx_queue_release(void *queue)
1904 {
1905         PMD_INIT_FUNC_TRACE();
1906
1907         rx_queue_free(queue);
1908 }
1909
1910 static inline int
1911 handle_txconf(struct fm10k_tx_queue *q, const struct rte_eth_txconf *conf)
1912 {
1913         uint16_t tx_free_thresh;
1914         uint16_t tx_rs_thresh;
1915
1916         /* constraint MACROs require that tx_free_thresh is configured
1917          * before tx_rs_thresh */
1918         if (conf->tx_free_thresh == 0)
1919                 tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(q);
1920         else
1921                 tx_free_thresh = conf->tx_free_thresh;
1922
1923         /* make sure the requested threshold satisfies the constraints */
1924         if (check_thresh(FM10K_TX_FREE_THRESH_MIN(q),
1925                         FM10K_TX_FREE_THRESH_MAX(q),
1926                         FM10K_TX_FREE_THRESH_DIV(q),
1927                         tx_free_thresh)) {
1928                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be "
1929                         "less than or equal to %u, "
1930                         "greater than or equal to %u, "
1931                         "and a divisor of %u",
1932                         tx_free_thresh, FM10K_TX_FREE_THRESH_MAX(q),
1933                         FM10K_TX_FREE_THRESH_MIN(q),
1934                         FM10K_TX_FREE_THRESH_DIV(q));
1935                 return -EINVAL;
1936         }
1937
1938         q->free_thresh = tx_free_thresh;
1939
1940         if (conf->tx_rs_thresh == 0)
1941                 tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(q);
1942         else
1943                 tx_rs_thresh = conf->tx_rs_thresh;
1944
1945         q->tx_deferred_start = conf->tx_deferred_start;
1946
1947         /* make sure the requested threshold satisfies the constraints */
1948         if (check_thresh(FM10K_TX_RS_THRESH_MIN(q),
1949                         FM10K_TX_RS_THRESH_MAX(q),
1950                         FM10K_TX_RS_THRESH_DIV(q),
1951                         tx_rs_thresh)) {
1952                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be "
1953                         "less than or equal to %u, "
1954                         "greater than or equal to %u, "
1955                         "and a divisor of %u",
1956                         tx_rs_thresh, FM10K_TX_RS_THRESH_MAX(q),
1957                         FM10K_TX_RS_THRESH_MIN(q),
1958                         FM10K_TX_RS_THRESH_DIV(q));
1959                 return -EINVAL;
1960         }
1961
1962         q->rs_thresh = tx_rs_thresh;
1963
1964         return 0;
1965 }
1966
1967 static int
1968 fm10k_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1969         uint16_t nb_desc, unsigned int socket_id,
1970         const struct rte_eth_txconf *conf)
1971 {
1972         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1973         struct fm10k_tx_queue *q;
1974         const struct rte_memzone *mz;
1975
1976         PMD_INIT_FUNC_TRACE();
1977
1978         /* make sure a valid number of descriptors have been requested */
1979         if (check_nb_desc(FM10K_MIN_TX_DESC, FM10K_MAX_TX_DESC,
1980                                 FM10K_MULT_TX_DESC, nb_desc)) {
1981                 PMD_INIT_LOG(ERR, "Number of Tx descriptors (%u) must be "
1982                         "less than or equal to %"PRIu32", "
1983                         "greater than or equal to %u, "
1984                         "and a multiple of %u",
1985                         nb_desc, (uint32_t)FM10K_MAX_TX_DESC, FM10K_MIN_TX_DESC,
1986                         FM10K_MULT_TX_DESC);
1987                 return -EINVAL;
1988         }
1989
1990         /*
1991          * if this queue existed already, free the associated memory. The
1992          * queue cannot be reused in case we need to allocate memory on
1993          * different socket than was previously used.
1994          */
1995         if (dev->data->tx_queues[queue_id] != NULL) {
1996                 struct fm10k_tx_queue *txq = dev->data->tx_queues[queue_id];
1997
1998                 tx_queue_free(txq);
1999                 dev->data->tx_queues[queue_id] = NULL;
2000         }
2001
2002         /* allocate memory for the queue structure */
2003         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
2004                                 socket_id);
2005         if (q == NULL) {
2006                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
2007                 return -ENOMEM;
2008         }
2009
2010         /* setup queue */
2011         q->nb_desc = nb_desc;
2012         q->port_id = dev->data->port_id;
2013         q->queue_id = queue_id;
2014         q->txq_flags = conf->txq_flags;
2015         q->ops = &def_txq_ops;
2016         q->tail_ptr = (volatile uint32_t *)
2017                 &((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];
2018         if (handle_txconf(q, conf))
2019                 return -EINVAL;
2020
2021         /* allocate memory for the software ring */
2022         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
2023                                         nb_desc * sizeof(struct rte_mbuf *),
2024                                         RTE_CACHE_LINE_SIZE, socket_id);
2025         if (q->sw_ring == NULL) {
2026                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
2027                 rte_free(q);
2028                 return -ENOMEM;
2029         }
2030
2031         /*
2032          * allocate memory for the hardware descriptor ring. A memzone large
2033          * enough to hold the maximum ring size is requested to allow for
2034          * resizing in later calls to the queue setup function.
2035          */
2036         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_id,
2037                                       FM10K_MAX_TX_RING_SZ, FM10K_ALIGN_TX_DESC,
2038                                       socket_id);
2039         if (mz == NULL) {
2040                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
2041                 rte_free(q->sw_ring);
2042                 rte_free(q);
2043                 return -ENOMEM;
2044         }
2045         q->hw_ring = mz->addr;
2046         q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2047
2048         /*
2049          * allocate memory for the RS bit tracker. Enough slots to hold the
2050          * descriptor index for each RS bit needing to be set are required.
2051          */
2052         q->rs_tracker.list = rte_zmalloc_socket("fm10k rs tracker",
2053                                 ((nb_desc + 1) / q->rs_thresh) *
2054                                 sizeof(uint16_t),
2055                                 RTE_CACHE_LINE_SIZE, socket_id);
2056         if (q->rs_tracker.list == NULL) {
2057                 PMD_INIT_LOG(ERR, "Cannot allocate RS bit tracker");
2058                 rte_free(q->sw_ring);
2059                 rte_free(q);
2060                 return -ENOMEM;
2061         }
2062
2063         dev->data->tx_queues[queue_id] = q;
2064         return 0;
2065 }
2066
2067 static void
2068 fm10k_tx_queue_release(void *queue)
2069 {
2070         struct fm10k_tx_queue *q = queue;
2071         PMD_INIT_FUNC_TRACE();
2072
2073         tx_queue_free(q);
2074 }
2075
2076 static int
2077 fm10k_reta_update(struct rte_eth_dev *dev,
2078                         struct rte_eth_rss_reta_entry64 *reta_conf,
2079                         uint16_t reta_size)
2080 {
2081         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2082         uint16_t i, j, idx, shift;
2083         uint8_t mask;
2084         uint32_t reta;
2085
2086         PMD_INIT_FUNC_TRACE();
2087
2088         if (reta_size > FM10K_MAX_RSS_INDICES) {
2089                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2090                         "(%d) doesn't match the number hardware can supported "
2091                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2092                 return -EINVAL;
2093         }
2094
2095         /*
2096          * Update Redirection Table RETA[n], n=0..31. The redirection table has
2097          * 128-entries in 32 registers
2098          */
2099         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2100                 idx = i / RTE_RETA_GROUP_SIZE;
2101                 shift = i % RTE_RETA_GROUP_SIZE;
2102                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2103                                 BIT_MASK_PER_UINT32);
2104                 if (mask == 0)
2105                         continue;
2106
2107                 reta = 0;
2108                 if (mask != BIT_MASK_PER_UINT32)
2109                         reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2110
2111                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2112                         if (mask & (0x1 << j)) {
2113                                 if (mask != 0xF)
2114                                         reta &= ~(UINT8_MAX << CHAR_BIT * j);
2115                                 reta |= reta_conf[idx].reta[shift + j] <<
2116                                                 (CHAR_BIT * j);
2117                         }
2118                 }
2119                 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2), reta);
2120         }
2121
2122         return 0;
2123 }
2124
2125 static int
2126 fm10k_reta_query(struct rte_eth_dev *dev,
2127                         struct rte_eth_rss_reta_entry64 *reta_conf,
2128                         uint16_t reta_size)
2129 {
2130         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2131         uint16_t i, j, idx, shift;
2132         uint8_t mask;
2133         uint32_t reta;
2134
2135         PMD_INIT_FUNC_TRACE();
2136
2137         if (reta_size < FM10K_MAX_RSS_INDICES) {
2138                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2139                         "(%d) doesn't match the number hardware can supported "
2140                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2141                 return -EINVAL;
2142         }
2143
2144         /*
2145          * Read Redirection Table RETA[n], n=0..31. The redirection table has
2146          * 128-entries in 32 registers
2147          */
2148         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2149                 idx = i / RTE_RETA_GROUP_SIZE;
2150                 shift = i % RTE_RETA_GROUP_SIZE;
2151                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2152                                 BIT_MASK_PER_UINT32);
2153                 if (mask == 0)
2154                         continue;
2155
2156                 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2157                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2158                         if (mask & (0x1 << j))
2159                                 reta_conf[idx].reta[shift + j] = ((reta >>
2160                                         CHAR_BIT * j) & UINT8_MAX);
2161                 }
2162         }
2163
2164         return 0;
2165 }
2166
2167 static int
2168 fm10k_rss_hash_update(struct rte_eth_dev *dev,
2169         struct rte_eth_rss_conf *rss_conf)
2170 {
2171         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2172         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2173         uint32_t mrqc;
2174         uint64_t hf = rss_conf->rss_hf;
2175         int i;
2176
2177         PMD_INIT_FUNC_TRACE();
2178
2179         if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2180                                 FM10K_RSSRK_ENTRIES_PER_REG))
2181                 return -EINVAL;
2182
2183         if (hf == 0)
2184                 return -EINVAL;
2185
2186         mrqc = 0;
2187         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
2188         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
2189         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
2190         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
2191         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
2192         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
2193         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
2194         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
2195         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
2196
2197         /* If the mapping doesn't fit any supported, return */
2198         if (mrqc == 0)
2199                 return -EINVAL;
2200
2201         if (key != NULL)
2202                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2203                         FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
2204
2205         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
2206
2207         return 0;
2208 }
2209
2210 static int
2211 fm10k_rss_hash_conf_get(struct rte_eth_dev *dev,
2212         struct rte_eth_rss_conf *rss_conf)
2213 {
2214         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2215         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2216         uint32_t mrqc;
2217         uint64_t hf;
2218         int i;
2219
2220         PMD_INIT_FUNC_TRACE();
2221
2222         if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2223                                 FM10K_RSSRK_ENTRIES_PER_REG))
2224                 return -EINVAL;
2225
2226         if (key != NULL)
2227                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2228                         key[i] = FM10K_READ_REG(hw, FM10K_RSSRK(0, i));
2229
2230         mrqc = FM10K_READ_REG(hw, FM10K_MRQC(0));
2231         hf = 0;
2232         hf |= (mrqc & FM10K_MRQC_IPV4)     ? ETH_RSS_IPV4              : 0;
2233         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6              : 0;
2234         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6_EX           : 0;
2235         hf |= (mrqc & FM10K_MRQC_TCP_IPV4) ? ETH_RSS_NONFRAG_IPV4_TCP  : 0;
2236         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_NONFRAG_IPV6_TCP  : 0;
2237         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_IPV6_TCP_EX       : 0;
2238         hf |= (mrqc & FM10K_MRQC_UDP_IPV4) ? ETH_RSS_NONFRAG_IPV4_UDP  : 0;
2239         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_NONFRAG_IPV6_UDP  : 0;
2240         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_IPV6_UDP_EX       : 0;
2241
2242         rss_conf->rss_hf = hf;
2243
2244         return 0;
2245 }
2246
2247 static void
2248 fm10k_dev_enable_intr_pf(struct rte_eth_dev *dev)
2249 {
2250         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2251         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2252
2253         /* Bind all local non-queue interrupt to vector 0 */
2254         int_map |= FM10K_MISC_VEC_ID;
2255
2256         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2257         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2258         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2259         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2260         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2261         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2262
2263         /* Enable misc causes */
2264         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
2265                                 FM10K_EIMR_ENABLE(THI_FAULT) |
2266                                 FM10K_EIMR_ENABLE(FUM_FAULT) |
2267                                 FM10K_EIMR_ENABLE(MAILBOX) |
2268                                 FM10K_EIMR_ENABLE(SWITCHREADY) |
2269                                 FM10K_EIMR_ENABLE(SWITCHNOTREADY) |
2270                                 FM10K_EIMR_ENABLE(SRAMERROR) |
2271                                 FM10K_EIMR_ENABLE(VFLR));
2272
2273         /* Enable ITR 0 */
2274         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2275                                         FM10K_ITR_MASK_CLEAR);
2276         FM10K_WRITE_FLUSH(hw);
2277 }
2278
2279 static void
2280 fm10k_dev_disable_intr_pf(struct rte_eth_dev *dev)
2281 {
2282         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2283         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2284
2285         int_map |= FM10K_MISC_VEC_ID;
2286
2287         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2288         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2289         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2290         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2291         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2292         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2293
2294         /* Disable misc causes */
2295         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(PCA_FAULT) |
2296                                 FM10K_EIMR_DISABLE(THI_FAULT) |
2297                                 FM10K_EIMR_DISABLE(FUM_FAULT) |
2298                                 FM10K_EIMR_DISABLE(MAILBOX) |
2299                                 FM10K_EIMR_DISABLE(SWITCHREADY) |
2300                                 FM10K_EIMR_DISABLE(SWITCHNOTREADY) |
2301                                 FM10K_EIMR_DISABLE(SRAMERROR) |
2302                                 FM10K_EIMR_DISABLE(VFLR));
2303
2304         /* Disable ITR 0 */
2305         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_MASK_SET);
2306         FM10K_WRITE_FLUSH(hw);
2307 }
2308
2309 static void
2310 fm10k_dev_enable_intr_vf(struct rte_eth_dev *dev)
2311 {
2312         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2313         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2314
2315         /* Bind all local non-queue interrupt to vector 0 */
2316         int_map |= FM10K_MISC_VEC_ID;
2317
2318         /* Only INT 0 available, other 15 are reserved. */
2319         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2320
2321         /* Enable ITR 0 */
2322         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2323                                         FM10K_ITR_MASK_CLEAR);
2324         FM10K_WRITE_FLUSH(hw);
2325 }
2326
2327 static void
2328 fm10k_dev_disable_intr_vf(struct rte_eth_dev *dev)
2329 {
2330         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2331         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2332
2333         int_map |= FM10K_MISC_VEC_ID;
2334
2335         /* Only INT 0 available, other 15 are reserved. */
2336         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2337
2338         /* Disable ITR 0 */
2339         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_MASK_SET);
2340         FM10K_WRITE_FLUSH(hw);
2341 }
2342
2343 static int
2344 fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2345 {
2346         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2347         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
2348
2349         /* Enable ITR */
2350         if (hw->mac.type == fm10k_mac_pf)
2351                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, queue_id)),
2352                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2353         else
2354                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
2355                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2356         rte_intr_enable(&pdev->intr_handle);
2357         return 0;
2358 }
2359
2360 static int
2361 fm10k_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2362 {
2363         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2364         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
2365
2366         /* Disable ITR */
2367         if (hw->mac.type == fm10k_mac_pf)
2368                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, queue_id)),
2369                         FM10K_ITR_MASK_SET);
2370         else
2371                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
2372                         FM10K_ITR_MASK_SET);
2373         return 0;
2374 }
2375
2376 static int
2377 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2378 {
2379         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2380         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
2381         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
2382         uint32_t intr_vector, vec;
2383         uint16_t queue_id;
2384         int result = 0;
2385
2386         /* fm10k needs one separate interrupt for mailbox,
2387          * so only drivers which support multiple interrupt vectors
2388          * e.g. vfio-pci can work for fm10k interrupt mode
2389          */
2390         if (!rte_intr_cap_multiple(intr_handle) ||
2391                         dev->data->dev_conf.intr_conf.rxq == 0)
2392                 return result;
2393
2394         intr_vector = dev->data->nb_rx_queues;
2395
2396         /* disable interrupt first */
2397         rte_intr_disable(intr_handle);
2398         if (hw->mac.type == fm10k_mac_pf)
2399                 fm10k_dev_disable_intr_pf(dev);
2400         else
2401                 fm10k_dev_disable_intr_vf(dev);
2402
2403         if (rte_intr_efd_enable(intr_handle, intr_vector)) {
2404                 PMD_INIT_LOG(ERR, "Failed to init event fd");
2405                 result = -EIO;
2406         }
2407
2408         if (rte_intr_dp_is_en(intr_handle) && !result) {
2409                 intr_handle->intr_vec = rte_zmalloc("intr_vec",
2410                         dev->data->nb_rx_queues * sizeof(int), 0);
2411                 if (intr_handle->intr_vec) {
2412                         for (queue_id = 0, vec = FM10K_RX_VEC_START;
2413                                         queue_id < dev->data->nb_rx_queues;
2414                                         queue_id++) {
2415                                 intr_handle->intr_vec[queue_id] = vec;
2416                                 if (vec < intr_handle->nb_efd - 1
2417                                                 + FM10K_RX_VEC_START)
2418                                         vec++;
2419                         }
2420                 } else {
2421                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2422                                 " intr_vec", dev->data->nb_rx_queues);
2423                         rte_intr_efd_disable(intr_handle);
2424                         result = -ENOMEM;
2425                 }
2426         }
2427
2428         if (hw->mac.type == fm10k_mac_pf)
2429                 fm10k_dev_enable_intr_pf(dev);
2430         else
2431                 fm10k_dev_enable_intr_vf(dev);
2432         rte_intr_enable(intr_handle);
2433         hw->mac.ops.update_int_moderator(hw);
2434         return result;
2435 }
2436
2437 static int
2438 fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr)
2439 {
2440         struct fm10k_fault fault;
2441         int err;
2442         const char *estr = "Unknown error";
2443
2444         /* Process PCA fault */
2445         if (eicr & FM10K_EICR_PCA_FAULT) {
2446                 err = fm10k_get_fault(hw, FM10K_PCA_FAULT, &fault);
2447                 if (err)
2448                         goto error;
2449                 switch (fault.type) {
2450                 case PCA_NO_FAULT:
2451                         estr = "PCA_NO_FAULT"; break;
2452                 case PCA_UNMAPPED_ADDR:
2453                         estr = "PCA_UNMAPPED_ADDR"; break;
2454                 case PCA_BAD_QACCESS_PF:
2455                         estr = "PCA_BAD_QACCESS_PF"; break;
2456                 case PCA_BAD_QACCESS_VF:
2457                         estr = "PCA_BAD_QACCESS_VF"; break;
2458                 case PCA_MALICIOUS_REQ:
2459                         estr = "PCA_MALICIOUS_REQ"; break;
2460                 case PCA_POISONED_TLP:
2461                         estr = "PCA_POISONED_TLP"; break;
2462                 case PCA_TLP_ABORT:
2463                         estr = "PCA_TLP_ABORT"; break;
2464                 default:
2465                         goto error;
2466                 }
2467                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2468                         estr, fault.func ? "VF" : "PF", fault.func,
2469                         fault.address, fault.specinfo);
2470         }
2471
2472         /* Process THI fault */
2473         if (eicr & FM10K_EICR_THI_FAULT) {
2474                 err = fm10k_get_fault(hw, FM10K_THI_FAULT, &fault);
2475                 if (err)
2476                         goto error;
2477                 switch (fault.type) {
2478                 case THI_NO_FAULT:
2479                         estr = "THI_NO_FAULT"; break;
2480                 case THI_MAL_DIS_Q_FAULT:
2481                         estr = "THI_MAL_DIS_Q_FAULT"; break;
2482                 default:
2483                         goto error;
2484                 }
2485                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2486                         estr, fault.func ? "VF" : "PF", fault.func,
2487                         fault.address, fault.specinfo);
2488         }
2489
2490         /* Process FUM fault */
2491         if (eicr & FM10K_EICR_FUM_FAULT) {
2492                 err = fm10k_get_fault(hw, FM10K_FUM_FAULT, &fault);
2493                 if (err)
2494                         goto error;
2495                 switch (fault.type) {
2496                 case FUM_NO_FAULT:
2497                         estr = "FUM_NO_FAULT"; break;
2498                 case FUM_UNMAPPED_ADDR:
2499                         estr = "FUM_UNMAPPED_ADDR"; break;
2500                 case FUM_POISONED_TLP:
2501                         estr = "FUM_POISONED_TLP"; break;
2502                 case FUM_BAD_VF_QACCESS:
2503                         estr = "FUM_BAD_VF_QACCESS"; break;
2504                 case FUM_ADD_DECODE_ERR:
2505                         estr = "FUM_ADD_DECODE_ERR"; break;
2506                 case FUM_RO_ERROR:
2507                         estr = "FUM_RO_ERROR"; break;
2508                 case FUM_QPRC_CRC_ERROR:
2509                         estr = "FUM_QPRC_CRC_ERROR"; break;
2510                 case FUM_CSR_TIMEOUT:
2511                         estr = "FUM_CSR_TIMEOUT"; break;
2512                 case FUM_INVALID_TYPE:
2513                         estr = "FUM_INVALID_TYPE"; break;
2514                 case FUM_INVALID_LENGTH:
2515                         estr = "FUM_INVALID_LENGTH"; break;
2516                 case FUM_INVALID_BE:
2517                         estr = "FUM_INVALID_BE"; break;
2518                 case FUM_INVALID_ALIGN:
2519                         estr = "FUM_INVALID_ALIGN"; break;
2520                 default:
2521                         goto error;
2522                 }
2523                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2524                         estr, fault.func ? "VF" : "PF", fault.func,
2525                         fault.address, fault.specinfo);
2526         }
2527
2528         return 0;
2529 error:
2530         PMD_INIT_LOG(ERR, "Failed to handle fault event.");
2531         return err;
2532 }
2533
2534 /**
2535  * PF interrupt handler triggered by NIC for handling specific interrupt.
2536  *
2537  * @param handle
2538  *  Pointer to interrupt handle.
2539  * @param param
2540  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2541  *
2542  * @return
2543  *  void
2544  */
2545 static void
2546 fm10k_dev_interrupt_handler_pf(void *param)
2547 {
2548         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2549         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2550         uint32_t cause, status;
2551
2552         if (hw->mac.type != fm10k_mac_pf)
2553                 return;
2554
2555         cause = FM10K_READ_REG(hw, FM10K_EICR);
2556
2557         /* Handle PCI fault cases */
2558         if (cause & FM10K_EICR_FAULT_MASK) {
2559                 PMD_INIT_LOG(ERR, "INT: find fault!");
2560                 fm10k_dev_handle_fault(hw, cause);
2561         }
2562
2563         /* Handle switch up/down */
2564         if (cause & FM10K_EICR_SWITCHNOTREADY)
2565                 PMD_INIT_LOG(ERR, "INT: Switch is not ready");
2566
2567         if (cause & FM10K_EICR_SWITCHREADY)
2568                 PMD_INIT_LOG(INFO, "INT: Switch is ready");
2569
2570         /* Handle mailbox message */
2571         fm10k_mbx_lock(hw);
2572         hw->mbx.ops.process(hw, &hw->mbx);
2573         fm10k_mbx_unlock(hw);
2574
2575         /* Handle SRAM error */
2576         if (cause & FM10K_EICR_SRAMERROR) {
2577                 PMD_INIT_LOG(ERR, "INT: SRAM error on PEP");
2578
2579                 status = FM10K_READ_REG(hw, FM10K_SRAM_IP);
2580                 /* Write to clear pending bits */
2581                 FM10K_WRITE_REG(hw, FM10K_SRAM_IP, status);
2582
2583                 /* Todo: print out error message after shared code  updates */
2584         }
2585
2586         /* Clear these 3 events if having any */
2587         cause &= FM10K_EICR_SWITCHNOTREADY | FM10K_EICR_MAILBOX |
2588                  FM10K_EICR_SWITCHREADY;
2589         if (cause)
2590                 FM10K_WRITE_REG(hw, FM10K_EICR, cause);
2591
2592         /* Re-enable interrupt from device side */
2593         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2594                                         FM10K_ITR_MASK_CLEAR);
2595         /* Re-enable interrupt from host side */
2596         rte_intr_enable(dev->intr_handle);
2597 }
2598
2599 /**
2600  * VF interrupt handler triggered by NIC for handling specific interrupt.
2601  *
2602  * @param handle
2603  *  Pointer to interrupt handle.
2604  * @param param
2605  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2606  *
2607  * @return
2608  *  void
2609  */
2610 static void
2611 fm10k_dev_interrupt_handler_vf(void *param)
2612 {
2613         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2614         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2615
2616         if (hw->mac.type != fm10k_mac_vf)
2617                 return;
2618
2619         /* Handle mailbox message if lock is acquired */
2620         fm10k_mbx_lock(hw);
2621         hw->mbx.ops.process(hw, &hw->mbx);
2622         fm10k_mbx_unlock(hw);
2623
2624         /* Re-enable interrupt from device side */
2625         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2626                                         FM10K_ITR_MASK_CLEAR);
2627         /* Re-enable interrupt from host side */
2628         rte_intr_enable(dev->intr_handle);
2629 }
2630
2631 /* Mailbox message handler in VF */
2632 static const struct fm10k_msg_data fm10k_msgdata_vf[] = {
2633         FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
2634         FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
2635         FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
2636         FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
2637 };
2638
2639 static int
2640 fm10k_setup_mbx_service(struct fm10k_hw *hw)
2641 {
2642         int err = 0;
2643
2644         /* Initialize mailbox lock */
2645         fm10k_mbx_initlock(hw);
2646
2647         /* Replace default message handler with new ones */
2648         if (hw->mac.type == fm10k_mac_vf)
2649                 err = hw->mbx.ops.register_handlers(&hw->mbx, fm10k_msgdata_vf);
2650
2651         if (err) {
2652                 PMD_INIT_LOG(ERR, "Failed to register mailbox handler.err:%d",
2653                                 err);
2654                 return err;
2655         }
2656         /* Connect to SM for PF device or PF for VF device */
2657         return hw->mbx.ops.connect(hw, &hw->mbx);
2658 }
2659
2660 static void
2661 fm10k_close_mbx_service(struct fm10k_hw *hw)
2662 {
2663         /* Disconnect from SM for PF device or PF for VF device */
2664         hw->mbx.ops.disconnect(hw, &hw->mbx);
2665 }
2666
2667 static const struct eth_dev_ops fm10k_eth_dev_ops = {
2668         .dev_configure          = fm10k_dev_configure,
2669         .dev_start              = fm10k_dev_start,
2670         .dev_stop               = fm10k_dev_stop,
2671         .dev_close              = fm10k_dev_close,
2672         .promiscuous_enable     = fm10k_dev_promiscuous_enable,
2673         .promiscuous_disable    = fm10k_dev_promiscuous_disable,
2674         .allmulticast_enable    = fm10k_dev_allmulticast_enable,
2675         .allmulticast_disable   = fm10k_dev_allmulticast_disable,
2676         .stats_get              = fm10k_stats_get,
2677         .xstats_get             = fm10k_xstats_get,
2678         .xstats_get_names       = fm10k_xstats_get_names,
2679         .stats_reset            = fm10k_stats_reset,
2680         .xstats_reset           = fm10k_stats_reset,
2681         .link_update            = fm10k_link_update,
2682         .dev_infos_get          = fm10k_dev_infos_get,
2683         .dev_supported_ptypes_get = fm10k_dev_supported_ptypes_get,
2684         .vlan_filter_set        = fm10k_vlan_filter_set,
2685         .vlan_offload_set       = fm10k_vlan_offload_set,
2686         .mac_addr_add           = fm10k_macaddr_add,
2687         .mac_addr_remove        = fm10k_macaddr_remove,
2688         .rx_queue_start         = fm10k_dev_rx_queue_start,
2689         .rx_queue_stop          = fm10k_dev_rx_queue_stop,
2690         .tx_queue_start         = fm10k_dev_tx_queue_start,
2691         .tx_queue_stop          = fm10k_dev_tx_queue_stop,
2692         .rx_queue_setup         = fm10k_rx_queue_setup,
2693         .rx_queue_release       = fm10k_rx_queue_release,
2694         .tx_queue_setup         = fm10k_tx_queue_setup,
2695         .tx_queue_release       = fm10k_tx_queue_release,
2696         .rx_descriptor_done     = fm10k_dev_rx_descriptor_done,
2697         .rx_queue_intr_enable   = fm10k_dev_rx_queue_intr_enable,
2698         .rx_queue_intr_disable  = fm10k_dev_rx_queue_intr_disable,
2699         .reta_update            = fm10k_reta_update,
2700         .reta_query             = fm10k_reta_query,
2701         .rss_hash_update        = fm10k_rss_hash_update,
2702         .rss_hash_conf_get      = fm10k_rss_hash_conf_get,
2703 };
2704
2705 static int ftag_check_handler(__rte_unused const char *key,
2706                 const char *value, __rte_unused void *opaque)
2707 {
2708         if (strcmp(value, "1"))
2709                 return -1;
2710
2711         return 0;
2712 }
2713
2714 static int
2715 fm10k_check_ftag(struct rte_devargs *devargs)
2716 {
2717         struct rte_kvargs *kvlist;
2718         const char *ftag_key = "enable_ftag";
2719
2720         if (devargs == NULL)
2721                 return 0;
2722
2723         kvlist = rte_kvargs_parse(devargs->args, NULL);
2724         if (kvlist == NULL)
2725                 return 0;
2726
2727         if (!rte_kvargs_count(kvlist, ftag_key)) {
2728                 rte_kvargs_free(kvlist);
2729                 return 0;
2730         }
2731         /* FTAG is enabled when there's key-value pair: enable_ftag=1 */
2732         if (rte_kvargs_process(kvlist, ftag_key,
2733                                 ftag_check_handler, NULL) < 0) {
2734                 rte_kvargs_free(kvlist);
2735                 return 0;
2736         }
2737         rte_kvargs_free(kvlist);
2738
2739         return 1;
2740 }
2741
2742 static uint16_t
2743 fm10k_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
2744                     uint16_t nb_pkts)
2745 {
2746         uint16_t nb_tx = 0;
2747         struct fm10k_tx_queue *txq = (struct fm10k_tx_queue *)tx_queue;
2748
2749         while (nb_pkts) {
2750                 uint16_t ret, num;
2751
2752                 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
2753                 ret = fm10k_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
2754                                                  num);
2755                 nb_tx += ret;
2756                 nb_pkts -= ret;
2757                 if (ret < num)
2758                         break;
2759         }
2760
2761         return nb_tx;
2762 }
2763
2764 static void __attribute__((cold))
2765 fm10k_set_tx_function(struct rte_eth_dev *dev)
2766 {
2767         struct fm10k_tx_queue *txq;
2768         int i;
2769         int use_sse = 1;
2770         uint16_t tx_ftag_en = 0;
2771
2772         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2773                 /* primary process has set the ftag flag and txq_flags */
2774                 txq = dev->data->tx_queues[0];
2775                 if (fm10k_tx_vec_condition_check(txq)) {
2776                         dev->tx_pkt_burst = fm10k_xmit_pkts;
2777                         dev->tx_pkt_prepare = fm10k_prep_pkts;
2778                         PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2779                 } else {
2780                         PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2781                         dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2782                         dev->tx_pkt_prepare = NULL;
2783                 }
2784                 return;
2785         }
2786
2787         if (fm10k_check_ftag(dev->device->devargs))
2788                 tx_ftag_en = 1;
2789
2790         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2791                 txq = dev->data->tx_queues[i];
2792                 txq->tx_ftag_en = tx_ftag_en;
2793                 /* Check if Vector Tx is satisfied */
2794                 if (fm10k_tx_vec_condition_check(txq))
2795                         use_sse = 0;
2796         }
2797
2798         if (use_sse) {
2799                 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2800                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2801                         txq = dev->data->tx_queues[i];
2802                         fm10k_txq_vec_setup(txq);
2803                 }
2804                 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2805                 dev->tx_pkt_prepare = NULL;
2806         } else {
2807                 dev->tx_pkt_burst = fm10k_xmit_pkts;
2808                 dev->tx_pkt_prepare = fm10k_prep_pkts;
2809                 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2810         }
2811 }
2812
2813 static void __attribute__((cold))
2814 fm10k_set_rx_function(struct rte_eth_dev *dev)
2815 {
2816         struct fm10k_dev_info *dev_info =
2817                 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2818         uint16_t i, rx_using_sse;
2819         uint16_t rx_ftag_en = 0;
2820
2821         if (fm10k_check_ftag(dev->device->devargs))
2822                 rx_ftag_en = 1;
2823
2824         /* In order to allow Vector Rx there are a few configuration
2825          * conditions to be met.
2826          */
2827         if (!fm10k_rx_vec_condition_check(dev) &&
2828                         dev_info->rx_vec_allowed && !rx_ftag_en) {
2829                 if (dev->data->scattered_rx)
2830                         dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec;
2831                 else
2832                         dev->rx_pkt_burst = fm10k_recv_pkts_vec;
2833         } else if (dev->data->scattered_rx)
2834                 dev->rx_pkt_burst = fm10k_recv_scattered_pkts;
2835         else
2836                 dev->rx_pkt_burst = fm10k_recv_pkts;
2837
2838         rx_using_sse =
2839                 (dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec ||
2840                 dev->rx_pkt_burst == fm10k_recv_pkts_vec);
2841
2842         if (rx_using_sse)
2843                 PMD_INIT_LOG(DEBUG, "Use vector Rx func");
2844         else
2845                 PMD_INIT_LOG(DEBUG, "Use regular Rx func");
2846
2847         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2848                 return;
2849
2850         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2851                 struct fm10k_rx_queue *rxq = dev->data->rx_queues[i];
2852
2853                 rxq->rx_using_sse = rx_using_sse;
2854                 rxq->rx_ftag_en = rx_ftag_en;
2855         }
2856 }
2857
2858 static void
2859 fm10k_params_init(struct rte_eth_dev *dev)
2860 {
2861         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2862         struct fm10k_dev_info *info =
2863                 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2864
2865         /* Inialize bus info. Normally we would call fm10k_get_bus_info(), but
2866          * there is no way to get link status without reading BAR4.  Until this
2867          * works, assume we have maximum bandwidth.
2868          * @todo - fix bus info
2869          */
2870         hw->bus_caps.speed = fm10k_bus_speed_8000;
2871         hw->bus_caps.width = fm10k_bus_width_pcie_x8;
2872         hw->bus_caps.payload = fm10k_bus_payload_512;
2873         hw->bus.speed = fm10k_bus_speed_8000;
2874         hw->bus.width = fm10k_bus_width_pcie_x8;
2875         hw->bus.payload = fm10k_bus_payload_256;
2876
2877         info->rx_vec_allowed = true;
2878 }
2879
2880 static int
2881 eth_fm10k_dev_init(struct rte_eth_dev *dev)
2882 {
2883         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2884         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
2885         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
2886         int diag, i;
2887         struct fm10k_macvlan_filter_info *macvlan;
2888
2889         PMD_INIT_FUNC_TRACE();
2890
2891         dev->dev_ops = &fm10k_eth_dev_ops;
2892         dev->rx_pkt_burst = &fm10k_recv_pkts;
2893         dev->tx_pkt_burst = &fm10k_xmit_pkts;
2894         dev->tx_pkt_prepare = &fm10k_prep_pkts;
2895
2896         /*
2897          * Primary process does the whole initialization, for secondary
2898          * processes, we just select the same Rx and Tx function as primary.
2899          */
2900         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2901                 fm10k_set_rx_function(dev);
2902                 fm10k_set_tx_function(dev);
2903                 return 0;
2904         }
2905
2906         rte_eth_copy_pci_info(dev, pdev);
2907         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
2908
2909         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
2910         memset(macvlan, 0, sizeof(*macvlan));
2911         /* Vendor and Device ID need to be set before init of shared code */
2912         memset(hw, 0, sizeof(*hw));
2913         hw->device_id = pdev->id.device_id;
2914         hw->vendor_id = pdev->id.vendor_id;
2915         hw->subsystem_device_id = pdev->id.subsystem_device_id;
2916         hw->subsystem_vendor_id = pdev->id.subsystem_vendor_id;
2917         hw->revision_id = 0;
2918         hw->hw_addr = (void *)pdev->mem_resource[0].addr;
2919         if (hw->hw_addr == NULL) {
2920                 PMD_INIT_LOG(ERR, "Bad mem resource."
2921                         " Try to blacklist unused devices.");
2922                 return -EIO;
2923         }
2924
2925         /* Store fm10k_adapter pointer */
2926         hw->back = dev->data->dev_private;
2927
2928         /* Initialize the shared code */
2929         diag = fm10k_init_shared_code(hw);
2930         if (diag != FM10K_SUCCESS) {
2931                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
2932                 return -EIO;
2933         }
2934
2935         /* Initialize parameters */
2936         fm10k_params_init(dev);
2937
2938         /* Initialize the hw */
2939         diag = fm10k_init_hw(hw);
2940         if (diag != FM10K_SUCCESS) {
2941                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
2942                 return -EIO;
2943         }
2944
2945         /* Initialize MAC address(es) */
2946         dev->data->mac_addrs = rte_zmalloc("fm10k",
2947                         ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM, 0);
2948         if (dev->data->mac_addrs == NULL) {
2949                 PMD_INIT_LOG(ERR, "Cannot allocate memory for MAC addresses");
2950                 return -ENOMEM;
2951         }
2952
2953         diag = fm10k_read_mac_addr(hw);
2954
2955         ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2956                         &dev->data->mac_addrs[0]);
2957
2958         if (diag != FM10K_SUCCESS ||
2959                 !is_valid_assigned_ether_addr(dev->data->mac_addrs)) {
2960
2961                 /* Generate a random addr */
2962                 eth_random_addr(hw->mac.addr);
2963                 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
2964                 ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2965                 &dev->data->mac_addrs[0]);
2966         }
2967
2968         /* Reset the hw statistics */
2969         fm10k_stats_reset(dev);
2970
2971         /* Reset the hw */
2972         diag = fm10k_reset_hw(hw);
2973         if (diag != FM10K_SUCCESS) {
2974                 PMD_INIT_LOG(ERR, "Hardware reset failed: %d", diag);
2975                 return -EIO;
2976         }
2977
2978         /* Setup mailbox service */
2979         diag = fm10k_setup_mbx_service(hw);
2980         if (diag != FM10K_SUCCESS) {
2981                 PMD_INIT_LOG(ERR, "Failed to setup mailbox: %d", diag);
2982                 return -EIO;
2983         }
2984
2985         /*PF/VF has different interrupt handling mechanism */
2986         if (hw->mac.type == fm10k_mac_pf) {
2987                 /* register callback func to eal lib */
2988                 rte_intr_callback_register(intr_handle,
2989                         fm10k_dev_interrupt_handler_pf, (void *)dev);
2990
2991                 /* enable MISC interrupt */
2992                 fm10k_dev_enable_intr_pf(dev);
2993         } else { /* VF */
2994                 rte_intr_callback_register(intr_handle,
2995                         fm10k_dev_interrupt_handler_vf, (void *)dev);
2996
2997                 fm10k_dev_enable_intr_vf(dev);
2998         }
2999
3000         /* Enable intr after callback registered */
3001         rte_intr_enable(intr_handle);
3002
3003         hw->mac.ops.update_int_moderator(hw);
3004
3005         /* Make sure Switch Manager is ready before going forward. */
3006         if (hw->mac.type == fm10k_mac_pf) {
3007                 int switch_ready = 0;
3008
3009                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
3010                         fm10k_mbx_lock(hw);
3011                         hw->mac.ops.get_host_state(hw, &switch_ready);
3012                         fm10k_mbx_unlock(hw);
3013                         if (switch_ready)
3014                                 break;
3015                         /* Delay some time to acquire async LPORT_MAP info. */
3016                         rte_delay_us(WAIT_SWITCH_MSG_US);
3017                 }
3018
3019                 if (switch_ready == 0) {
3020                         PMD_INIT_LOG(ERR, "switch is not ready");
3021                         return -1;
3022                 }
3023         }
3024
3025         /*
3026          * Below function will trigger operations on mailbox, acquire lock to
3027          * avoid race condition from interrupt handler. Operations on mailbox
3028          * FIFO will trigger interrupt to PF/SM, in which interrupt handler
3029          * will handle and generate an interrupt to our side. Then,  FIFO in
3030          * mailbox will be touched.
3031          */
3032         fm10k_mbx_lock(hw);
3033         /* Enable port first */
3034         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
3035                                         MAX_LPORT_NUM, 1);
3036
3037         /* Set unicast mode by default. App can change to other mode in other
3038          * API func.
3039          */
3040         hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
3041                                         FM10K_XCAST_MODE_NONE);
3042
3043         fm10k_mbx_unlock(hw);
3044
3045         /* Make sure default VID is ready before going forward. */
3046         if (hw->mac.type == fm10k_mac_pf) {
3047                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
3048                         if (hw->mac.default_vid)
3049                                 break;
3050                         /* Delay some time to acquire async port VLAN info. */
3051                         rte_delay_us(WAIT_SWITCH_MSG_US);
3052                 }
3053
3054                 if (!hw->mac.default_vid) {
3055                         PMD_INIT_LOG(ERR, "default VID is not ready");
3056                         return -1;
3057                 }
3058         }
3059
3060         /* Add default mac address */
3061         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
3062                 MAIN_VSI_POOL_NUMBER);
3063
3064         return 0;
3065 }
3066
3067 static int
3068 eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
3069 {
3070         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3071         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
3072         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
3073         PMD_INIT_FUNC_TRACE();
3074
3075         /* only uninitialize in the primary process */
3076         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3077                 return 0;
3078
3079         /* safe to close dev here */
3080         fm10k_dev_close(dev);
3081
3082         dev->dev_ops = NULL;
3083         dev->rx_pkt_burst = NULL;
3084         dev->tx_pkt_burst = NULL;
3085
3086         /* disable uio/vfio intr */
3087         rte_intr_disable(intr_handle);
3088
3089         /*PF/VF has different interrupt handling mechanism */
3090         if (hw->mac.type == fm10k_mac_pf) {
3091                 /* disable interrupt */
3092                 fm10k_dev_disable_intr_pf(dev);
3093
3094                 /* unregister callback func to eal lib */
3095                 rte_intr_callback_unregister(intr_handle,
3096                         fm10k_dev_interrupt_handler_pf, (void *)dev);
3097         } else {
3098                 /* disable interrupt */
3099                 fm10k_dev_disable_intr_vf(dev);
3100
3101                 rte_intr_callback_unregister(intr_handle,
3102                         fm10k_dev_interrupt_handler_vf, (void *)dev);
3103         }
3104
3105         /* free mac memory */
3106         if (dev->data->mac_addrs) {
3107                 rte_free(dev->data->mac_addrs);
3108                 dev->data->mac_addrs = NULL;
3109         }
3110
3111         memset(hw, 0, sizeof(*hw));
3112
3113         return 0;
3114 }
3115
3116 static int eth_fm10k_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3117         struct rte_pci_device *pci_dev)
3118 {
3119         return rte_eth_dev_pci_generic_probe(pci_dev,
3120                 sizeof(struct fm10k_adapter), eth_fm10k_dev_init);
3121 }
3122
3123 static int eth_fm10k_pci_remove(struct rte_pci_device *pci_dev)
3124 {
3125         return rte_eth_dev_pci_generic_remove(pci_dev, eth_fm10k_dev_uninit);
3126 }
3127
3128 /*
3129  * The set of PCI devices this driver supports. This driver will enable both PF
3130  * and SRIOV-VF devices.
3131  */
3132 static const struct rte_pci_id pci_id_fm10k_map[] = {
3133         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_PF) },
3134         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_SDI_FM10420_QDA2) },
3135         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_VF) },
3136         { .vendor_id = 0, /* sentinel */ },
3137 };
3138
3139 static struct rte_pci_driver rte_pmd_fm10k = {
3140         .id_table = pci_id_fm10k_map,
3141         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3142         .probe = eth_fm10k_pci_probe,
3143         .remove = eth_fm10k_pci_remove,
3144 };
3145
3146 RTE_PMD_REGISTER_PCI(net_fm10k, rte_pmd_fm10k);
3147 RTE_PMD_REGISTER_PCI_TABLE(net_fm10k, pci_id_fm10k_map);
3148 RTE_PMD_REGISTER_KMOD_DEP(net_fm10k, "* igb_uio | uio_pci_generic | vfio");